sh: Support for SH7770/SH7780 CPU subtypes.

Merge support for SH7770 and SH7780 SH-4A subtypes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 6 insertions, 0 deletions

diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index a6de3d06a3d9..b4000c8bf31b 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -32,6 +32,10 @@ static void __init check_bugs(void)
         case CPU_SH7750 ... CPU_SH4_501:
                 *p++ = '4';
                 break;
+        case CPU_SH7770 ... CPU_SH7781:
+                *p++ = '4';
+                *p++ = 'a';
+                break;
         default:
                 *p++ = '?';
                 *p++ = '!';
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
index 1fe20359312c..6e9c7e6ee8e4 100644
--- a/include/asm-sh/cpu-sh4/cache.h
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -22,7 +22,9 @@
 #define CCR_CACHE_ICE   0x0100  /* Instruction Cache Enable */
 #define CCR_CACHE_ICI   0x0800  /* IC Invalidate */
 #define CCR_CACHE_IIX   0x8000  /* IC Index Enable */
+#ifndef CONFIG_CPU_SUBTYPE_SH7780
 #define CCR_CACHE_EMODE 0x80000000      /* EMODE Enable */
+#endif
 
 /* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
 #define CCR_CACHE_ENABLE        (CCR_CACHE_OCE|CCR_CACHE_ICE)