diff options
author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2008-07-07 08:11:54 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 05:10:34 -0400 |
commit | cafd63b0076b78bc8f114abbeb724c7e5f5bfe5d (patch) | |
tree | e12be13bbac6d45260f9aa0c507a2712ac272c79 /include/asm-sh | |
parent | a4e1d08491b06b17eb77c92caacd40b330ca8146 (diff) |
sh: update Solution Engine 7343
updated the following codes for Solution Endine 7343:
- fix compile error in arch/sh/boards/se/7343/irq.c
- add nor flash physmaps
- update defconfig
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r-- | include/asm-sh/se7343.h | 97 |
1 files changed, 84 insertions, 13 deletions
diff --git a/include/asm-sh/se7343.h b/include/asm-sh/se7343.h index e7914a54aa96..8d2af779fbc9 100644 --- a/include/asm-sh/se7343.h +++ b/include/asm-sh/se7343.h | |||
@@ -59,24 +59,95 @@ | |||
59 | #define PA_LCD1 0xb8000000 | 59 | #define PA_LCD1 0xb8000000 |
60 | #define PA_LCD2 0xb8800000 | 60 | #define PA_LCD2 0xb8800000 |
61 | 61 | ||
62 | #define PORT_PACR 0xA4050100 | ||
63 | #define PORT_PBCR 0xA4050102 | ||
64 | #define PORT_PCCR 0xA4050104 | ||
65 | #define PORT_PDCR 0xA4050106 | ||
66 | #define PORT_PECR 0xA4050108 | ||
67 | #define PORT_PFCR 0xA405010A | ||
68 | #define PORT_PGCR 0xA405010C | ||
69 | #define PORT_PHCR 0xA405010E | ||
70 | #define PORT_PJCR 0xA4050110 | ||
71 | #define PORT_PKCR 0xA4050112 | ||
72 | #define PORT_PLCR 0xA4050114 | ||
73 | #define PORT_PMCR 0xA4050116 | ||
74 | #define PORT_PNCR 0xA4050118 | ||
75 | #define PORT_PQCR 0xA405011A | ||
76 | #define PORT_PRCR 0xA405011C | ||
77 | #define PORT_PSCR 0xA405011E | ||
78 | #define PORT_PTCR 0xA4050140 | ||
79 | #define PORT_PUCR 0xA4050142 | ||
80 | #define PORT_PVCR 0xA4050144 | ||
81 | #define PORT_PWCR 0xA4050146 | ||
82 | #define PORT_PYCR 0xA4050148 | ||
83 | #define PORT_PZCR 0xA405014A | ||
84 | |||
85 | #define PORT_PSELA 0xA405014C | ||
86 | #define PORT_PSELB 0xA405014E | ||
87 | #define PORT_PSELC 0xA4050150 | ||
88 | #define PORT_PSELD 0xA4050152 | ||
89 | #define PORT_PSELE 0xA4050154 | ||
90 | |||
91 | #define PORT_HIZCRA 0xA4050156 | ||
92 | #define PORT_HIZCRB 0xA4050158 | ||
93 | #define PORT_HIZCRC 0xA405015C | ||
94 | |||
95 | #define PORT_DRVCR 0xA4050180 | ||
96 | |||
97 | #define PORT_PADR 0xA4050120 | ||
98 | #define PORT_PBDR 0xA4050122 | ||
99 | #define PORT_PCDR 0xA4050124 | ||
100 | #define PORT_PDDR 0xA4050126 | ||
101 | #define PORT_PEDR 0xA4050128 | ||
102 | #define PORT_PFDR 0xA405012A | ||
103 | #define PORT_PGDR 0xA405012C | ||
104 | #define PORT_PHDR 0xA405012E | ||
105 | #define PORT_PJDR 0xA4050130 | ||
106 | #define PORT_PKDR 0xA4050132 | ||
107 | #define PORT_PLDR 0xA4050134 | ||
108 | #define PORT_PMDR 0xA4050136 | ||
109 | #define PORT_PNDR 0xA4050138 | ||
110 | #define PORT_PQDR 0xA405013A | ||
111 | #define PORT_PRDR 0xA405013C | ||
112 | #define PORT_PTDR 0xA4050160 | ||
113 | #define PORT_PUDR 0xA4050162 | ||
114 | #define PORT_PVDR 0xA4050164 | ||
115 | #define PORT_PWDR 0xA4050166 | ||
116 | #define PORT_PYDR 0xA4050168 | ||
117 | |||
118 | #define MSTPCR0 0xA4150030 | ||
119 | #define MSTPCR1 0xA4150034 | ||
120 | #define MSTPCR2 0xA4150038 | ||
121 | |||
122 | #define FPGA_IN 0xb1400000 | ||
123 | #define FPGA_OUT 0xb1400002 | ||
124 | |||
62 | #define __IO_PREFIX sh7343se | 125 | #define __IO_PREFIX sh7343se |
63 | #include <asm/io_generic.h> | 126 | #include <asm/io_generic.h> |
64 | 127 | ||
65 | /* External Multiplexed interrupts */ | 128 | #define IRQ0_IRQ 32 |
66 | #define PC_IRQ0 OFFCHIP_IRQ_BASE | 129 | #define IRQ1_IRQ 33 |
67 | #define PC_IRQ1 (PC_IRQ0 + 1) | 130 | #define IRQ4_IRQ 36 |
68 | #define PC_IRQ2 (PC_IRQ1 + 1) | 131 | #define IRQ5_IRQ 37 |
69 | #define PC_IRQ3 (PC_IRQ2 + 1) | 132 | |
133 | #define SE7343_FPGA_IRQ_MRSHPC0 0 | ||
134 | #define SE7343_FPGA_IRQ_MRSHPC1 1 | ||
135 | #define SE7343_FPGA_IRQ_MRSHPC2 2 | ||
136 | #define SE7343_FPGA_IRQ_MRSHPC3 3 | ||
137 | #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ | ||
138 | #define SE7343_FPGA_IRQ_USB 8 | ||
70 | 139 | ||
71 | #define EXT_IRQ0 (PC_IRQ3 + 1) | 140 | #define SE7343_FPGA_IRQ_NR 11 |
72 | #define EXT_IRQ1 (EXT_IRQ0 + 1) | 141 | #define SE7343_FPGA_IRQ_BASE 120 |
73 | #define EXT_IRQ2 (EXT_IRQ1 + 1) | ||
74 | #define EXT_IRQ3 (EXT_IRQ2 + 1) | ||
75 | 142 | ||
76 | #define USB_IRQ0 (EXT_IRQ3 + 1) | 143 | #define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3) |
77 | #define USB_IRQ1 (USB_IRQ0 + 1) | 144 | #define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2) |
145 | #define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1) | ||
146 | #define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0) | ||
147 | #define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC) | ||
148 | #define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB) | ||
78 | 149 | ||
79 | #define UART_IRQ0 (USB_IRQ1 + 1) | 150 | /* arch/sh/boards/se/7343/irq.c */ |
80 | #define UART_IRQ1 (UART_IRQ0 + 1) | 151 | void init_7343se_IRQ(void); |
81 | 152 | ||
82 | #endif /* __ASM_SH_HITACHI_SE7343_H */ | 153 | #endif /* __ASM_SH_HITACHI_SE7343_H */ |