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authorMarkus Brunner <super.firetwister@gmail.com>2007-08-19 19:59:33 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:49 -0400
commit3ea6bc3de4f15fcae84fb31eeea4d420685a3da2 (patch)
tree2b9e37135052aab926b7be0822d024c4ba71c32e /include/asm-sh
parentdfc5ed2a939baf08f9385a8c6249b719cac63665 (diff)
sh: Add SH7720 CPU support.
This adds support for the SH7720 (SH3-DSP) CPU. Signed-off by: Markus Brunner <super.firetwister@gmail.com> Signed-off by: Mark Jonas <toertel@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/cpu-sh3/cache.h4
-rw-r--r--include/asm-sh/cpu-sh3/dma.h13
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h9
-rw-r--r--include/asm-sh/cpu-sh3/timer.h9
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h3
-rw-r--r--include/asm-sh/processor.h2
6 files changed, 30 insertions, 10 deletions
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index ffe08d2813f9..255016fc91f0 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -26,7 +26,9 @@
26#define CCR_CACHE_ENABLE CCR_CACHE_CE 26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28 28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710) 29#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720)
30#define CCR3 0xa40000b4 32#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000 33#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000 34#define CCR_CACHE_32KB 0x00020000
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 3a66dc458023..e56203086eb4 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -1,7 +1,20 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720)
6#define SH_DMAC_BASE 0xa4010020
7
8#define DMTE0_IRQ 48
9#define DMTE1_IRQ 49
10#define DMTE2_IRQ 50
11#define DMTE3_IRQ 51
12#define DMTE4_IRQ 76
13#define DMTE5_IRQ 77
14
15#else
4#define SH_DMAC_BASE 0xa4000020 16#define SH_DMAC_BASE 0xa4000020
17#endif
5 18
6/* Definitions for the SuperH DMAC */ 19/* Definitions for the SuperH DMAC */
7#define TM_BURST 0x00000020 20#define TM_BURST 0x00000020
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index b20786d42d09..16c2d63b7e39 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -27,12 +27,13 @@
27#define TRA 0xffffffd0 27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4 28#define EXPEVT 0xffffffd4
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 31 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 32 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7712) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710) 36 defined(CONFIG_CPU_SUBTYPE_SH7720)
36#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 37#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
37#else 38#else
38#define INTEVT 0xffffffd8 39#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index b6c2020a2ad3..3880ce047fe0 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -23,11 +23,13 @@
23 * --------------------------------------------------------------------------- 23 * ---------------------------------------------------------------------------
24 */ 24 */
25 25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7727) 26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
27 !defined(CONFIG_CPU_SUBTYPE_SH7727)
27#define TMU_TOCR 0xfffffe90 /* Byte access */ 28#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif 29#endif
29 30
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) 31#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7720)
31#define TMU_012_TSTR 0xa412fe92 /* Byte access */ 33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
32 34
33#define TMU0_TCOR 0xa412fe94 /* Long access */ 35#define TMU0_TCOR 0xa412fe94 /* Long access */
@@ -56,7 +58,8 @@
56#define TMU2_TCOR 0xfffffeac /* Long access */ 58#define TMU2_TCOR 0xfffffeac /* Long access */
57#define TMU2_TCNT 0xfffffeb0 /* Long access */ 59#define TMU2_TCNT 0xfffffeb0 /* Long access */
58#define TMU2_TCR 0xfffffeb4 /* Word access */ 60#define TMU2_TCR 0xfffffeb4 /* Word access */
59#if !defined(CONFIG_CPU_SUBTYPE_SH7727) 61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
62 !defined(CONFIG_CPU_SUBTYPE_SH7727)
60#define TMU2_TCPR2 0xfffffeb8 /* Long access */ 63#define TMU2_TCPR2 0xfffffeb8 /* Long access */
61#endif 64#endif
62#endif 65#endif
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 9d308cbe9b29..18467c574534 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,7 +11,8 @@
11#ifndef __ASM_CPU_SH3_UBC_H 11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710) 14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7720)
15#define UBC_BARA 0xa4ffffb0 16#define UBC_BARA 0xa4ffffb0
16#define UBC_BAMRA 0xa4ffffb4 17#define UBC_BAMRA 0xa4ffffb4
17#define UBC_BBRA 0xa4ffffb8 18#define UBC_BBRA 0xa4ffffb8
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 26d52174f4b4..56cb3c89f840 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -45,7 +45,7 @@ enum cpu_type {
45 CPU_SH7705, CPU_SH7706, CPU_SH7707, 45 CPU_SH7705, CPU_SH7706, CPU_SH7707,
46 CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 46 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
47 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 47 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
48 CPU_SH7729, 48 CPU_SH7720, CPU_SH7729,
49 49
50 /* SH-4 types */ 50 /* SH-4 types */
51 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 51 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,