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authorAdrian Bunk <bunk@kernel.org>2008-03-30 18:40:17 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-05-08 06:51:39 -0400
commitf5f826c685464301e4316a9321eb95801c653158 (patch)
tree44ca0475e4894edde26f5e16de0e311a9ef3c927 /include/asm-sh
parent2a6b8148c050941dd61779cb0b49c5c3ea854ebf (diff)
sh: remove the broken SH_MPC1211 support
SH_MPC1211 has been marked as BROKEN for some time. Unless someone is working on reviving it now, I'd therefore suggest this patch to remove it. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/keyboard.h13
-rw-r--r--include/asm-sh/mpc1211/dma.h303
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h60
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h38
8 files changed, 0 insertions, 660 deletions
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f28..000000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_KEYBOARD_H
2#define __ASM_SH_KEYBOARD_H
3/*
4 * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
5 */
6
7#include <linux/kd.h>
8#include <asm/machvec.h>
9
10#ifdef CONFIG_SH_MPC1211
11#include <asm/mpc1211/keyboard-mpc1211.h>
12#endif
13#endif
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d0..000000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
1/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8#ifndef _ASM_MPC1211_DMA_H
9#define _ASM_MPC1211_DMA_H
10
11#include <linux/spinlock.h> /* And spinlocks */
12#include <asm/io.h> /* need byte IO */
13#include <linux/delay.h>
14
15
16#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
17#define dma_outb outb_p
18#else
19#define dma_outb outb
20#endif
21
22#define dma_inb inb
23
24/*
25 * NOTES about DMA transfers:
26 *
27 * controller 1: channels 0-3, byte operations, ports 00-1F
28 * controller 2: channels 4-7, word operations, ports C0-DF
29 *
30 * - ALL registers are 8 bits only, regardless of transfer size
31 * - channel 4 is not used - cascades 1 into 2.
32 * - channels 0-3 are byte - addresses/counts are for physical bytes
33 * - channels 5-7 are word - addresses/counts are for physical words
34 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
35 * - transfer count loaded to registers is 1 less than actual count
36 * - controller 2 offsets are all even (2x offsets for controller 1)
37 * - page registers for 5-7 don't use data bit 0, represent 128K pages
38 * - page registers for 0-3 use bit 0, represent 64K pages
39 *
40 * DMA transfers are limited to the lower 16MB of _physical_ memory.
41 * Note that addresses loaded into registers must be _physical_ addresses,
42 * not logical addresses (which may differ if paging is active).
43 *
44 * Address mapping for channels 0-3:
45 *
46 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
47 * | ... | | ... | | ... |
48 * | ... | | ... | | ... |
49 * | ... | | ... | | ... |
50 * P7 ... P0 A7 ... A0 A7 ... A0
51 * | Page | Addr MSB | Addr LSB | (DMA registers)
52 *
53 * Address mapping for channels 5-7:
54 *
55 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
56 * | ... | \ \ ... \ \ \ ... \ \
57 * | ... | \ \ ... \ \ \ ... \ (not used)
58 * | ... | \ \ ... \ \ \ ... \
59 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
60 * | Page | Addr MSB | Addr LSB | (DMA registers)
61 *
62 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
63 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
64 * the hardware level, so odd-byte transfers aren't possible).
65 *
66 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
67 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
68 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
69 *
70 */
71
72#define MAX_DMA_CHANNELS 8
73
74/* The maximum address that we can perform a DMA transfer to on this platform */
75#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
76
77/* 8237 DMA controllers */
78#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
79#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
80
81/* DMA controller registers */
82#define DMA1_CMD_REG 0x08 /* command register (w) */
83#define DMA1_STAT_REG 0x08 /* status register (r) */
84#define DMA1_REQ_REG 0x09 /* request register (w) */
85#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
86#define DMA1_MODE_REG 0x0B /* mode register (w) */
87#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
88#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
89#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
90#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
91#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
92
93#define DMA2_CMD_REG 0xD0 /* command register (w) */
94#define DMA2_STAT_REG 0xD0 /* status register (r) */
95#define DMA2_REQ_REG 0xD2 /* request register (w) */
96#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
97#define DMA2_MODE_REG 0xD6 /* mode register (w) */
98#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
99#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
100#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
101#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
102#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
103
104#define DMA_ADDR_0 0x00 /* DMA address registers */
105#define DMA_ADDR_1 0x02
106#define DMA_ADDR_2 0x04
107#define DMA_ADDR_3 0x06
108#define DMA_ADDR_4 0xC0
109#define DMA_ADDR_5 0xC4
110#define DMA_ADDR_6 0xC8
111#define DMA_ADDR_7 0xCC
112
113#define DMA_CNT_0 0x01 /* DMA count registers */
114#define DMA_CNT_1 0x03
115#define DMA_CNT_2 0x05
116#define DMA_CNT_3 0x07
117#define DMA_CNT_4 0xC2
118#define DMA_CNT_5 0xC6
119#define DMA_CNT_6 0xCA
120#define DMA_CNT_7 0xCE
121
122#define DMA_PAGE_0 0x87 /* DMA page registers */
123#define DMA_PAGE_1 0x83
124#define DMA_PAGE_2 0x81
125#define DMA_PAGE_3 0x82
126#define DMA_PAGE_5 0x8B
127#define DMA_PAGE_6 0x89
128#define DMA_PAGE_7 0x8A
129
130#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
131#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
132#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
133
134#define DMA_AUTOINIT 0x10
135
136
137extern spinlock_t dma_spin_lock;
138
139static __inline__ unsigned long claim_dma_lock(void)
140{
141 unsigned long flags;
142 spin_lock_irqsave(&dma_spin_lock, flags);
143 return flags;
144}
145
146static __inline__ void release_dma_lock(unsigned long flags)
147{
148 spin_unlock_irqrestore(&dma_spin_lock, flags);
149}
150
151/* enable/disable a specific DMA channel */
152static __inline__ void enable_dma(unsigned int dmanr)
153{
154 if (dmanr<=3)
155 dma_outb(dmanr, DMA1_MASK_REG);
156 else
157 dma_outb(dmanr & 3, DMA2_MASK_REG);
158}
159
160static __inline__ void disable_dma(unsigned int dmanr)
161{
162 if (dmanr<=3)
163 dma_outb(dmanr | 4, DMA1_MASK_REG);
164 else
165 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
166}
167
168/* Clear the 'DMA Pointer Flip Flop'.
169 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
170 * Use this once to initialize the FF to a known state.
171 * After that, keep track of it. :-)
172 * --- In order to do that, the DMA routines below should ---
173 * --- only be used while holding the DMA lock ! ---
174 */
175static __inline__ void clear_dma_ff(unsigned int dmanr)
176{
177 if (dmanr<=3)
178 dma_outb(0, DMA1_CLEAR_FF_REG);
179 else
180 dma_outb(0, DMA2_CLEAR_FF_REG);
181}
182
183/* set mode (above) for a specific DMA channel */
184static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
185{
186 if (dmanr<=3)
187 dma_outb(mode | dmanr, DMA1_MODE_REG);
188 else
189 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
190}
191
192/* Set only the page register bits of the transfer address.
193 * This is used for successive transfers when we know the contents of
194 * the lower 16 bits of the DMA current address register, but a 64k boundary
195 * may have been crossed.
196 */
197static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
198{
199 switch(dmanr) {
200 case 0:
201 dma_outb( pagenr & 0xff, DMA_PAGE_0);
202 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
203 break;
204 case 1:
205 dma_outb( pagenr & 0xff, DMA_PAGE_1);
206 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
207 break;
208 case 2:
209 dma_outb( pagenr & 0xff, DMA_PAGE_2);
210 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
211 break;
212 case 3:
213 dma_outb( pagenr & 0xff, DMA_PAGE_3);
214 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
215 break;
216 case 5:
217 dma_outb( pagenr & 0xfe, DMA_PAGE_5);
218 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
219 break;
220 case 6:
221 dma_outb( pagenr & 0xfe, DMA_PAGE_6);
222 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
223 break;
224 case 7:
225 dma_outb( pagenr & 0xfe, DMA_PAGE_7);
226 dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
227 break;
228 }
229}
230
231
232/* Set transfer address & page bits for specific DMA channel.
233 * Assumes dma flipflop is clear.
234 */
235static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
236{
237 set_dma_page(dmanr, a>>16);
238 if (dmanr <= 3) {
239 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
240 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
241 } else {
242 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
243 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
244 }
245}
246
247
248/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
249 * a specific DMA channel.
250 * You must ensure the parameters are valid.
251 * NOTE: from a manual: "the number of transfers is one more
252 * than the initial word count"! This is taken into account.
253 * Assumes dma flip-flop is clear.
254 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
255 */
256static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
257{
258 count--;
259 if (dmanr <= 3) {
260 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
261 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
262 } else {
263 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
264 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
265 }
266}
267
268
269/* Get DMA residue count. After a DMA transfer, this
270 * should return zero. Reading this while a DMA transfer is
271 * still in progress will return unpredictable results.
272 * If called before the channel has been used, it may return 1.
273 * Otherwise, it returns the number of _bytes_ left to transfer.
274 *
275 * Assumes DMA flip-flop is clear.
276 */
277static __inline__ int get_dma_residue(unsigned int dmanr)
278{
279 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
280 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
281
282 /* using short to get 16-bit wrap around */
283 unsigned short count;
284
285 count = 1 + dma_inb(io_port);
286 count += dma_inb(io_port) << 8;
287 return (dmanr<=3)? count : (count<<1);
288}
289
290
291/* These are in kernel/dma.c: */
292extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
293extern void free_dma(unsigned int dmanr); /* release it again */
294
295/* From PCI */
296
297#ifdef CONFIG_PCI
298extern int isa_dma_bridge_buggy;
299#else
300#define isa_dma_bridge_buggy (0)
301#endif
302
303#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2d..000000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-sh/mpc1211/io.h
3 *
4 * Copyright 2001 Saito.K & Jeanne
5 *
6 * IO functions for an Interface MPC-1211
7 */
8
9#ifndef _ASM_SH_IO_MPC1211_H
10#define _ASM_SH_IO_MPC1211_H
11
12#include <linux/time.h>
13
14extern int mpc1211_irq_demux(int irq);
15
16extern void init_mpc1211_IRQ(void);
17extern void heartbeat_mpc1211(void);
18
19extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
20extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
21
22#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4c..000000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * MPC1211 specific keybord definitions
3 * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
4 * created 3 Nov 1996 by Geert Uytterhoeven.
5 */
6
7#ifdef __KERNEL__
8
9#include <linux/kernel.h>
10#include <linux/ioport.h>
11#include <linux/kd.h>
12#include <linux/pm.h>
13#include <asm/io.h>
14
15#define KEYBOARD_IRQ 1
16#define DISABLE_KBD_DURING_INTERRUPTS 0
17
18extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
19extern int pckbd_getkeycode(unsigned int scancode);
20extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
21 char raw_mode);
22extern char pckbd_unexpected_up(unsigned char keycode);
23extern void pckbd_leds(unsigned char leds);
24extern void pckbd_init_hw(void);
25extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
26extern pm_callback pm_kbd_request_override;
27
28#define kbd_setkeycode pckbd_setkeycode
29#define kbd_getkeycode pckbd_getkeycode
30#define kbd_translate pckbd_translate
31#define kbd_unexpected_up pckbd_unexpected_up
32#define kbd_leds pckbd_leds
33#define kbd_init_hw pckbd_init_hw
34
35/* resource allocation */
36#define kbd_request_region()
37#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
38 "keyboard", NULL)
39
40/* How to access the keyboard macros on this platform. */
41#define kbd_read_input() inb(KBD_DATA_REG)
42#define kbd_read_status() inb(KBD_STATUS_REG)
43#define kbd_write_output(val) outb(val, KBD_DATA_REG)
44#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
45
46/* Some stoneage hardware needs delays after some operations. */
47#define kbd_pause() do { } while(0)
48
49/*
50 * Machine specific bits for the PS/2 driver
51 */
52
53#define AUX_IRQ 12
54
55#define aux_request_irq(hand, dev_id) \
56 request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
57
58#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
59
60#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3b..000000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
1#ifndef __ASM_SH_M1543C_H
2#define __ASM_SH_M1543C_H
3
4/*
5 * linux/include/asm-sh/m1543c.h
6 * Copyright (C) 2001 Nobuhiro Sakawa
7 * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
8 *
9 * from
10 *
11 * linux/include/asm-sh/smc37c93x.h
12 *
13 * Copyright (C) 2000 Kazumoto Kojima
14 *
15 * SMSC 37C93x Super IO Chip support
16 */
17
18/* Default base I/O address */
19#define FDC_PRIMARY_BASE 0x3f0
20#define IDE1_PRIMARY_BASE 0x1f0
21#define IDE1_SECONDARY_BASE 0x170
22#define PARPORT_PRIMARY_BASE 0x378
23#define COM1_PRIMARY_BASE 0x2f8
24#define COM2_PRIMARY_BASE 0x3f8
25#define COM3_PRIMARY_BASE 0x3e8
26#define RTC_PRIMARY_BASE 0x070
27#define KBC_PRIMARY_BASE 0x060
28#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
29#define I8259_M_CR 0x20
30#define I8259_M_MR 0x21
31#define I8259_S_CR 0xa0
32#define I8259_S_MR 0xa1
33
34/* Logical device number */
35#define LDN_FDC 0
36#define LDN_IDE1 1
37#define LDN_IDE2 2
38#define LDN_PARPORT 3
39#define LDN_COM1 4
40#define LDN_COM2 5
41#define LDN_COM3 11
42#define LDN_RTC 6
43#define LDN_KBC 7
44
45/* Configuration port and key */
46#define CONFIG_PORT 0x3f0
47#define INDEX_PORT CONFIG_PORT
48#define DATA_PORT 0x3f1
49#define CONFIG_ENTER1 0x51
50#define CONFIG_ENTER2 0x23
51#define CONFIG_EXIT 0xbb
52
53/* Configuration index */
54#define CURRENT_LDN_INDEX 0x07
55#define POWER_CONTROL_INDEX 0x22
56#define ACTIVATE_INDEX 0x30
57#define IO_BASE_HI_INDEX 0x60
58#define IO_BASE_LO_INDEX 0x61
59#define IRQ_SELECT_INDEX 0x70
60#define PS2_IRQ_INDEX 0x72
61#define DMA_SELECT_INDEX 0x74
62
63/* UART stuff. Only for debugging. */
64/* UART Register */
65
66#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
67#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
68#define UART_IER 0x2 /* Interrupt Enable Register */
69#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
70#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
71#define UART_LCR 0x6 /* Line Control Register */
72#define UART_MCR 0x8 /* MODEM Control Register */
73#define UART_LSR 0xa /* Line Status Register */
74#define UART_MSR 0xc /* MODEM Status Register */
75#define UART_SCR 0xe /* Scratch Register */
76#define UART_DLL 0x0 /* Divisor Latch (LS) */
77#define UART_DLM 0x2 /* Divisor Latch (MS) */
78
79#ifndef __ASSEMBLY__
80typedef struct uart_reg {
81 volatile __u16 rbr;
82 volatile __u16 ier;
83 volatile __u16 iir;
84 volatile __u16 lcr;
85 volatile __u16 mcr;
86 volatile __u16 lsr;
87 volatile __u16 msr;
88 volatile __u16 scr;
89} uart_reg;
90#endif /* ! __ASSEMBLY__ */
91
92/* Alias for Write Only Register */
93
94#define thr rbr
95#define tcr iir
96
97/* Alias for Divisor Latch Register */
98
99#define dll rbr
100#define dlm ier
101#define fcr iir
102
103/* Interrupt Enable Register */
104
105#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
106#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
107#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
108#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
109
110/* Interrupt Ident Register */
111
112#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
113#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
114#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
115#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
116#define IIR_FIFO 0xc000 /* FIFOs enabled */
117
118/* FIFO Control Register */
119
120#define FCR_FEN 0x0100 /* FIFO enable */
121#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
122#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
123#define FCR_DMA 0x0800 /* DMA mode select */
124#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
125#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
126
127/* Line Control Register */
128
129#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
130#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
131#define LCR_STB 0x0400 /* Number of Stop Bits */
132#define LCR_PEN 0x0800 /* Parity Enable */
133#define LCR_EPS 0x1000 /* Even Parity Select */
134#define LCR_SP 0x2000 /* Stick Parity */
135#define LCR_SB 0x4000 /* Set Break */
136#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
137
138/* MODEM Control Register */
139
140#define MCR_DTR 0x0100 /* Data Terminal Ready */
141#define MCR_RTS 0x0200 /* Request to Send */
142#define MCR_OUT1 0x0400 /* Out 1 */
143#define MCR_IRQEN 0x0800 /* IRQ Enable */
144#define MCR_LOOP 0x1000 /* Loop */
145
146/* Line Status Register */
147
148#define LSR_DR 0x0100 /* Data Ready */
149#define LSR_OE 0x0200 /* Overrun Error */
150#define LSR_PE 0x0400 /* Parity Error */
151#define LSR_FE 0x0800 /* Framing Error */
152#define LSR_BI 0x1000 /* Break Interrupt */
153#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
154#define LSR_TEMT 0x4000 /* Transmitter Empty */
155#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
156
157/* MODEM Status Register */
158
159#define MSR_DCTS 0x0100 /* Delta Clear to Send */
160#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
161#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
162#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
163#define MSR_CTS 0x1000 /* Clear to Send */
164#define MSR_DSR 0x2000 /* Data Set Ready */
165#define MSR_RI 0x4000 /* Ring Indicator */
166#define MSR_DCD 0x8000 /* Data Carrier Detect */
167
168/* Baud Rate Divisor */
169
170#define UART_CLK (1843200) /* 1.8432 MHz */
171#define UART_BAUD(x) (UART_CLK / (16 * (x)))
172
173/* RTC register definition */
174#define RTC_SECONDS 0
175#define RTC_SECONDS_ALARM 1
176#define RTC_MINUTES 2
177#define RTC_MINUTES_ALARM 3
178#define RTC_HOURS 4
179#define RTC_HOURS_ALARM 5
180#define RTC_DAY_OF_WEEK 6
181#define RTC_DAY_OF_MONTH 7
182#define RTC_MONTH 8
183#define RTC_YEAR 9
184#define RTC_FREQ_SELECT 10
185# define RTC_UIP 0x80
186# define RTC_DIV_CTL 0x70
187/* This RTC can work under 32.768KHz clock only. */
188# define RTC_OSC_ENABLE 0x20
189# define RTC_OSC_DISABLE 0x00
190#define RTC_CONTROL 11
191# define RTC_SET 0x80
192# define RTC_PIE 0x40
193# define RTC_AIE 0x20
194# define RTC_UIE 0x10
195# define RTC_SQWE 0x08
196# define RTC_DM_BINARY 0x04
197# define RTC_24H 0x02
198# define RTC_DST_EN 0x01
199
200#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd78..000000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
1/*
2 * MPC1211 uses PC/AT style RTC definitions.
3 */
4#include <asm-x86/mc146818rtc_32.h>
5
6
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e01..000000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
1#ifndef __ASM_SH_MPC1211_H
2#define __ASM_SH_MPC1211_H
3
4/*
5 * linux/include/asm-sh/mpc1211.h
6 *
7 * Copyright (C) 2001 Saito.K & Jeanne
8 *
9 * Interface MPC-1211 support
10 */
11
12#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
13#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
14
15#define PCIPAR (0xa4000cf8) /* PCI Config address */
16#define PCIPDR (0xa4000cfc) /* PCI Config data */
17
18#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76a..000000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Low-Level PCI Support for MPC-1211
3 *
4 * (c) 2002 Saito.K & Jeanne
5 *
6 */
7
8#ifndef _PCI_MPC1211_H_
9#define _PCI_MPC1211_H_
10
11#include <linux/pci.h>
12
13/* set debug level 4=verbose...1=terse */
14//#define DEBUG_PCI 3
15#undef DEBUG_PCI
16
17#ifdef DEBUG_PCI
18#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
19#else
20#define PCIDBG(n, x...)
21#endif
22
23/* startup values */
24#define PCI_PROBE_BIOS 1
25#define PCI_PROBE_CONF1 2
26#define PCI_PROBE_CONF2 4
27#define PCI_NO_CHECKS 0x400
28#define PCI_ASSIGN_ROMS 0x1000
29#define PCI_BIOS_IRQ_SCAN 0x2000
30
31/* MPC-1211 Specific Values */
32#define PCIPAR (0xa4000cf8) /* PCI Config address */
33#define PCIPDR (0xa4000cfc) /* PCI Config data */
34
35#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
36#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
37
38#endif /* _PCI_MPC1211_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 08:20:13 -0400