sh: intc - remove redundant irq code for sh03, snapgear and titan

This patch removes redundant board specific interrupt code for boards
using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode"
aka IRLM.

Three boards are affected: sh03, snapgear and titan.

The right way to do this is to use cpu specific code provided by intc.
A nice side effect is that sh03 now compiles, board not BROKEN any more.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

3 files changed, 4 insertions, 22 deletions

diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 921ddec6ccf4..8f5bf98d053e 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -41,11 +41,6 @@ struct ipr_desc {
 
 void register_ipr_controller(struct ipr_desc *);
 
-/*
- * Enable individual interrupt mode for external IPR IRQs.
- */
-void __init ipr_irq_enable_irlm(void);
-
 typedef unsigned char intc_enum;
 
 struct intc_vect {
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index 4ff1eb900301..c39c785bba94 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -11,22 +11,13 @@
 
 #include <linux/time.h>
 
-#define INTC_IPRD       0xffd00010UL
-
 #define IRL0_IRQ        2
-#define IRL0_IPR_POS    3
 #define IRL0_PRIORITY   13
-
 #define IRL1_IRQ        5
-#define IRL1_IPR_POS    2
 #define IRL1_PRIORITY   10
-
 #define IRL2_IRQ        8
-#define IRL2_IPR_POS    1
 #define IRL2_PRIORITY   7
-
 #define IRL3_IRQ        11
-#define IRL3_IPR_POS    0
 #define IRL3_PRIORITY   4
 
 void heartbeat_sh03(void);
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 3554e3a74e99..042d95f51c4d 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -19,20 +19,16 @@
  * is the interrupt :-)
  */
 
-#define IRL0_IRQ                2
-#define IRL0_IPR_POS    3
+#define IRL0_IRQ        2
 #define IRL0_PRIORITY   13
 
-#define IRL1_IRQ                5
-#define IRL1_IPR_POS    2
+#define IRL1_IRQ        5
 #define IRL1_PRIORITY   10
 
-#define IRL2_IRQ                8
-#define IRL2_IPR_POS    1
+#define IRL2_IRQ        8
 #define IRL2_PRIORITY   7
 
-#define IRL3_IRQ                11
-#define IRL3_IPR_POS    0
+#define IRL3_IRQ        11
 #define IRL3_PRIORITY   4
 #endif