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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 02:59:17 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 02:59:17 -0400
commit5283ecb5ccbdb90d49fce6488d3944bba63a591c (patch)
treea58e20bd532fa5f933d099bb7b5dd0637b581d33 /include/asm-sh
parentd7c30c682a278abe1a52db83f69efec1a9d8f8c2 (diff)
sh: Add support for R7780RP and R7780MP boards.
This adds support for the Renesas SH7780 development boards, R7780RP and R7780MP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h3
-rw-r--r--include/asm-sh/cpu-sh4/dma-sh7780.h39
-rw-r--r--include/asm-sh/cpu-sh4/dma.h11
-rw-r--r--include/asm-sh/hs7751rvoip/hs7751rvoip.h2
-rw-r--r--include/asm-sh/irq-sh7780.h5
-rw-r--r--include/asm-sh/irq.h2
-rw-r--r--include/asm-sh/landisk/iodata_landisk.h2
-rw-r--r--include/asm-sh/r7780rp/ide.h8
-rw-r--r--include/asm-sh/r7780rp/r7780rp.h177
-rw-r--r--include/asm-sh/rts7751r2d/rts7751r2d.h2
10 files changed, 236 insertions, 15 deletions
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
index 727634d886ce..bb2e1b03060c 100644
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -22,5 +22,8 @@
22#define P4SEG_TLB_DATA 0xf7000000 22#define P4SEG_TLB_DATA 0xf7000000
23#define P4SEG_REG_BASE 0xff000000 23#define P4SEG_REG_BASE 0xff000000
24 24
25#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
26#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
27
25#endif /* __ASM_CPU_SH4_ADDRSPACE_H */ 28#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
26 29
diff --git a/include/asm-sh/cpu-sh4/dma-sh7780.h b/include/asm-sh/cpu-sh4/dma-sh7780.h
new file mode 100644
index 000000000000..6c90d28331b2
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma-sh7780.h
@@ -0,0 +1,39 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int __attribute__ ((used)) ts_shift[] = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index 0dfe61f14802..3e4b3e6d80c0 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,11 +1,17 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
4#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
5#define SH_DMAC_BASE 0xfc808020 7#define SH_DMAC_BASE 0xfc808020
8
9#define CHCR_TS_MASK 0x18
10#define CHCR_TS_SHIFT 3
11
12#include <asm/cpu/dma-sh7780.h>
6#else 13#else
7#define SH_DMAC_BASE 0xffa00000 14#define SH_DMAC_BASE 0xffa00000
8#endif
9 15
10/* Definitions for the SuperH DMAC */ 16/* Definitions for the SuperH DMAC */
11#define TM_BURST 0x0000080 17#define TM_BURST 0x0000080
@@ -19,8 +25,6 @@
19 25
20#define DMAOR_COD 0x00000008 26#define DMAOR_COD 0x00000008
21 27
22#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
23
24/* 28/*
25 * The SuperH DMAC supports a number of transmit sizes, we list them here, 29 * The SuperH DMAC supports a number of transmit sizes, we list them here,
26 * with their respective values as they appear in the CHCR registers. 30 * with their respective values as they appear in the CHCR registers.
@@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = {
45 [XMIT_SZ_32BIT] = 2, 49 [XMIT_SZ_32BIT] = 2,
46 [XMIT_SZ_256BIT] = 5, 50 [XMIT_SZ_256BIT] = 5,
47}; 51};
52#endif
48 53
49#endif /* __ASM_CPU_SH4_DMA_H */ 54#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
index 69faf0171473..c4cff9d33927 100644
--- a/include/asm-sh/hs7751rvoip/hs7751rvoip.h
+++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
@@ -19,8 +19,6 @@
19#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */ 19#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
20#define PA_VERREG 0xa4000014 /* FPGA Version Register */ 20#define PA_VERREG 0xa4000014 /* FPGA Version Register */
21 21
22#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
23#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
24#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 22#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
25 23
26#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 24#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
index 7f90315cd830..895c5780e454 100644
--- a/include/asm-sh/irq-sh7780.h
+++ b/include/asm-sh/irq-sh7780.h
@@ -145,11 +145,6 @@
145#define TMU_CH5_IPR_POS 1 145#define TMU_CH5_IPR_POS 1
146#define TMU_CH5_PRIORITY 2 146#define TMU_CH5_PRIORITY 2
147 147
148#define RTC_IRQ 22
149#define RTC_IPR_ADDR INTC_INT2PRI1
150#define RTC_IPR_POS 0
151#define RTC_PRIORITY TIMER_PRIORITY
152
153/* SCIF0 */ 148/* SCIF0 */
154#define SCIF0_ERI_IRQ 40 149#define SCIF0_ERI_IRQ 40
155#define SCIF0_RXI_IRQ 41 150#define SCIF0_RXI_IRQ 41
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 611e67cd0627..7e8455b1cb44 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq);
577#define NR_INTC2_IRQS 64 577#define NR_INTC2_IRQS 64
578#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 578#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
579#define INTC2_BASE 0xffd40000 579#define INTC2_BASE 0xffd40000
580#define INTC2_FIRST_IRQ 22 580#define INTC2_FIRST_IRQ 21
581#define INTC2_INTMSK_OFFSET (0x38) 581#define INTC2_INTMSK_OFFSET (0x38)
582#define INTC2_INTMSKCLR_OFFSET (0x3c) 582#define INTC2_INTMSKCLR_OFFSET (0x3c)
583#define NR_INTC2_IRQS 60 583#define NR_INTC2_IRQS 60
diff --git a/include/asm-sh/landisk/iodata_landisk.h b/include/asm-sh/landisk/iodata_landisk.h
index 9db3cdfe6776..c74d3c73f377 100644
--- a/include/asm-sh/landisk/iodata_landisk.h
+++ b/include/asm-sh/landisk/iodata_landisk.h
@@ -22,8 +22,6 @@
22/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */ 22/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
23#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */ 23#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
24 24
25#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
26#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
27#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */ 25#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
28#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */ 26#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
29#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */ 27#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
diff --git a/include/asm-sh/r7780rp/ide.h b/include/asm-sh/r7780rp/ide.h
new file mode 100644
index 000000000000..a1ed78e0f617
--- /dev/null
+++ b/include/asm-sh/r7780rp/ide.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_SH_R7780RP_IDE_H
2#define __ASM_SH_R7780RP_IDE_H
3
4/* Nothing to see here.. */
5#include <asm/mach/r7780rp.h>
6
7#endif /* __ASM_SH_R7780RP_IDE_H */
8
diff --git a/include/asm-sh/r7780rp/r7780rp.h b/include/asm-sh/r7780rp/r7780rp.h
new file mode 100644
index 000000000000..f95d9dba31a2
--- /dev/null
+++ b/include/asm-sh/r7780rp/r7780rp.h
@@ -0,0 +1,177 @@
1#ifndef __ASM_SH_RENESAS_R7780RP_H
2#define __ASM_SH_RENESAS_R7780RP_H
3
4/*
5 * linux/include/asm-sh/r7780rp.h
6 *
7 * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
8 *
9 * Renesas Solutions Highlander R7780RP support
10 */
11
12/* Box specific addresses. */
13#if defined(CONFIG_SH_R7780MP)
14#define PA_BCR 0xa4000000 /* FPGA */
15#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
16#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
17#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
18#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
19#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
20#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
21#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
22#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
23#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
24#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
25#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
26#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
27#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
28#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
29#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
30#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
31#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
32#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
33#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
34#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
35#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
36#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
37#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
38#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
39#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
40#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
41#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
42#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
43#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
44#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
45#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
46#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
47#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
48#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
49#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
50#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
51#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
52#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
53#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
54#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
55#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
56#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
57#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
58#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
59#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
60#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
61#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
62#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
63#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
64#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
65#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
66#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
67#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
68#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
69#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
70#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
71#define PA_PMR (PA_BCR+0x0900) /* */
72
73#define PA_AX88796L 0xa4100400 /* AX88796L Area */
74#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
75#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
76#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
77#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
78#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
79
80#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
81
82#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
83#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
84#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
85#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
86#define IRQ_CFCARD 1 /* CF Card IRQ */
87// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
88#define IRQ_TP 2 /* Touch Panel IRQ */
89#define IRQ_SCI1 3 /* SCI1 IRQ */
90#define IRQ_SCI0 4 /* SCI0 IRQ */
91#define IRQ_2SERIAL 5 /* Serial IRQ */
92#define IRQ_RTC 6 /* RTC A / B IRQ */
93#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
94#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
95#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
96#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
97#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
98#define IRQ_ONETH 13 /* On board Ethernet IRQ */
99#define IRQ_PSW 14 /* Push Switch IRQ */
100
101#else /* R7780RP */
102
103#define PA_BCR 0xa5000000 /* FPGA */
104#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
105#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
106#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
107#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
108#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
109#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
110#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
111#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
112#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
113#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
114#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
115#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
116#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
117#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
118#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
119#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
120#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
121#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
122#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
123#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
124#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
125#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
126#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
127#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
128#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
129#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
130#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
131#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
132#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
133#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
134#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
135#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
136#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
137#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
138#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
139#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
140#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
141#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
142#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
143#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
144#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
145#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
146
147#define PA_AX88796L 0xa5800400 /* AX88796L Area */
148#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
149#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
150#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
151#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
152#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
153
154#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
155
156#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
157#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
158#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
159#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
160#define IRQ_CFCARD 4 /* CF Card IRQ */
161#define IRQ_CFINST 5 /* CF Card Insert IRQ */
162#define IRQ_M66596 6 /* M66596 IRQ */
163#define IRQ_SDCARD 7 /* SD Card IRQ */
164#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
165#define IRQ_SCI 9 /* SCI IRQ */
166#define IRQ_2SERIAL 10 /* Serial IRQ */
167#define IRQ_EXTENTION 11 /* EXTn IRQ */
168#define IRQ_ONETH 12 /* On board Ethernet IRQ */
169#define IRQ_PSW 13 /* Push Switch IRQ */
170#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
171
172#endif /* CONFIG_SH_R7780MP */
173
174#define __IO_PREFIX r7780rp
175#include <asm/io_generic.h>
176
177#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/rts7751r2d/rts7751r2d.h b/include/asm-sh/rts7751r2d/rts7751r2d.h
index 4e09ba597e9a..b112ae221fd1 100644
--- a/include/asm-sh/rts7751r2d/rts7751r2d.h
+++ b/include/asm-sh/rts7751r2d/rts7751r2d.h
@@ -41,8 +41,6 @@
41 41
42#define PA_AX88796L 0xaa000400 /* AX88796L Area */ 42#define PA_AX88796L 0xaa000400 /* AX88796L Area */
43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ 43#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
44#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
45#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
46#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ 44#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
47#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ 45#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
48 46