diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-13 12:49:04 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-13 12:49:04 -0400 |
commit | dcf397f037f52add9945eced57ca300ab6a4413c (patch) | |
tree | e78767d164589e9097a54bf564b072fb01f80820 /include/asm-sh | |
parent | 6faf035cf9fdd8283c2b2b2c34b76b5445ec6fc4 (diff) | |
parent | 68ee0f9c98a42e36f9eab29155b2bb0e7e409ac6 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (124 commits)
sh: allow building for both r2d boards in same binary.
sh: fix r2d board detection
sh: Discard .exit.text/.exit.data at runtime.
sh: Fix up some section alignments in linker script.
sh: Fix SH-4 DMAC CHCR masking.
sh: Rip out left-over nommu cond syscall cruft.
sh: Make kgdb i-cache flushing less inept.
sh: kgdb section mismatches and tidying.
sh: cleanup struct irqaction initializers.
sh: early_printk tidying.
video: pvr2fb: Add TV (RGB) support to Dreamcast PVR driver.
sh: Conditionalize gUSA support.
sh: Follow gUSA preempt changes in __switch_to().
sh: Tidy up gUSA preempt handling.
sh: __copy_user() optimizations for small copies.
sh: clkfwk: Support multi-level clock propagation.
sh: Fix URAM start address on SH7785.
sh: Use boot_cpu_data for CPU probe.
sh: Support extended mode TLB on SH-X3.
sh: Bump MAX_ACTIVE_REGIONS for SH7785.
...
Diffstat (limited to 'include/asm-sh')
33 files changed, 705 insertions, 270 deletions
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h index 07f62ec9ff0c..aa558da08471 100644 --- a/include/asm-sh/cacheflush.h +++ b/include/asm-sh/cacheflush.h | |||
@@ -1,16 +1,47 @@ | |||
1 | #ifndef __ASM_SH_CACHEFLUSH_H | 1 | #ifndef __ASM_SH_CACHEFLUSH_H |
2 | #define __ASM_SH_CACHEFLUSH_H | 2 | #define __ASM_SH_CACHEFLUSH_H |
3 | |||
3 | #ifdef __KERNEL__ | 4 | #ifdef __KERNEL__ |
4 | 5 | ||
5 | #include <linux/mm.h> | 6 | #ifdef CONFIG_CACHE_OFF |
7 | /* | ||
8 | * Nothing to do when the cache is disabled, initial flush and explicit | ||
9 | * disabling is handled at CPU init time. | ||
10 | * | ||
11 | * See arch/sh/kernel/cpu/init.c:cache_init(). | ||
12 | */ | ||
13 | #define p3_cache_init() do { } while (0) | ||
14 | #define flush_cache_all() do { } while (0) | ||
15 | #define flush_cache_mm(mm) do { } while (0) | ||
16 | #define flush_cache_dup_mm(mm) do { } while (0) | ||
17 | #define flush_cache_range(vma, start, end) do { } while (0) | ||
18 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | ||
19 | #define flush_dcache_page(page) do { } while (0) | ||
20 | #define flush_icache_range(start, end) do { } while (0) | ||
21 | #define flush_icache_page(vma,pg) do { } while (0) | ||
22 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
23 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
24 | #define flush_cache_sigtramp(vaddr) do { } while (0) | ||
25 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
26 | #define __flush_wback_region(start, size) do { (void)(start); } while (0) | ||
27 | #define __flush_purge_region(start, size) do { (void)(start); } while (0) | ||
28 | #define __flush_invalidate_region(start, size) do { (void)(start); } while (0) | ||
29 | #else | ||
6 | #include <asm/cpu/cacheflush.h> | 30 | #include <asm/cpu/cacheflush.h> |
7 | 31 | ||
32 | /* | ||
33 | * Consistent DMA requires that the __flush_xxx() primitives must be set | ||
34 | * for any of the enabled non-coherent caches (most of the UP CPUs), | ||
35 | * regardless of PIPT or VIPT cache configurations. | ||
36 | */ | ||
37 | |||
8 | /* Flush (write-back only) a region (smaller than a page) */ | 38 | /* Flush (write-back only) a region (smaller than a page) */ |
9 | extern void __flush_wback_region(void *start, int size); | 39 | extern void __flush_wback_region(void *start, int size); |
10 | /* Flush (write-back & invalidate) a region (smaller than a page) */ | 40 | /* Flush (write-back & invalidate) a region (smaller than a page) */ |
11 | extern void __flush_purge_region(void *start, int size); | 41 | extern void __flush_purge_region(void *start, int size); |
12 | /* Flush (invalidate only) a region (smaller than a page) */ | 42 | /* Flush (invalidate only) a region (smaller than a page) */ |
13 | extern void __flush_invalidate_region(void *start, int size); | 43 | extern void __flush_invalidate_region(void *start, int size); |
44 | #endif | ||
14 | 45 | ||
15 | #define flush_cache_vmap(start, end) flush_cache_all() | 46 | #define flush_cache_vmap(start, end) flush_cache_all() |
16 | #define flush_cache_vunmap(start, end) flush_cache_all() | 47 | #define flush_cache_vunmap(start, end) flush_cache_all() |
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h index ffe08d2813f9..255016fc91f0 100644 --- a/include/asm-sh/cpu-sh3/cache.h +++ b/include/asm-sh/cpu-sh3/cache.h | |||
@@ -26,7 +26,9 @@ | |||
26 | #define CCR_CACHE_ENABLE CCR_CACHE_CE | 26 | #define CCR_CACHE_ENABLE CCR_CACHE_CE |
27 | #define CCR_CACHE_INVALIDATE CCR_CACHE_CF | 27 | #define CCR_CACHE_INVALIDATE CCR_CACHE_CF |
28 | 28 | ||
29 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710) | 29 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
30 | defined(CONFIG_CPU_SUBTYPE_SH7710) || \ | ||
31 | defined(CONFIG_CPU_SUBTYPE_SH7720) | ||
30 | #define CCR3 0xa40000b4 | 32 | #define CCR3 0xa40000b4 |
31 | #define CCR_CACHE_16KB 0x00010000 | 33 | #define CCR_CACHE_16KB 0x00010000 |
32 | #define CCR_CACHE_32KB 0x00020000 | 34 | #define CCR_CACHE_32KB 0x00020000 |
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h index 3a66dc458023..54bfece328c2 100644 --- a/include/asm-sh/cpu-sh3/dma.h +++ b/include/asm-sh/cpu-sh3/dma.h | |||
@@ -1,7 +1,20 @@ | |||
1 | #ifndef __ASM_CPU_SH3_DMA_H | 1 | #ifndef __ASM_CPU_SH3_DMA_H |
2 | #define __ASM_CPU_SH3_DMA_H | 2 | #define __ASM_CPU_SH3_DMA_H |
3 | 3 | ||
4 | |||
5 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) | ||
6 | #define SH_DMAC_BASE 0xa4010020 | ||
7 | |||
8 | #define DMTE0_IRQ 48 | ||
9 | #define DMTE1_IRQ 49 | ||
10 | #define DMTE2_IRQ 50 | ||
11 | #define DMTE3_IRQ 51 | ||
12 | #define DMTE4_IRQ 76 | ||
13 | #define DMTE5_IRQ 77 | ||
14 | |||
15 | #else | ||
4 | #define SH_DMAC_BASE 0xa4000020 | 16 | #define SH_DMAC_BASE 0xa4000020 |
17 | #endif | ||
5 | 18 | ||
6 | /* Definitions for the SuperH DMAC */ | 19 | /* Definitions for the SuperH DMAC */ |
7 | #define TM_BURST 0x00000020 | 20 | #define TM_BURST 0x00000020 |
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h new file mode 100644 index 000000000000..48770c1c7bdf --- /dev/null +++ b/include/asm-sh/cpu-sh3/gpio.h | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * include/asm-sh/cpu-sh3/gpio.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Markus Brunner, Mark Jonas | ||
5 | * | ||
6 | * Addresses for the Pin Function Controller | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | #ifndef _CPU_SH3_GPIO_H | ||
13 | #define _CPU_SH3_GPIO_H | ||
14 | |||
15 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) | ||
16 | |||
17 | /* Control registers */ | ||
18 | #define PORT_PACR 0xA4050100UL | ||
19 | #define PORT_PBCR 0xA4050102UL | ||
20 | #define PORT_PCCR 0xA4050104UL | ||
21 | #define PORT_PDCR 0xA4050106UL | ||
22 | #define PORT_PECR 0xA4050108UL | ||
23 | #define PORT_PFCR 0xA405010AUL | ||
24 | #define PORT_PGCR 0xA405010CUL | ||
25 | #define PORT_PHCR 0xA405010EUL | ||
26 | #define PORT_PJCR 0xA4050110UL | ||
27 | #define PORT_PKCR 0xA4050112UL | ||
28 | #define PORT_PLCR 0xA4050114UL | ||
29 | #define PORT_PMCR 0xA4050116UL | ||
30 | #define PORT_PPCR 0xA4050118UL | ||
31 | #define PORT_PRCR 0xA405011AUL | ||
32 | #define PORT_PSCR 0xA405011CUL | ||
33 | #define PORT_PTCR 0xA405011EUL | ||
34 | #define PORT_PUCR 0xA4050120UL | ||
35 | #define PORT_PVCR 0xA4050122UL | ||
36 | |||
37 | /* Data registers */ | ||
38 | #define PORT_PADR 0xA4050140UL | ||
39 | /* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */ | ||
40 | #define PORT_PBDR 0xA4050142UL | ||
41 | #define PORT_PCDR 0xA4050144UL | ||
42 | #define PORT_PDDR 0xA4050146UL | ||
43 | #define PORT_PEDR 0xA4050148UL | ||
44 | #define PORT_PFDR 0xA405014AUL | ||
45 | #define PORT_PGDR 0xA405014CUL | ||
46 | #define PORT_PHDR 0xA405014EUL | ||
47 | #define PORT_PJDR 0xA4050150UL | ||
48 | #define PORT_PKDR 0xA4050152UL | ||
49 | #define PORT_PLDR 0xA4050154UL | ||
50 | #define PORT_PMDR 0xA4050156UL | ||
51 | #define PORT_PPDR 0xA4050158UL | ||
52 | #define PORT_PRDR 0xA405015AUL | ||
53 | #define PORT_PSDR 0xA405015CUL | ||
54 | #define PORT_PTDR 0xA405015EUL | ||
55 | #define PORT_PUDR 0xA4050160UL | ||
56 | #define PORT_PVDR 0xA4050162UL | ||
57 | |||
58 | /* Pin Select Registers */ | ||
59 | #define PORT_PSELA 0xA4050124UL | ||
60 | #define PORT_PSELB 0xA4050126UL | ||
61 | #define PORT_PSELC 0xA4050128UL | ||
62 | #define PORT_PSELD 0xA405012AUL | ||
63 | |||
64 | #endif | ||
65 | |||
66 | #endif | ||
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h index b20786d42d09..16c2d63b7e39 100644 --- a/include/asm-sh/cpu-sh3/mmu_context.h +++ b/include/asm-sh/cpu-sh3/mmu_context.h | |||
@@ -27,12 +27,13 @@ | |||
27 | #define TRA 0xffffffd0 | 27 | #define TRA 0xffffffd0 |
28 | #define EXPEVT 0xffffffd4 | 28 | #define EXPEVT 0xffffffd4 |
29 | 29 | ||
30 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 30 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | ||
32 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 31 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
33 | defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 32 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
33 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | ||
34 | defined(CONFIG_CPU_SUBTYPE_SH7710) || \ | ||
34 | defined(CONFIG_CPU_SUBTYPE_SH7712) || \ | 35 | defined(CONFIG_CPU_SUBTYPE_SH7712) || \ |
35 | defined(CONFIG_CPU_SUBTYPE_SH7710) | 36 | defined(CONFIG_CPU_SUBTYPE_SH7720) |
36 | #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ | 37 | #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ |
37 | #else | 38 | #else |
38 | #define INTEVT 0xffffffd8 | 39 | #define INTEVT 0xffffffd8 |
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index b6c2020a2ad3..3880ce047fe0 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h | |||
@@ -23,11 +23,13 @@ | |||
23 | * --------------------------------------------------------------------------- | 23 | * --------------------------------------------------------------------------- |
24 | */ | 24 | */ |
25 | 25 | ||
26 | #if !defined(CONFIG_CPU_SUBTYPE_SH7727) | 26 | #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ |
27 | !defined(CONFIG_CPU_SUBTYPE_SH7727) | ||
27 | #define TMU_TOCR 0xfffffe90 /* Byte access */ | 28 | #define TMU_TOCR 0xfffffe90 /* Byte access */ |
28 | #endif | 29 | #endif |
29 | 30 | ||
30 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) | 31 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ |
32 | defined(CONFIG_CPU_SUBTYPE_SH7720) | ||
31 | #define TMU_012_TSTR 0xa412fe92 /* Byte access */ | 33 | #define TMU_012_TSTR 0xa412fe92 /* Byte access */ |
32 | 34 | ||
33 | #define TMU0_TCOR 0xa412fe94 /* Long access */ | 35 | #define TMU0_TCOR 0xa412fe94 /* Long access */ |
@@ -56,7 +58,8 @@ | |||
56 | #define TMU2_TCOR 0xfffffeac /* Long access */ | 58 | #define TMU2_TCOR 0xfffffeac /* Long access */ |
57 | #define TMU2_TCNT 0xfffffeb0 /* Long access */ | 59 | #define TMU2_TCNT 0xfffffeb0 /* Long access */ |
58 | #define TMU2_TCR 0xfffffeb4 /* Word access */ | 60 | #define TMU2_TCR 0xfffffeb4 /* Word access */ |
59 | #if !defined(CONFIG_CPU_SUBTYPE_SH7727) | 61 | #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ |
62 | !defined(CONFIG_CPU_SUBTYPE_SH7727) | ||
60 | #define TMU2_TCPR2 0xfffffeb8 /* Long access */ | 63 | #define TMU2_TCPR2 0xfffffeb8 /* Long access */ |
61 | #endif | 64 | #endif |
62 | #endif | 65 | #endif |
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h index 9d308cbe9b29..18467c574534 100644 --- a/include/asm-sh/cpu-sh3/ubc.h +++ b/include/asm-sh/cpu-sh3/ubc.h | |||
@@ -11,7 +11,8 @@ | |||
11 | #ifndef __ASM_CPU_SH3_UBC_H | 11 | #ifndef __ASM_CPU_SH3_UBC_H |
12 | #define __ASM_CPU_SH3_UBC_H | 12 | #define __ASM_CPU_SH3_UBC_H |
13 | 13 | ||
14 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) | 14 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ |
15 | defined(CONFIG_CPU_SUBTYPE_SH7720) | ||
15 | #define UBC_BARA 0xa4ffffb0 | 16 | #define UBC_BARA 0xa4ffffb0 |
16 | #define UBC_BAMRA 0xa4ffffb4 | 17 | #define UBC_BAMRA 0xa4ffffb4 |
17 | #define UBC_BBRA 0xa4ffffb8 | 18 | #define UBC_BBRA 0xa4ffffb8 |
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h index 36e26a964765..aaf71b018c28 100644 --- a/include/asm-sh/cpu-sh4/dma.h +++ b/include/asm-sh/cpu-sh4/dma.h | |||
@@ -31,7 +31,7 @@ | |||
31 | #define TS_32 0x00000030 | 31 | #define TS_32 0x00000030 |
32 | #define TS_64 0x00000000 | 32 | #define TS_64 0x00000000 |
33 | 33 | ||
34 | #define CHCR_TS_MASK 0x30 | 34 | #define CHCR_TS_MASK 0x70 |
35 | #define CHCR_TS_SHIFT 4 | 35 | #define CHCR_TS_SHIFT 4 |
36 | 36 | ||
37 | #define DMAOR_COD 0x00000008 | 37 | #define DMAOR_COD 0x00000008 |
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h index ff4c5fbbfaf0..979acddc0f8e 100644 --- a/include/asm-sh/cpu-sh4/mmu_context.h +++ b/include/asm-sh/cpu-sh4/mmu_context.h | |||
@@ -22,13 +22,21 @@ | |||
22 | #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 | 22 | #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 |
23 | #define MMU_PAGE_ASSOC_BIT 0x80 | 23 | #define MMU_PAGE_ASSOC_BIT 0x80 |
24 | 24 | ||
25 | #define MMU_NTLB_ENTRIES 64 /* for 7750 */ | 25 | #ifdef CONFIG_X2TLB |
26 | #define MMUCR_ME (1 << 7) | ||
27 | #else | ||
28 | #define MMUCR_ME (0) | ||
29 | #endif | ||
30 | |||
26 | #ifdef CONFIG_SH_STORE_QUEUES | 31 | #ifdef CONFIG_SH_STORE_QUEUES |
27 | #define MMU_CONTROL_INIT 0x05 /* SQMD=0, SV=0, TI=1, AT=1 */ | 32 | #define MMUCR_SQMD (1 << 9) |
28 | #else | 33 | #else |
29 | #define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ | 34 | #define MMUCR_SQMD (0) |
30 | #endif | 35 | #endif |
31 | 36 | ||
37 | #define MMU_NTLB_ENTRIES 64 | ||
38 | #define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME) | ||
39 | |||
32 | #define MMU_ITLB_DATA_ARRAY 0xF3000000 | 40 | #define MMU_ITLB_DATA_ARRAY 0xF3000000 |
33 | #define MMU_UTLB_DATA_ARRAY 0xF7000000 | 41 | #define MMU_UTLB_DATA_ARRAY 0xF7000000 |
34 | 42 | ||
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h index 4c75b70b6414..a65b02fd186e 100644 --- a/include/asm-sh/dma.h +++ b/include/asm-sh/dma.h | |||
@@ -152,14 +152,9 @@ extern struct dma_info *get_dma_info_by_name(const char *dmac_name); | |||
152 | extern int dma_extend(unsigned int chan, unsigned long op, void *param); | 152 | extern int dma_extend(unsigned int chan, unsigned long op, void *param); |
153 | extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); | 153 | extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist); |
154 | 154 | ||
155 | #ifdef CONFIG_SYSFS | ||
156 | /* arch/sh/drivers/dma/dma-sysfs.c */ | 155 | /* arch/sh/drivers/dma/dma-sysfs.c */ |
157 | extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); | 156 | extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *); |
158 | extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); | 157 | extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *); |
159 | #else | ||
160 | #define dma_create_sysfs_file(channel, info) do { } while (0) | ||
161 | #define dma_remove_sysfs_file(channel, info) do { } while (0) | ||
162 | #endif | ||
163 | 158 | ||
164 | #ifdef CONFIG_PCI | 159 | #ifdef CONFIG_PCI |
165 | extern int isa_dma_bridge_buggy; | 160 | extern int isa_dma_bridge_buggy; |
diff --git a/include/asm-sh/dreamcast/maple.h b/include/asm-sh/dreamcast/maple.h new file mode 100644 index 000000000000..51f6a87f1f11 --- /dev/null +++ b/include/asm-sh/dreamcast/maple.h | |||
@@ -0,0 +1,37 @@ | |||
1 | #ifndef __ASM_MAPLE_H | ||
2 | #define __ASM_MAPLE_H | ||
3 | |||
4 | #define MAPLE_PORTS 4 | ||
5 | #define MAPLE_PNP_INTERVAL HZ | ||
6 | #define MAPLE_MAXPACKETS 8 | ||
7 | #define MAPLE_DMA_ORDER 14 | ||
8 | #define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER) | ||
9 | #define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \ | ||
10 | MAPLE_DMA_ORDER - PAGE_SHIFT : 0) | ||
11 | |||
12 | /* Maple Bus registers */ | ||
13 | #define MAPLE_BASE 0xa05f6c00 | ||
14 | #define MAPLE_DMAADDR (MAPLE_BASE+0x04) | ||
15 | #define MAPLE_TRIGTYPE (MAPLE_BASE+0x10) | ||
16 | #define MAPLE_ENABLE (MAPLE_BASE+0x14) | ||
17 | #define MAPLE_STATE (MAPLE_BASE+0x18) | ||
18 | #define MAPLE_SPEED (MAPLE_BASE+0x80) | ||
19 | #define MAPLE_RESET (MAPLE_BASE+0x8c) | ||
20 | |||
21 | #define MAPLE_MAGIC 0x6155404f | ||
22 | #define MAPLE_2MBPS 0 | ||
23 | #define MAPLE_TIMEOUT(n) ((n)<<15) | ||
24 | |||
25 | /* Function codes */ | ||
26 | #define MAPLE_FUNC_CONTROLLER 0x001 | ||
27 | #define MAPLE_FUNC_MEMCARD 0x002 | ||
28 | #define MAPLE_FUNC_LCD 0x004 | ||
29 | #define MAPLE_FUNC_CLOCK 0x008 | ||
30 | #define MAPLE_FUNC_MICROPHONE 0x010 | ||
31 | #define MAPLE_FUNC_ARGUN 0x020 | ||
32 | #define MAPLE_FUNC_KEYBOARD 0x040 | ||
33 | #define MAPLE_FUNC_LIGHTGUN 0x080 | ||
34 | #define MAPLE_FUNC_PURUPURU 0x100 | ||
35 | #define MAPLE_FUNC_MOUSE 0x200 | ||
36 | |||
37 | #endif /* __ASM_MAPLE_H */ | ||
diff --git a/include/asm-sh/gpio.h b/include/asm-sh/gpio.h new file mode 100644 index 000000000000..9bb27e0f11a4 --- /dev/null +++ b/include/asm-sh/gpio.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * include/asm-sh/gpio.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Markus Brunner, Mark Jonas | ||
5 | * | ||
6 | * Addresses for the Pin Function Controller | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | #ifndef __ASM_SH_GPIO_H | ||
13 | #define __ASM_SH_GPIO_H | ||
14 | |||
15 | #if defined(CONFIG_CPU_SH3) | ||
16 | #include <asm/cpu/gpio.h> | ||
17 | #endif | ||
18 | |||
19 | #endif /* __ASM_SH_GPIO_H */ | ||
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index 4dd8592ca014..342ca55a266a 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h | |||
@@ -226,6 +226,7 @@ | |||
226 | #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) | 226 | #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) |
227 | 227 | ||
228 | #define HD64461_IRQBASE OFFCHIP_IRQ_BASE | 228 | #define HD64461_IRQBASE OFFCHIP_IRQ_BASE |
229 | #define OFFCHIP_IRQ_BASE 64 | ||
229 | #define HD64461_IRQ_NUM 16 | 230 | #define HD64461_IRQ_NUM 16 |
230 | 231 | ||
231 | #define HD64461_IRQ_UART (HD64461_IRQBASE+5) | 232 | #define HD64461_IRQ_UART (HD64461_IRQBASE+5) |
diff --git a/include/asm-sh/heartbeat.h b/include/asm-sh/heartbeat.h new file mode 100644 index 000000000000..724a43ed245e --- /dev/null +++ b/include/asm-sh/heartbeat.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifndef __ASM_SH_HEARTBEAT_H | ||
2 | #define __ASM_SH_HEARTBEAT_H | ||
3 | |||
4 | #include <linux/timer.h> | ||
5 | |||
6 | #define HEARTBEAT_INVERTED (1 << 0) | ||
7 | |||
8 | struct heartbeat_data { | ||
9 | void __iomem *base; | ||
10 | unsigned char *bit_pos; | ||
11 | unsigned int nr_bits; | ||
12 | struct timer_list timer; | ||
13 | unsigned int regsize; | ||
14 | unsigned long flags; | ||
15 | }; | ||
16 | |||
17 | #endif /* __ASM_SH_HEARTBEAT_H */ | ||
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 20d42959f52a..cb0b6c9f7020 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h | |||
@@ -6,24 +6,6 @@ | |||
6 | 6 | ||
7 | extern atomic_t irq_err_count; | 7 | extern atomic_t irq_err_count; |
8 | 8 | ||
9 | struct intc2_data { | ||
10 | unsigned short irq; | ||
11 | unsigned char ipr_offset, ipr_shift; | ||
12 | unsigned char msk_offset, msk_shift; | ||
13 | unsigned char priority; | ||
14 | }; | ||
15 | |||
16 | struct intc2_desc { | ||
17 | unsigned long prio_base; | ||
18 | unsigned long msk_base; | ||
19 | unsigned long mskclr_base; | ||
20 | struct intc2_data *intc2_data; | ||
21 | unsigned int nr_irqs; | ||
22 | struct irq_chip chip; | ||
23 | }; | ||
24 | |||
25 | void register_intc2_controller(struct intc2_desc *); | ||
26 | |||
27 | struct ipr_data { | 9 | struct ipr_data { |
28 | unsigned char irq; | 10 | unsigned char irq; |
29 | unsigned char ipr_idx; /* Index for the IPR registered */ | 11 | unsigned char ipr_idx; /* Index for the IPR registered */ |
@@ -41,11 +23,6 @@ struct ipr_desc { | |||
41 | 23 | ||
42 | void register_ipr_controller(struct ipr_desc *); | 24 | void register_ipr_controller(struct ipr_desc *); |
43 | 25 | ||
44 | /* | ||
45 | * Enable individual interrupt mode for external IPR IRQs. | ||
46 | */ | ||
47 | void __init ipr_irq_enable_irlm(void); | ||
48 | |||
49 | typedef unsigned char intc_enum; | 26 | typedef unsigned char intc_enum; |
50 | 27 | ||
51 | struct intc_vect { | 28 | struct intc_vect { |
@@ -54,6 +31,7 @@ struct intc_vect { | |||
54 | }; | 31 | }; |
55 | 32 | ||
56 | #define INTC_VECT(enum_id, vect) { enum_id, vect } | 33 | #define INTC_VECT(enum_id, vect) { enum_id, vect } |
34 | #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq)) | ||
57 | 35 | ||
58 | struct intc_prio { | 36 | struct intc_prio { |
59 | intc_enum enum_id; | 37 | intc_enum enum_id; |
@@ -64,19 +42,25 @@ struct intc_prio { | |||
64 | 42 | ||
65 | struct intc_group { | 43 | struct intc_group { |
66 | intc_enum enum_id; | 44 | intc_enum enum_id; |
67 | intc_enum *enum_ids; | 45 | intc_enum enum_ids[32]; |
68 | }; | 46 | }; |
69 | 47 | ||
70 | #define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } } | 48 | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } |
71 | 49 | ||
72 | struct intc_mask_reg { | 50 | struct intc_mask_reg { |
73 | unsigned long set_reg, clr_reg, reg_width; | 51 | unsigned long set_reg, clr_reg, reg_width; |
74 | intc_enum enum_ids[32]; | 52 | intc_enum enum_ids[32]; |
53 | #ifdef CONFIG_SMP | ||
54 | unsigned long smp; | ||
55 | #endif | ||
75 | }; | 56 | }; |
76 | 57 | ||
77 | struct intc_prio_reg { | 58 | struct intc_prio_reg { |
78 | unsigned long reg, reg_width, field_width; | 59 | unsigned long set_reg, clr_reg, reg_width, field_width; |
79 | intc_enum enum_ids[16]; | 60 | intc_enum enum_ids[16]; |
61 | #ifdef CONFIG_SMP | ||
62 | unsigned long smp; | ||
63 | #endif | ||
80 | }; | 64 | }; |
81 | 65 | ||
82 | struct intc_sense_reg { | 66 | struct intc_sense_reg { |
@@ -84,6 +68,12 @@ struct intc_sense_reg { | |||
84 | intc_enum enum_ids[16]; | 68 | intc_enum enum_ids[16]; |
85 | }; | 69 | }; |
86 | 70 | ||
71 | #ifdef CONFIG_SMP | ||
72 | #define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8) | ||
73 | #else | ||
74 | #define INTC_SMP(stride, nr) | ||
75 | #endif | ||
76 | |||
87 | struct intc_desc { | 77 | struct intc_desc { |
88 | struct intc_vect *vectors; | 78 | struct intc_vect *vectors; |
89 | unsigned int nr_vectors; | 79 | unsigned int nr_vectors; |
@@ -97,25 +87,28 @@ struct intc_desc { | |||
97 | unsigned int nr_prio_regs; | 87 | unsigned int nr_prio_regs; |
98 | struct intc_sense_reg *sense_regs; | 88 | struct intc_sense_reg *sense_regs; |
99 | unsigned int nr_sense_regs; | 89 | unsigned int nr_sense_regs; |
100 | struct irq_chip chip; | 90 | char *name; |
101 | }; | 91 | }; |
102 | 92 | ||
103 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) | 93 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) |
104 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ | 94 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ |
105 | priorities, mask_regs, prio_regs, sense_regs) \ | 95 | priorities, mask_regs, prio_regs, sense_regs) \ |
106 | struct intc_desc symbol = { \ | 96 | struct intc_desc symbol __initdata = { \ |
107 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ | 97 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ |
108 | _INTC_ARRAY(priorities), \ | 98 | _INTC_ARRAY(priorities), \ |
109 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ | 99 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ |
110 | _INTC_ARRAY(sense_regs), \ | 100 | _INTC_ARRAY(sense_regs), \ |
111 | .chip.name = chipname, \ | 101 | chipname, \ |
112 | } | 102 | } |
113 | 103 | ||
114 | void __init register_intc_controller(struct intc_desc *desc); | 104 | void __init register_intc_controller(struct intc_desc *desc); |
105 | int intc_set_priority(unsigned int irq, unsigned int prio); | ||
115 | 106 | ||
116 | void __init plat_irq_setup(void); | 107 | void __init plat_irq_setup(void); |
117 | 108 | ||
118 | enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; | 109 | enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210, |
110 | IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK, | ||
111 | IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 }; | ||
119 | void __init plat_irq_setup_pins(int mode); | 112 | void __init plat_irq_setup_pins(int mode); |
120 | 113 | ||
121 | #endif /* __ASM_SH_HW_IRQ_H */ | 114 | #endif /* __ASM_SH_HW_IRQ_H */ |
diff --git a/include/asm-sh/ilsel.h b/include/asm-sh/ilsel.h new file mode 100644 index 000000000000..e3d304b280f6 --- /dev/null +++ b/include/asm-sh/ilsel.h | |||
@@ -0,0 +1,45 @@ | |||
1 | #ifndef __ASM_SH_ILSEL_H | ||
2 | #define __ASM_SH_ILSEL_H | ||
3 | |||
4 | typedef enum { | ||
5 | ILSEL_NONE, | ||
6 | ILSEL_LAN, | ||
7 | ILSEL_USBH_I, | ||
8 | ILSEL_USBH_S, | ||
9 | ILSEL_USBH_V, | ||
10 | ILSEL_RTC, | ||
11 | ILSEL_USBP_I, | ||
12 | ILSEL_USBP_S, | ||
13 | ILSEL_USBP_V, | ||
14 | ILSEL_KEY, | ||
15 | |||
16 | /* | ||
17 | * ILSEL Aliases - corner cases for interleaved level tables. | ||
18 | * | ||
19 | * Someone thought this was a good idea and less hassle than | ||
20 | * demuxing a shared vector, really. | ||
21 | */ | ||
22 | |||
23 | /* ILSEL0 and 2 */ | ||
24 | ILSEL_FPGA0, | ||
25 | ILSEL_FPGA1, | ||
26 | ILSEL_EX1, | ||
27 | ILSEL_EX2, | ||
28 | ILSEL_EX3, | ||
29 | ILSEL_EX4, | ||
30 | |||
31 | /* ILSEL1 and 3 */ | ||
32 | ILSEL_FPGA2 = ILSEL_FPGA0, | ||
33 | ILSEL_FPGA3 = ILSEL_FPGA1, | ||
34 | ILSEL_EX5 = ILSEL_EX1, | ||
35 | ILSEL_EX6 = ILSEL_EX2, | ||
36 | ILSEL_EX7 = ILSEL_EX3, | ||
37 | ILSEL_EX8 = ILSEL_EX4, | ||
38 | } ilsel_source_t; | ||
39 | |||
40 | /* arch/sh/boards/renesas/x3proto/ilsel.c */ | ||
41 | int ilsel_enable(ilsel_source_t set); | ||
42 | int ilsel_enable_fixed(ilsel_source_t set, unsigned int level); | ||
43 | void ilsel_disable(unsigned int irq); | ||
44 | |||
45 | #endif /* __ASM_SH_ILSEL_H */ | ||
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index e6a1877dcb20..1a336cdc75fe 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h | |||
@@ -135,6 +135,32 @@ void __raw_readsl(unsigned long addr, void *data, int longlen); | |||
135 | # define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) | 135 | # define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) |
136 | #endif | 136 | #endif |
137 | 137 | ||
138 | #define __BUILD_MEMORY_STRING(bwlq, type) \ | ||
139 | \ | ||
140 | static inline void writes##bwlq(volatile void __iomem *mem, \ | ||
141 | const void *addr, unsigned int count) \ | ||
142 | { \ | ||
143 | const volatile type *__addr = addr; \ | ||
144 | \ | ||
145 | while (count--) { \ | ||
146 | __raw_write##bwlq(*__addr, mem); \ | ||
147 | __addr++; \ | ||
148 | } \ | ||
149 | } \ | ||
150 | \ | ||
151 | static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ | ||
152 | unsigned int count) \ | ||
153 | { \ | ||
154 | volatile type *__addr = addr; \ | ||
155 | \ | ||
156 | while (count--) { \ | ||
157 | *__addr = __raw_read##bwlq(mem); \ | ||
158 | __addr++; \ | ||
159 | } \ | ||
160 | } | ||
161 | |||
162 | __BUILD_MEMORY_STRING(b, u8) | ||
163 | __BUILD_MEMORY_STRING(w, u16) | ||
138 | #define writesl __raw_writesl | 164 | #define writesl __raw_writesl |
139 | #define readsl __raw_readsl | 165 | #define readsl __raw_readsl |
140 | 166 | ||
diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h index 74bd0953e5ce..4bc8cb187d11 100644 --- a/include/asm-sh/kgdb.h +++ b/include/asm-sh/kgdb.h | |||
@@ -17,9 +17,6 @@ | |||
17 | #define __KGDB_H | 17 | #define __KGDB_H |
18 | 18 | ||
19 | #include <asm/ptrace.h> | 19 | #include <asm/ptrace.h> |
20 | #include <asm/cacheflush.h> | ||
21 | |||
22 | struct console; | ||
23 | 20 | ||
24 | /* Same as pt_regs but has vbr in place of syscall_nr */ | 21 | /* Same as pt_regs but has vbr in place of syscall_nr */ |
25 | struct kgdb_regs { | 22 | struct kgdb_regs { |
@@ -35,10 +32,7 @@ struct kgdb_regs { | |||
35 | 32 | ||
36 | /* State info */ | 33 | /* State info */ |
37 | extern char kgdb_in_gdb_mode; | 34 | extern char kgdb_in_gdb_mode; |
38 | extern int kgdb_done_init; | ||
39 | extern int kgdb_enabled; | ||
40 | extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */ | 35 | extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */ |
41 | extern int kgdb_halt; /* Execute initial breakpoint at startup */ | ||
42 | extern char in_nmi; /* Debounce flag to prevent NMI reentry*/ | 36 | extern char in_nmi; /* Debounce flag to prevent NMI reentry*/ |
43 | 37 | ||
44 | /* SCI */ | 38 | /* SCI */ |
@@ -59,6 +53,7 @@ extern kgdb_debug_hook_t *kgdb_debug_hook; | |||
59 | extern kgdb_bus_error_hook_t *kgdb_bus_err_hook; | 53 | extern kgdb_bus_error_hook_t *kgdb_bus_err_hook; |
60 | 54 | ||
61 | /* Console */ | 55 | /* Console */ |
56 | struct console; | ||
62 | void kgdb_console_write(struct console *co, const char *s, unsigned count); | 57 | void kgdb_console_write(struct console *co, const char *s, unsigned count); |
63 | extern int kgdb_console_setup(struct console *, char *); | 58 | extern int kgdb_console_setup(struct console *, char *); |
64 | 59 | ||
@@ -69,22 +64,7 @@ extern void longjmp(jmp_buf __jmpb, int __retval); | |||
69 | extern int setjmp(jmp_buf __jmpb); | 64 | extern int setjmp(jmp_buf __jmpb); |
70 | 65 | ||
71 | /* Forced breakpoint */ | 66 | /* Forced breakpoint */ |
72 | #define breakpoint() \ | 67 | #define breakpoint() __asm__ __volatile__("trapa #0x3c") |
73 | do { \ | ||
74 | if (kgdb_enabled) \ | ||
75 | __asm__ __volatile__("trapa #0x3c"); \ | ||
76 | } while (0) | ||
77 | |||
78 | /* KGDB should be able to flush all kernel text space */ | ||
79 | #if defined(CONFIG_CPU_SH4) | ||
80 | #define kgdb_flush_icache_range(start, end) \ | ||
81 | { \ | ||
82 | __flush_purge_region((void*)(start), (int)(end) - (int)(start));\ | ||
83 | flush_icache_range((start), (end)); \ | ||
84 | } | ||
85 | #else | ||
86 | #define kgdb_flush_icache_range(start, end) do { } while (0) | ||
87 | #endif | ||
88 | 68 | ||
89 | /* Taken from sh-stub.c of GDB 4.18 */ | 69 | /* Taken from sh-stub.c of GDB 4.18 */ |
90 | static const char hexchars[] = "0123456789abcdef"; | 70 | static const char hexchars[] = "0123456789abcdef"; |
diff --git a/include/asm-sh/magicpanelr2.h b/include/asm-sh/magicpanelr2.h new file mode 100644 index 000000000000..c644a77ee357 --- /dev/null +++ b/include/asm-sh/magicpanelr2.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /* | ||
2 | * include/asm-sh/magicpanelr2.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Markus Brunner, Mark Jonas | ||
5 | * | ||
6 | * I/O addresses and bitmasks for Magic Panel Release 2 board | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_SH_MAGICPANELR2_H | ||
14 | #define __ASM_SH_MAGICPANELR2_H | ||
15 | |||
16 | #include <asm/gpio.h> | ||
17 | |||
18 | #define __IO_PREFIX mpr2 | ||
19 | #include <asm/io_generic.h> | ||
20 | |||
21 | |||
22 | #define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg) | ||
23 | #define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg) | ||
24 | #define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg) | ||
25 | #define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg) | ||
26 | #define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg) | ||
27 | #define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg) | ||
28 | |||
29 | |||
30 | #define PA_LED PORT_PADR /* LED */ | ||
31 | |||
32 | |||
33 | /* BSC */ | ||
34 | #define CMNCR 0xA4FD0000UL | ||
35 | #define CS0BCR 0xA4FD0004UL | ||
36 | #define CS2BCR 0xA4FD0008UL | ||
37 | #define CS3BCR 0xA4FD000CUL | ||
38 | #define CS4BCR 0xA4FD0010UL | ||
39 | #define CS5ABCR 0xA4FD0014UL | ||
40 | #define CS5BBCR 0xA4FD0018UL | ||
41 | #define CS6ABCR 0xA4FD001CUL | ||
42 | #define CS6BBCR 0xA4FD0020UL | ||
43 | #define CS0WCR 0xA4FD0024UL | ||
44 | #define CS2WCR 0xA4FD0028UL | ||
45 | #define CS3WCR 0xA4FD002CUL | ||
46 | #define CS4WCR 0xA4FD0030UL | ||
47 | #define CS5AWCR 0xA4FD0034UL | ||
48 | #define CS5BWCR 0xA4FD0038UL | ||
49 | #define CS6AWCR 0xA4FD003CUL | ||
50 | #define CS6BWCR 0xA4FD0040UL | ||
51 | |||
52 | |||
53 | /* usb */ | ||
54 | |||
55 | #define PORT_UTRCTL 0xA405012CUL | ||
56 | #define PORT_UCLKCR_W 0xA40A0008UL | ||
57 | |||
58 | #define INTC_ICR0 0xA414FEE0UL | ||
59 | #define INTC_ICR1 0xA4140010UL | ||
60 | #define INTC_ICR2 0xA4140012UL | ||
61 | |||
62 | /* MTD */ | ||
63 | |||
64 | #define MPR2_MTD_BOOTLOADER_SIZE 0x00060000UL | ||
65 | #define MPR2_MTD_KERNEL_SIZE 0x00200000UL | ||
66 | |||
67 | #endif /* __ASM_SH_MAGICPANELR2_H */ | ||
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index 6bc9bba10105..cb3d46c59eab 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h | |||
@@ -70,14 +70,14 @@ extern void clear_page_nommu(void *to); | |||
70 | extern void copy_page_nommu(void *to, void *from); | 70 | extern void copy_page_nommu(void *to, void *from); |
71 | #endif | 71 | #endif |
72 | 72 | ||
73 | #if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \ | 73 | #if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ |
74 | defined(CONFIG_SH7705_CACHE_32KB)) | 74 | (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)) |
75 | struct page; | 75 | struct page; |
76 | extern void clear_user_page(void *to, unsigned long address, struct page *pg); | 76 | extern void clear_user_page(void *to, unsigned long address, struct page *pg); |
77 | extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); | 77 | extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); |
78 | extern void __clear_user_page(void *to, void *orig_to); | 78 | extern void __clear_user_page(void *to, void *orig_to); |
79 | extern void __copy_user_page(void *to, void *from, void *orig_to); | 79 | extern void __copy_user_page(void *to, void *from, void *orig_to); |
80 | #elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU) | 80 | #else |
81 | #define clear_user_page(page, vaddr, pg) clear_page(page) | 81 | #define clear_user_page(page, vaddr, pg) clear_page(page) |
82 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) | 82 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) |
83 | #endif | 83 | #endif |
@@ -88,6 +88,7 @@ extern void __copy_user_page(void *to, void *from, void *orig_to); | |||
88 | #ifdef CONFIG_X2TLB | 88 | #ifdef CONFIG_X2TLB |
89 | typedef struct { unsigned long pte_low, pte_high; } pte_t; | 89 | typedef struct { unsigned long pte_low, pte_high; } pte_t; |
90 | typedef struct { unsigned long long pgprot; } pgprot_t; | 90 | typedef struct { unsigned long long pgprot; } pgprot_t; |
91 | typedef struct { unsigned long long pgd; } pgd_t; | ||
91 | #define pte_val(x) \ | 92 | #define pte_val(x) \ |
92 | ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) | 93 | ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) |
93 | #define __pte(x) \ | 94 | #define __pte(x) \ |
@@ -95,12 +96,11 @@ typedef struct { unsigned long long pgprot; } pgprot_t; | |||
95 | #else | 96 | #else |
96 | typedef struct { unsigned long pte_low; } pte_t; | 97 | typedef struct { unsigned long pte_low; } pte_t; |
97 | typedef struct { unsigned long pgprot; } pgprot_t; | 98 | typedef struct { unsigned long pgprot; } pgprot_t; |
99 | typedef struct { unsigned long pgd; } pgd_t; | ||
98 | #define pte_val(x) ((x).pte_low) | 100 | #define pte_val(x) ((x).pte_low) |
99 | #define __pte(x) ((pte_t) { (x) } ) | 101 | #define __pte(x) ((pte_t) { (x) } ) |
100 | #endif | 102 | #endif |
101 | 103 | ||
102 | typedef struct { unsigned long pgd; } pgd_t; | ||
103 | |||
104 | #define pgd_val(x) ((x).pgd) | 104 | #define pgd_val(x) ((x).pgd) |
105 | #define pgprot_val(x) ((x).pgprot) | 105 | #define pgprot_val(x) ((x).pgprot) |
106 | 106 | ||
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index e3fae12c0e49..cf0dd2b648c2 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h | |||
@@ -42,13 +42,12 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; | |||
42 | 42 | ||
43 | /* PGD bits */ | 43 | /* PGD bits */ |
44 | #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) | 44 | #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) |
45 | #define PGDIR_BITS (32 - PGDIR_SHIFT) | ||
46 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | 45 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
47 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | 46 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
48 | 47 | ||
49 | /* Entries per level */ | 48 | /* Entries per level */ |
50 | #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) | 49 | #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) |
51 | #define PTRS_PER_PGD (PAGE_SIZE / 4) | 50 | #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) |
52 | 51 | ||
53 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) | 52 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) |
54 | #define FIRST_USER_ADDRESS 0 | 53 | #define FIRST_USER_ADDRESS 0 |
@@ -100,17 +99,18 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; | |||
100 | #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ | 99 | #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ |
101 | #define _PAGE_DIRTY 0x004 /* D-bit : page changed */ | 100 | #define _PAGE_DIRTY 0x004 /* D-bit : page changed */ |
102 | #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ | 101 | #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ |
103 | #ifndef CONFIG_X2TLB | 102 | #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ |
104 | # define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ | 103 | #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ |
105 | # define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ | 104 | #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ |
106 | # define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ | 105 | #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ |
107 | # define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ | ||
108 | #endif | ||
109 | #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ | 106 | #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ |
110 | #define _PAGE_PROTNONE 0x200 /* software: if not present */ | 107 | #define _PAGE_PROTNONE 0x200 /* software: if not present */ |
111 | #define _PAGE_ACCESSED 0x400 /* software: page referenced */ | 108 | #define _PAGE_ACCESSED 0x400 /* software: page referenced */ |
112 | #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ | 109 | #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ |
113 | 110 | ||
111 | #define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1) | ||
112 | #define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER) | ||
113 | |||
114 | /* Extended mode bits */ | 114 | /* Extended mode bits */ |
115 | #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */ | 115 | #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */ |
116 | #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */ | 116 | #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */ |
@@ -126,11 +126,7 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; | |||
126 | #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */ | 126 | #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */ |
127 | 127 | ||
128 | /* Wrapper for extended mode pgprot twiddling */ | 128 | /* Wrapper for extended mode pgprot twiddling */ |
129 | #ifdef CONFIG_X2TLB | 129 | #define _PAGE_EXT(x) ((unsigned long long)(x) << 32) |
130 | # define _PAGE_EXT(x) ((unsigned long long)(x) << 32) | ||
131 | #else | ||
132 | # define _PAGE_EXT(x) (0) | ||
133 | #endif | ||
134 | 130 | ||
135 | /* software: moves to PTEA.TC (Timing Control) */ | 131 | /* software: moves to PTEA.TC (Timing Control) */ |
136 | #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ | 132 | #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ |
@@ -146,10 +142,14 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; | |||
146 | #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ | 142 | #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ |
147 | 143 | ||
148 | /* Mask which drops unused bits from the PTEL value */ | 144 | /* Mask which drops unused bits from the PTEL value */ |
149 | #ifdef CONFIG_CPU_SH3 | 145 | #if defined(CONFIG_CPU_SH3) |
150 | #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ | 146 | #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \ |
151 | _PAGE_FILE | _PAGE_SZ1 | \ | 147 | _PAGE_FILE | _PAGE_SZ1 | \ |
152 | _PAGE_HW_SHARED) | 148 | _PAGE_HW_SHARED) |
149 | #elif defined(CONFIG_X2TLB) | ||
150 | /* Get rid of the legacy PR/SZ bits when using extended mode */ | ||
151 | #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \ | ||
152 | _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK) | ||
153 | #else | 153 | #else |
154 | #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE) | 154 | #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE) |
155 | #endif | 155 | #endif |
@@ -212,27 +212,36 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; | |||
212 | 212 | ||
213 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | 213 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ |
214 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ | 214 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ |
215 | _PAGE_EXT(_PAGE_EXT_USER_READ | \ | 215 | _PAGE_EXT(_PAGE_EXT_KERN_READ | \ |
216 | _PAGE_EXT_KERN_WRITE | \ | ||
217 | _PAGE_EXT_USER_READ | \ | ||
216 | _PAGE_EXT_USER_WRITE)) | 218 | _PAGE_EXT_USER_WRITE)) |
217 | 219 | ||
218 | #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | 220 | #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ |
219 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ | 221 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ |
220 | _PAGE_EXT(_PAGE_EXT_USER_EXEC | \ | 222 | _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \ |
223 | _PAGE_EXT_KERN_READ | \ | ||
224 | _PAGE_EXT_USER_EXEC | \ | ||
221 | _PAGE_EXT_USER_READ)) | 225 | _PAGE_EXT_USER_READ)) |
222 | 226 | ||
223 | #define PAGE_COPY PAGE_EXECREAD | 227 | #define PAGE_COPY PAGE_EXECREAD |
224 | 228 | ||
225 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | 229 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ |
226 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ | 230 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ |
227 | _PAGE_EXT(_PAGE_EXT_USER_READ)) | 231 | _PAGE_EXT(_PAGE_EXT_KERN_READ | \ |
232 | _PAGE_EXT_USER_READ)) | ||
228 | 233 | ||
229 | #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | 234 | #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ |
230 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ | 235 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ |
231 | _PAGE_EXT(_PAGE_EXT_USER_WRITE)) | 236 | _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ |
237 | _PAGE_EXT_USER_WRITE)) | ||
232 | 238 | ||
233 | #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | 239 | #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ |
234 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ | 240 | _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \ |
235 | _PAGE_EXT(_PAGE_EXT_USER_WRITE | \ | 241 | _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \ |
242 | _PAGE_EXT_KERN_READ | \ | ||
243 | _PAGE_EXT_KERN_EXEC | \ | ||
244 | _PAGE_EXT_USER_WRITE | \ | ||
236 | _PAGE_EXT_USER_READ | \ | 245 | _PAGE_EXT_USER_READ | \ |
237 | _PAGE_EXT_USER_EXEC)) | 246 | _PAGE_EXT_USER_EXEC)) |
238 | 247 | ||
@@ -373,11 +382,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte) | |||
373 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) | 382 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) |
374 | 383 | ||
375 | #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) | 384 | #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) |
376 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
377 | #define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
378 | 385 | ||
379 | #define pte_none(x) (!pte_val(x)) | 386 | #define pfn_pte(pfn, prot) \ |
380 | #define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) | 387 | __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) |
388 | #define pfn_pmd(pfn, prot) \ | ||
389 | __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
390 | |||
391 | #define pte_none(x) (!pte_val(x)) | ||
392 | #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE)) | ||
393 | |||
381 | #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) | 394 | #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) |
382 | 395 | ||
383 | #define pmd_none(x) (!pmd_val(x)) | 396 | #define pmd_none(x) (!pmd_val(x)) |
@@ -392,15 +405,15 @@ static inline void set_pte(pte_t *ptep, pte_t pte) | |||
392 | * The following only work if pte_present() is true. | 405 | * The following only work if pte_present() is true. |
393 | * Undefined behaviour if not.. | 406 | * Undefined behaviour if not.. |
394 | */ | 407 | */ |
395 | #define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT)) | 408 | #define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT)) |
396 | #define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY) | 409 | #define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY) |
397 | #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED) | 410 | #define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED) |
398 | #define pte_file(pte) (pte_val(pte) & _PAGE_FILE) | 411 | #define pte_file(pte) ((pte).pte_low & _PAGE_FILE) |
399 | 412 | ||
400 | #ifdef CONFIG_X2TLB | 413 | #ifdef CONFIG_X2TLB |
401 | #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) | 414 | #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE) |
402 | #else | 415 | #else |
403 | #define pte_write(pte) (pte_val(pte) & _PAGE_RW) | 416 | #define pte_write(pte) ((pte).pte_low & _PAGE_RW) |
404 | #endif | 417 | #endif |
405 | 418 | ||
406 | #define PTE_BIT_FUNC(h,fn,op) \ | 419 | #define PTE_BIT_FUNC(h,fn,op) \ |
@@ -429,17 +442,10 @@ PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED); | |||
429 | /* | 442 | /* |
430 | * Macro and implementation to make a page protection as uncachable. | 443 | * Macro and implementation to make a page protection as uncachable. |
431 | */ | 444 | */ |
432 | #define pgprot_noncached pgprot_noncached | 445 | #define pgprot_writecombine(prot) \ |
446 | __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) | ||
433 | 447 | ||
434 | static inline pgprot_t pgprot_noncached(pgprot_t _prot) | 448 | #define pgprot_noncached pgprot_writecombine |
435 | { | ||
436 | unsigned long prot = pgprot_val(_prot); | ||
437 | |||
438 | prot &= ~_PAGE_CACHABLE; | ||
439 | return __pgprot(prot); | ||
440 | } | ||
441 | |||
442 | #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) | ||
443 | 449 | ||
444 | /* | 450 | /* |
445 | * Conversion functions: convert a page and protection to a page entry, | 451 | * Conversion functions: convert a page and protection to a page entry, |
@@ -451,28 +457,33 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot) | |||
451 | 457 | ||
452 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | 458 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
453 | { | 459 | { |
454 | set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | | 460 | pte.pte_low &= _PAGE_CHG_MASK; |
455 | pgprot_val(newprot))); | 461 | pte.pte_low |= pgprot_val(newprot); |
462 | |||
463 | #ifdef CONFIG_X2TLB | ||
464 | pte.pte_high |= pgprot_val(newprot) >> 32; | ||
465 | #endif | ||
466 | |||
456 | return pte; | 467 | return pte; |
457 | } | 468 | } |
458 | 469 | ||
459 | #define pmd_page_vaddr(pmd) pmd_val(pmd) | 470 | #define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd)) |
460 | #define pmd_page(pmd) (virt_to_page(pmd_val(pmd))) | 471 | #define pmd_page(pmd) (virt_to_page(pmd_val(pmd))) |
461 | 472 | ||
462 | /* to find an entry in a page-table-directory. */ | 473 | /* to find an entry in a page-table-directory. */ |
463 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) | 474 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
464 | #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) | 475 | #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) |
465 | 476 | ||
466 | /* to find an entry in a kernel page-table-directory */ | 477 | /* to find an entry in a kernel page-table-directory */ |
467 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | 478 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
468 | 479 | ||
469 | /* Find an entry in the third-level page table.. */ | 480 | /* Find an entry in the third-level page table.. */ |
470 | #define pte_index(address) \ | 481 | #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |
471 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
472 | #define pte_offset_kernel(dir, address) \ | 482 | #define pte_offset_kernel(dir, address) \ |
473 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) | 483 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address)) |
474 | #define pte_offset_map(dir, address) pte_offset_kernel(dir, address) | 484 | #define pte_offset_map(dir, address) pte_offset_kernel(dir, address) |
475 | #define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address) | 485 | #define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address) |
486 | |||
476 | #define pte_unmap(pte) do { } while (0) | 487 | #define pte_unmap(pte) do { } while (0) |
477 | #define pte_unmap_nested(pte) do { } while (0) | 488 | #define pte_unmap_nested(pte) do { } while (0) |
478 | 489 | ||
@@ -480,13 +491,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |||
480 | #define pte_ERROR(e) \ | 491 | #define pte_ERROR(e) \ |
481 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \ | 492 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \ |
482 | &(e), (e).pte_high, (e).pte_low) | 493 | &(e), (e).pte_high, (e).pte_low) |
494 | #define pgd_ERROR(e) \ | ||
495 | printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
483 | #else | 496 | #else |
484 | #define pte_ERROR(e) \ | 497 | #define pte_ERROR(e) \ |
485 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | 498 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) |
486 | #endif | ||
487 | |||
488 | #define pgd_ERROR(e) \ | 499 | #define pgd_ERROR(e) \ |
489 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | 500 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) |
501 | #endif | ||
490 | 502 | ||
491 | struct vm_area_struct; | 503 | struct vm_area_struct; |
492 | extern void update_mmu_cache(struct vm_area_struct * vma, | 504 | extern void update_mmu_cache(struct vm_area_struct * vma, |
@@ -563,7 +575,8 @@ struct mm_struct; | |||
563 | extern unsigned int kobjsize(const void *objp); | 575 | extern unsigned int kobjsize(const void *objp); |
564 | #endif /* !CONFIG_MMU */ | 576 | #endif /* !CONFIG_MMU */ |
565 | 577 | ||
566 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) | 578 | #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ |
579 | defined(CONFIG_SH7705_CACHE_32KB)) | ||
567 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | 580 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
568 | extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | 581 | extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); |
569 | #endif | 582 | #endif |
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 26d52174f4b4..4f2922a1979c 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h | |||
@@ -45,7 +45,7 @@ enum cpu_type { | |||
45 | CPU_SH7705, CPU_SH7706, CPU_SH7707, | 45 | CPU_SH7705, CPU_SH7706, CPU_SH7707, |
46 | CPU_SH7708, CPU_SH7708S, CPU_SH7708R, | 46 | CPU_SH7708, CPU_SH7708S, CPU_SH7708R, |
47 | CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, | 47 | CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, |
48 | CPU_SH7729, | 48 | CPU_SH7720, CPU_SH7729, |
49 | 49 | ||
50 | /* SH-4 types */ | 50 | /* SH-4 types */ |
51 | CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, | 51 | CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, |
@@ -73,15 +73,10 @@ struct sh_cpuinfo { | |||
73 | unsigned long flags; | 73 | unsigned long flags; |
74 | } __attribute__ ((aligned(SMP_CACHE_BYTES))); | 74 | } __attribute__ ((aligned(SMP_CACHE_BYTES))); |
75 | 75 | ||
76 | extern struct sh_cpuinfo boot_cpu_data; | ||
77 | |||
78 | #ifdef CONFIG_SMP | ||
79 | extern struct sh_cpuinfo cpu_data[]; | 76 | extern struct sh_cpuinfo cpu_data[]; |
77 | #define boot_cpu_data cpu_data[0] | ||
80 | #define current_cpu_data cpu_data[smp_processor_id()] | 78 | #define current_cpu_data cpu_data[smp_processor_id()] |
81 | #else | 79 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] |
82 | #define cpu_data (&boot_cpu_data) | ||
83 | #define current_cpu_data boot_cpu_data | ||
84 | #endif | ||
85 | 80 | ||
86 | /* | 81 | /* |
87 | * User space process size: 2GB. | 82 | * User space process size: 2GB. |
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h index 4083b5949928..de37f933aa42 100644 --- a/include/asm-sh/r7780rp.h +++ b/include/asm-sh/r7780rp.h | |||
@@ -65,24 +65,6 @@ | |||
65 | #define PA_PMR (PA_BCR+0x0900) /* */ | 65 | #define PA_PMR (PA_BCR+0x0900) /* */ |
66 | 66 | ||
67 | #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ | 67 | #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ |
68 | |||
69 | #define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */ | ||
70 | #define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */ | ||
71 | #define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */ | ||
72 | #define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */ | ||
73 | #define IRQ_TP 2 /* Touch Panel IRQ */ | ||
74 | #define IRQ_SCI1 3 /* SCI1 IRQ */ | ||
75 | #define IRQ_SCI0 4 /* SCI0 IRQ */ | ||
76 | #define IRQ_2SERIAL 5 /* Serial IRQ */ | ||
77 | #define IRQ_RTC 6 /* RTC A / B IRQ */ | ||
78 | #define IRQ_EXTENTION6 7 /* EXT6n IRQ */ | ||
79 | #define IRQ_EXTENTION5 8 /* EXT5n IRQ */ | ||
80 | #define IRQ_EXTENTION4 9 /* EXT4n IRQ */ | ||
81 | #define IRQ_EXTENTION2 10 /* EXT2n IRQ */ | ||
82 | #define IRQ_EXTENTION1 11 /* EXT1n IRQ */ | ||
83 | #define IRQ_ONETH 13 /* On board Ethernet IRQ */ | ||
84 | #define IRQ_PSW 14 /* Push Switch IRQ */ | ||
85 | |||
86 | #define IVDR_CK_ON 8 /* iVDR Clock ON */ | 68 | #define IVDR_CK_ON 8 /* iVDR Clock ON */ |
87 | 69 | ||
88 | #elif defined(CONFIG_SH_R7780RP) | 70 | #elif defined(CONFIG_SH_R7780RP) |
@@ -203,11 +185,24 @@ | |||
203 | #define PA_MMSR (PA_BCR+0x0400) | 185 | #define PA_MMSR (PA_BCR+0x0400) |
204 | 186 | ||
205 | #define IVDR_CK_ON 4 /* iVDR Clock ON */ | 187 | #define IVDR_CK_ON 4 /* iVDR Clock ON */ |
188 | #endif | ||
206 | 189 | ||
190 | #define HL_FPGA_IRQ_BASE 200 | ||
191 | #define HL_NR_IRL 15 | ||
192 | |||
193 | #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) | ||
194 | #define IRQ_CF (HL_FPGA_IRQ_BASE + 1) | ||
195 | #ifndef IRQ_PSW | ||
196 | #define IRQ_PSW (HL_FPGA_IRQ_BASE + 2) | ||
207 | #endif | 197 | #endif |
198 | #define IRQ_EXT1 (HL_FPGA_IRQ_BASE + 3) | ||
199 | #define IRQ_EXT4 (HL_FPGA_IRQ_BASE + 4) | ||
208 | 200 | ||
209 | void make_r7780rp_irq(unsigned int irq); | 201 | void make_r7780rp_irq(unsigned int irq); |
210 | void highlander_init_irq(void); | 202 | |
203 | unsigned char *highlander_init_irq_r7780mp(void); | ||
204 | unsigned char *highlander_init_irq_r7780rp(void); | ||
205 | unsigned char *highlander_init_irq_r7785rp(void); | ||
211 | 206 | ||
212 | #define __IO_PREFIX r7780rp | 207 | #define __IO_PREFIX r7780rp |
213 | #include <asm/io_generic.h> | 208 | #include <asm/io_generic.h> |
diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h index 91aacc96151b..858da99d37e0 100644 --- a/include/asm-sh/rtc.h +++ b/include/asm-sh/rtc.h | |||
@@ -5,4 +5,10 @@ extern void (*board_time_init)(void); | |||
5 | extern void (*rtc_sh_get_time)(struct timespec *); | 5 | extern void (*rtc_sh_get_time)(struct timespec *); |
6 | extern int (*rtc_sh_set_time)(const time_t); | 6 | extern int (*rtc_sh_set_time)(const time_t); |
7 | 7 | ||
8 | #define RTC_CAP_4_DIGIT_YEAR (1 << 0) | ||
9 | |||
10 | struct sh_rtc_platform_info { | ||
11 | unsigned long capabilities; | ||
12 | }; | ||
13 | |||
8 | #endif /* _ASM_RTC_H */ | 14 | #endif /* _ASM_RTC_H */ |
diff --git a/include/asm-sh/rts7751r2d.h b/include/asm-sh/rts7751r2d.h index 5d7800aa31b5..83b9c111f171 100644 --- a/include/asm-sh/rts7751r2d.h +++ b/include/asm-sh/rts7751r2d.h | |||
@@ -9,7 +9,7 @@ | |||
9 | * Renesas Technology Sales RTS7751R2D support | 9 | * Renesas Technology Sales RTS7751R2D support |
10 | */ | 10 | */ |
11 | 11 | ||
12 | /* Box specific addresses. */ | 12 | /* Board specific addresses. */ |
13 | 13 | ||
14 | #define PA_BCR 0xa4000000 /* FPGA */ | 14 | #define PA_BCR 0xa4000000 /* FPGA */ |
15 | #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ | 15 | #define PA_IRLMON 0xa4000002 /* Interrupt Status control */ |
@@ -20,19 +20,19 @@ | |||
20 | #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ | 20 | #define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ |
21 | #define PA_PCICD 0xa400000e /* PCI Extention detect control */ | 21 | #define PA_PCICD 0xa400000e /* PCI Extention detect control */ |
22 | #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ | 22 | #define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ |
23 | #if defined(CONFIG_RTS7751R2D_REV11) | 23 | |
24 | #define PA_AXRST 0xa4000022 /* AX_LAN Reset control */ | 24 | #define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */ |
25 | #define PA_CFRST 0xa4000024 /* CF Reset control */ | 25 | #define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */ |
26 | #define PA_ADMRTS 0xa4000026 /* SD Reset control */ | 26 | #define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */ |
27 | #define PA_EXTRST 0xa4000028 /* Extention Reset control */ | 27 | #define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */ |
28 | #define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ | 28 | #define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ |
29 | #else | 29 | |
30 | #define PA_CFRST 0xa4000022 /* CF Reset control */ | 30 | #define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */ |
31 | #define PA_ADMRTS 0xa4000024 /* SD Reset control */ | 31 | #define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */ |
32 | #define PA_EXTRST 0xa4000026 /* Extention Reset control */ | 32 | #define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */ |
33 | #define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ | 33 | #define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ |
34 | #define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ | 34 | #define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ |
35 | #endif | 35 | |
36 | #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ | 36 | #define PA_POWOFF 0xa4000030 /* Board Power OFF control */ |
37 | #define PA_VERREG 0xa4000032 /* FPGA Version Register */ | 37 | #define PA_VERREG 0xa4000032 /* FPGA Version Register */ |
38 | #define PA_INPORT 0xa4000034 /* KEY Input Port control */ | 38 | #define PA_INPORT 0xa4000034 /* KEY Input Port control */ |
@@ -46,27 +46,22 @@ | |||
46 | 46 | ||
47 | #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ | 47 | #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ |
48 | 48 | ||
49 | #if defined(CONFIG_RTS7751R2D_REV11) | 49 | #define R2D_FPGA_IRQ_BASE 100 |
50 | #define IRQ_PCIETH 0 /* PCI Ethernet IRQ */ | 50 | |
51 | #define IRQ_CFCARD 1 /* CF Card IRQ */ | 51 | #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) |
52 | #define IRQ_CFINST 2 /* CF Card Insert IRQ */ | 52 | #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) |
53 | #define IRQ_PCMCIA 3 /* PCMCIA IRQ */ | 53 | #define IRQ_TP (R2D_FPGA_IRQ_BASE + 2) |
54 | #define IRQ_VOYAGER 4 /* VOYAGER IRQ */ | 54 | #define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3) |
55 | #define IRQ_ONETH 5 /* On board Ethernet IRQ */ | 55 | #define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4) |
56 | #else | 56 | #define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5) |
57 | #define IRQ_KEYIN 0 /* Key Input IRQ */ | 57 | #define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6) |
58 | #define IRQ_PCIETH 1 /* PCI Ethernet IRQ */ | 58 | #define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7) |
59 | #define IRQ_CFCARD 2 /* CF Card IRQ */ | 59 | #define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8) |
60 | #define IRQ_CFINST 3 /* CF Card Insert IRQ */ | 60 | #define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9) |
61 | #define IRQ_PCMCIA 4 /* PCMCIA IRQ */ | 61 | #define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10) |
62 | #define IRQ_VOYAGER 5 /* VOYAGER IRQ */ | 62 | #define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11) |
63 | #endif | 63 | #define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12) |
64 | #define IRQ_RTCALM 6 /* RTC Alarm IRQ */ | 64 | #define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13) |
65 | #define IRQ_RTCTIME 7 /* RTC Timer IRQ */ | ||
66 | #define IRQ_SDCARD 8 /* SD Card IRQ */ | ||
67 | #define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */ | ||
68 | #define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */ | ||
69 | #define IRQ_EXTENTION 11 /* EXTn IRQ */ | ||
70 | 65 | ||
71 | /* arch/sh/boards/renesas/rts7751r2d/irq.c */ | 66 | /* arch/sh/boards/renesas/rts7751r2d/irq.c */ |
72 | void init_rts7751r2d_IRQ(void); | 67 | void init_rts7751r2d_IRQ(void); |
diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h index 2a696b8ee4f5..bd9cbc967c2a 100644 --- a/include/asm-sh/sections.h +++ b/include/asm-sh/sections.h | |||
@@ -4,6 +4,7 @@ | |||
4 | #include <asm-generic/sections.h> | 4 | #include <asm-generic/sections.h> |
5 | 5 | ||
6 | extern long __machvec_start, __machvec_end; | 6 | extern long __machvec_start, __machvec_end; |
7 | extern char _ebss[]; | ||
7 | 8 | ||
8 | #endif /* __ASM_SH_SECTIONS_H */ | 9 | #endif /* __ASM_SH_SECTIONS_H */ |
9 | 10 | ||
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h index 4ff1eb900301..c39c785bba94 100644 --- a/include/asm-sh/sh03/io.h +++ b/include/asm-sh/sh03/io.h | |||
@@ -11,22 +11,13 @@ | |||
11 | 11 | ||
12 | #include <linux/time.h> | 12 | #include <linux/time.h> |
13 | 13 | ||
14 | #define INTC_IPRD 0xffd00010UL | ||
15 | |||
16 | #define IRL0_IRQ 2 | 14 | #define IRL0_IRQ 2 |
17 | #define IRL0_IPR_POS 3 | ||
18 | #define IRL0_PRIORITY 13 | 15 | #define IRL0_PRIORITY 13 |
19 | |||
20 | #define IRL1_IRQ 5 | 16 | #define IRL1_IRQ 5 |
21 | #define IRL1_IPR_POS 2 | ||
22 | #define IRL1_PRIORITY 10 | 17 | #define IRL1_PRIORITY 10 |
23 | |||
24 | #define IRL2_IRQ 8 | 18 | #define IRL2_IRQ 8 |
25 | #define IRL2_IPR_POS 1 | ||
26 | #define IRL2_PRIORITY 7 | 19 | #define IRL2_PRIORITY 7 |
27 | |||
28 | #define IRL3_IRQ 11 | 20 | #define IRL3_IRQ 11 |
29 | #define IRL3_IPR_POS 0 | ||
30 | #define IRL3_PRIORITY 4 | 21 | #define IRL3_PRIORITY 4 |
31 | 22 | ||
32 | void heartbeat_sh03(void); | 23 | void heartbeat_sh03(void); |
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h index b99ca786c0c1..9c8d34b07ebf 100644 --- a/include/asm-sh/smp.h +++ b/include/asm-sh/smp.h | |||
@@ -1,12 +1,3 @@ | |||
1 | /* | ||
2 | * include/asm-sh/smp.h | ||
3 | * | ||
4 | * Copyright (C) 2002, 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive for | ||
8 | * more details. | ||
9 | */ | ||
10 | #ifndef __ASM_SH_SMP_H | 1 | #ifndef __ASM_SH_SMP_H |
11 | #define __ASM_SH_SMP_H | 2 | #define __ASM_SH_SMP_H |
12 | 3 | ||
@@ -20,6 +11,15 @@ | |||
20 | #include <asm/current.h> | 11 | #include <asm/current.h> |
21 | 12 | ||
22 | #define raw_smp_processor_id() (current_thread_info()->cpu) | 13 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
14 | #define hard_smp_processor_id() plat_smp_processor_id() | ||
15 | |||
16 | /* Map from cpu id to sequential logical cpu number. */ | ||
17 | extern int __cpu_number_map[NR_CPUS]; | ||
18 | #define cpu_number_map(cpu) __cpu_number_map[cpu] | ||
19 | |||
20 | /* The reverse map from sequential logical cpu number to cpu id. */ | ||
21 | extern int __cpu_logical_map[NR_CPUS]; | ||
22 | #define cpu_logical_map(cpu) __cpu_logical_map[cpu] | ||
23 | 23 | ||
24 | /* I've no idea what the real meaning of this is */ | 24 | /* I've no idea what the real meaning of this is */ |
25 | #define PROC_CHANGE_PENALTY 20 | 25 | #define PROC_CHANGE_PENALTY 20 |
@@ -35,10 +35,22 @@ struct smp_fn_call_struct { | |||
35 | 35 | ||
36 | extern struct smp_fn_call_struct smp_fn_call; | 36 | extern struct smp_fn_call_struct smp_fn_call; |
37 | 37 | ||
38 | #define SMP_MSG_RESCHEDULE 0x0001 | 38 | #define SMP_MSG_FUNCTION 0 |
39 | #define SMP_MSG_RESCHEDULE 1 | ||
40 | #define SMP_MSG_NR 2 | ||
39 | 41 | ||
40 | #endif /* CONFIG_SMP */ | 42 | void plat_smp_setup(void); |
43 | void plat_prepare_cpus(unsigned int max_cpus); | ||
44 | int plat_smp_processor_id(void); | ||
45 | void plat_start_cpu(unsigned int cpu, unsigned long entry_point); | ||
46 | void plat_send_ipi(unsigned int cpu, unsigned int message); | ||
47 | int plat_register_ipi_handler(unsigned int message, | ||
48 | void (*handler)(void *), void *arg); | ||
49 | |||
50 | #else | ||
41 | 51 | ||
42 | #define hard_smp_processor_id() (0) | 52 | #define hard_smp_processor_id() (0) |
43 | 53 | ||
54 | #endif /* CONFIG_SMP */ | ||
55 | |||
44 | #endif /* __ASM_SH_SMP_H */ | 56 | #endif /* __ASM_SH_SMP_H */ |
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h index 3554e3a74e99..042d95f51c4d 100644 --- a/include/asm-sh/snapgear.h +++ b/include/asm-sh/snapgear.h | |||
@@ -19,20 +19,16 @@ | |||
19 | * is the interrupt :-) | 19 | * is the interrupt :-) |
20 | */ | 20 | */ |
21 | 21 | ||
22 | #define IRL0_IRQ 2 | 22 | #define IRL0_IRQ 2 |
23 | #define IRL0_IPR_POS 3 | ||
24 | #define IRL0_PRIORITY 13 | 23 | #define IRL0_PRIORITY 13 |
25 | 24 | ||
26 | #define IRL1_IRQ 5 | 25 | #define IRL1_IRQ 5 |
27 | #define IRL1_IPR_POS 2 | ||
28 | #define IRL1_PRIORITY 10 | 26 | #define IRL1_PRIORITY 10 |
29 | 27 | ||
30 | #define IRL2_IRQ 8 | 28 | #define IRL2_IRQ 8 |
31 | #define IRL2_IPR_POS 1 | ||
32 | #define IRL2_PRIORITY 7 | 29 | #define IRL2_PRIORITY 7 |
33 | 30 | ||
34 | #define IRL3_IRQ 11 | 31 | #define IRL3_IRQ 11 |
35 | #define IRL3_IPR_POS 0 | ||
36 | #define IRL3_PRIORITY 4 | 32 | #define IRL3_PRIORITY 4 |
37 | #endif | 33 | #endif |
38 | 34 | ||
diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h index 92f6e2008b2e..e793181d64da 100644 --- a/include/asm-sh/spinlock.h +++ b/include/asm-sh/spinlock.h | |||
@@ -2,6 +2,7 @@ | |||
2 | * include/asm-sh/spinlock.h | 2 | * include/asm-sh/spinlock.h |
3 | * | 3 | * |
4 | * Copyright (C) 2002, 2003 Paul Mundt | 4 | * Copyright (C) 2002, 2003 Paul Mundt |
5 | * Copyright (C) 2006, 2007 Akio Idehara | ||
5 | * | 6 | * |
6 | * This file is subject to the terms and conditions of the GNU General Public | 7 | * This file is subject to the terms and conditions of the GNU General Public |
7 | * License. See the file "COPYING" in the main directory of this archive | 8 | * License. See the file "COPYING" in the main directory of this archive |
@@ -10,17 +11,22 @@ | |||
10 | #ifndef __ASM_SH_SPINLOCK_H | 11 | #ifndef __ASM_SH_SPINLOCK_H |
11 | #define __ASM_SH_SPINLOCK_H | 12 | #define __ASM_SH_SPINLOCK_H |
12 | 13 | ||
13 | #include <asm/atomic.h> | 14 | /* |
14 | #include <asm/spinlock_types.h> | 15 | * The only locking implemented here uses SH-4A opcodes. For others, |
16 | * split this out as per atomic-*.h. | ||
17 | */ | ||
18 | #ifndef CONFIG_CPU_SH4A | ||
19 | #error "Need movli.l/movco.l for spinlocks" | ||
20 | #endif | ||
15 | 21 | ||
16 | /* | 22 | /* |
17 | * Your basic SMP spinlocks, allowing only a single CPU anywhere | 23 | * Your basic SMP spinlocks, allowing only a single CPU anywhere |
18 | */ | 24 | */ |
19 | 25 | ||
20 | #define __raw_spin_is_locked(x) ((x)->lock != 0) | 26 | #define __raw_spin_is_locked(x) ((x)->lock <= 0) |
21 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) | 27 | #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) |
22 | #define __raw_spin_unlock_wait(x) \ | 28 | #define __raw_spin_unlock_wait(x) \ |
23 | do { cpu_relax(); } while (__raw_spin_is_locked(x)) | 29 | do { cpu_relax(); } while ((x)->lock) |
24 | 30 | ||
25 | /* | 31 | /* |
26 | * Simple spin lock operations. There are two variants, one clears IRQ's | 32 | * Simple spin lock operations. There are two variants, one clears IRQ's |
@@ -30,12 +36,19 @@ | |||
30 | */ | 36 | */ |
31 | static inline void __raw_spin_lock(raw_spinlock_t *lock) | 37 | static inline void __raw_spin_lock(raw_spinlock_t *lock) |
32 | { | 38 | { |
39 | unsigned long tmp; | ||
40 | unsigned long oldval; | ||
41 | |||
33 | __asm__ __volatile__ ( | 42 | __asm__ __volatile__ ( |
34 | "1:\n\t" | 43 | "1: \n\t" |
35 | "tas.b @%0\n\t" | 44 | "movli.l @%2, %0 ! __raw_spin_lock \n\t" |
36 | "bf/s 1b\n\t" | 45 | "mov %0, %1 \n\t" |
37 | "nop\n\t" | 46 | "mov #0, %0 \n\t" |
38 | : "=r" (lock->lock) | 47 | "movco.l %0, @%2 \n\t" |
48 | "bf 1b \n\t" | ||
49 | "cmp/pl %1 \n\t" | ||
50 | "bf 1b \n\t" | ||
51 | : "=&z" (tmp), "=&r" (oldval) | ||
39 | : "r" (&lock->lock) | 52 | : "r" (&lock->lock) |
40 | : "t", "memory" | 53 | : "t", "memory" |
41 | ); | 54 | ); |
@@ -43,12 +56,36 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) | |||
43 | 56 | ||
44 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | 57 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) |
45 | { | 58 | { |
46 | //assert_spin_locked(lock); | 59 | unsigned long tmp; |
47 | 60 | ||
48 | lock->lock = 0; | 61 | __asm__ __volatile__ ( |
62 | "mov #1, %0 ! __raw_spin_unlock \n\t" | ||
63 | "mov.l %0, @%1 \n\t" | ||
64 | : "=&z" (tmp) | ||
65 | : "r" (&lock->lock) | ||
66 | : "t", "memory" | ||
67 | ); | ||
49 | } | 68 | } |
50 | 69 | ||
51 | #define __raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock)) | 70 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) |
71 | { | ||
72 | unsigned long tmp, oldval; | ||
73 | |||
74 | __asm__ __volatile__ ( | ||
75 | "1: \n\t" | ||
76 | "movli.l @%2, %0 ! __raw_spin_trylock \n\t" | ||
77 | "mov %0, %1 \n\t" | ||
78 | "mov #0, %0 \n\t" | ||
79 | "movco.l %0, @%2 \n\t" | ||
80 | "bf 1b \n\t" | ||
81 | "synco \n\t" | ||
82 | : "=&z" (tmp), "=&r" (oldval) | ||
83 | : "r" (&lock->lock) | ||
84 | : "t", "memory" | ||
85 | ); | ||
86 | |||
87 | return oldval; | ||
88 | } | ||
52 | 89 | ||
53 | /* | 90 | /* |
54 | * Read-write spinlocks, allowing multiple readers but only one writer. | 91 | * Read-write spinlocks, allowing multiple readers but only one writer. |
@@ -59,58 +96,124 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) | |||
59 | * read-locks. | 96 | * read-locks. |
60 | */ | 97 | */ |
61 | 98 | ||
99 | /** | ||
100 | * read_can_lock - would read_trylock() succeed? | ||
101 | * @lock: the rwlock in question. | ||
102 | */ | ||
103 | #define __raw_read_can_lock(x) ((x)->lock > 0) | ||
104 | |||
105 | /** | ||
106 | * write_can_lock - would write_trylock() succeed? | ||
107 | * @lock: the rwlock in question. | ||
108 | */ | ||
109 | #define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS) | ||
110 | |||
62 | static inline void __raw_read_lock(raw_rwlock_t *rw) | 111 | static inline void __raw_read_lock(raw_rwlock_t *rw) |
63 | { | 112 | { |
64 | __raw_spin_lock(&rw->lock); | 113 | unsigned long tmp; |
65 | |||
66 | atomic_inc(&rw->counter); | ||
67 | 114 | ||
68 | __raw_spin_unlock(&rw->lock); | 115 | __asm__ __volatile__ ( |
116 | "1: \n\t" | ||
117 | "movli.l @%1, %0 ! __raw_read_lock \n\t" | ||
118 | "cmp/pl %0 \n\t" | ||
119 | "bf 1b \n\t" | ||
120 | "add #-1, %0 \n\t" | ||
121 | "movco.l %0, @%1 \n\t" | ||
122 | "bf 1b \n\t" | ||
123 | : "=&z" (tmp) | ||
124 | : "r" (&rw->lock) | ||
125 | : "t", "memory" | ||
126 | ); | ||
69 | } | 127 | } |
70 | 128 | ||
71 | static inline void __raw_read_unlock(raw_rwlock_t *rw) | 129 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
72 | { | 130 | { |
73 | __raw_spin_lock(&rw->lock); | 131 | unsigned long tmp; |
74 | |||
75 | atomic_dec(&rw->counter); | ||
76 | 132 | ||
77 | __raw_spin_unlock(&rw->lock); | 133 | __asm__ __volatile__ ( |
134 | "1: \n\t" | ||
135 | "movli.l @%1, %0 ! __raw_read_unlock \n\t" | ||
136 | "add #1, %0 \n\t" | ||
137 | "movco.l %0, @%1 \n\t" | ||
138 | "bf 1b \n\t" | ||
139 | : "=&z" (tmp) | ||
140 | : "r" (&rw->lock) | ||
141 | : "t", "memory" | ||
142 | ); | ||
78 | } | 143 | } |
79 | 144 | ||
80 | static inline void __raw_write_lock(raw_rwlock_t *rw) | 145 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
81 | { | 146 | { |
82 | __raw_spin_lock(&rw->lock); | 147 | unsigned long tmp; |
83 | atomic_set(&rw->counter, -1); | 148 | |
149 | __asm__ __volatile__ ( | ||
150 | "1: \n\t" | ||
151 | "movli.l @%1, %0 ! __raw_write_lock \n\t" | ||
152 | "cmp/hs %2, %0 \n\t" | ||
153 | "bf 1b \n\t" | ||
154 | "sub %2, %0 \n\t" | ||
155 | "movco.l %0, @%1 \n\t" | ||
156 | "bf 1b \n\t" | ||
157 | : "=&z" (tmp) | ||
158 | : "r" (&rw->lock), "r" (RW_LOCK_BIAS) | ||
159 | : "t", "memory" | ||
160 | ); | ||
84 | } | 161 | } |
85 | 162 | ||
86 | static inline void __raw_write_unlock(raw_rwlock_t *rw) | 163 | static inline void __raw_write_unlock(raw_rwlock_t *rw) |
87 | { | 164 | { |
88 | atomic_set(&rw->counter, 0); | 165 | __asm__ __volatile__ ( |
89 | __raw_spin_unlock(&rw->lock); | 166 | "mov.l %1, @%0 ! __raw_write_unlock \n\t" |
167 | : | ||
168 | : "r" (&rw->lock), "r" (RW_LOCK_BIAS) | ||
169 | : "t", "memory" | ||
170 | ); | ||
90 | } | 171 | } |
91 | 172 | ||
92 | static inline int __raw_write_can_lock(raw_rwlock_t *rw) | 173 | static inline int __raw_read_trylock(raw_rwlock_t *rw) |
93 | { | 174 | { |
94 | return (atomic_read(&rw->counter) == RW_LOCK_BIAS); | 175 | unsigned long tmp, oldval; |
95 | } | ||
96 | 176 | ||
97 | static inline int __raw_read_trylock(raw_rwlock_t *lock) | 177 | __asm__ __volatile__ ( |
98 | { | 178 | "1: \n\t" |
99 | atomic_t *count = (atomic_t*)lock; | 179 | "movli.l @%2, %0 ! __raw_read_trylock \n\t" |
100 | if (atomic_dec_return(count) >= 0) | 180 | "mov %0, %1 \n\t" |
101 | return 1; | 181 | "cmp/pl %0 \n\t" |
102 | atomic_inc(count); | 182 | "bf 2f \n\t" |
103 | return 0; | 183 | "add #-1, %0 \n\t" |
184 | "movco.l %0, @%2 \n\t" | ||
185 | "bf 1b \n\t" | ||
186 | "2: \n\t" | ||
187 | "synco \n\t" | ||
188 | : "=&z" (tmp), "=&r" (oldval) | ||
189 | : "r" (&rw->lock) | ||
190 | : "t", "memory" | ||
191 | ); | ||
192 | |||
193 | return (oldval > 0); | ||
104 | } | 194 | } |
105 | 195 | ||
106 | static inline int __raw_write_trylock(raw_rwlock_t *rw) | 196 | static inline int __raw_write_trylock(raw_rwlock_t *rw) |
107 | { | 197 | { |
108 | if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter)) | 198 | unsigned long tmp, oldval; |
109 | return 1; | 199 | |
110 | 200 | __asm__ __volatile__ ( | |
111 | atomic_add(RW_LOCK_BIAS, &rw->counter); | 201 | "1: \n\t" |
202 | "movli.l @%2, %0 ! __raw_write_trylock \n\t" | ||
203 | "mov %0, %1 \n\t" | ||
204 | "cmp/hs %3, %0 \n\t" | ||
205 | "bf 2f \n\t" | ||
206 | "sub %3, %0 \n\t" | ||
207 | "2: \n\t" | ||
208 | "movco.l %0, @%2 \n\t" | ||
209 | "bf 1b \n\t" | ||
210 | "synco \n\t" | ||
211 | : "=&z" (tmp), "=&r" (oldval) | ||
212 | : "r" (&rw->lock), "r" (RW_LOCK_BIAS) | ||
213 | : "t", "memory" | ||
214 | ); | ||
112 | 215 | ||
113 | return 0; | 216 | return (oldval > (RW_LOCK_BIAS - 1)); |
114 | } | 217 | } |
115 | 218 | ||
116 | #define _raw_spin_relax(lock) cpu_relax() | 219 | #define _raw_spin_relax(lock) cpu_relax() |
diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h index 5c58134f2c4e..b4d244e7b60c 100644 --- a/include/asm-sh/spinlock_types.h +++ b/include/asm-sh/spinlock_types.h | |||
@@ -6,19 +6,16 @@ | |||
6 | #endif | 6 | #endif |
7 | 7 | ||
8 | typedef struct { | 8 | typedef struct { |
9 | volatile unsigned long lock; | 9 | volatile unsigned int lock; |
10 | } raw_spinlock_t; | 10 | } raw_spinlock_t; |
11 | 11 | ||
12 | #define __RAW_SPIN_LOCK_UNLOCKED { 1 } | 12 | #define __RAW_SPIN_LOCK_UNLOCKED { 1 } |
13 | |||
14 | #include <asm/atomic.h> | ||
15 | 13 | ||
16 | typedef struct { | 14 | typedef struct { |
17 | raw_spinlock_t lock; | 15 | volatile unsigned int lock; |
18 | atomic_t counter; | ||
19 | } raw_rwlock_t; | 16 | } raw_rwlock_t; |
20 | 17 | ||
21 | #define RW_LOCK_BIAS 0x01000000 | 18 | #define RW_LOCK_BIAS 0x01000000 |
22 | #define __RAW_RW_LOCK_UNLOCKED { { 0 }, { RW_LOCK_BIAS } } | 19 | #define __RAW_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } |
23 | 20 | ||
24 | #endif | 21 | #endif |
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 245042537205..9d849e6df268 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h | |||
@@ -266,6 +266,7 @@ void disable_hlt(void); | |||
266 | void enable_hlt(void); | 266 | void enable_hlt(void); |
267 | 267 | ||
268 | void default_idle(void); | 268 | void default_idle(void); |
269 | void per_cpu_trap_init(void); | ||
269 | 270 | ||
270 | asmlinkage void break_point_trap(void); | 271 | asmlinkage void break_point_trap(void); |
271 | asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, | 272 | asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5, |
diff --git a/include/asm-sh/voyagergx.h b/include/asm-sh/voyagergx.h index 64c936b22715..d825596562df 100644 --- a/include/asm-sh/voyagergx.h +++ b/include/asm-sh/voyagergx.h | |||
@@ -27,13 +27,35 @@ | |||
27 | #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) | 27 | #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) |
28 | #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) | 28 | #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) |
29 | 29 | ||
30 | #define VOYAGER_IRQ_NUM 32 | 30 | #define VOYAGER_IRQ_NUM 26 |
31 | #define VOYAGER_IRQ_BASE 50 | 31 | #define VOYAGER_IRQ_BASE 200 |
32 | #define VOYAGER_USBH_IRQ VOYAGER_IRQ_BASE + 6 | 32 | |
33 | #define VOYAGER_8051_IRQ VOYAGER_IRQ_BASE + 10 | 33 | #define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0) |
34 | #define VOYAGER_UART0_IRQ VOYAGER_IRQ_BASE + 12 | 34 | #define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1) |
35 | #define VOYAGER_UART1_IRQ VOYAGER_IRQ_BASE + 13 | 35 | #define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2) |
36 | #define VOYAGER_AC97_IRQ VOYAGER_IRQ_BASE + 17 | 36 | #define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3) |
37 | #define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4) | ||
38 | #define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5) | ||
39 | #define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6) | ||
40 | #define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7) | ||
41 | #define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8) | ||
42 | #define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9) | ||
43 | #define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10) | ||
44 | #define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11) | ||
45 | #define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12) | ||
46 | #define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13) | ||
47 | #define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14) | ||
48 | #define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15) | ||
49 | #define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16) | ||
50 | #define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17) | ||
51 | #define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18) | ||
52 | #define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19) | ||
53 | #define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20) | ||
54 | #define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21) | ||
55 | #define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22) | ||
56 | #define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23) | ||
57 | #define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24) | ||
58 | #define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25) | ||
37 | 59 | ||
38 | /* ----- MISC controle register ------------------------------ */ | 60 | /* ----- MISC controle register ------------------------------ */ |
39 | #define MISC_CTRL (0x000004 + VOYAGER_BASE) | 61 | #define MISC_CTRL (0x000004 + VOYAGER_BASE) |
@@ -313,4 +335,7 @@ | |||
313 | void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t); | 335 | void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t); |
314 | int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t); | 336 | int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t); |
315 | 337 | ||
338 | /* arch/sh/cchips/voyagergx/irq.c */ | ||
339 | void setup_voyagergx_irq(void); | ||
340 | |||
316 | #endif /* _VOYAGER_GX_REG_H */ | 341 | #endif /* _VOYAGER_GX_REG_H */ |