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authorJamie Lenehan <lenehan@twibble.org>2006-12-05 22:05:02 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-12-05 22:05:02 -0500
commitea0f8feaa041f3ccec3d6b8ee51325b177daef06 (patch)
tree261c7d75e5caccbaface63370bae029ecd81b98a /include/asm-sh/titan.h
parentfe9687dec0400c6de7187ab5efa91facd958ca84 (diff)
sh: sh775x/titan fixes for irq header changes.
The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/titan.h')
-rw-r--r--include/asm-sh/titan.h32
1 files changed, 3 insertions, 29 deletions
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h
index 270a4f4bc8a9..03f3583c8918 100644
--- a/include/asm-sh/titan.h
+++ b/include/asm-sh/titan.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Platform defintions for Titan 2 * Platform defintions for Titan
3 */ 3 */
4 4#ifndef _ASM_SH_TITAN_H
5#ifndef _ASM_SH_TITAN_TITAN_H 5#define _ASM_SH_TITAN_H
6#define _ASM_SH_TITAN_TITAN_H
7 6
8#define __IO_PREFIX titan 7#define __IO_PREFIX titan
9#include <asm/io_generic.h> 8#include <asm/io_generic.h>
@@ -15,29 +14,4 @@
15#define TITAN_IRQ_MPCIB 11 /* mPCI B */ 14#define TITAN_IRQ_MPCIB 11 /* mPCI B */
16#define TITAN_IRQ_USB 11 /* USB */ 15#define TITAN_IRQ_USB 11 /* USB */
17 16
18/* 17#endif /* __ASM_SH_TITAN_H */
19 * The external interrupt lines, these take up ints 0 - 15 inclusive
20 * depending on the priority for the interrupt. In fact the priority
21 * is the interrupt :-)
22 */
23#define IRL0_IRQ 0
24#define IRL0_IPR_ADDR INTC_IPRD
25#define IRL0_IPR_POS 3
26#define IRL0_PRIORITY 8
27
28#define IRL1_IRQ 1
29#define IRL1_IPR_ADDR INTC_IPRD
30#define IRL1_IPR_POS 2
31#define IRL1_PRIORITY 8
32
33#define IRL2_IRQ 2
34#define IRL2_IPR_ADDR INTC_IPRD
35#define IRL2_IPR_POS 1
36#define IRL2_PRIORITY 8
37
38#define IRL3_IRQ 3
39#define IRL3_IPR_ADDR INTC_IPRD
40#define IRL3_IPR_POS 0
41#define IRL3_PRIORITY 8
42
43#endif