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authorPaul Mundt <lethal@linux-sh.org>2007-11-10 05:46:31 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:18:42 -0500
commita62a3861e0adfd2612372883b5b1fc05a5182796 (patch)
treed3ff2c41f2a059173c8959f006bef770de528a0b /include/asm-sh/system_32.h
parent36bcd39dbca824daffe16d607ae574b6edc7d31a (diff)
sh: Split out system.h in to _32 and _64 variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/system_32.h')
-rw-r--r--include/asm-sh/system_32.h97
1 files changed, 97 insertions, 0 deletions
diff --git a/include/asm-sh/system_32.h b/include/asm-sh/system_32.h
new file mode 100644
index 000000000000..ad37e8d5f31e
--- /dev/null
+++ b/include/asm-sh/system_32.h
@@ -0,0 +1,97 @@
1#ifndef __ASM_SH_SYSTEM_32_H
2#define __ASM_SH_SYSTEM_32_H
3
4#include <linux/types.h>
5
6struct task_struct *__switch_to(struct task_struct *prev,
7 struct task_struct *next);
8
9/*
10 * switch_to() should switch tasks to task nr n, first
11 */
12#define switch_to(prev, next, last) \
13do { \
14 register u32 *__ts1 __asm__ ("r1") = &prev->thread.sp; \
15 register u32 *__ts2 __asm__ ("r2") = &prev->thread.pc; \
16 register u32 *__ts4 __asm__ ("r4") = (u32 *)prev; \
17 register u32 *__ts5 __asm__ ("r5") = (u32 *)next; \
18 register u32 *__ts6 __asm__ ("r6") = &next->thread.sp; \
19 register u32 __ts7 __asm__ ("r7") = next->thread.pc; \
20 struct task_struct *__last; \
21 \
22 __asm__ __volatile__ ( \
23 ".balign 4\n\t" \
24 "stc.l gbr, @-r15\n\t" \
25 "sts.l pr, @-r15\n\t" \
26 "mov.l r8, @-r15\n\t" \
27 "mov.l r9, @-r15\n\t" \
28 "mov.l r10, @-r15\n\t" \
29 "mov.l r11, @-r15\n\t" \
30 "mov.l r12, @-r15\n\t" \
31 "mov.l r13, @-r15\n\t" \
32 "mov.l r14, @-r15\n\t" \
33 "mov.l r15, @r1\t! save SP\n\t" \
34 "mov.l @r6, r15\t! change to new stack\n\t" \
35 "mova 1f, %0\n\t" \
36 "mov.l %0, @r2\t! save PC\n\t" \
37 "mov.l 2f, %0\n\t" \
38 "jmp @%0\t! call __switch_to\n\t" \
39 " lds r7, pr\t! with return to new PC\n\t" \
40 ".balign 4\n" \
41 "2:\n\t" \
42 ".long __switch_to\n" \
43 "1:\n\t" \
44 "mov.l @r15+, r14\n\t" \
45 "mov.l @r15+, r13\n\t" \
46 "mov.l @r15+, r12\n\t" \
47 "mov.l @r15+, r11\n\t" \
48 "mov.l @r15+, r10\n\t" \
49 "mov.l @r15+, r9\n\t" \
50 "mov.l @r15+, r8\n\t" \
51 "lds.l @r15+, pr\n\t" \
52 "ldc.l @r15+, gbr\n\t" \
53 : "=z" (__last) \
54 : "r" (__ts1), "r" (__ts2), "r" (__ts4), \
55 "r" (__ts5), "r" (__ts6), "r" (__ts7) \
56 : "r3", "t"); \
57 \
58 last = __last; \
59} while (0)
60
61/*
62 * Jump to P2 area.
63 * When handling TLB or caches, we need to do it from P2 area.
64 */
65#define jump_to_P2() \
66do { \
67 unsigned long __dummy; \
68 __asm__ __volatile__( \
69 "mov.l 1f, %0\n\t" \
70 "or %1, %0\n\t" \
71 "jmp @%0\n\t" \
72 " nop\n\t" \
73 ".balign 4\n" \
74 "1: .long 2f\n" \
75 "2:" \
76 : "=&r" (__dummy) \
77 : "r" (0x20000000)); \
78} while (0)
79
80/*
81 * Back to P1 area.
82 */
83#define back_to_P1() \
84do { \
85 unsigned long __dummy; \
86 ctrl_barrier(); \
87 __asm__ __volatile__( \
88 "mov.l 1f, %0\n\t" \
89 "jmp @%0\n\t" \
90 " nop\n\t" \
91 ".balign 4\n" \
92 "1: .long 2f\n" \
93 "2:" \
94 : "=&r" (__dummy)); \
95} while (0)
96
97#endif /* __ASM_SH_SYSTEM_32_H */