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authorMagnus Damm <damm@igel.co.jp>2007-06-15 05:56:19 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-06-15 05:56:19 -0400
commit68abdbbb03476a60d932eeba0035dd5069afec38 (patch)
treede3854f76d6d9aec121c432a3cd276bb756003c9 /include/asm-sh/snapgear.h
parent50f63f2518ee68bc132d357d2b6fdb7f60ef79e0 (diff)
sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together with the ipr_data structure in a new data structure called ipr_desc. This new structure also contains the name of the controller in struct irq_chip. The idea behind putting struct irq_chip in there is that we can use offsetof() to locate the base addresses in the irq_chip callbacks. This strategy has much in common with the recently merged intc2 code. One logic change has been made - the original ipr code enabled the interrupts by default but with this patch they are all disabled by default. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/snapgear.h')
-rw-r--r--include/asm-sh/snapgear.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 2d712e72c9e5..3554e3a74e99 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -20,22 +20,18 @@
20 */ 20 */
21 21
22#define IRL0_IRQ 2 22#define IRL0_IRQ 2
23#define IRL0_IPR_ADDR INTC_IPRD
24#define IRL0_IPR_POS 3 23#define IRL0_IPR_POS 3
25#define IRL0_PRIORITY 13 24#define IRL0_PRIORITY 13
26 25
27#define IRL1_IRQ 5 26#define IRL1_IRQ 5
28#define IRL1_IPR_ADDR INTC_IPRD
29#define IRL1_IPR_POS 2 27#define IRL1_IPR_POS 2
30#define IRL1_PRIORITY 10 28#define IRL1_PRIORITY 10
31 29
32#define IRL2_IRQ 8 30#define IRL2_IRQ 8
33#define IRL2_IPR_ADDR INTC_IPRD
34#define IRL2_IPR_POS 1 31#define IRL2_IPR_POS 1
35#define IRL2_PRIORITY 7 32#define IRL2_PRIORITY 7
36 33
37#define IRL3_IRQ 11 34#define IRL3_IRQ 11
38#define IRL3_IPR_ADDR INTC_IPRD
39#define IRL3_IPR_POS 0 35#define IRL3_IPR_POS 0
40#define IRL3_PRIORITY 4 36#define IRL3_PRIORITY 4
41#endif 37#endif