diff options
author | Magnus Damm <damm@igel.co.jp> | 2007-06-15 05:56:19 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-06-15 05:56:19 -0400 |
commit | 68abdbbb03476a60d932eeba0035dd5069afec38 (patch) | |
tree | de3854f76d6d9aec121c432a3cd276bb756003c9 /include/asm-sh/sh03 | |
parent | 50f63f2518ee68bc132d357d2b6fdb7f60ef79e0 (diff) |
sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together
with the ipr_data structure in a new data structure called ipr_desc.
This new structure also contains the name of the controller in struct
irq_chip. The idea behind putting struct irq_chip in there is that we
can use offsetof() to locate the base addresses in the irq_chip
callbacks. This strategy has much in common with the recently merged
intc2 code.
One logic change has been made - the original ipr code enabled the
interrupts by default but with this patch they are all disabled by
default.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/sh03')
-rw-r--r-- | include/asm-sh/sh03/io.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h index df3b187ef883..4ff1eb900301 100644 --- a/include/asm-sh/sh03/io.h +++ b/include/asm-sh/sh03/io.h | |||
@@ -14,22 +14,18 @@ | |||
14 | #define INTC_IPRD 0xffd00010UL | 14 | #define INTC_IPRD 0xffd00010UL |
15 | 15 | ||
16 | #define IRL0_IRQ 2 | 16 | #define IRL0_IRQ 2 |
17 | #define IRL0_IPR_ADDR INTC_IPRD | ||
18 | #define IRL0_IPR_POS 3 | 17 | #define IRL0_IPR_POS 3 |
19 | #define IRL0_PRIORITY 13 | 18 | #define IRL0_PRIORITY 13 |
20 | 19 | ||
21 | #define IRL1_IRQ 5 | 20 | #define IRL1_IRQ 5 |
22 | #define IRL1_IPR_ADDR INTC_IPRD | ||
23 | #define IRL1_IPR_POS 2 | 21 | #define IRL1_IPR_POS 2 |
24 | #define IRL1_PRIORITY 10 | 22 | #define IRL1_PRIORITY 10 |
25 | 23 | ||
26 | #define IRL2_IRQ 8 | 24 | #define IRL2_IRQ 8 |
27 | #define IRL2_IPR_ADDR INTC_IPRD | ||
28 | #define IRL2_IPR_POS 1 | 25 | #define IRL2_IPR_POS 1 |
29 | #define IRL2_PRIORITY 7 | 26 | #define IRL2_PRIORITY 7 |
30 | 27 | ||
31 | #define IRL3_IRQ 11 | 28 | #define IRL3_IRQ 11 |
32 | #define IRL3_IPR_ADDR INTC_IPRD | ||
33 | #define IRL3_IPR_POS 0 | 29 | #define IRL3_IPR_POS 0 |
34 | #define IRL3_PRIORITY 4 | 30 | #define IRL3_PRIORITY 4 |
35 | 31 | ||