sh: Support for L2 cache on newer SH-4A CPUs.

This implements preliminary support for the L2 caches found
on newer SH-4A CPUs.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 5 insertions, 4 deletions

diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index bdd472705546..b7cba4e91a72 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -54,14 +54,15 @@ enum cpu_type {
 };
 
 struct sh_cpuinfo {
-        enum cpu_type type;
+        unsigned int type;
         unsigned long loops_per_jiffy;
 
-        struct cache_info icache;
-        struct cache_info dcache;
+        struct cache_info icache;       /* Primary I-cache */
+        struct cache_info dcache;       /* Primary D-cache */
+        struct cache_info scache;       /* Secondary cache */
 
         unsigned long flags;
-};
+} __attribute__ ((aligned(SMP_CACHE_BYTES)));
 
 extern struct sh_cpuinfo boot_cpu_data;