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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
commite5723e0eeb2dc16629e86d66785024ead9169000 (patch)
tree7fe39cdaf3106cc726d3b84fdc998b382b6c5e22 /include/asm-sh/irq.h
parentecd9561687a0952a96a0a705f618e59cb6f3189b (diff)
sh: Add support for SH7706/SH7710/SH7343 CPUs.
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/irq.h')
-rw-r--r--include/asm-sh/irq.h119
1 files changed, 115 insertions, 4 deletions
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 648102e9236f..00886f9adb4d 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -192,7 +192,7 @@
192 192
193#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \ 193#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \ 194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
195 defined (CONFIG_CPU_SUBTYPE_SH7751) 195 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
196#define SCI_ERI_IRQ 23 196#define SCI_ERI_IRQ 23
197#define SCI_RXI_IRQ 24 197#define SCI_RXI_IRQ 24
198#define SCI_TXI_IRQ 25 198#define SCI_TXI_IRQ 25
@@ -207,6 +207,7 @@
207#define SCIF0_IPR_POS 3 207#define SCIF0_IPR_POS 3
208#define SCIF0_PRIORITY 3 208#define SCIF0_PRIORITY 3
209#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 209#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 211 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7709) 212 defined(CONFIG_CPU_SUBTYPE_SH7709)
212#define SCIF_ERI_IRQ 56 213#define SCIF_ERI_IRQ 56
@@ -261,9 +262,12 @@
261#elif defined(CONFIG_CPU_SUBTYPE_SH7708) 262#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
262# define ONCHIP_NR_IRQS 32 263# define ONCHIP_NR_IRQS 32
263#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 264#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7705) 266 defined(CONFIG_CPU_SUBTYPE_SH7705)
265# define ONCHIP_NR_IRQS 64 // Actually 61 267# define ONCHIP_NR_IRQS 64 // Actually 61
266# define PINT_NR_IRQS 16 268# define PINT_NR_IRQS 16
269#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
270# define ONCHIP_NR_IRQS 104
267#elif defined(CONFIG_CPU_SUBTYPE_SH7750) 271#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
268# define ONCHIP_NR_IRQS 48 // Actually 44 272# define ONCHIP_NR_IRQS 48 // Actually 44
269#elif defined(CONFIG_CPU_SUBTYPE_SH7751) 273#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
@@ -275,7 +279,8 @@
275#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 279#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
276# define ONCHIP_NR_IRQS 144 280# define ONCHIP_NR_IRQS 144
277#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 281#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
278 defined(CONFIG_CPU_SUBTYPE_SH73180) 282 defined(CONFIG_CPU_SUBTYPE_SH73180) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7343)
279# define ONCHIP_NR_IRQS 109 284# define ONCHIP_NR_IRQS 109
280#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 285#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
281# define ONCHIP_NR_IRQS 111 286# define ONCHIP_NR_IRQS 111
@@ -476,8 +481,10 @@ extern int ipr_irq_demux(int irq);
476 481
477#define INTC_ICR 0xfffffee0UL 482#define INTC_ICR 0xfffffee0UL
478#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 483#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
484 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
479 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 485 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
480 defined(CONFIG_CPU_SUBTYPE_SH7709) 486 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
487 defined(CONFIG_CPU_SUBTYPE_SH7710)
481#define INTC_IRR0 0xa4000004UL 488#define INTC_IRR0 0xa4000004UL
482#define INTC_IRR1 0xa4000006UL 489#define INTC_IRR1 0xa4000006UL
483#define INTC_IRR2 0xa4000008UL 490#define INTC_IRR2 0xa4000008UL
@@ -496,8 +503,105 @@ extern int ipr_irq_demux(int irq);
496#define INTC_IPRF 0xa4080000UL 503#define INTC_IPRF 0xa4080000UL
497#define INTC_IPRG 0xa4080002UL 504#define INTC_IPRG 0xa4080002UL
498#define INTC_IPRH 0xa4080004UL 505#define INTC_IPRH 0xa4080004UL
499#endif 506#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
507/* Interrupt Controller Registers */
508#undef INTC_IPRA
509#undef INTC_IPRB
510#define INTC_IPRA 0xA414FEE2UL
511#define INTC_IPRB 0xA414FEE4UL
512#define INTC_IPRF 0xA4080000UL
513#define INTC_IPRG 0xA4080002UL
514#define INTC_IPRH 0xA4080004UL
515#define INTC_IPRI 0xA4080006UL
516
517#undef INTC_ICR0
518#undef INTC_ICR1
519#define INTC_ICR0 0xA414FEE0UL
520#define INTC_ICR1 0xA4140010UL
521
522#define INTC_IRR0 0xa4000004UL
523#define INTC_IRR1 0xa4000006UL
524#define INTC_IRR2 0xa4000008UL
525#define INTC_IRR3 0xa400000AUL
526#define INTC_IRR4 0xa400000CUL
527#define INTC_IRR5 0xa4080020UL
528#define INTC_IRR7 0xa4080024UL
529#define INTC_IRR8 0xa4080026UL
530
531/* Interrupt numbers */
532#define TIMER2_IRQ 18
533#define TIMER2_IPR_ADDR INTC_IPRA
534#define TIMER2_IPR_POS 1
535#define TIMER2_PRIORITY 2
500 536
537/* WDT */
538#define WDT_IRQ 27
539#define WDT_IPR_ADDR INTC_IPRB
540#define WDT_IPR_POS 3
541#define WDT_PRIORITY 2
542
543#define SCIF0_ERI_IRQ 52
544#define SCIF0_RXI_IRQ 53
545#define SCIF0_BRI_IRQ 54
546#define SCIF0_TXI_IRQ 55
547#define SCIF0_IPR_ADDR INTC_IPRE
548#define SCIF0_IPR_POS 2
549#define SCIF0_PRIORITY 3
550
551#define DMTE4_IRQ 76
552#define DMTE5_IRQ 77
553#define DMA2_IPR_ADDR INTC_IPRF
554#define DMA2_IPR_POS 2
555#define DMA2_PRIORITY 7
556
557#define IPSEC_IRQ 79
558#define IPSEC_IPR_ADDR INTC_IPRF
559#define IPSEC_IPR_POS 3
560#define IPSEC_PRIORITY 3
561
562/* EDMAC */
563#define EDMAC0_IRQ 80
564#define EDMAC0_IPR_ADDR INTC_IPRG
565#define EDMAC0_IPR_POS 3
566#define EDMAC0_PRIORITY 3
567
568#define EDMAC1_IRQ 81
569#define EDMAC1_IPR_ADDR INTC_IPRG
570#define EDMAC1_IPR_POS 2
571#define EDMAC1_PRIORITY 3
572
573#define EDMAC2_IRQ 82
574#define EDMAC2_IPR_ADDR INTC_IPRG
575#define EDMAC2_IPR_POS 1
576#define EDMAC2_PRIORITY 3
577
578/* SIOF */
579#define SIOF0_ERI_IRQ 96
580#define SIOF0_TXI_IRQ 97
581#define SIOF0_RXI_IRQ 98
582#define SIOF0_CCI_IRQ 99
583#define SIOF0_IPR_ADDR INTC_IPRH
584#define SIOF0_IPR_POS 0
585#define SIOF0_PRIORITY 7
586
587#define SIOF1_ERI_IRQ 100
588#define SIOF1_TXI_IRQ 101
589#define SIOF1_RXI_IRQ 102
590#define SIOF1_CCI_IRQ 103
591#define SIOF1_IPR_ADDR INTC_IPRI
592#define SIOF1_IPR_POS 1
593#define SIOF1_PRIORITY 7
594#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
595
596#if defined(CONFIG_CPU_SUBTYPE_SH7710)
597#define PORT_PACR 0xa4050100UL
598#define PORT_PBCR 0xa4050102UL
599#define PORT_PCCR 0xa4050104UL
600#define PORT_PETCR 0xa4050106UL
601#define PORT_PADR 0xa4050120UL
602#define PORT_PBDR 0xa4050122UL
603#define PORT_PCDR 0xa4050124UL
604#else
501#define PORT_PACR 0xa4000100UL 605#define PORT_PACR 0xa4000100UL
502#define PORT_PBCR 0xa4000102UL 606#define PORT_PBCR 0xa4000102UL
503#define PORT_PCCR 0xa4000104UL 607#define PORT_PCCR 0xa4000104UL
@@ -506,6 +610,7 @@ extern int ipr_irq_demux(int irq);
506#define PORT_PBDR 0xa4000122UL 610#define PORT_PBDR 0xa4000122UL
507#define PORT_PCDR 0xa4000124UL 611#define PORT_PCDR 0xa4000124UL
508#define PORT_PFDR 0xa400012aUL 612#define PORT_PFDR 0xa400012aUL
613#endif
509 614
510#define IRQ0_IRQ 32 615#define IRQ0_IRQ 32
511#define IRQ1_IRQ 33 616#define IRQ1_IRQ 33
@@ -599,6 +704,8 @@ void intc2_add_clear_irq(int irq, int (*fn)(int));
599 704
600#endif 705#endif
601 706
707extern int shmse_irq_demux(int irq);
708
602static inline int generic_irq_demux(int irq) 709static inline int generic_irq_demux(int irq)
603{ 710{
604 return irq; 711 return irq;
@@ -614,4 +721,8 @@ static inline int generic_irq_demux(int irq)
614#include <asm/irq-sh73180.h> 721#include <asm/irq-sh73180.h>
615#endif 722#endif
616 723
724#if defined(CONFIG_CPU_SUBTYPE_SH7343)
725#include <asm/irq-sh7343.h>
726#endif
727
617#endif /* __ASM_SH_IRQ_H */ 728#endif /* __ASM_SH_IRQ_H */