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authorPaul Mundt <lethal@linux-sh.org>2006-01-17 01:14:14 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-01-17 02:15:28 -0500
commitbf3a00f88c926635932c91afd90b4a0907dfbe78 (patch)
tree179a56c061461a0f3d25cd0171ba8ce90e5e7ed5 /include/asm-sh/irq-sh7780.h
parent9d44190eae97ad4c9ce30f1084e1b0dabd646df5 (diff)
[PATCH] sh: IRQ handler updates
This moves the various IRQ controller drivers into a new subdirectory, and also extends the INTC2 IRQ handler to also deal with SH7760 and SH7780 interrupts, rather than just ST-40. The old CONFIG_SH_GENERIC has also been removed from the IRQ definitions, as new ports are expected to be based off of CONFIG_SH_UNKNOWN. Since there are plenty of incompatible machvecs, CONFIG_SH_GENERIC doesn't make sense anymore. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-sh/irq-sh7780.h')
-rw-r--r--include/asm-sh/irq-sh7780.h349
1 files changed, 349 insertions, 0 deletions
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
new file mode 100644
index 000000000000..8c8ca1281084
--- /dev/null
+++ b/include/asm-sh/irq-sh7780.h
@@ -0,0 +1,349 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#ifdef CONFIG_IDE
11# ifndef IRQ_CFCARD
12# define IRQ_CFCARD 14
13# endif
14# ifndef IRQ_PCMCIA
15# define IRQ_PCMCIA 15
16# endif
17#endif
18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR0 (INTC_BASE+0x0)
21#define INTC_ICR1 (INTC_BASE+0x1c)
22#define INTC_INTPRI (INTC_BASE+0x10)
23#define INTC_INTREQ (INTC_BASE+0x24)
24#define INTC_INTMSK0 (INTC_BASE+0x44)
25#define INTC_INTMSK1 (INTC_BASE+0x48)
26#define INTC_INTMSK2 (INTC_BASE+0x40080)
27#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
28#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
29#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
30#define INTC_NMIFCR (INTC_BASE+0xc0)
31#define INTC_USERIMASK (INTC_BASE+0x30000)
32
33#define INTC_INT2PRI0 (INTC_BASE+0x40000)
34#define INTC_INT2PRI1 (INTC_BASE+0x40004)
35#define INTC_INT2PRI2 (INTC_BASE+0x40008)
36#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
37#define INTC_INT2PRI4 (INTC_BASE+0x40010)
38#define INTC_INT2PRI5 (INTC_BASE+0x40014)
39#define INTC_INT2PRI6 (INTC_BASE+0x40018)
40#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
41#define INTC_INT2A0 (INTC_BASE+0x40030)
42#define INTC_INT2A1 (INTC_BASE+0x40034)
43#define INTC_INT2MSKR (INTC_BASE+0x40038)
44#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
45#define INTC_INT2B0 (INTC_BASE+0x40040)
46#define INTC_INT2B1 (INTC_BASE+0x40044)
47#define INTC_INT2B2 (INTC_BASE+0x40048)
48#define INTC_INT2B3 (INTC_BASE+0x4004c)
49#define INTC_INT2B4 (INTC_BASE+0x40050)
50#define INTC_INT2B5 (INTC_BASE+0x40054)
51#define INTC_INT2B6 (INTC_BASE+0x40058)
52#define INTC_INT2B7 (INTC_BASE+0x4005c)
53#define INTC_INT2GPIC (INTC_BASE+0x40090)
54/*
55 NOTE:
56 *_IRQ = (INTEVT2 - 0x200)/0x20
57*/
58/* IRQ 0-7 line external int*/
59#define IRQ0_IRQ 2
60#define IRQ0_IPR_ADDR INTC_INTPRI
61#define IRQ0_IPR_POS 7
62#define IRQ0_PRIORITY 2
63
64#define IRQ1_IRQ 4
65#define IRQ1_IPR_ADDR INTC_INTPRI
66#define IRQ1_IPR_POS 6
67#define IRQ1_PRIORITY 2
68
69#define IRQ2_IRQ 6
70#define IRQ2_IPR_ADDR INTC_INTPRI
71#define IRQ2_IPR_POS 5
72#define IRQ2_PRIORITY 2
73
74#define IRQ3_IRQ 8
75#define IRQ3_IPR_ADDR INTC_INTPRI
76#define IRQ3_IPR_POS 4
77#define IRQ3_PRIORITY 2
78
79#define IRQ4_IRQ 10
80#define IRQ4_IPR_ADDR INTC_INTPRI
81#define IRQ4_IPR_POS 3
82#define IRQ4_PRIORITY 2
83
84#define IRQ5_IRQ 12
85#define IRQ5_IPR_ADDR INTC_INTPRI
86#define IRQ5_IPR_POS 2
87#define IRQ5_PRIORITY 2
88
89#define IRQ6_IRQ 14
90#define IRQ6_IPR_ADDR INTC_INTPRI
91#define IRQ6_IPR_POS 1
92#define IRQ6_PRIORITY 2
93
94#define IRQ7_IRQ 0
95#define IRQ7_IPR_ADDR INTC_INTPRI
96#define IRQ7_IPR_POS 0
97#define IRQ7_PRIORITY 2
98
99/* TMU */
100/* ch0 */
101#define TMU_IRQ 28
102#define TMU_IPR_ADDR INTC_INT2PRI0
103#define TMU_IPR_POS 3
104#define TMU_PRIORITY 2
105
106#define TIMER_IRQ 28
107#define TIMER_IPR_ADDR INTC_INT2PRI0
108#define TIMER_IPR_POS 3
109#define TIMER_PRIORITY 2
110
111/* ch 1*/
112#define TMU_CH1_IRQ 29
113#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
114#define TMU_CH1_IPR_POS 2
115#define TMU_CH1_PRIORITY 2
116
117#define TIMER1_IRQ 29
118#define TIMER1_IPR_ADDR INTC_INT2PRI0
119#define TIMER1_IPR_POS 2
120#define TIMER1_PRIORITY 2
121
122/* ch 2*/
123#define TMU_CH2_IRQ 30
124#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
125#define TMU_CH2_IPR_POS 1
126#define TMU_CH2_PRIORITY 2
127/* ch 2 Input capture */
128#define TMU_CH2IC_IRQ 31
129#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
130#define TMU_CH2IC_IPR_POS 0
131#define TMU_CH2IC_PRIORITY 2
132/* ch 3 */
133#define TMU_CH3_IRQ 96
134#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH3_IPR_POS 3
136#define TMU_CH3_PRIORITY 2
137/* ch 4 */
138#define TMU_CH4_IRQ 97
139#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
140#define TMU_CH4_IPR_POS 2
141#define TMU_CH4_PRIORITY 2
142/* ch 5*/
143#define TMU_CH5_IRQ 98
144#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
145#define TMU_CH5_IPR_POS 1
146#define TMU_CH5_PRIORITY 2
147
148#define RTC_IRQ 22
149#define RTC_IPR_ADDR INTC_INT2PRI1
150#define RTC_IPR_POS 0
151#define RTC_PRIORITY TIMER_PRIORITY
152
153/* SCIF0 */
154#define SCIF0_ERI_IRQ 40
155#define SCIF0_RXI_IRQ 41
156#define SCIF0_BRI_IRQ 42
157#define SCIF0_TXI_IRQ 43
158#define SCIF0_IPR_ADDR INTC_INT2PRI2
159#define SCIF0_IPR_POS 3
160#define SCIF0_PRIORITY 3
161
162/* SCIF1 */
163#define SCIF1_ERI_IRQ 76
164#define SCIF1_RXI_IRQ 77
165#define SCIF1_BRI_IRQ 78
166#define SCIF1_TXI_IRQ 79
167#define SCIF1_IPR_ADDR INTC_INT2PRI2
168#define SCIF1_IPR_POS 2
169#define SCIF1_PRIORITY 3
170
171#define WDT_IRQ 27
172#define WDT_IPR_ADDR INTC_INT2PRI2
173#define WDT_IPR_POS 1
174#define WDT_PRIORITY 2
175
176/* DMAC(0) */
177#define DMINT0_IRQ 34
178#define DMINT1_IRQ 35
179#define DMINT2_IRQ 36
180#define DMINT3_IRQ 37
181#define DMINT4_IRQ 44
182#define DMINT5_IRQ 45
183#define DMINT6_IRQ 46
184#define DMINT7_IRQ 47
185#define DMAE_IRQ 38
186#define DMA0_IPR_ADDR INTC_INT2PRI3
187#define DMA0_IPR_POS 2
188#define DMA0_PRIORITY 7
189
190/* DMAC(1) */
191#define DMINT8_IRQ 92
192#define DMINT9_IRQ 93
193#define DMINT10_IRQ 94
194#define DMINT11_IRQ 95
195#define DMA1_IPR_ADDR INTC_INT2PRI3
196#define DMA1_IPR_POS 1
197#define DMA1_PRIORITY 7
198
199#define DMTE0_IRQ DMINT0_IRQ
200#define DMTE4_IRQ DMINT4_IRQ
201#define DMA_IPR_ADDR DMA0_IPR_ADDR
202#define DMA_IPR_POS DMA0_IPR_POS
203#define DMA_PRIORITY DMA0_PRIORITY
204
205/* CMT */
206#define CMT_IRQ 56
207#define CMT_IPR_ADDR INTC_INT2PRI4
208#define CMT_IPR_POS 3
209#define CMT_PRIORITY 0
210
211/* HAC */
212#define HAC_IRQ 60
213#define HAC_IPR_ADDR INTC_INT2PRI4
214#define HAC_IPR_POS 2
215#define CMT_PRIORITY 0
216
217/* PCIC(0) */
218#define PCIC0_IRQ 64
219#define PCIC0_IPR_ADDR INTC_INT2PRI4
220#define PCIC0_IPR_POS 1
221#define PCIC0_PRIORITY 2
222
223/* PCIC(1) */
224#define PCIC1_IRQ 65
225#define PCIC1_IPR_ADDR INTC_INT2PRI4
226#define PCIC1_IPR_POS 0
227#define PCIC1_PRIORITY 2
228
229/* PCIC(2) */
230#define PCIC2_IRQ 66
231#define PCIC2_IPR_ADDR INTC_INT2PRI5
232#define PCIC2_IPR_POS 3
233#define PCIC2_PRIORITY 2
234
235/* PCIC(3) */
236#define PCIC3_IRQ 67
237#define PCIC3_IPR_ADDR INTC_INT2PRI5
238#define PCIC3_IPR_POS 2
239#define PCIC3_PRIORITY 2
240
241/* PCIC(4) */
242#define PCIC4_IRQ 68
243#define PCIC4_IPR_ADDR INTC_INT2PRI5
244#define PCIC4_IPR_POS 1
245#define PCIC4_PRIORITY 2
246
247/* PCIC(5) */
248#define PCICERR_IRQ 69
249#define PCICPWD3_IRQ 70
250#define PCICPWD2_IRQ 71
251#define PCICPWD1_IRQ 72
252#define PCICPWD0_IRQ 73
253#define PCIC5_IPR_ADDR INTC_INT2PRI5
254#define PCIC5_IPR_POS 0
255#define PCIC5_PRIORITY 2
256
257/* SIOF */
258#define SIOF_IRQ 80
259#define SIOF_IPR_ADDR INTC_INT2PRI6
260#define SIOF_IPR_POS 3
261#define SIOF_PRIORITY 3
262
263/* HSPI */
264#define HSPI_IRQ 84
265#define HSPI_IPR_ADDR INTC_INT2PRI6
266#define HSPI_IPR_POS 2
267#define HSPI_PRIORITY 3
268
269/* MMCIF */
270#define MMCIF_FSTAT_IRQ 88
271#define MMCIF_TRAN_IRQ 89
272#define MMCIF_ERR_IRQ 90
273#define MMCIF_FRDY_IRQ 91
274#define MMCIF_IPR_ADDR INTC_INT2PRI6
275#define MMCIF_IPR_POS 1
276#define HSPI_PRIORITY 3
277
278/* SSI */
279#define SSI_IRQ 100
280#define SSI_IPR_ADDR INTC_INT2PRI6
281#define SSI_IPR_POS 0
282#define SSI_PRIORITY 3
283
284/* FLCTL */
285#define FLCTL_FLSTE_IRQ 104
286#define FLCTL_FLTEND_IRQ 105
287#define FLCTL_FLTRQ0_IRQ 106
288#define FLCTL_FLTRQ1_IRQ 107
289#define FLCTL_IPR_ADDR INTC_INT2PRI7
290#define FLCTL_IPR_POS 3
291#define FLCTL_PRIORITY 3
292
293/* GPIO */
294#define GPIO0_IRQ 108
295#define GPIO1_IRQ 109
296#define GPIO2_IRQ 110
297#define GPIO3_IRQ 111
298#define GPIO_IPR_ADDR INTC_INT2PRI7
299#define GPIO_IPR_POS 2
300#define GPIO_PRIORITY 3
301
302/* ONCHIP_NR_IRQS */
303#define NR_IRQS 150 /* 111 + 16 */
304
305/* In a generic kernel, NR_IRQS is an upper bound, and we should use
306 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
307 */
308#define ACTUAL_NR_IRQS NR_IRQS
309
310extern void disable_irq(unsigned int);
311extern void disable_irq_nosync(unsigned int);
312extern void enable_irq(unsigned int);
313
314/*
315 * Simple Mask Register Support
316 */
317extern void make_maskreg_irq(unsigned int irq);
318extern unsigned short *irq_mask_register;
319
320/*
321 * Function for "on chip support modules".
322 */
323extern void make_imask_irq(unsigned int irq);
324
325#define INTC_TMU0_MSK 0
326#define INTC_TMU3_MSK 1
327#define INTC_RTC_MSK 2
328#define INTC_SCIF0_MSK 3
329#define INTC_SCIF1_MSK 4
330#define INTC_WDT_MSK 5
331#define INTC_HUID_MSK 7
332#define INTC_DMAC0_MSK 8
333#define INTC_DMAC1_MSK 9
334#define INTC_CMT_MSK 12
335#define INTC_HAC_MSK 13
336#define INTC_PCIC0_MSK 14
337#define INTC_PCIC1_MSK 15
338#define INTC_PCIC2_MSK 16
339#define INTC_PCIC3_MSK 17
340#define INTC_PCIC4_MSK 18
341#define INTC_PCIC5_MSK 19
342#define INTC_SIOF_MSK 20
343#define INTC_HSPI_MSK 21
344#define INTC_MMCIF_MSK 22
345#define INTC_SSI_MSK 23
346#define INTC_FLCTL_MSK 24
347#define INTC_GPIO_MSK 25
348
349#endif /* __ASM_SH_IRQ_SH7780_H */