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authorPaul Mundt <lethal@linux-sh.org>2006-11-19 23:55:34 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-12-05 20:45:37 -0500
commit9a7ef6d59f9d4780ff5bc9c4d05266b52dcb9211 (patch)
tree47094da0cd858abb54607b139c41686d293b130f /include/asm-sh/irq-sh7780.h
parent417528a2e35f46bc42721de5c4efd33a0eba019d (diff)
sh: Drop CPU subtype IRQ headers.
This drops the various IRQ headers that were floating around and primarily providing hardcoded IRQ definitions for the various CPU subtypes. This quickly got to be an unmaintainable mess, made even more evident by the subtle breakage introduced by the SH-2 and SH-2A changes. Now that subtypes are able to register IRQ maps directly, just rip all of the headers out. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/irq-sh7780.h')
-rw-r--r--include/asm-sh/irq-sh7780.h311
1 files changed, 0 insertions, 311 deletions
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
deleted file mode 100644
index 19912ae6a7f7..000000000000
--- a/include/asm-sh/irq-sh7780.h
+++ /dev/null
@@ -1,311 +0,0 @@
1#ifndef __ASM_SH_IRQ_SH7780_H
2#define __ASM_SH_IRQ_SH7780_H
3
4/*
5 * linux/include/asm-sh/irq-sh7780.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9#define INTC_BASE 0xffd00000
10#define INTC_ICR0 (INTC_BASE+0x0)
11#define INTC_ICR1 (INTC_BASE+0x1c)
12#define INTC_INTPRI (INTC_BASE+0x10)
13#define INTC_INTREQ (INTC_BASE+0x24)
14#define INTC_INTMSK0 (INTC_BASE+0x44)
15#define INTC_INTMSK1 (INTC_BASE+0x48)
16#define INTC_INTMSK2 (INTC_BASE+0x40080)
17#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
18#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
19#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
20#define INTC_NMIFCR (INTC_BASE+0xc0)
21#define INTC_USERIMASK (INTC_BASE+0x30000)
22
23#define INTC_INT2PRI0 (INTC_BASE+0x40000)
24#define INTC_INT2PRI1 (INTC_BASE+0x40004)
25#define INTC_INT2PRI2 (INTC_BASE+0x40008)
26#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
27#define INTC_INT2PRI4 (INTC_BASE+0x40010)
28#define INTC_INT2PRI5 (INTC_BASE+0x40014)
29#define INTC_INT2PRI6 (INTC_BASE+0x40018)
30#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
31#define INTC_INT2A0 (INTC_BASE+0x40030)
32#define INTC_INT2A1 (INTC_BASE+0x40034)
33#define INTC_INT2MSKR (INTC_BASE+0x40038)
34#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
35#define INTC_INT2B0 (INTC_BASE+0x40040)
36#define INTC_INT2B1 (INTC_BASE+0x40044)
37#define INTC_INT2B2 (INTC_BASE+0x40048)
38#define INTC_INT2B3 (INTC_BASE+0x4004c)
39#define INTC_INT2B4 (INTC_BASE+0x40050)
40#define INTC_INT2B5 (INTC_BASE+0x40054)
41#define INTC_INT2B6 (INTC_BASE+0x40058)
42#define INTC_INT2B7 (INTC_BASE+0x4005c)
43#define INTC_INT2GPIC (INTC_BASE+0x40090)
44/*
45 NOTE:
46 *_IRQ = (INTEVT2 - 0x200)/0x20
47*/
48/* IRQ 0-7 line external int*/
49#define IRQ0_IRQ 2
50#define IRQ0_IPR_ADDR INTC_INTPRI
51#define IRQ0_IPR_POS 7
52#define IRQ0_PRIORITY 2
53
54#define IRQ1_IRQ 4
55#define IRQ1_IPR_ADDR INTC_INTPRI
56#define IRQ1_IPR_POS 6
57#define IRQ1_PRIORITY 2
58
59#define IRQ2_IRQ 6
60#define IRQ2_IPR_ADDR INTC_INTPRI
61#define IRQ2_IPR_POS 5
62#define IRQ2_PRIORITY 2
63
64#define IRQ3_IRQ 8
65#define IRQ3_IPR_ADDR INTC_INTPRI
66#define IRQ3_IPR_POS 4
67#define IRQ3_PRIORITY 2
68
69#define IRQ4_IRQ 10
70#define IRQ4_IPR_ADDR INTC_INTPRI
71#define IRQ4_IPR_POS 3
72#define IRQ4_PRIORITY 2
73
74#define IRQ5_IRQ 12
75#define IRQ5_IPR_ADDR INTC_INTPRI
76#define IRQ5_IPR_POS 2
77#define IRQ5_PRIORITY 2
78
79#define IRQ6_IRQ 14
80#define IRQ6_IPR_ADDR INTC_INTPRI
81#define IRQ6_IPR_POS 1
82#define IRQ6_PRIORITY 2
83
84#define IRQ7_IRQ 0
85#define IRQ7_IPR_ADDR INTC_INTPRI
86#define IRQ7_IPR_POS 0
87#define IRQ7_PRIORITY 2
88
89/* TMU */
90/* ch0 */
91#define TMU_IRQ 28
92#define TMU_IPR_ADDR INTC_INT2PRI0
93#define TMU_IPR_POS 3
94#define TMU_PRIORITY 2
95
96#define TIMER_IRQ 28
97#define TIMER_IPR_ADDR INTC_INT2PRI0
98#define TIMER_IPR_POS 3
99#define TIMER_PRIORITY 2
100
101/* ch 1*/
102#define TMU_CH1_IRQ 29
103#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
104#define TMU_CH1_IPR_POS 2
105#define TMU_CH1_PRIORITY 2
106
107#define TIMER1_IRQ 29
108#define TIMER1_IPR_ADDR INTC_INT2PRI0
109#define TIMER1_IPR_POS 2
110#define TIMER1_PRIORITY 2
111
112/* ch 2*/
113#define TMU_CH2_IRQ 30
114#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
115#define TMU_CH2_IPR_POS 1
116#define TMU_CH2_PRIORITY 2
117/* ch 2 Input capture */
118#define TMU_CH2IC_IRQ 31
119#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
120#define TMU_CH2IC_IPR_POS 0
121#define TMU_CH2IC_PRIORITY 2
122/* ch 3 */
123#define TMU_CH3_IRQ 96
124#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
125#define TMU_CH3_IPR_POS 3
126#define TMU_CH3_PRIORITY 2
127/* ch 4 */
128#define TMU_CH4_IRQ 97
129#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
130#define TMU_CH4_IPR_POS 2
131#define TMU_CH4_PRIORITY 2
132/* ch 5*/
133#define TMU_CH5_IRQ 98
134#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
135#define TMU_CH5_IPR_POS 1
136#define TMU_CH5_PRIORITY 2
137
138/* SCIF0 */
139#define SCIF0_ERI_IRQ 40
140#define SCIF0_RXI_IRQ 41
141#define SCIF0_BRI_IRQ 42
142#define SCIF0_TXI_IRQ 43
143#define SCIF0_IPR_ADDR INTC_INT2PRI2
144#define SCIF0_IPR_POS 3
145#define SCIF0_PRIORITY 3
146
147/* SCIF1 */
148#define SCIF1_ERI_IRQ 76
149#define SCIF1_RXI_IRQ 77
150#define SCIF1_BRI_IRQ 78
151#define SCIF1_TXI_IRQ 79
152#define SCIF1_IPR_ADDR INTC_INT2PRI2
153#define SCIF1_IPR_POS 2
154#define SCIF1_PRIORITY 3
155
156#define WDT_IRQ 27
157#define WDT_IPR_ADDR INTC_INT2PRI2
158#define WDT_IPR_POS 1
159#define WDT_PRIORITY 2
160
161/* DMAC(0) */
162#define DMINT0_IRQ 34
163#define DMINT1_IRQ 35
164#define DMINT2_IRQ 36
165#define DMINT3_IRQ 37
166#define DMINT4_IRQ 44
167#define DMINT5_IRQ 45
168#define DMINT6_IRQ 46
169#define DMINT7_IRQ 47
170#define DMAE_IRQ 38
171#define DMA0_IPR_ADDR INTC_INT2PRI3
172#define DMA0_IPR_POS 2
173#define DMA0_PRIORITY 7
174
175/* DMAC(1) */
176#define DMINT8_IRQ 92
177#define DMINT9_IRQ 93
178#define DMINT10_IRQ 94
179#define DMINT11_IRQ 95
180#define DMA1_IPR_ADDR INTC_INT2PRI3
181#define DMA1_IPR_POS 1
182#define DMA1_PRIORITY 7
183
184#define DMTE0_IRQ DMINT0_IRQ
185#define DMTE4_IRQ DMINT4_IRQ
186#define DMA_IPR_ADDR DMA0_IPR_ADDR
187#define DMA_IPR_POS DMA0_IPR_POS
188#define DMA_PRIORITY DMA0_PRIORITY
189
190/* CMT */
191#define CMT_IRQ 56
192#define CMT_IPR_ADDR INTC_INT2PRI4
193#define CMT_IPR_POS 3
194#define CMT_PRIORITY 0
195
196/* HAC */
197#define HAC_IRQ 60
198#define HAC_IPR_ADDR INTC_INT2PRI4
199#define HAC_IPR_POS 2
200#define CMT_PRIORITY 0
201
202/* PCIC(0) */
203#define PCIC0_IRQ 64
204#define PCIC0_IPR_ADDR INTC_INT2PRI4
205#define PCIC0_IPR_POS 1
206#define PCIC0_PRIORITY 2
207
208/* PCIC(1) */
209#define PCIC1_IRQ 65
210#define PCIC1_IPR_ADDR INTC_INT2PRI4
211#define PCIC1_IPR_POS 0
212#define PCIC1_PRIORITY 2
213
214/* PCIC(2) */
215#define PCIC2_IRQ 66
216#define PCIC2_IPR_ADDR INTC_INT2PRI5
217#define PCIC2_IPR_POS 3
218#define PCIC2_PRIORITY 2
219
220/* PCIC(3) */
221#define PCIC3_IRQ 67
222#define PCIC3_IPR_ADDR INTC_INT2PRI5
223#define PCIC3_IPR_POS 2
224#define PCIC3_PRIORITY 2
225
226/* PCIC(4) */
227#define PCIC4_IRQ 68
228#define PCIC4_IPR_ADDR INTC_INT2PRI5
229#define PCIC4_IPR_POS 1
230#define PCIC4_PRIORITY 2
231
232/* PCIC(5) */
233#define PCICERR_IRQ 69
234#define PCICPWD3_IRQ 70
235#define PCICPWD2_IRQ 71
236#define PCICPWD1_IRQ 72
237#define PCICPWD0_IRQ 73
238#define PCIC5_IPR_ADDR INTC_INT2PRI5
239#define PCIC5_IPR_POS 0
240#define PCIC5_PRIORITY 2
241
242/* SIOF */
243#define SIOF_IRQ 80
244#define SIOF_IPR_ADDR INTC_INT2PRI6
245#define SIOF_IPR_POS 3
246#define SIOF_PRIORITY 3
247
248/* HSPI */
249#define HSPI_IRQ 84
250#define HSPI_IPR_ADDR INTC_INT2PRI6
251#define HSPI_IPR_POS 2
252#define HSPI_PRIORITY 3
253
254/* MMCIF */
255#define MMCIF_FSTAT_IRQ 88
256#define MMCIF_TRAN_IRQ 89
257#define MMCIF_ERR_IRQ 90
258#define MMCIF_FRDY_IRQ 91
259#define MMCIF_IPR_ADDR INTC_INT2PRI6
260#define MMCIF_IPR_POS 1
261#define HSPI_PRIORITY 3
262
263/* SSI */
264#define SSI_IRQ 100
265#define SSI_IPR_ADDR INTC_INT2PRI6
266#define SSI_IPR_POS 0
267#define SSI_PRIORITY 3
268
269/* FLCTL */
270#define FLCTL_FLSTE_IRQ 104
271#define FLCTL_FLTEND_IRQ 105
272#define FLCTL_FLTRQ0_IRQ 106
273#define FLCTL_FLTRQ1_IRQ 107
274#define FLCTL_IPR_ADDR INTC_INT2PRI7
275#define FLCTL_IPR_POS 3
276#define FLCTL_PRIORITY 3
277
278/* GPIO */
279#define GPIO0_IRQ 108
280#define GPIO1_IRQ 109
281#define GPIO2_IRQ 110
282#define GPIO3_IRQ 111
283#define GPIO_IPR_ADDR INTC_INT2PRI7
284#define GPIO_IPR_POS 2
285#define GPIO_PRIORITY 3
286
287#define INTC_TMU0_MSK 0
288#define INTC_TMU3_MSK 1
289#define INTC_RTC_MSK 2
290#define INTC_SCIF0_MSK 3
291#define INTC_SCIF1_MSK 4
292#define INTC_WDT_MSK 5
293#define INTC_HUID_MSK 7
294#define INTC_DMAC0_MSK 8
295#define INTC_DMAC1_MSK 9
296#define INTC_CMT_MSK 12
297#define INTC_HAC_MSK 13
298#define INTC_PCIC0_MSK 14
299#define INTC_PCIC1_MSK 15
300#define INTC_PCIC2_MSK 16
301#define INTC_PCIC3_MSK 17
302#define INTC_PCIC4_MSK 18
303#define INTC_PCIC5_MSK 19
304#define INTC_SIOF_MSK 20
305#define INTC_HSPI_MSK 21
306#define INTC_MMCIF_MSK 22
307#define INTC_SSI_MSK 23
308#define INTC_FLCTL_MSK 24
309#define INTC_GPIO_MSK 25
310
311#endif /* __ASM_SH_IRQ_SH7780_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 05:52:51 -0500