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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 00:42:57 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 00:42:57 -0400
commit6d75e650f1d0d59fd97c7629f0903ef18e8dfb7b (patch)
tree71753efdb503c351079e7ece10229a87cf263901 /include/asm-sh/hd64461
parentd95fb13c960ae19e9fd4a95807eb68fa20caf537 (diff)
sh: Move hd64461.h to a more sensible location.
With the I/O rework for hd64461 we're down to a single header, so move it by itself and get rid of the directory. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/hd64461')
-rw-r--r--include/asm-sh/hd64461/hd64461.h202
-rw-r--r--include/asm-sh/hd64461/io.h43
2 files changed, 0 insertions, 245 deletions
diff --git a/include/asm-sh/hd64461/hd64461.h b/include/asm-sh/hd64461/hd64461.h
deleted file mode 100644
index 87f13d24c630..000000000000
--- a/include/asm-sh/hd64461/hd64461.h
+++ /dev/null
@@ -1,202 +0,0 @@
1#ifndef __ASM_SH_HD64461
2#define __ASM_SH_HD64461
3/*
4 * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
5 * Copyright (C) 2000 YAEGASHI Takeshi
6 * Hitachi HD64461 companion chip support
7 */
8
9/* Constants for PCMCIA mappings */
10#define HD64461_PCC_WINDOW 0x01000000
11
12#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */
13#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE)
14#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
15#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
16
17#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */
18#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE)
19#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
20
21#define HD64461_STBCR 0x10000
22#define HD64461_STBCR_CKIO_STBY 0x2000
23#define HD64461_STBCR_SAFECKE_IST 0x1000
24#define HD64461_STBCR_SLCKE_IST 0x0800
25#define HD64461_STBCR_SAFECKE_OST 0x0400
26#define HD64461_STBCR_SLCKE_OST 0x0200
27#define HD64461_STBCR_SMIAST 0x0100
28#define HD64461_STBCR_SLCDST 0x0080
29#define HD64461_STBCR_SPC0ST 0x0040
30#define HD64461_STBCR_SPC1ST 0x0020
31#define HD64461_STBCR_SAFEST 0x0010
32#define HD64461_STBCR_STM0ST 0x0008
33#define HD64461_STBCR_STM1ST 0x0004
34#define HD64461_STBCR_SIRST 0x0002
35#define HD64461_STBCR_SURTST 0x0001
36
37#define HD64461_SYSCR 0x10002
38#define HD64461_SCPUCR 0x10004
39
40#define HD64461_LCDCBAR 0x11000
41#define HD64461_LCDCLOR 0x11002
42#define HD64461_LCDCCR 0x11004
43#define HD64461_LCDCCR_MOFF 0x80
44
45#define HD64461_LDR1 0x11010
46#define HD64461_LDR1_DON 0x01
47#define HD64461_LDR1_DINV 0x80
48
49#define HD64461_LDR2 0x11012
50#define HD64461_LDHNCR 0x11014
51#define HD64461_LDHNSR 0x11016
52#define HD64461_LDVNTR 0x11018
53#define HD64461_LDVNDR 0x1101a
54#define HD64461_LDVSPR 0x1101c
55#define HD64461_LDR3 0x1101e
56
57#define HD64461_CPTWAR 0x11030
58#define HD64461_CPTWDR 0x11032
59#define HD64461_CPTRAR 0x11034
60#define HD64461_CPTRDR 0x11036
61
62#define HD64461_GRDOR 0x11040
63#define HD64461_GRSCR 0x11042
64#define HD64461_GRCFGR 0x11044
65#define HD64461_GRCFGR_ACCSTATUS 0x10
66#define HD64461_GRCFGR_ACCRESET 0x08
67#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06
68#define HD64461_GRCFGR_ACCSTART_LINE 0x04
69#define HD64461_GRCFGR_COLORDEPTH16 0x01
70
71#define HD64461_LNSARH 0x11046
72#define HD64461_LNSARL 0x11048
73#define HD64461_LNAXLR 0x1104a
74#define HD64461_LNDGR 0x1104c
75#define HD64461_LNAXR 0x1104e
76#define HD64461_LNERTR 0x11050
77#define HD64461_LNMDR 0x11052
78#define HD64461_BBTSSARH 0x11054
79#define HD64461_BBTSSARL 0x11056
80#define HD64461_BBTDSARH 0x11058
81#define HD64461_BBTDSARL 0x1105a
82#define HD64461_BBTDWR 0x1105c
83#define HD64461_BBTDHR 0x1105e
84#define HD64461_BBTPARH 0x11060
85#define HD64461_BBTPARL 0x11062
86#define HD64461_BBTMARH 0x11064
87#define HD64461_BBTMARL 0x11066
88#define HD64461_BBTROPR 0x11068
89#define HD64461_BBTMDR 0x1106a
90
91/* PC Card Controller Registers */
92#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */
93#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */
94#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */
95#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */
96#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */
97#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */
98#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */
99#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */
100#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */
101#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */
102
103/* PCC Interface Status Register */
104#define HD64461_PCCISR_READY 0x80 /* card ready */
105#define HD64461_PCCISR_MWP 0x40 /* card write-protected */
106#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
107#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
108#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
109#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
110#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
111#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
112
113#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
114#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
115#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
116#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
117#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
118#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
119
120/* PCC General Control Register */
121#define HD64461_PCCGCR_DRVE 0x80 /* output drive */
122#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
123#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
124#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
125#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
126#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
127#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
128#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
129
130/* PCC Card Status Change Register */
131#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
132#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
133#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
134#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
135#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
136#define HD64461_PCCCSCR_RC 0x04 /* READY change */
137#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
138#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
139
140/* PCC Card Status Change Interrupt Enable Register */
141#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
142#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
143#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
144#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
145#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
146#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
147
148#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
149#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
150#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
151#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
152#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
153
154/* PCC Software Control Register */
155#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
156#define HD64461_PCCSCR_SWP 0x01 /* write protect */
157
158
159#define HD64461_P0OCR 0x1202a
160#define HD64461_P1OCR 0x1202c
161#define HD64461_PGCR 0x1202e
162
163#define HD64461_GPACR 0x14000
164#define HD64461_GPBCR 0x14002
165#define HD64461_GPCCR 0x14004
166#define HD64461_GPDCR 0x14006
167#define HD64461_GPADR 0x14010
168#define HD64461_GPBDR 0x14012
169#define HD64461_GPCDR 0x14014
170#define HD64461_GPDDR 0x14016
171#define HD64461_GPAICR 0x14020
172#define HD64461_GPBICR 0x14022
173#define HD64461_GPCICR 0x14024
174#define HD64461_GPDICR 0x14026
175#define HD64461_GPAISR 0x14040
176#define HD64461_GPBISR 0x14042
177#define HD64461_GPCISR 0x14044
178#define HD64461_GPDISR 0x14046
179
180#define HD64461_NIRR 0x15000
181#define HD64461_NIMR 0x15002
182
183#ifndef CONFIG_HD64461_IOBASE
184#define CONFIG_HD64461_IOBASE 0xb0000000
185#endif
186#ifndef CONFIG_HD64461_IRQ
187#define CONFIG_HD64461_IRQ 36
188#endif
189
190#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
191#define HD64461_IRQ_NUM 16
192
193#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
194#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
195#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
196#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
197#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
198#define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
199#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
200#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
201
202#endif
diff --git a/include/asm-sh/hd64461/io.h b/include/asm-sh/hd64461/io.h
deleted file mode 100644
index 67f2489088d9..000000000000
--- a/include/asm-sh/hd64461/io.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-sh/io_hd64461.h
3 *
4 * Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * IO functions for an HD64461
10 */
11
12#ifndef _ASM_SH_IO_HD64461_H
13#define _ASM_SH_IO_HD64461_H
14
15extern unsigned char hd64461_inb(unsigned long port);
16extern unsigned short hd64461_inw(unsigned long port);
17extern unsigned int hd64461_inl(unsigned long port);
18
19extern void hd64461_outb(unsigned char value, unsigned long port);
20extern void hd64461_outw(unsigned short value, unsigned long port);
21extern void hd64461_outl(unsigned int value, unsigned long port);
22
23extern unsigned char hd64461_inb_p(unsigned long port);
24extern void hd64461_outb_p(unsigned char value, unsigned long port);
25
26extern void hd64461_insb(unsigned long port, void *addr, unsigned long count);
27extern void hd64461_insw(unsigned long port, void *addr, unsigned long count);
28extern void hd64461_insl(unsigned long port, void *addr, unsigned long count);
29
30extern void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count);
31extern void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count);
32extern void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count);
33
34extern unsigned short hd64461_readw(unsigned long addr);
35extern void hd64461_writew(unsigned short b, unsigned long addr);
36
37
38extern int hd64461_irq_demux(int irq);
39extern void hd64461_register_irq_demux(int irq,
40 int (*demux)(int irq, void *dev), void *dev);
41extern void hd64461_unregister_irq_demux(int irq);
42
43#endif /* _ASM_SH_IO_HD64461_H */
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