diff options
| author | Kristoffer Ericson <kristoffer.ericson@gmail.com> | 2007-07-11 21:44:41 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-07-11 21:44:41 -0400 |
| commit | be15d65d97f924e11ad7b59b1dc23b9db8d02209 (patch) | |
| tree | 2e5f9973639669176c19847a0d55e62d40a0c3b6 /include/asm-sh/hd64461.h | |
| parent | bdf4fa536ba5c6eff125f18231d54e227b1f3629 (diff) | |
sh: hd64461.h cleanup and added comments.
Now that we dont have PIO mapping anymore we need to make sure we
got the correct value in our headers. Some well needed comments
have also been added.
Signed-off-by: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/hd64461.h')
| -rw-r--r-- | include/asm-sh/hd64461.h | 397 |
1 files changed, 219 insertions, 178 deletions
diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h index c9050b2b5510..4dd8592ca014 100644 --- a/include/asm-sh/hd64461.h +++ b/include/asm-sh/hd64461.h | |||
| @@ -1,200 +1,241 @@ | |||
| 1 | #ifndef __ASM_SH_HD64461 | 1 | #ifndef __ASM_SH_HD64461 |
| 2 | #define __ASM_SH_HD64461 | 2 | #define __ASM_SH_HD64461 |
| 3 | /* | 3 | /* |
| 4 | * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ | 4 | * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> |
| 5 | * Copyright (C) 2004 Paul Mundt | ||
| 5 | * Copyright (C) 2000 YAEGASHI Takeshi | 6 | * Copyright (C) 2000 YAEGASHI Takeshi |
| 6 | * Hitachi HD64461 companion chip support | 7 | * |
| 8 | * Hitachi HD64461 companion chip support | ||
| 9 | * (please note manual reference 0x10000000 = 0xb0000000) | ||
| 7 | */ | 10 | */ |
| 8 | 11 | ||
| 9 | /* Constants for PCMCIA mappings */ | 12 | /* Constants for PCMCIA mappings */ |
| 10 | #define HD64461_PCC_WINDOW 0x01000000 | 13 | #define HD64461_PCC_WINDOW 0x01000000 |
| 11 | 14 | ||
| 12 | #define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ | 15 | /* Area 6 - Slot 0 - memory and/or IO card */ |
| 13 | #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) | 16 | #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) |
| 14 | #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) | 17 | #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ |
| 15 | #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) | 18 | #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ |
| 16 | 19 | #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ | |
| 17 | #define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ | 20 | |
| 18 | #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) | 21 | /* Area 5 - Slot 1 - memory card only */ |
| 19 | #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) | 22 | #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) |
| 20 | 23 | #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ | |
| 21 | #define HD64461_STBCR 0x10000 | 24 | #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ |
| 22 | #define HD64461_STBCR_CKIO_STBY 0x2000 | 25 | |
| 23 | #define HD64461_STBCR_SAFECKE_IST 0x1000 | 26 | /* Standby Control Register for HD64461 */ |
| 24 | #define HD64461_STBCR_SLCKE_IST 0x0800 | 27 | #define HD64461_STBCR CONFIG_HD64461_IOBASE |
| 25 | #define HD64461_STBCR_SAFECKE_OST 0x0400 | 28 | #define HD64461_STBCR_CKIO_STBY 0x2000 |
| 26 | #define HD64461_STBCR_SLCKE_OST 0x0200 | 29 | #define HD64461_STBCR_SAFECKE_IST 0x1000 |
| 27 | #define HD64461_STBCR_SMIAST 0x0100 | 30 | #define HD64461_STBCR_SLCKE_IST 0x0800 |
| 28 | #define HD64461_STBCR_SLCDST 0x0080 | 31 | #define HD64461_STBCR_SAFECKE_OST 0x0400 |
| 29 | #define HD64461_STBCR_SPC0ST 0x0040 | 32 | #define HD64461_STBCR_SLCKE_OST 0x0200 |
| 30 | #define HD64461_STBCR_SPC1ST 0x0020 | 33 | #define HD64461_STBCR_SMIAST 0x0100 |
| 31 | #define HD64461_STBCR_SAFEST 0x0010 | 34 | #define HD64461_STBCR_SLCDST 0x0080 |
| 32 | #define HD64461_STBCR_STM0ST 0x0008 | 35 | #define HD64461_STBCR_SPC0ST 0x0040 |
| 33 | #define HD64461_STBCR_STM1ST 0x0004 | 36 | #define HD64461_STBCR_SPC1ST 0x0020 |
| 34 | #define HD64461_STBCR_SIRST 0x0002 | 37 | #define HD64461_STBCR_SAFEST 0x0010 |
| 35 | #define HD64461_STBCR_SURTST 0x0001 | 38 | #define HD64461_STBCR_STM0ST 0x0008 |
| 36 | 39 | #define HD64461_STBCR_STM1ST 0x0004 | |
| 37 | #define HD64461_SYSCR 0x10002 | 40 | #define HD64461_STBCR_SIRST 0x0002 |
| 38 | #define HD64461_SCPUCR 0x10004 | 41 | #define HD64461_STBCR_SURTST 0x0001 |
| 39 | 42 | ||
| 40 | #define HD64461_LCDCBAR 0x11000 | 43 | /* System Configuration Register */ |
| 41 | #define HD64461_LCDCLOR 0x11002 | 44 | #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) |
| 42 | #define HD64461_LCDCCR 0x11004 | 45 | |
| 43 | #define HD64461_LCDCCR_STBACK 0x0400 | 46 | /* CPU Data Bus Control Register */ |
| 44 | #define HD64461_LCDCCR_STREQ 0x0100 | 47 | #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) |
| 45 | #define HD64461_LCDCCR_MOFF 0x0080 | 48 | |
| 46 | #define HD64461_LCDCCR_REFSEL 0x0040 | 49 | /* Base Adress Register */ |
| 47 | #define HD64461_LCDCCR_EPON 0x0020 | 50 | #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) |
| 48 | #define HD64461_LCDCCR_SPON 0x0010 | 51 | |
| 49 | 52 | /* Line increment adress */ | |
| 50 | #define HD64461_LDR1 0x11010 | 53 | #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) |
| 51 | #define HD64461_LDR1_DON 0x01 | 54 | |
| 52 | #define HD64461_LDR1_DINV 0x80 | 55 | /* Controls LCD controller */ |
| 53 | 56 | #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) | |
| 54 | #define HD64461_LDR2 0x11012 | 57 | |
| 55 | #define HD64461_LDHNCR 0x11014 | 58 | /* LCCDR control bits */ |
| 56 | #define HD64461_LDHNSR 0x11016 | 59 | #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ |
| 57 | #define HD64461_LDVNTR 0x11018 | 60 | #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ |
| 58 | #define HD64461_LDVNDR 0x1101a | 61 | #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ |
| 59 | #define HD64461_LDVSPR 0x1101c | 62 | #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ |
| 60 | #define HD64461_LDR3 0x1101e | 63 | #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ |
| 61 | 64 | #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ | |
| 62 | #define HD64461_CPTWAR 0x11030 | 65 | |
| 63 | #define HD64461_CPTWDR 0x11032 | 66 | /* Controls LCD (1) */ |
| 64 | #define HD64461_CPTRAR 0x11034 | 67 | #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) |
| 65 | #define HD64461_CPTRDR 0x11036 | 68 | #define HD64461_LDR1_DON 0x01 /* Display On */ |
| 66 | 69 | #define HD64461_LDR1_DINV 0x80 /* Display Invert */ | |
| 67 | #define HD64461_GRDOR 0x11040 | 70 | |
| 68 | #define HD64461_GRSCR 0x11042 | 71 | /* Controls LCD (2) */ |
| 69 | #define HD64461_GRCFGR 0x11044 | 72 | #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) |
| 70 | #define HD64461_GRCFGR_ACCSTATUS 0x10 | 73 | #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ |
| 71 | #define HD64461_GRCFGR_ACCRESET 0x08 | 74 | #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ |
| 72 | #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 | 75 | #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ |
| 73 | #define HD64461_GRCFGR_ACCSTART_LINE 0x04 | 76 | #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ |
| 74 | #define HD64461_GRCFGR_COLORDEPTH16 0x01 | 77 | #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ |
| 75 | 78 | ||
| 76 | #define HD64461_LNSARH 0x11046 | 79 | /* Controls LCD (3) */ |
| 77 | #define HD64461_LNSARL 0x11048 | 80 | #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) |
| 78 | #define HD64461_LNAXLR 0x1104a | 81 | |
| 79 | #define HD64461_LNDGR 0x1104c | 82 | /* Palette Registers */ |
| 80 | #define HD64461_LNAXR 0x1104e | 83 | #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */ |
| 81 | #define HD64461_LNERTR 0x11050 | 84 | #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ |
| 82 | #define HD64461_LNMDR 0x11052 | 85 | #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */ |
| 83 | #define HD64461_BBTSSARH 0x11054 | 86 | #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ |
| 84 | #define HD64461_BBTSSARL 0x11056 | 87 | |
| 85 | #define HD64461_BBTDSARH 0x11058 | 88 | #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ |
| 86 | #define HD64461_BBTDSARL 0x1105a | 89 | #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ |
| 87 | #define HD64461_BBTDWR 0x1105c | 90 | #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ |
| 88 | #define HD64461_BBTDHR 0x1105e | 91 | |
| 89 | #define HD64461_BBTPARH 0x11060 | 92 | #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ |
| 90 | #define HD64461_BBTPARL 0x11062 | 93 | #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ |
| 91 | #define HD64461_BBTMARH 0x11064 | 94 | #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ |
| 92 | #define HD64461_BBTMARL 0x11066 | 95 | #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ |
| 93 | #define HD64461_BBTROPR 0x11068 | 96 | #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ |
| 94 | #define HD64461_BBTMDR 0x1106a | 97 | #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ |
| 98 | |||
| 99 | /* Line Drawing Registers */ | ||
| 100 | #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */ | ||
| 101 | #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */ | ||
| 102 | #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ | ||
| 103 | #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ | ||
| 104 | #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ | ||
| 105 | #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ | ||
| 106 | #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ | ||
| 107 | |||
| 108 | /* BitBLT Registers */ | ||
| 109 | #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */ | ||
| 110 | #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */ | ||
| 111 | #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */ | ||
| 112 | #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */ | ||
| 113 | #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ | ||
| 114 | #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ | ||
| 115 | #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */ | ||
| 116 | #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */ | ||
| 117 | #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */ | ||
| 118 | #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */ | ||
| 119 | #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ | ||
| 120 | #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ | ||
| 95 | 121 | ||
| 96 | /* PC Card Controller Registers */ | 122 | /* PC Card Controller Registers */ |
| 97 | #define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ | 123 | /* Maps to Physical Area 6 */ |
| 98 | #define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ | 124 | #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ |
| 99 | #define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ | 125 | #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ |
| 100 | #define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ | 126 | #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ |
| 101 | #define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ | 127 | #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ |
| 102 | #define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ | 128 | #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ |
| 103 | #define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ | 129 | /* Maps to Physical Area 5 */ |
| 104 | #define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ | 130 | #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ |
| 105 | #define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ | 131 | #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ |
| 106 | #define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ | 132 | #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ |
| 133 | #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ | ||
| 134 | #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ | ||
| 107 | 135 | ||
| 108 | /* PCC Interface Status Register */ | 136 | /* PCC Interface Status Register */ |
| 109 | #define HD64461_PCCISR_READY 0x80 /* card ready */ | 137 | #define HD64461_PCCISR_READY 0x80 /* card ready */ |
| 110 | #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ | 138 | #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ |
| 111 | #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ | 139 | #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ |
| 112 | #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ | 140 | #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ |
| 113 | #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ | 141 | #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ |
| 114 | #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ | 142 | #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ |
| 115 | #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ | 143 | #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ |
| 116 | #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ | 144 | #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ |
| 117 | 145 | ||
| 118 | #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ | 146 | #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ |
| 119 | #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ | 147 | #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ |
| 120 | #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ | 148 | #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ |
| 121 | #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ | 149 | #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ |
| 122 | #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ | 150 | #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ |
| 123 | #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ | 151 | #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ |
| 124 | 152 | ||
| 125 | /* PCC General Control Register */ | 153 | /* PCC General Control Register */ |
| 126 | #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ | 154 | #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ |
| 127 | #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ | 155 | #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ |
| 128 | #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ | 156 | #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ |
| 129 | #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ | 157 | #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ |
| 130 | #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ | 158 | #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ |
| 131 | #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ | 159 | #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ |
| 132 | #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ | 160 | #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ |
| 133 | #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ | 161 | #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ |
| 134 | 162 | ||
| 135 | /* PCC Card Status Change Register */ | 163 | /* PCC Card Status Change Register */ |
| 136 | #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ | 164 | #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ |
| 137 | #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ | 165 | #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ |
| 138 | #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ | 166 | #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ |
| 139 | #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ | 167 | #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ |
| 140 | #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ | 168 | #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ |
| 141 | #define HD64461_PCCCSCR_RC 0x04 /* READY change */ | 169 | #define HD64461_PCCCSCR_RC 0x04 /* READY change */ |
| 142 | #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ | 170 | #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ |
| 143 | #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ | 171 | #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ |
| 144 | 172 | ||
| 145 | /* PCC Card Status Change Interrupt Enable Register */ | 173 | /* PCC Card Status Change Interrupt Enable Register */ |
| 146 | #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ | 174 | #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ |
| 147 | #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ | 175 | #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ |
| 148 | #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ | 176 | #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ |
| 149 | #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ | 177 | #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ |
| 150 | #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ | 178 | #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ |
| 151 | #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ | 179 | #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ |
| 152 | 180 | ||
| 153 | #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ | 181 | #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ |
| 154 | #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ | 182 | #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ |
| 155 | #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ | 183 | #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ |
| 156 | #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ | 184 | #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ |
| 157 | #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ | 185 | #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ |
| 158 | 186 | ||
| 159 | /* PCC Software Control Register */ | 187 | /* PCC Software Control Register */ |
| 160 | #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ | 188 | #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ |
| 161 | #define HD64461_PCCSCR_SWP 0x01 /* write protect */ | 189 | #define HD64461_PCCSCR_SWP 0x01 /* write protect */ |
| 162 | 190 | ||
| 163 | #define HD64461_P0OCR 0x1202a | 191 | /* PCC0 Output Pins Control Register */ |
| 164 | #define HD64461_P1OCR 0x1202c | 192 | #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) |
| 165 | #define HD64461_PGCR 0x1202e | 193 | |
| 166 | 194 | /* PCC1 Output Pins Control Register */ | |
| 167 | #define HD64461_GPACR 0x14000 | 195 | #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) |
| 168 | #define HD64461_GPBCR 0x14002 | 196 | |
| 169 | #define HD64461_GPCCR 0x14004 | 197 | /* PC Card General Control Register */ |
| 170 | #define HD64461_GPDCR 0x14006 | 198 | #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) |
| 171 | #define HD64461_GPADR 0x14010 | 199 | |
| 172 | #define HD64461_GPBDR 0x14012 | 200 | /* Port Control Registers */ |
| 173 | #define HD64461_GPCDR 0x14014 | 201 | #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ |
| 174 | #define HD64461_GPDDR 0x14016 | 202 | #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ |
| 175 | #define HD64461_GPAICR 0x14020 | 203 | #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ |
| 176 | #define HD64461_GPBICR 0x14022 | 204 | #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ |
| 177 | #define HD64461_GPCICR 0x14024 | 205 | |
| 178 | #define HD64461_GPDICR 0x14026 | 206 | /* Port Control Data Registers */ |
| 179 | #define HD64461_GPAISR 0x14040 | 207 | #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ |
| 180 | #define HD64461_GPBISR 0x14042 | 208 | #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ |
| 181 | #define HD64461_GPCISR 0x14044 | 209 | #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ |
| 182 | #define HD64461_GPDISR 0x14046 | 210 | #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ |
| 183 | 211 | ||
| 184 | #define HD64461_NIRR 0x15000 | 212 | /* Interrupt Control Registers */ |
| 185 | #define HD64461_NIMR 0x15002 | 213 | #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ |
| 186 | 214 | #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ | |
| 187 | #define HD64461_IRQBASE 64 | 215 | #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ |
| 188 | #define HD64461_IRQ_NUM 16 | 216 | #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ |
| 189 | 217 | ||
| 190 | #define HD64461_IRQ_UART (HD64461_IRQBASE+5) | 218 | /* Interrupt Status Registers */ |
| 191 | #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) | 219 | #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ |
| 192 | #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) | 220 | #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ |
| 193 | #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) | 221 | #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ |
| 194 | #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) | 222 | #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ |
| 195 | #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) | 223 | |
| 196 | #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) | 224 | /* Interrupt Request Register & Interrupt Mask Register */ |
| 197 | #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) | 225 | #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) |
| 226 | #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) | ||
| 227 | |||
| 228 | #define HD64461_IRQBASE OFFCHIP_IRQ_BASE | ||
| 229 | #define HD64461_IRQ_NUM 16 | ||
| 230 | |||
| 231 | #define HD64461_IRQ_UART (HD64461_IRQBASE+5) | ||
| 232 | #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) | ||
| 233 | #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) | ||
| 234 | #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) | ||
| 235 | #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) | ||
| 236 | #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) | ||
| 237 | #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) | ||
| 238 | #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) | ||
| 198 | 239 | ||
| 199 | #define __IO_PREFIX hd64461 | 240 | #define __IO_PREFIX hd64461 |
| 200 | #include <asm/io_generic.h> | 241 | #include <asm/io_generic.h> |