diff options
author | Paul Mundt <lethal@linux-sh.org> | 2007-11-21 08:53:34 -0500 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-27 23:18:54 -0500 |
commit | caead5ef34e5abdda8c5189cf698e0b863904701 (patch) | |
tree | fc0c82357973f0e9c00a8c8ef93080d903fd8213 /include/asm-sh/cpu-sh5/irq.h | |
parent | 9895f9429cb489ba271c06767531083ae4c4bcbe (diff) |
sh: Kill off the last of the sh64 headers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh5/irq.h')
-rw-r--r-- | include/asm-sh/cpu-sh5/irq.h | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh5/irq.h b/include/asm-sh/cpu-sh5/irq.h new file mode 100644 index 000000000000..5c9e6a873aeb --- /dev/null +++ b/include/asm-sh/cpu-sh5/irq.h | |||
@@ -0,0 +1,144 @@ | |||
1 | #ifndef __ASM_SH64_IRQ_H | ||
2 | #define __ASM_SH64_IRQ_H | ||
3 | |||
4 | /* | ||
5 | * This file is subject to the terms and conditions of the GNU General Public | ||
6 | * License. See the file "COPYING" in the main directory of this archive | ||
7 | * for more details. | ||
8 | * | ||
9 | * include/asm-sh64/irq.h | ||
10 | * | ||
11 | * Copyright (C) 2000, 2001 Paolo Alberelli | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | |||
16 | /* | ||
17 | * Encoded IRQs are not considered worth to be supported. | ||
18 | * Main reason is that there's no per-encoded-interrupt | ||
19 | * enable/disable mechanism (as there was in SH3/4). | ||
20 | * An all enabled/all disabled is worth only if there's | ||
21 | * a cascaded IC to disable/enable/ack on. Until such | ||
22 | * IC is available there's no such support. | ||
23 | * | ||
24 | * Presumably Encoded IRQs may use extra IRQs beyond 64, | ||
25 | * below. Some logic must be added to cope with IRQ_IRL? | ||
26 | * in an exclusive way. | ||
27 | * | ||
28 | * Priorities are set at Platform level, when IRQ_IRL0-3 | ||
29 | * are set to 0 Encoding is allowed. Otherwise it's not | ||
30 | * allowed. | ||
31 | */ | ||
32 | |||
33 | /* Independent IRQs */ | ||
34 | #define IRQ_IRL0 0 | ||
35 | #define IRQ_IRL1 1 | ||
36 | #define IRQ_IRL2 2 | ||
37 | #define IRQ_IRL3 3 | ||
38 | |||
39 | #define IRQ_INTA 4 | ||
40 | #define IRQ_INTB 5 | ||
41 | #define IRQ_INTC 6 | ||
42 | #define IRQ_INTD 7 | ||
43 | |||
44 | #define IRQ_SERR 12 | ||
45 | #define IRQ_ERR 13 | ||
46 | #define IRQ_PWR3 14 | ||
47 | #define IRQ_PWR2 15 | ||
48 | #define IRQ_PWR1 16 | ||
49 | #define IRQ_PWR0 17 | ||
50 | |||
51 | #define IRQ_DMTE0 18 | ||
52 | #define IRQ_DMTE1 19 | ||
53 | #define IRQ_DMTE2 20 | ||
54 | #define IRQ_DMTE3 21 | ||
55 | #define IRQ_DAERR 22 | ||
56 | |||
57 | #define IRQ_TUNI0 32 | ||
58 | #define IRQ_TUNI1 33 | ||
59 | #define IRQ_TUNI2 34 | ||
60 | #define IRQ_TICPI2 35 | ||
61 | |||
62 | #define IRQ_ATI 36 | ||
63 | #define IRQ_PRI 37 | ||
64 | #define IRQ_CUI 38 | ||
65 | |||
66 | #define IRQ_ERI 39 | ||
67 | #define IRQ_RXI 40 | ||
68 | #define IRQ_BRI 41 | ||
69 | #define IRQ_TXI 42 | ||
70 | |||
71 | #define IRQ_ITI 63 | ||
72 | |||
73 | #define NR_INTC_IRQS 64 | ||
74 | |||
75 | #ifdef CONFIG_SH_CAYMAN | ||
76 | #define NR_EXT_IRQS 32 | ||
77 | #define START_EXT_IRQS 64 | ||
78 | |||
79 | /* PCI bus 2 uses encoded external interrupts on the Cayman board */ | ||
80 | #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0) | ||
81 | #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1) | ||
82 | #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2) | ||
83 | #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3) | ||
84 | |||
85 | #define I8042_KBD_IRQ (START_EXT_IRQS + 2) | ||
86 | #define I8042_AUX_IRQ (START_EXT_IRQS + 6) | ||
87 | |||
88 | #define IRQ_CFCARD (START_EXT_IRQS + 7) | ||
89 | #define IRQ_PCMCIA (0) | ||
90 | |||
91 | #else | ||
92 | #define NR_EXT_IRQS 0 | ||
93 | #endif | ||
94 | |||
95 | #define NR_IRQS (NR_INTC_IRQS+NR_EXT_IRQS) | ||
96 | |||
97 | |||
98 | /* Default IRQs, fixed */ | ||
99 | #define TIMER_IRQ IRQ_TUNI0 | ||
100 | #define RTC_IRQ IRQ_CUI | ||
101 | |||
102 | /* Default Priorities, Platform may choose differently */ | ||
103 | #define NO_PRIORITY 0 /* Disabled */ | ||
104 | #define TIMER_PRIORITY 2 | ||
105 | #define RTC_PRIORITY TIMER_PRIORITY | ||
106 | #define SCIF_PRIORITY 3 | ||
107 | #define INTD_PRIORITY 3 | ||
108 | #define IRL3_PRIORITY 4 | ||
109 | #define INTC_PRIORITY 6 | ||
110 | #define IRL2_PRIORITY 7 | ||
111 | #define INTB_PRIORITY 9 | ||
112 | #define IRL1_PRIORITY 10 | ||
113 | #define INTA_PRIORITY 12 | ||
114 | #define IRL0_PRIORITY 13 | ||
115 | #define TOP_PRIORITY 15 | ||
116 | |||
117 | extern int intc_evt_to_irq[(0xE20/0x20)+1]; | ||
118 | int intc_irq_describe(char* p, int irq); | ||
119 | |||
120 | #define irq_canonicalize(irq) (irq) | ||
121 | |||
122 | #ifdef CONFIG_SH_CAYMAN | ||
123 | int cayman_irq_demux(int evt); | ||
124 | int cayman_irq_describe(char* p, int irq); | ||
125 | #define irq_demux(x) cayman_irq_demux(x) | ||
126 | #define irq_describe(p, x) cayman_irq_describe(p, x) | ||
127 | #else | ||
128 | #define irq_demux(x) (intc_evt_to_irq[x]) | ||
129 | #define irq_describe(p, x) intc_irq_describe(p, x) | ||
130 | #endif | ||
131 | |||
132 | /* | ||
133 | * Function for "on chip support modules". | ||
134 | */ | ||
135 | |||
136 | /* | ||
137 | * SH-5 supports Priority based interrupts only. | ||
138 | * Interrupt priorities are defined at platform level. | ||
139 | */ | ||
140 | #define set_ipr_data(a, b, c, d) | ||
141 | #define make_ipr_irq(a) | ||
142 | #define make_imask_irq(a) | ||
143 | |||
144 | #endif /* __ASM_SH64_IRQ_H */ | ||