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authorPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 19:09:44 -0400
commitf15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch)
tree774d7b11abaaf33561ab8268bf51ddd9ceb79025 /include/asm-sh/cpu-sh4
parent25326277d8d1393d1c66240e6255aca780f9e3eb (diff)
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh4')
-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h35
-rw-r--r--include/asm-sh/cpu-sh4/cache.h42
-rw-r--r--include/asm-sh/cpu-sh4/cacheflush.h43
-rw-r--r--include/asm-sh/cpu-sh4/dma-sh7780.h39
-rw-r--r--include/asm-sh/cpu-sh4/dma.h65
-rw-r--r--include/asm-sh/cpu-sh4/fpu.h32
-rw-r--r--include/asm-sh/cpu-sh4/freq.h44
-rw-r--r--include/asm-sh/cpu-sh4/mmu_context.h63
-rw-r--r--include/asm-sh/cpu-sh4/rtc.h13
-rw-r--r--include/asm-sh/cpu-sh4/sigcontext.h24
-rw-r--r--include/asm-sh/cpu-sh4/sq.h35
-rw-r--r--include/asm-sh/cpu-sh4/timer.h60
-rw-r--r--include/asm-sh/cpu-sh4/ubc.h64
-rw-r--r--include/asm-sh/cpu-sh4/watchdog.h25
14 files changed, 0 insertions, 584 deletions
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
deleted file mode 100644
index a3fa733c1c7d..000000000000
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-4 CPUs.
9 */
10#ifndef __ASM_CPU_SH4_ADDRSPACE_H
11#define __ASM_CPU_SH4_ADDRSPACE_H
12
13#define P0SEG 0x00000000
14#define P1SEG 0x80000000
15#define P2SEG 0xa0000000
16#define P3SEG 0xc0000000
17#define P4SEG 0xe0000000
18
19/* Detailed P4SEG */
20#define P4SEG_STORE_QUE (P4SEG)
21#define P4SEG_IC_ADDR 0xf0000000
22#define P4SEG_IC_DATA 0xf1000000
23#define P4SEG_ITLB_ADDR 0xf2000000
24#define P4SEG_ITLB_DATA 0xf3000000
25#define P4SEG_OC_ADDR 0xf4000000
26#define P4SEG_OC_DATA 0xf5000000
27#define P4SEG_TLB_ADDR 0xf6000000
28#define P4SEG_TLB_DATA 0xf7000000
29#define P4SEG_REG_BASE 0xff000000
30
31#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
32#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
33
34#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
35
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
deleted file mode 100644
index 1c61ebf5c8e3..000000000000
--- a/include/asm-sh/cpu-sh4/cache.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_CACHE_H
11#define __ASM_CPU_SH4_CACHE_H
12
13#define L1_CACHE_SHIFT 5
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define CCR 0xff00001c /* Address of Cache Control Register */
21#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
22#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
23#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
24#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
25#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
26#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
27#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
28#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
29#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
30#ifndef CONFIG_CPU_SH4A
31#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
32#endif
33
34/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
35#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
36#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
37
38#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
39#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
40
41#endif /* __ASM_CPU_SH4_CACHE_H */
42
diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h
deleted file mode 100644
index 065306d376eb..000000000000
--- a/include/asm-sh/cpu-sh4/cacheflush.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
12#define __ASM_CPU_SH4_CACHEFLUSH_H
13
14/*
15 * Caches are broken on SH-4 (unless we use write-through
16 * caching; in which case they're only semi-broken),
17 * so we need them.
18 */
19void flush_cache_all(void);
20void flush_dcache_all(void);
21void flush_cache_mm(struct mm_struct *mm);
22#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
23void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
24 unsigned long end);
25void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
26 unsigned long pfn);
27void flush_dcache_page(struct page *pg);
28
29#define flush_dcache_mmap_lock(mapping) do { } while (0)
30#define flush_dcache_mmap_unlock(mapping) do { } while (0)
31
32void flush_icache_range(unsigned long start, unsigned long end);
33void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
34 unsigned long addr, int len);
35
36#define flush_icache_page(vma,pg) do { } while (0)
37
38/* Initialization of P3 area for copy_user_page */
39void p3_cache_init(void);
40
41#define PG_mapped PG_arch_1
42
43#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
diff --git a/include/asm-sh/cpu-sh4/dma-sh7780.h b/include/asm-sh/cpu-sh4/dma-sh7780.h
deleted file mode 100644
index 71b426a6e482..000000000000
--- a/include/asm-sh/cpu-sh4/dma-sh7780.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int ts_shift[] __maybe_unused = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
deleted file mode 100644
index aaf71b018c28..000000000000
--- a/include/asm-sh/cpu-sh4/dma.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H
3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
6/* SH7751/7760/7780 DMA IRQ sources */
7#define DMTE0_IRQ 34
8#define DMTE1_IRQ 35
9#define DMTE2_IRQ 36
10#define DMTE3_IRQ 37
11#define DMTE4_IRQ 44
12#define DMTE5_IRQ 45
13#define DMTE6_IRQ 46
14#define DMTE7_IRQ 47
15#define DMAE_IRQ 38
16
17#ifdef CONFIG_CPU_SH4A
18#define SH_DMAC_BASE 0xfc808020
19
20#define CHCR_TS_MASK 0x18
21#define CHCR_TS_SHIFT 3
22
23#include <asm/cpu/dma-sh7780.h>
24#else
25#define SH_DMAC_BASE 0xffa00000
26
27/* Definitions for the SuperH DMAC */
28#define TM_BURST 0x0000080
29#define TS_8 0x00000010
30#define TS_16 0x00000020
31#define TS_32 0x00000030
32#define TS_64 0x00000000
33
34#define CHCR_TS_MASK 0x70
35#define CHCR_TS_SHIFT 4
36
37#define DMAOR_COD 0x00000008
38
39/*
40 * The SuperH DMAC supports a number of transmit sizes, we list them here,
41 * with their respective values as they appear in the CHCR registers.
42 *
43 * Defaults to a 64-bit transfer size.
44 */
45enum {
46 XMIT_SZ_64BIT,
47 XMIT_SZ_8BIT,
48 XMIT_SZ_16BIT,
49 XMIT_SZ_32BIT,
50 XMIT_SZ_256BIT,
51};
52
53/*
54 * The DMA count is defined as the number of bytes to transfer.
55 */
56static unsigned int ts_shift[] __maybe_unused = {
57 [XMIT_SZ_64BIT] = 3,
58 [XMIT_SZ_8BIT] = 0,
59 [XMIT_SZ_16BIT] = 1,
60 [XMIT_SZ_32BIT] = 2,
61 [XMIT_SZ_256BIT] = 5,
62};
63#endif
64
65#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/cpu-sh4/fpu.h b/include/asm-sh/cpu-sh4/fpu.h
deleted file mode 100644
index febef7342528..000000000000
--- a/include/asm-sh/cpu-sh4/fpu.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
3 *
4 * Copyright (C) 2006 STMicroelectronics Limited
5 * Author: Carl Shaw <carl.shaw@st.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License Version 2. See linux/COPYING for more information.
9 *
10 * Definitions for SH4 FPU operations
11 */
12
13#ifndef __CPU_SH4_FPU_H
14#define __CPU_SH4_FPU_H
15
16#define FPSCR_ENABLE_MASK 0x00000f80UL
17
18#define FPSCR_FMOV_DOUBLE (1<<1)
19
20#define FPSCR_CAUSE_INEXACT (1<<12)
21#define FPSCR_CAUSE_UNDERFLOW (1<<13)
22#define FPSCR_CAUSE_OVERFLOW (1<<14)
23#define FPSCR_CAUSE_DIVZERO (1<<15)
24#define FPSCR_CAUSE_INVALID (1<<16)
25#define FPSCR_CAUSE_ERROR (1<<17)
26
27#define FPSCR_DBL_PRECISION (1<<19)
28#define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3)
29#define FPSCR_RM_NEAREST (0)
30#define FPSCR_RM_ZERO (1)
31
32#endif
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
deleted file mode 100644
index c23af81c2e70..000000000000
--- a/include/asm-sh/cpu-sh4/freq.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_FREQ_H
11#define __ASM_CPU_SH4_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7723) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7343) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7366)
17#define FRQCR 0xa4150000
18#define VCLKCR 0xa4150004
19#define SCLKACR 0xa4150008
20#define SCLKBCR 0xa415000c
21#define IrDACLKCR 0xa4150010
22#define MSTPCR0 0xa4150030
23#define MSTPCR1 0xa4150034
24#define MSTPCR2 0xa4150038
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000
28#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
29#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004
31#define FRQMR1 0xffc80014
32#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
33#define FRQCR 0xffc00014
34#else
35#define FRQCR 0xffc00000
36#define FRQCR_PSTBY 0x0200
37#define FRQCR_PLLEN 0x0400
38#define FRQCR_CKOEN 0x0800
39#endif
40#define MIN_DIVISOR_NR 0
41#define MAX_DIVISOR_NR 3
42
43#endif /* __ASM_CPU_SH4_FREQ_H */
44
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
deleted file mode 100644
index 9ea8eb27b18e..000000000000
--- a/include/asm-sh/cpu-sh4/mmu_context.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11#define __ASM_CPU_SH4_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15#define MMU_TTB 0xFF000008 /* Translation table base register */
16#define MMU_TEA 0xFF00000C /* TLB Exception Address */
17#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
18
19#define MMUCR 0xFF000010 /* MMU Control Register */
20
21#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_PAGE_ASSOC_BIT 0x80
24
25#define MMUCR_TI (1<<2)
26
27#ifdef CONFIG_X2TLB
28#define MMUCR_ME (1 << 7)
29#else
30#define MMUCR_ME (0)
31#endif
32
33#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
34#define MMUCR_SE (1 << 4)
35#else
36#define MMUCR_SE (0)
37#endif
38
39#ifdef CONFIG_SH_STORE_QUEUES
40#define MMUCR_SQMD (1 << 9)
41#else
42#define MMUCR_SQMD (0)
43#endif
44
45#define MMU_NTLB_ENTRIES 64
46#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
47
48#define MMU_ITLB_DATA_ARRAY 0xF3000000
49#define MMU_UTLB_DATA_ARRAY 0xF7000000
50
51#define MMU_UTLB_ENTRIES 64
52#define MMU_U_ENTRY_SHIFT 8
53#define MMU_UTLB_VALID 0x100
54#define MMU_ITLB_ENTRIES 4
55#define MMU_I_ENTRY_SHIFT 8
56#define MMU_ITLB_VALID 0x100
57
58#define TRA 0xff000020
59#define EXPEVT 0xff000024
60#define INTEVT 0xff000028
61
62#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
63
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
deleted file mode 100644
index 25b1e6adfe8c..000000000000
--- a/include/asm-sh/cpu-sh4/rtc.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_RTC_H
2#define __ASM_SH_CPU_SH4_RTC_H
3
4#ifdef CONFIG_CPU_SUBTYPE_SH7723
5#define rtc_reg_size sizeof(u16)
6#else
7#define rtc_reg_size sizeof(u32)
8#endif
9
10#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
11#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
12
13#endif /* __ASM_SH_CPU_SH4_RTC_H */
diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h
deleted file mode 100644
index ab392f120e06..000000000000
--- a/include/asm-sh/cpu-sh4/sigcontext.h
+++ /dev/null
@@ -1,24 +0,0 @@
1#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
2#define __ASM_CPU_SH4_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15
16 /* FPU registers */
17 unsigned long sc_fpregs[16];
18 unsigned long sc_xfpregs[16];
19 unsigned int sc_fpscr;
20 unsigned int sc_fpul;
21 unsigned int sc_ownedfp;
22};
23
24#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h
deleted file mode 100644
index 586d6491816a..000000000000
--- a/include/asm-sh/cpu-sh4/sq.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/sq.h
3 *
4 * Copyright (C) 2001, 2002, 2003 Paul Mundt
5 * Copyright (C) 2001, 2002 M. R. Brown
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH4_SQ_H
12#define __ASM_CPU_SH4_SQ_H
13
14#include <asm/addrspace.h>
15
16/*
17 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
18 * mapped to any physical address space. Since data is written (and aligned)
19 * to 32-byte boundaries, we need to be sure that all allocations are aligned.
20 */
21#define SQ_SIZE 32
22#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
23#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
24
25#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
26#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
27#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
28
29/* arch/sh/kernel/cpu/sh4/sq.c */
30unsigned long sq_remap(unsigned long phys, unsigned int size,
31 const char *name, unsigned long flags);
32void sq_unmap(unsigned long vaddr);
33void sq_flush_range(unsigned long start, unsigned int len);
34
35#endif /* __ASM_CPU_SH4_SQ_H */
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
deleted file mode 100644
index d1e796b96888..000000000000
--- a/include/asm-sh/cpu-sh4/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * SH-X3
20 * ---------------------------------------------------------------------------
21 */
22#ifdef CONFIG_CPU_SUBTYPE_SHX3
23#define TMU_012_BASE 0xffc10000
24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
28#endif
29
30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
31
32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
34
35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU0_TCR (TMU_012_BASE + 0x10)
38
39#define TMU1_TCOR (TMU_012_BASE + 0x14)
40#define TMU1_TCNT (TMU_012_BASE + 0x18)
41#define TMU1_TCR (TMU_012_BASE + 0x1c)
42
43#define TMU2_TCOR (TMU_012_BASE + 0x20)
44#define TMU2_TCNT (TMU_012_BASE + 0x24)
45#define TMU2_TCR (TMU_012_BASE + 0x28)
46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
47
48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h
deleted file mode 100644
index c86e17050935..000000000000
--- a/include/asm-sh/cpu-sh4/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_CPU_SH4_UBC_H
13#define __ASM_CPU_SH4_UBC_H
14
15#if defined(CONFIG_CPU_SH4A)
16#define UBC_CBR0 0xff200000
17#define UBC_CRR0 0xff200004
18#define UBC_CAR0 0xff200008
19#define UBC_CAMR0 0xff20000c
20#define UBC_CBR1 0xff200020
21#define UBC_CRR1 0xff200024
22#define UBC_CAR1 0xff200028
23#define UBC_CAMR1 0xff20002c
24#define UBC_CDR1 0xff200030
25#define UBC_CDMR1 0xff200034
26#define UBC_CETR1 0xff200038
27#define UBC_CCMFR 0xff200600
28#define UBC_CBCR 0xff200620
29
30/* CBR */
31#define UBC_CBR_AIE (0x01<<30)
32#define UBC_CBR_ID_INST (0x01<<4)
33#define UBC_CBR_RW_READ (0x01<<1)
34#define UBC_CBR_CE (0x01)
35
36#define UBC_CBR_AIV_MASK (0x00FF0000)
37#define UBC_CBR_AIV_SHIFT (16)
38#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
39
40#define UBC_CBR_INIT 0x20000000
41
42/* CRR */
43#define UBC_CRR_RES (0x01<<13)
44#define UBC_CRR_PCB (0x01<<1)
45#define UBC_CRR_BIE (0x01)
46
47#define UBC_CRR_INIT 0x00002000
48
49#else /* CONFIG_CPU_SH4 */
50#define UBC_BARA 0xff200000
51#define UBC_BAMRA 0xff200004
52#define UBC_BBRA 0xff200008
53#define UBC_BASRA 0xff000014
54#define UBC_BARB 0xff20000c
55#define UBC_BAMRB 0xff200010
56#define UBC_BBRB 0xff200014
57#define UBC_BASRB 0xff000018
58#define UBC_BDRB 0xff200018
59#define UBC_BDMRB 0xff20001c
60#define UBC_BRCR 0xff200020
61#endif /* CONFIG_CPU_SH4 */
62
63#endif /* __ASM_CPU_SH4_UBC_H */
64
diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h
deleted file mode 100644
index 259f6a0ce23d..000000000000
--- a/include/asm-sh/cpu-sh4/watchdog.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_WATCHDOG_H
11#define __ASM_CPU_SH4_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffc00008
15#define WTCSR 0xffc0000c
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH4_WATCHDOG_H */
25
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