sh: Fix up extended mode TLB for SH-X2+ cores.

The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
correspondingly, the PGD also has to be 64-bits, so fix that up.

The kernel and user permission bits really are decoupled in early
cuts of the silicon, which means that we also have to set corresponding
kernel permissions on user pages or we end up with user pages that the
kernel simply can't touch (!).

Finally, with those things corrected, really enable MMUCR.ME and
correct the PTEA value (this simply needs to be the upper 32-bits
of the PTE, with the size and protection bit encoding).

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 11 insertions, 3 deletions

diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h
index ff4c5fbbfaf0..979acddc0f8e 100644
--- a/include/asm-sh/cpu-sh4/mmu_context.h
+++ b/include/asm-sh/cpu-sh4/mmu_context.h
@@ -22,13 +22,21 @@
 #define MMU_UTLB_ADDRESS_ARRAY  0xF6000000
 #define MMU_PAGE_ASSOC_BIT      0x80
 
-#define MMU_NTLB_ENTRIES        64      /* for 7750 */
+#ifdef CONFIG_X2TLB
+#define MMUCR_ME                (1 << 7)
+#else
+#define MMUCR_ME                (0)
+#endif
+
 #ifdef CONFIG_SH_STORE_QUEUES
-#define MMU_CONTROL_INIT        0x05    /* SQMD=0, SV=0, TI=1, AT=1 */
+#define MMUCR_SQMD              (1 << 9)
 #else
-#define MMU_CONTROL_INIT        0x205   /* SQMD=1, SV=0, TI=1, AT=1 */
+#define MMUCR_SQMD              (0)
 #endif
 
+#define MMU_NTLB_ENTRIES        64
+#define MMU_CONTROL_INIT        (0x05|MMUCR_SQMD|MMUCR_ME)
+
 #define MMU_ITLB_DATA_ARRAY     0xF3000000
 #define MMU_UTLB_DATA_ARRAY     0xF7000000