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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 04:38:11 -0400
commite5723e0eeb2dc16629e86d66785024ead9169000 (patch)
tree7fe39cdaf3106cc726d3b84fdc998b382b6c5e22 /include/asm-sh/cpu-sh3
parentecd9561687a0952a96a0a705f618e59cb6f3189b (diff)
sh: Add support for SH7706/SH7710/SH7343 CPUs.
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh3')
-rw-r--r--include/asm-sh/cpu-sh3/cache.h4
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h8
-rw-r--r--include/asm-sh/cpu-sh3/timer.h1
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h15
4 files changed, 22 insertions, 6 deletions
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 406aa8d9b947..ffe08d2813f9 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -26,12 +26,10 @@
26#define CCR_CACHE_ENABLE CCR_CACHE_CE 26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28 28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705) 29#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
30#define CCR3 0xa40000b4 30#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000 31#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000 32#define CCR_CACHE_32KB 0x00020000
33#endif 33#endif
34 34
35
36#endif /* __ASM_CPU_SH3_CACHE_H */ 35#endif /* __ASM_CPU_SH3_CACHE_H */
37
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index a844ea0965b6..bccb7ddb438b 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -27,8 +27,12 @@
27#define TRA 0xffffffd0 27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4 28#define EXPEVT 0xffffffd4
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7300) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710)
32#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 36#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
33#else 37#else
34#define INTEVT 0xffffffd8 38#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 2082ad956f21..b2394cf76f49 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -20,6 +20,7 @@
20 * SH7710 20 * SH7710
21 * SH7720 21 * SH7720
22 * SH7300 22 * SH7300
23 * SH7710
23 * --------------------------------------------------------------------------- 24 * ---------------------------------------------------------------------------
24 */ 25 */
25 26
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 0f809dec4e17..9d308cbe9b29 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,6 +11,19 @@
11#ifndef __ASM_CPU_SH3_UBC_H 11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710)
15#define UBC_BARA 0xa4ffffb0
16#define UBC_BAMRA 0xa4ffffb4
17#define UBC_BBRA 0xa4ffffb8
18#define UBC_BASRA 0xffffffe4
19#define UBC_BARB 0xa4ffffa0
20#define UBC_BAMRB 0xa4ffffa4
21#define UBC_BBRB 0xa4ffffa8
22#define UBC_BASRB 0xffffffe8
23#define UBC_BDRB 0xa4ffff90
24#define UBC_BDMRB 0xa4ffff94
25#define UBC_BRCR 0xa4ffff98
26#else
14#define UBC_BARA 0xffffffb0 27#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4 28#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8 29#define UBC_BBRA 0xffffffb8
@@ -22,6 +35,6 @@
22#define UBC_BDRB 0xffffff90 35#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94 36#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98 37#define UBC_BRCR 0xffffff98
38#endif
25 39
26#endif /* __ASM_CPU_SH3_UBC_H */ 40#endif /* __ASM_CPU_SH3_UBC_H */
27