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authorJeff Garzik <jeff@garzik.org>2006-12-07 04:57:19 -0500
committerJeff Garzik <jeff@garzik.org>2006-12-07 04:57:19 -0500
commit8d1413b28033c49c7f1a4d320e815d7a5531acee (patch)
treeb37281abef014cd60803b81c100388d7a475d49e /include/asm-sh/cpu-sh2
parented25ffa16434724f5ed825aa48734c7f3aefa203 (diff)
parent620034c84d1d939717bdfbe02c51a3fee43541c3 (diff)
Merge branch 'master' into upstream
Conflicts: drivers/net/netxen/netxen_nic.h drivers/net/netxen/netxen_nic_main.c
Diffstat (limited to 'include/asm-sh/cpu-sh2')
-rw-r--r--include/asm-sh/cpu-sh2/cache.h22
-rw-r--r--include/asm-sh/cpu-sh2/freq.h18
-rw-r--r--include/asm-sh/cpu-sh2/mmu_context.h16
-rw-r--r--include/asm-sh/cpu-sh2/timer.h6
4 files changed, 62 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604)
15#define CCR 0xfffffe92 /* Address of Cache Control Register */ 16#define CCR 0xfffffe92 /* Address of Cache Control Register */
16 17
17#define CCR_CACHE_CE 0x01 /* Cache enable */ 18#define CCR_CACHE_CE 0x01 /* Cache enable */
@@ -27,5 +28,26 @@
27#define CCR_CACHE_ORA CCR_CACHE_TW 28#define CCR_CACHE_ORA CCR_CACHE_TW
28#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ 29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
29 30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec
33#define CCR CCR1
34
35#define CCR_CACHE_CE 0x01 /* Cache enable */
36#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
37 /* 0x00000000-0x7fffffff: Write-through */
38 /* 0x80000000-0x9fffffff: Write-back */
39 /* 0xc0000000-0xdfffffff: Write-through */
40#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
41 /* 0x00000000-0x7fffffff: Write-back */
42 /* 0x80000000-0x9fffffff: Write-through */
43 /* 0xc0000000-0xdfffffff: Write-back */
44#define CCR_CACHE_CF 0x08 /* Cache invalidate */
45
46#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
47#define CACHE_OC_DATA_ARRAY 0xf1000000
48
49#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif
30#endif /* __ASM_CPU_SH2_CACHE_H */ 52#endif /* __ASM_CPU_SH2_CACHE_H */
31 53
diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h
new file mode 100644
index 000000000000..31de475da70b
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/freq.h
@@ -0,0 +1,18 @@
1/*
2 * include/asm-sh/cpu-sh2/freq.h
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_FREQ_H
11#define __ASM_CPU_SH2_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7619)
14#define FREQCR 0xf815ff80
15#endif
16
17#endif /* __ASM_CPU_SH2_FREQ_H */
18
diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h
new file mode 100644
index 000000000000..beeb299e01ec
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/mmu_context.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh2/mmu_context.h
3 *
4 * Copyright (C) 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
11#define __ASM_CPU_SH2_MMU_CONTEXT_H
12
13/* No MMU */
14
15#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
16
diff --git a/include/asm-sh/cpu-sh2/timer.h b/include/asm-sh/cpu-sh2/timer.h
new file mode 100644
index 000000000000..a39c241e8195
--- /dev/null
+++ b/include/asm-sh/cpu-sh2/timer.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_CPU_SH2_TIMER_H
2#define __ASM_CPU_SH2_TIMER_H
3
4/* Nothing needed yet */
5
6#endif /* __ASM_CPU_SH2_TIMER_H */