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authorYoshinori Sato <ysato@users.sourceforge.jp>2006-11-05 02:18:08 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-12-05 20:45:36 -0500
commitb229632abd451ab2c797010b9788e48c9314db4f (patch)
treebe097331d66985376057ff3ffbab742d60ac55ed /include/asm-sh/cpu-sh2/cache.h
parentde39840646a223ae13a346048c280b7c871bf56e (diff)
sh: Add SH-2A platform headers.
Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh2/cache.h')
-rw-r--r--include/asm-sh/cpu-sh2/cache.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index cd96402e8562..20b9796842dc 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604)
15#define CCR 0xfffffe92 /* Address of Cache Control Register */ 16#define CCR 0xfffffe92 /* Address of Cache Control Register */
16 17
17#define CCR_CACHE_CE 0x01 /* Cache enable */ 18#define CCR_CACHE_CE 0x01 /* Cache enable */
@@ -27,5 +28,26 @@
27#define CCR_CACHE_ORA CCR_CACHE_TW 28#define CCR_CACHE_ORA CCR_CACHE_TW
28#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ 29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
29 30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec
33#define CCR CCR1
34
35#define CCR_CACHE_CE 0x01 /* Cache enable */
36#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
37 /* 0x00000000-0x7fffffff: Write-through */
38 /* 0x80000000-0x9fffffff: Write-back */
39 /* 0xc0000000-0xdfffffff: Write-through */
40#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
41 /* 0x00000000-0x7fffffff: Write-back */
42 /* 0x80000000-0x9fffffff: Write-through */
43 /* 0xc0000000-0xdfffffff: Write-back */
44#define CCR_CACHE_CF 0x08 /* Cache invalidate */
45
46#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
47#define CACHE_OC_DATA_ARRAY 0xf1000000
48
49#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif
30#endif /* __ASM_CPU_SH2_CACHE_H */ 52#endif /* __ASM_CPU_SH2_CACHE_H */
31 53