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authorPaul Mundt <lethal@linux-sh.org>2007-06-07 22:55:28 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-06-07 22:55:28 -0400
commitb9601c5e59dd25693345558a301e833741bf5874 (patch)
tree992d8114b381354bc5e588766c065cc7728fe5df /include/asm-sh/cpu-sh2/cache.h
parent33d63bd83bf9aa6b662a376a96b825acba721e8f (diff)
sh: Kill off dead SH7604 support.
This was added during 2.5.x, but was never moved along. This can easily be resurrected if someone has one they wish to work with, but it's not worth keeping around in its current form. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh2/cache.h')
-rw-r--r--include/asm-sh/cpu-sh2/cache.h20
1 files changed, 2 insertions, 18 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index 20b9796842dc..f02ba7a672b2 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,23 +12,7 @@
12 12
13#define L1_CACHE_SHIFT 4 13#define L1_CACHE_SHIFT 4
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7604) 15#if defined(CONFIG_CPU_SUBTYPE_SH7619)
16#define CCR 0xfffffe92 /* Address of Cache Control Register */
17
18#define CCR_CACHE_CE 0x01 /* Cache enable */
19#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */
20#define CCR_CACHE_OD 0x04 /* Data Replacement disable */
21#define CCR_CACHE_TW 0x08 /* Two-way mode */
22#define CCR_CACHE_CP 0x10 /* Cache purge */
23
24#define CACHE_OC_ADDRESS_ARRAY 0x60000000
25
26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CP
28#define CCR_CACHE_ORA CCR_CACHE_TW
29#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */
30
31#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
32#define CCR1 0xffffffec 16#define CCR1 0xffffffec
33#define CCR CCR1 17#define CCR CCR1
34 18
@@ -49,5 +33,5 @@
49#define CCR_CACHE_ENABLE CCR_CACHE_CE 33#define CCR_CACHE_ENABLE CCR_CACHE_CE
50#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 34#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
51#endif 35#endif
52#endif /* __ASM_CPU_SH2_CACHE_H */
53 36
37#endif /* __ASM_CPU_SH2_CACHE_H */