diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 19:09:44 -0400 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 19:09:44 -0400 |
| commit | f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch) | |
| tree | 774d7b11abaaf33561ab8268bf51ddd9ceb79025 /include/asm-sh/cpu-sh2/cache.h | |
| parent | 25326277d8d1393d1c66240e6255aca780f9e3eb (diff) | |
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh2/cache.h')
| -rw-r--r-- | include/asm-sh/cpu-sh2/cache.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h deleted file mode 100644 index 4e0b16500686..000000000000 --- a/include/asm-sh/cpu-sh2/cache.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-sh/cpu-sh2/cache.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Paul Mundt | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file "COPYING" in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_CPU_SH2_CACHE_H | ||
| 11 | #define __ASM_CPU_SH2_CACHE_H | ||
| 12 | |||
| 13 | #define L1_CACHE_SHIFT 4 | ||
| 14 | |||
| 15 | #define SH_CACHE_VALID 1 | ||
| 16 | #define SH_CACHE_UPDATED 2 | ||
| 17 | #define SH_CACHE_COMBINED 4 | ||
| 18 | #define SH_CACHE_ASSOC 8 | ||
| 19 | |||
| 20 | #if defined(CONFIG_CPU_SUBTYPE_SH7619) | ||
| 21 | #define CCR 0xffffffec | ||
| 22 | |||
| 23 | #define CCR_CACHE_CE 0x01 /* Cache enable */ | ||
| 24 | #define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */ | ||
| 25 | /* 0x00000000-0x7fffffff: Write-through */ | ||
| 26 | /* 0x80000000-0x9fffffff: Write-back */ | ||
| 27 | /* 0xc0000000-0xdfffffff: Write-through */ | ||
| 28 | #define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */ | ||
| 29 | /* 0x00000000-0x7fffffff: Write-back */ | ||
| 30 | /* 0x80000000-0x9fffffff: Write-through */ | ||
| 31 | /* 0xc0000000-0xdfffffff: Write-back */ | ||
| 32 | #define CCR_CACHE_CF 0x08 /* Cache invalidate */ | ||
| 33 | |||
| 34 | #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 | ||
| 35 | #define CACHE_OC_DATA_ARRAY 0xf1000000 | ||
| 36 | |||
| 37 | #define CCR_CACHE_ENABLE CCR_CACHE_CE | ||
| 38 | #define CCR_CACHE_INVALIDATE CCR_CACHE_CF | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #endif /* __ASM_CPU_SH2_CACHE_H */ | ||