diff options
author | Stuart Menefy <stuart.menefy@st.com> | 2007-11-30 02:12:36 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-27 23:18:58 -0500 |
commit | 1efe4ce3ca126da77e450d5a83f7201949d76f62 (patch) | |
tree | fbae9902aa4103a9e86d06f841d580f24682e7b3 /include/asm-sh/bitops-irq.h | |
parent | 53ff09422e5e7a6d6198b767c8f494e43ec8e3ae (diff) |
sh: GUSA atomic rollback support.
This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/bitops-irq.h')
-rw-r--r-- | include/asm-sh/bitops-irq.h | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/include/asm-sh/bitops-irq.h b/include/asm-sh/bitops-irq.h new file mode 100644 index 000000000000..653a12750584 --- /dev/null +++ b/include/asm-sh/bitops-irq.h | |||
@@ -0,0 +1,91 @@ | |||
1 | #ifndef __ASM_SH_BITOPS_IRQ_H | ||
2 | #define __ASM_SH_BITOPS_IRQ_H | ||
3 | |||
4 | static inline void set_bit(int nr, volatile void *addr) | ||
5 | { | ||
6 | int mask; | ||
7 | volatile unsigned int *a = addr; | ||
8 | unsigned long flags; | ||
9 | |||
10 | a += nr >> 5; | ||
11 | mask = 1 << (nr & 0x1f); | ||
12 | local_irq_save(flags); | ||
13 | *a |= mask; | ||
14 | local_irq_restore(flags); | ||
15 | } | ||
16 | |||
17 | static inline void clear_bit(int nr, volatile void *addr) | ||
18 | { | ||
19 | int mask; | ||
20 | volatile unsigned int *a = addr; | ||
21 | unsigned long flags; | ||
22 | |||
23 | a += nr >> 5; | ||
24 | mask = 1 << (nr & 0x1f); | ||
25 | local_irq_save(flags); | ||
26 | *a &= ~mask; | ||
27 | local_irq_restore(flags); | ||
28 | } | ||
29 | |||
30 | static inline void change_bit(int nr, volatile void *addr) | ||
31 | { | ||
32 | int mask; | ||
33 | volatile unsigned int *a = addr; | ||
34 | unsigned long flags; | ||
35 | |||
36 | a += nr >> 5; | ||
37 | mask = 1 << (nr & 0x1f); | ||
38 | local_irq_save(flags); | ||
39 | *a ^= mask; | ||
40 | local_irq_restore(flags); | ||
41 | } | ||
42 | |||
43 | static inline int test_and_set_bit(int nr, volatile void *addr) | ||
44 | { | ||
45 | int mask, retval; | ||
46 | volatile unsigned int *a = addr; | ||
47 | unsigned long flags; | ||
48 | |||
49 | a += nr >> 5; | ||
50 | mask = 1 << (nr & 0x1f); | ||
51 | local_irq_save(flags); | ||
52 | retval = (mask & *a) != 0; | ||
53 | *a |= mask; | ||
54 | local_irq_restore(flags); | ||
55 | |||
56 | return retval; | ||
57 | } | ||
58 | |||
59 | static inline int test_and_clear_bit(int nr, volatile void *addr) | ||
60 | { | ||
61 | int mask, retval; | ||
62 | volatile unsigned int *a = addr; | ||
63 | unsigned long flags; | ||
64 | |||
65 | a += nr >> 5; | ||
66 | mask = 1 << (nr & 0x1f); | ||
67 | local_irq_save(flags); | ||
68 | retval = (mask & *a) != 0; | ||
69 | *a &= ~mask; | ||
70 | local_irq_restore(flags); | ||
71 | |||
72 | return retval; | ||
73 | } | ||
74 | |||
75 | static inline int test_and_change_bit(int nr, volatile void *addr) | ||
76 | { | ||
77 | int mask, retval; | ||
78 | volatile unsigned int *a = addr; | ||
79 | unsigned long flags; | ||
80 | |||
81 | a += nr >> 5; | ||
82 | mask = 1 << (nr & 0x1f); | ||
83 | local_irq_save(flags); | ||
84 | retval = (mask & *a) != 0; | ||
85 | *a ^= mask; | ||
86 | local_irq_restore(flags); | ||
87 | |||
88 | return retval; | ||
89 | } | ||
90 | |||
91 | #endif /* __ASM_SH_BITOPS_IRQ_H */ | ||