diff options
| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2006-09-28 10:56:43 -0400 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2006-09-28 10:56:43 -0400 |
| commit | 94c12cc7d196bab34aaa98d38521549fa1e5ef76 (patch) | |
| tree | 8e0cec0ed44445d74a2cb5160303d6b4dfb1bc31 /include/asm-s390/sfp-machine.h | |
| parent | 25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (diff) | |
[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common
coding style. Quite a few have been shortened, mainly by using register
asm variables. Use of the EX_TABLE macro helps as well. The atomic ops,
bit ops and locking inlines new use the Q-constraint if a newer gcc
is used. That results in slightly better code.
Thanks to Christian Borntraeger for proof reading the changes.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'include/asm-s390/sfp-machine.h')
| -rw-r--r-- | include/asm-s390/sfp-machine.h | 64 |
1 files changed, 34 insertions, 30 deletions
diff --git a/include/asm-s390/sfp-machine.h b/include/asm-s390/sfp-machine.h index de69dfa46fbb..8ca8c77b2d04 100644 --- a/include/asm-s390/sfp-machine.h +++ b/include/asm-s390/sfp-machine.h | |||
| @@ -76,21 +76,23 @@ | |||
| 76 | unsigned int __r2 = (x2) + (y2); \ | 76 | unsigned int __r2 = (x2) + (y2); \ |
| 77 | unsigned int __r1 = (x1); \ | 77 | unsigned int __r1 = (x1); \ |
| 78 | unsigned int __r0 = (x0); \ | 78 | unsigned int __r0 = (x0); \ |
| 79 | __asm__ (" alr %2,%3\n" \ | 79 | asm volatile( \ |
| 80 | " brc 12,0f\n" \ | 80 | " alr %2,%3\n" \ |
| 81 | " lhi 0,1\n" \ | 81 | " brc 12,0f\n" \ |
| 82 | " alr %1,0\n" \ | 82 | " lhi 0,1\n" \ |
| 83 | " brc 12,0f\n" \ | 83 | " alr %1,0\n" \ |
| 84 | " alr %0,0\n" \ | 84 | " brc 12,0f\n" \ |
| 85 | "0:" \ | 85 | " alr %0,0\n" \ |
| 86 | : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \ | 86 | "0:" \ |
| 87 | : "d" (y0), "i" (1) : "cc", "0" ); \ | 87 | : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \ |
| 88 | __asm__ (" alr %1,%2\n" \ | 88 | : "d" (y0), "i" (1) : "cc", "0" ); \ |
| 89 | " brc 12,0f\n" \ | 89 | asm volatile( \ |
| 90 | " ahi %0,1\n" \ | 90 | " alr %1,%2\n" \ |
| 91 | "0:" \ | 91 | " brc 12,0f\n" \ |
| 92 | : "+&d" (__r2), "+&d" (__r1) \ | 92 | " ahi %0,1\n" \ |
| 93 | : "d" (y1) : "cc" ); \ | 93 | "0:" \ |
| 94 | : "+&d" (__r2), "+&d" (__r1) \ | ||
| 95 | : "d" (y1) : "cc"); \ | ||
| 94 | (r2) = __r2; \ | 96 | (r2) = __r2; \ |
| 95 | (r1) = __r1; \ | 97 | (r1) = __r1; \ |
| 96 | (r0) = __r0; \ | 98 | (r0) = __r0; \ |
| @@ -100,21 +102,23 @@ | |||
| 100 | unsigned int __r2 = (x2) - (y2); \ | 102 | unsigned int __r2 = (x2) - (y2); \ |
| 101 | unsigned int __r1 = (x1); \ | 103 | unsigned int __r1 = (x1); \ |
| 102 | unsigned int __r0 = (x0); \ | 104 | unsigned int __r0 = (x0); \ |
| 103 | __asm__ (" slr %2,%3\n" \ | 105 | asm volatile( \ |
| 104 | " brc 3,0f\n" \ | 106 | " slr %2,%3\n" \ |
| 105 | " lhi 0,1\n" \ | 107 | " brc 3,0f\n" \ |
| 106 | " slr %1,0\n" \ | 108 | " lhi 0,1\n" \ |
| 107 | " brc 3,0f\n" \ | 109 | " slr %1,0\n" \ |
| 108 | " slr %0,0\n" \ | 110 | " brc 3,0f\n" \ |
| 109 | "0:" \ | 111 | " slr %0,0\n" \ |
| 110 | : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \ | 112 | "0:" \ |
| 111 | : "d" (y0) : "cc", "0" ); \ | 113 | : "+&d" (__r2), "+&d" (__r1), "+&d" (__r0) \ |
| 112 | __asm__ (" slr %1,%2\n" \ | 114 | : "d" (y0) : "cc", "0"); \ |
| 113 | " brc 3,0f\n" \ | 115 | asm volatile( \ |
| 114 | " ahi %0,-1\n" \ | 116 | " slr %1,%2\n" \ |
| 115 | "0:" \ | 117 | " brc 3,0f\n" \ |
| 116 | : "+&d" (__r2), "+&d" (__r1) \ | 118 | " ahi %0,-1\n" \ |
| 117 | : "d" (y1) : "cc" ); \ | 119 | "0:" \ |
| 120 | : "+&d" (__r2), "+&d" (__r1) \ | ||
| 121 | : "d" (y1) : "cc"); \ | ||
| 118 | (r2) = __r2; \ | 122 | (r2) = __r2; \ |
| 119 | (r1) = __r1; \ | 123 | (r1) = __r1; \ |
| 120 | (r0) = __r0; \ | 124 | (r0) = __r0; \ |