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authorMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2006-09-28 10:56:43 -0400
commit94c12cc7d196bab34aaa98d38521549fa1e5ef76 (patch)
tree8e0cec0ed44445d74a2cb5160303d6b4dfb1bc31 /include/asm-s390/irqflags.h
parent25d83cbfaa44e1b9170c0941c3ef52ca39f54ccc (diff)
[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'include/asm-s390/irqflags.h')
-rw-r--r--include/asm-s390/irqflags.h110
1 files changed, 80 insertions, 30 deletions
diff --git a/include/asm-s390/irqflags.h b/include/asm-s390/irqflags.h
index 3b566a5b3cc7..3f26131120b7 100644
--- a/include/asm-s390/irqflags.h
+++ b/include/asm-s390/irqflags.h
@@ -10,43 +10,93 @@
10 10
11#ifdef __KERNEL__ 11#ifdef __KERNEL__
12 12
13#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
14
15/* store then or system mask. */
16#define __raw_local_irq_stosm(__or) \
17({ \
18 unsigned long __mask; \
19 asm volatile( \
20 " stosm %0,%1" \
21 : "=Q" (__mask) : "i" (__or) : "memory"); \
22 __mask; \
23})
24
25/* store then and system mask. */
26#define __raw_local_irq_stnsm(__and) \
27({ \
28 unsigned long __mask; \
29 asm volatile( \
30 " stnsm %0,%1" \
31 : "=Q" (__mask) : "i" (__and) : "memory"); \
32 __mask; \
33})
34
35/* set system mask. */
36#define __raw_local_irq_ssm(__mask) \
37({ \
38 asm volatile("ssm %0" : : "Q" (__mask) : "memory"); \
39})
40
41#else /* __GNUC__ */
42
43/* store then or system mask. */
44#define __raw_local_irq_stosm(__or) \
45({ \
46 unsigned long __mask; \
47 asm volatile( \
48 " stosm 0(%1),%2" \
49 : "=m" (__mask) \
50 : "a" (&__mask), "i" (__or) : "memory"); \
51 __mask; \
52})
53
54/* store then and system mask. */
55#define __raw_local_irq_stnsm(__and) \
56({ \
57 unsigned long __mask; \
58 asm volatile( \
59 " stnsm 0(%1),%2" \
60 : "=m" (__mask) \
61 : "a" (&__mask), "i" (__and) : "memory"); \
62 __mask; \
63})
64
65/* set system mask. */
66#define __raw_local_irq_ssm(__mask) \
67({ \
68 asm volatile( \
69 " ssm 0(%0)" \
70 : : "a" (&__mask), "m" (__mask) : "memory"); \
71})
72
73#endif /* __GNUC__ */
74
13/* interrupt control.. */ 75/* interrupt control.. */
14#define raw_local_irq_enable() ({ \ 76static inline unsigned long raw_local_irq_enable(void)
15 unsigned long __dummy; \ 77{
16 __asm__ __volatile__ ( \ 78 return __raw_local_irq_stosm(0x03);
17 "stosm 0(%1),0x03" \ 79}
18 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
19 })
20
21#define raw_local_irq_disable() ({ \
22 unsigned long __flags; \
23 __asm__ __volatile__ ( \
24 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
25 __flags; \
26 })
27
28#define raw_local_save_flags(x) \
29do { \
30 typecheck(unsigned long, x); \
31 __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) ); \
32} while (0)
33 80
34#define raw_local_irq_restore(x) \ 81static inline unsigned long raw_local_irq_disable(void)
35do { \ 82{
36 typecheck(unsigned long, x); \ 83 return __raw_local_irq_stnsm(0xfc);
37 __asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory"); \ 84}
85
86#define raw_local_save_flags(x) \
87do { \
88 typecheck(unsigned long, x); \
89 (x) = __raw_local_irq_stosm(0x00); \
38} while (0) 90} while (0)
39 91
40#define raw_irqs_disabled() \ 92static inline void raw_local_irq_restore(unsigned long flags)
41({ \ 93{
42 unsigned long flags; \ 94 __raw_local_irq_ssm(flags);
43 raw_local_save_flags(flags); \ 95}
44 !((flags >> __FLAG_SHIFT) & 3); \
45})
46 96
47static inline int raw_irqs_disabled_flags(unsigned long flags) 97static inline int raw_irqs_disabled_flags(unsigned long flags)
48{ 98{
49 return !((flags >> __FLAG_SHIFT) & 3); 99 return !(flags & (3UL << (BITS_PER_LONG - 8)));
50} 100}
51 101
52/* For spinlocks etc */ 102/* For spinlocks etc */