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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2007-12-20 23:39:21 -0500
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-12-23 14:11:59 -0500
commit47c0bd1ae24c34e851cf0f2b02ef2a6847d7ae15 (patch)
tree86fab68618a4afa03660cc576c9e7da3e5a0b520 /include/asm-ppc
parentc2a7dcad9f0d92d7a96e735abb8bec7b9c621536 (diff)
[POWERPC] Reworking machine check handling and Fix 440/440A
This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/reg_booke.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 4cad45a055dd..2f1a2afcfc28 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -207,7 +207,7 @@
207#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 207#define CCR1_TCS 0x00000080 /* Timer Clock Select */
208 208
209/* Bit definitions for the MCSR. */ 209/* Bit definitions for the MCSR. */
210#ifdef CONFIG_440A 210#ifdef CONFIG_4xx
211#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 211#define MCSR_MCS 0x80000000 /* Machine Check Summary */
212#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 212#define MCSR_IB 0x40000000 /* Instruction PLB Error */
213#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 213#define MCSR_DRB 0x20000000 /* Data Read PLB Error */