Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

177 files changed, 26140 insertions, 0 deletions

diff --git a/include/asm-ppc/8253pit.h b/include/asm-ppc/8253pit.h
new file mode 100644
index 000000000000..285f78488ccb
--- /dev/null
+++ b/include/asm-ppc/8253pit.h
@@ -0,0 +1,10 @@
+/*
+ * 8253/8254 Programmable Interval Timer
+ */
+
+#ifndef _8253PIT_H
+#define _8253PIT_H
+
+#define PIT_TICK_RATE   1193182UL
+
+#endif
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
new file mode 100644
index 000000000000..1311cefdfd30
--- /dev/null
+++ b/include/asm-ppc/8xx_immap.h
@@ -0,0 +1,564 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifdef __KERNEL__
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef struct sys_conf {
+        uint    sc_siumcr;
+        uint    sc_sypcr;
+        uint    sc_swt;
+        char    res1[2];
+        ushort  sc_swsr;
+        uint    sc_sipend;
+        uint    sc_simask;
+        uint    sc_siel;
+        uint    sc_sivec;
+        uint    sc_tesr;
+        char    res2[0xc];
+        uint    sc_sdcr;
+        char    res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+        uint    pcmc_pbr0;
+        uint    pcmc_por0;
+        uint    pcmc_pbr1;
+        uint    pcmc_por1;
+        uint    pcmc_pbr2;
+        uint    pcmc_por2;
+        uint    pcmc_pbr3;
+        uint    pcmc_por3;
+        uint    pcmc_pbr4;
+        uint    pcmc_por4;
+        uint    pcmc_pbr5;
+        uint    pcmc_por5;
+        uint    pcmc_pbr6;
+        uint    pcmc_por6;
+        uint    pcmc_pbr7;
+        uint    pcmc_por7;
+        char    res1[0x20];
+        uint    pcmc_pgcra;
+        uint    pcmc_pgcrb;
+        uint    pcmc_pscr;
+        char    res2[4];
+        uint    pcmc_pipr;
+        char    res3[4];
+        uint    pcmc_per;
+        char    res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct  mem_ctlr {
+        uint    memc_br0;
+        uint    memc_or0;
+        uint    memc_br1;
+        uint    memc_or1;
+        uint    memc_br2;
+        uint    memc_or2;
+        uint    memc_br3;
+        uint    memc_or3;
+        uint    memc_br4;
+        uint    memc_or4;
+        uint    memc_br5;
+        uint    memc_or5;
+        uint    memc_br6;
+        uint    memc_or6;
+        uint    memc_br7;
+        uint    memc_or7;
+        char    res1[0x24];
+        uint    memc_mar;
+        uint    memc_mcr;
+        char    res2[4];
+        uint    memc_mamr;
+        uint    memc_mbmr;
+        ushort  memc_mstat;
+        ushort  memc_mptpr;
+        uint    memc_mdr;
+        char    res3[0x80];
+} memctl8xx_t;
+
+/*-----------------------------------------------------------------------
+ * BR - Memory Controler: Base Register                                 16-9
+ */
+#define BR_BA_MSK       0xffff8000      /* Base Address Mask                    */
+#define BR_AT_MSK       0x00007000      /* Address Type Mask                    */
+#define BR_PS_MSK       0x00000c00      /* Port Size Mask                       */
+#define BR_PS_32        0x00000000      /* 32 bit port size                     */
+#define BR_PS_16        0x00000800      /* 16 bit port size                     */
+#define BR_PS_8         0x00000400      /*  8 bit port size                     */
+#define BR_PARE         0x00000200      /* Parity Enable                        */
+#define BR_WP           0x00000100      /* Write Protect                        */
+#define BR_MS_MSK       0x000000c0      /* Machine Select Mask                  */
+#define BR_MS_GPCM      0x00000000      /* G.P.C.M. Machine Select              */
+#define BR_MS_UPMA      0x00000080      /* U.P.M.A Machine Select               */
+#define BR_MS_UPMB      0x000000c0      /* U.P.M.B Machine Select               */
+#define BR_V            0x00000001      /* Bank Valid                           */
+
+/*-----------------------------------------------------------------------
+ * OR - Memory Controler: Option Register                               16-11
+ */
+#define OR_AM_MSK       0xffff8000      /* Address Mask Mask                    */
+#define OR_ATM_MSK      0x00007000      /* Address Type Mask Mask               */
+#define OR_CSNT_SAM     0x00000800      /* Chip Select Negation Time/ Start     */
+                                        /* Address Multiplex                    */
+#define OR_ACS_MSK      0x00000600      /* Address to Chip Select Setup mask    */
+#define OR_ACS_DIV1     0x00000000      /* CS is output at the same time        */
+#define OR_ACS_DIV4     0x00000400      /* CS is output 1/4 a clock later       */
+#define OR_ACS_DIV2     0x00000600      /* CS is output 1/2 a clock later       */
+#define OR_G5LA         0x00000400      /* Output #GPL5 on #GPL_A5              */
+#define OR_G5LS         0x00000200      /* Drive #GPL high on falling edge of...*/
+#define OR_BI           0x00000100      /* Burst inhibit                        */
+#define OR_SCY_MSK      0x000000f0      /* Cycle Lenght in Clocks               */
+#define OR_SCY_0_CLK    0x00000000      /* 0 clock cycles wait states           */
+#define OR_SCY_1_CLK    0x00000010      /* 1 clock cycles wait states           */
+#define OR_SCY_2_CLK    0x00000020      /* 2 clock cycles wait states           */
+#define OR_SCY_3_CLK    0x00000030      /* 3 clock cycles wait states           */
+#define OR_SCY_4_CLK    0x00000040      /* 4 clock cycles wait states           */
+#define OR_SCY_5_CLK    0x00000050      /* 5 clock cycles wait states           */
+#define OR_SCY_6_CLK    0x00000060      /* 6 clock cycles wait states           */
+#define OR_SCY_7_CLK    0x00000070      /* 7 clock cycles wait states           */
+#define OR_SCY_8_CLK    0x00000080      /* 8 clock cycles wait states           */
+#define OR_SCY_9_CLK    0x00000090      /* 9 clock cycles wait states           */
+#define OR_SCY_10_CLK   0x000000a0      /* 10 clock cycles wait states          */
+#define OR_SCY_11_CLK   0x000000b0      /* 11 clock cycles wait states          */
+#define OR_SCY_12_CLK   0x000000c0      /* 12 clock cycles wait states          */
+#define OR_SCY_13_CLK   0x000000d0      /* 13 clock cycles wait states          */
+#define OR_SCY_14_CLK   0x000000e0      /* 14 clock cycles wait states          */
+#define OR_SCY_15_CLK   0x000000f0      /* 15 clock cycles wait states          */
+#define OR_SETA         0x00000008      /* External Transfer Acknowledge        */
+#define OR_TRLX         0x00000004      /* Timing Relaxed                       */
+#define OR_EHTR         0x00000002      /* Extended Hold Time on Read           */
+
+/* System Integration Timers.
+*/
+typedef struct  sys_int_timers {
+        ushort  sit_tbscr;
+        char    res0[0x02];
+        uint    sit_tbreff0;
+        uint    sit_tbreff1;
+        char    res1[0x14];
+        ushort  sit_rtcsc;
+        char    res2[0x02];
+        uint    sit_rtc;
+        uint    sit_rtsec;
+        uint    sit_rtcal;
+        char    res3[0x10];
+        ushort  sit_piscr;
+        char    res4[2];
+        uint    sit_pitc;
+        uint    sit_pitr;
+        char    res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK        ((ushort)0xff00)
+#define TBSCR_REFA              ((ushort)0x0080)
+#define TBSCR_REFB              ((ushort)0x0040)
+#define TBSCR_REFAE             ((ushort)0x0008)
+#define TBSCR_REFBE             ((ushort)0x0004)
+#define TBSCR_TBF               ((ushort)0x0002)
+#define TBSCR_TBE               ((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK       ((ushort)0xff00)
+#define RTCSC_SEC               ((ushort)0x0080)
+#define RTCSC_ALR               ((ushort)0x0040)
+#define RTCSC_38K               ((ushort)0x0010)
+#define RTCSC_SIE               ((ushort)0x0008)
+#define RTCSC_ALE               ((ushort)0x0004)
+#define RTCSC_RTF               ((ushort)0x0002)
+#define RTCSC_RTE               ((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK         ((ushort)0xff00)
+#define PISCR_PS                ((ushort)0x0080)
+#define PISCR_PIE               ((ushort)0x0004)
+#define PISCR_PTF               ((ushort)0x0002)
+#define PISCR_PTE               ((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+        uint    car_sccr;
+        uint    car_plprcr;
+        uint    car_rsr;
+        char    res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+        uint    sitk_tbscrk;
+        uint    sitk_tbreff0k;
+        uint    sitk_tbreff1k;
+        uint    sitk_tbk;
+        char    res1[0x10];
+        uint    sitk_rtcsck;
+        uint    sitk_rtck;
+        uint    sitk_rtseck;
+        uint    sitk_rtcalk;
+        char    res2[0x10];
+        uint    sitk_piscrk;
+        uint    sitk_pitck;
+        char    res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+        uint    cark_sccrk;
+        uint    cark_plprcrk;
+        uint    cark_rsrk;
+        char    res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY       ((unsigned int)0x55ccaa33)
+
+/* Video interface.  MPC823 Only.
+*/
+typedef struct vid823 {
+        ushort  vid_vccr;
+        ushort  res1;
+        u_char  vid_vsr;
+        u_char  res2;
+        u_char  vid_vcmr;
+        u_char  res3;
+        uint    vid_vbcb;
+        uint    res4;
+        uint    vid_vfcr0;
+        uint    vid_vfaa0;
+        uint    vid_vfba0;
+        uint    vid_vfcr1;
+        uint    vid_vfaa1;
+        uint    vid_vfba1;
+        u_char  res5[0x18];
+} vid823_t;
+
+/* LCD interface.  823 Only.
+*/
+typedef struct lcd {
+        uint    lcd_lccr;
+        uint    lcd_lchcr;
+        uint    lcd_lcvcr;
+        char    res1[4];
+        uint    lcd_lcfaa;
+        uint    lcd_lcfba;
+        char    lcd_lcsr;
+        char    res2[0x7];
+} lcd823_t;
+
+/* I2C
+*/
+typedef struct i2c {
+        u_char  i2c_i2mod;
+        char    res1[3];
+        u_char  i2c_i2add;
+        char    res2[3];
+        u_char  i2c_i2brg;
+        char    res3[3];
+        u_char  i2c_i2com;
+        char    res4[3];
+        u_char  i2c_i2cer;
+        char    res5[3];
+        u_char  i2c_i2cmr;
+        char    res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+        char    res1[4];
+        uint    sdma_sdar;
+        u_char  sdma_sdsr;
+        char    res3[3];
+        u_char  sdma_sdmr;
+        char    res4[3];
+        u_char  sdma_idsr1;
+        char    res5[3];
+        u_char  sdma_idmr1;
+        char    res6[3];
+        u_char  sdma_idsr2;
+        char    res7[3];
+        u_char  sdma_idmr2;
+        char    res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+        ushort  cpic_civr;
+        char    res[0xe];
+        uint    cpic_cicr;
+        uint    cpic_cipr;
+        uint    cpic_cimr;
+        uint    cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+        ushort  iop_padir;
+        ushort  iop_papar;
+        ushort  iop_paodr;
+        ushort  iop_padat;
+        char    res1[8];
+        ushort  iop_pcdir;
+        ushort  iop_pcpar;
+        ushort  iop_pcso;
+        ushort  iop_pcdat;
+        ushort  iop_pcint;
+        char    res2[6];
+        ushort  iop_pddir;
+        ushort  iop_pdpar;
+        char    res3[2];
+        ushort  iop_pddat;
+        uint    utmode;
+        char    res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+        ushort  cpmt_tgcr;
+        char    res1[0xe];
+        ushort  cpmt_tmr1;
+        ushort  cpmt_tmr2;
+        ushort  cpmt_trr1;
+        ushort  cpmt_trr2;
+        ushort  cpmt_tcr1;
+        ushort  cpmt_tcr2;
+        ushort  cpmt_tcn1;
+        ushort  cpmt_tcn2;
+        ushort  cpmt_tmr3;
+        ushort  cpmt_tmr4;
+        ushort  cpmt_trr3;
+        ushort  cpmt_trr4;
+        ushort  cpmt_tcr3;
+        ushort  cpmt_tcr4;
+        ushort  cpmt_tcn3;
+        ushort  cpmt_tcn4;
+        ushort  cpmt_ter1;
+        ushort  cpmt_ter2;
+        ushort  cpmt_ter3;
+        ushort  cpmt_ter4;
+        char    res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {            /* Serial communication channels */
+        uint    scc_gsmrl;
+        uint    scc_gsmrh;
+        ushort  scc_psmr;
+        char    res1[2];
+        ushort  scc_todr;
+        ushort  scc_dsr;
+        ushort  scc_scce;
+        char    res2[2];
+        ushort  scc_sccm;
+        char    res3;
+        u_char  scc_sccs;
+        char    res4[8];
+} scc_t;
+
+typedef struct smc {            /* Serial management channels */
+        char    res1[2];
+        ushort  smc_smcmr;
+        char    res2[2];
+        u_char  smc_smce;
+        char    res3[3];
+        u_char  smc_smcm;
+        char    res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+        uint    fec_addr_low;           /* lower 32 bits of station address     */
+        ushort  fec_addr_high;          /* upper 16 bits of station address     */
+        ushort  res1;                   /* reserved                             */
+        uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
+        uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
+        uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
+        uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
+        uint    fec_r_buff_size;        /* Rx buffer size                       */
+        uint    res2[9];                /* reserved                             */
+        uint    fec_ecntrl;             /* ethernet control register            */
+        uint    fec_ievent;             /* interrupt event register             */
+        uint    fec_imask;              /* interrupt mask register              */
+        uint    fec_ivec;               /* interrupt level and vector status    */
+        uint    fec_r_des_active;       /* Rx ring updated flag                 */
+        uint    fec_x_des_active;       /* Tx ring updated flag                 */
+        uint    res3[10];               /* reserved                             */
+        uint    fec_mii_data;           /* MII data register                    */
+        uint    fec_mii_speed;          /* MII speed control register           */
+        uint    res4[17];               /* reserved                             */
+        uint    fec_r_bound;            /* end of RAM (read-only)               */
+        uint    fec_r_fstart;           /* Rx FIFO start address                */
+        uint    res5[6];                /* reserved                             */
+        uint    fec_x_fstart;           /* Tx FIFO start address                */
+        uint    res6[17];               /* reserved                             */
+        uint    fec_fun_code;           /* fec SDMA function code               */
+        uint    res7[3];                /* reserved                             */
+        uint    fec_r_cntrl;            /* Rx control register                  */
+        uint    fec_r_hash;             /* Rx hash register                     */
+        uint    res8[14];               /* reserved                             */
+        uint    fec_x_cntrl;            /* Tx control register                  */
+        uint    res9[0x1e];             /* reserved                             */
+} fec_t;
+
+/* The FEC and LCD color map share the same address space....
+ * I guess we will never see an 823T :-).
+ */
+union fec_lcd {
+        fec_t   fl_un_fec;
+        u_char  fl_un_cmap[0x200];
+};
+
+typedef struct comm_proc {
+        /* General control and status registers.
+        */
+        ushort  cp_cpcr;
+        u_char  res1[2];
+        ushort  cp_rccr;
+        u_char  res2;
+        u_char  cp_rmds;
+        u_char  res3[4];
+        ushort  cp_cpmcr1;
+        ushort  cp_cpmcr2;
+        ushort  cp_cpmcr3;
+        ushort  cp_cpmcr4;
+        u_char  res4[2];
+        ushort  cp_rter;
+        u_char  res5[2];
+        ushort  cp_rtmr;
+        u_char  res6[0x14];
+
+        /* Baud rate generators.
+        */
+        uint    cp_brgc1;
+        uint    cp_brgc2;
+        uint    cp_brgc3;
+        uint    cp_brgc4;
+
+        /* Serial Communication Channels.
+        */
+        scc_t   cp_scc[4];
+
+        /* Serial Management Channels.
+        */
+        smc_t   cp_smc[2];
+
+        /* Serial Peripheral Interface.
+        */
+        ushort  cp_spmode;
+        u_char  res7[4];
+        u_char  cp_spie;
+        u_char  res8[3];
+        u_char  cp_spim;
+        u_char  res9[2];
+        u_char  cp_spcom;
+        u_char  res10[2];
+
+        /* Parallel Interface Port.
+        */
+        u_char  res11[2];
+        ushort  cp_pipc;
+        u_char  res12[2];
+        ushort  cp_ptpr;
+        uint    cp_pbdir;
+        uint    cp_pbpar;
+        u_char  res13[2];
+        ushort  cp_pbodr;
+        uint    cp_pbdat;
+
+        /* Port E - MPC87x/88x only.
+         */
+        uint    cp_pedir;
+        uint    cp_pepar;
+        uint    cp_peso;
+        uint    cp_peodr;
+        uint    cp_pedat;
+
+        /* Communications Processor Timing Register -
+           Contains RMII Timing for the FECs on MPC87x/88x only.
+        */
+        uint    cp_cptr;
+
+        /* Serial Interface and Time Slot Assignment.
+        */
+        uint    cp_simode;
+        u_char  cp_sigmr;
+        u_char  res15;
+        u_char  cp_sistr;
+        u_char  cp_sicmr;
+        u_char  res16[4];
+        uint    cp_sicr;
+        uint    cp_sirp;
+        u_char  res17[0xc];
+
+        /* 256 bytes of MPC823 video controller RAM array.
+        */
+        u_char  cp_vcram[0x100];
+        u_char  cp_siram[0x200];
+
+        /* The fast ethernet controller is not really part of the CPM,
+         * but it resides in the address space.
+         * The LCD color map is also here.
+         */
+        union   fec_lcd fl_un;
+#define cp_fec          fl_un.fl_un_fec
+#define lcd_cmap        fl_un.fl_un_cmap
+        char    res18[0xE00];
+
+        /* The DUET family has a second FEC here */
+        fec_t   cp_fec2;
+#define cp_fec1 cp_fec  /* consistency macro */
+
+        /* Dual Ported RAM follows.
+         * There are many different formats for this memory area
+         * depending upon the devices used and options chosen.
+         * Some processors don't have all of it populated.
+         */
+        u_char  cp_dpmem[0x1C00];       /* BD / Data / ucode */
+        u_char  cp_dparam[0x400];       /* Parameter RAM */
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+        sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
+        pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
+        memctl8xx_t     im_memctl;      /* Memory Controller */
+        sit8xx_t        im_sit;         /* System integration timers */
+        car8xx_t        im_clkrst;      /* Clocks and reset */
+        sitk8xx_t       im_sitk;        /* Sys int timer keys */
+        cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
+        vid823_t        im_vid;         /* Video (823 only) */
+        lcd823_t        im_lcd;         /* LCD (823 only) */
+        i2c8xx_t        im_i2c;         /* I2C control/status */
+        sdma8xx_t       im_sdma;        /* SDMA control/status */
+        cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
+        iop8xx_t        im_ioport;      /* IO Port control/status */
+        cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
+        cpm8xx_t        im_cpm;         /* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/a.out.h b/include/asm-ppc/a.out.h
new file mode 100644
index 000000000000..8979a94c4a81
--- /dev/null
+++ b/include/asm-ppc/a.out.h
@@ -0,0 +1,26 @@
+#ifndef __PPC_A_OUT_H__
+#define __PPC_A_OUT_H__
+
+/* grabbed from the intel stuff  */
+#define STACK_TOP TASK_SIZE
+
+
+struct exec
+{
+  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
+  unsigned a_text;              /* length of text, in bytes */
+  unsigned a_data;              /* length of data, in bytes */
+  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
+  unsigned a_syms;              /* length of symbol table data in file, in bytes */
+  unsigned a_entry;             /* start address */
+  unsigned a_trsize;            /* length of relocation info for text, in bytes */
+  unsigned a_drsize;            /* length of relocation info for data, in bytes */
+};
+
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+
+#endif
diff --git a/include/asm-ppc/agp.h b/include/asm-ppc/agp.h
new file mode 100644
index 000000000000..be27cfa8c5b0
--- /dev/null
+++ b/include/asm-ppc/agp.h
@@ -0,0 +1,13 @@
+#ifndef AGP_H
+#define AGP_H 1
+
+#include <asm/io.h>
+
+/* nothing much needed here */
+
+#define map_page_into_agp(page)
+#define unmap_page_from_agp(page)
+#define flush_agp_mappings()
+#define flush_agp_cache() mb()
+
+#endif
diff --git a/include/asm-ppc/amigahw.h b/include/asm-ppc/amigahw.h
new file mode 100644
index 000000000000..8c98945e7dc1
--- /dev/null
+++ b/include/asm-ppc/amigahw.h
@@ -0,0 +1,17 @@
+#ifdef __KERNEL__
+#ifndef __ASMPPC_AMIGAHW_H
+#define __ASMPPC_AMIGAHW_H
+
+#include <linux/config.h>
+#include <asm-m68k/amigahw.h>
+
+#undef CHIP_PHYSADDR
+#ifdef CONFIG_APUS_FAST_EXCEPT
+#define CHIP_PHYSADDR      (0x000000)
+#else
+#define CHIP_PHYSADDR      (0x004000)
+#endif
+
+
+#endif /* __ASMPPC_AMIGAHW_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/amigaints.h b/include/asm-ppc/amigaints.h
new file mode 100644
index 000000000000..aa3ff6349e81
--- /dev/null
+++ b/include/asm-ppc/amigaints.h
@@ -0,0 +1,133 @@
+/*
+** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License.  See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created 10/2/92 by Greg Harp
+*/
+
+#ifdef __KERNEL__
+#ifndef _ASMm68k_AMIGAINTS_H_
+#define _ASMm68k_AMIGAINTS_H_
+
+/*
+** Amiga Interrupt sources.
+**
+*/
+
+#define AUTO_IRQS           (8)
+#define AMI_STD_IRQS        (14)
+#define CIA_IRQS            (5)
+#define AMI_IRQS            (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
+
+/* vertical blanking interrupt */
+#define IRQ_AMIGA_VERTB     0
+
+/* copper interrupt */
+#define IRQ_AMIGA_COPPER    1
+
+/* Audio interrupts */
+#define IRQ_AMIGA_AUD0      2
+#define IRQ_AMIGA_AUD1      3
+#define IRQ_AMIGA_AUD2      4
+#define IRQ_AMIGA_AUD3      5
+
+/* Blitter done interrupt */
+#define IRQ_AMIGA_BLIT      6
+
+/* floppy disk interrupts */
+#define IRQ_AMIGA_DSKSYN    7
+#define IRQ_AMIGA_DSKBLK    8
+
+/* builtin serial port interrupts */
+#define IRQ_AMIGA_RBF       9
+#define IRQ_AMIGA_TBE       10
+
+/* software interrupts */
+#define IRQ_AMIGA_SOFT      11
+
+/* interrupts from external hardware */
+#define IRQ_AMIGA_PORTS     12
+#define IRQ_AMIGA_EXTER     13
+
+/* CIA interrupt sources */
+#define IRQ_AMIGA_CIAA      14
+#define IRQ_AMIGA_CIAA_TA   14
+#define IRQ_AMIGA_CIAA_TB   15
+#define IRQ_AMIGA_CIAA_ALRM 16
+#define IRQ_AMIGA_CIAA_SP   17
+#define IRQ_AMIGA_CIAA_FLG  18
+#define IRQ_AMIGA_CIAB      19
+#define IRQ_AMIGA_CIAB_TA   19
+#define IRQ_AMIGA_CIAB_TB   20
+#define IRQ_AMIGA_CIAB_ALRM 21
+#define IRQ_AMIGA_CIAB_SP   22
+#define IRQ_AMIGA_CIAB_FLG  23
+
+/* auto-vector interrupts */
+#define IRQ_AMIGA_AUTO      24
+#define IRQ_AMIGA_AUTO_0    24 /* This is just a dummy */
+#define IRQ_AMIGA_AUTO_1    25
+#define IRQ_AMIGA_AUTO_2    26
+#define IRQ_AMIGA_AUTO_3    27
+#define IRQ_AMIGA_AUTO_4    28
+#define IRQ_AMIGA_AUTO_5    29
+#define IRQ_AMIGA_AUTO_6    30
+#define IRQ_AMIGA_AUTO_7    31
+
+#define IRQ_FLOPPY          IRQ_AMIGA_DSKBLK
+
+/* INTREQR masks */
+#define IRQ1_MASK   0x0007      /* INTREQR mask for IRQ 1 */
+#define IRQ2_MASK   0x0008      /* INTREQR mask for IRQ 2 */
+#define IRQ3_MASK   0x0070      /* INTREQR mask for IRQ 3 */
+#define IRQ4_MASK   0x0780      /* INTREQR mask for IRQ 4 */
+#define IRQ5_MASK   0x1800      /* INTREQR mask for IRQ 5 */
+#define IRQ6_MASK   0x2000      /* INTREQR mask for IRQ 6 */
+#define IRQ7_MASK   0x4000      /* INTREQR mask for IRQ 7 */
+
+#define IF_SETCLR   0x8000      /* set/clr bit */
+#define IF_INTEN    0x4000      /* master interrupt bit in INT* registers */
+#define IF_EXTER    0x2000      /* external level 6 and CIA B interrupt */
+#define IF_DSKSYN   0x1000      /* disk sync interrupt */
+#define IF_RBF      0x0800      /* serial receive buffer full interrupt */
+#define IF_AUD3     0x0400      /* audio channel 3 done interrupt */
+#define IF_AUD2     0x0200      /* audio channel 2 done interrupt */
+#define IF_AUD1     0x0100      /* audio channel 1 done interrupt */
+#define IF_AUD0     0x0080      /* audio channel 0 done interrupt */
+#define IF_BLIT     0x0040      /* blitter done interrupt */
+#define IF_VERTB    0x0020      /* vertical blanking interrupt */
+#define IF_COPER    0x0010      /* copper interrupt */
+#define IF_PORTS    0x0008      /* external level 2 and CIA A interrupt */
+#define IF_SOFT     0x0004      /* software initiated interrupt */
+#define IF_DSKBLK   0x0002      /* diskblock DMA finished */
+#define IF_TBE      0x0001      /* serial transmit buffer empty interrupt */
+
+extern void amiga_do_irq(int irq, struct pt_regs *fp);
+extern void amiga_do_irq_list(int irq, struct pt_regs *fp);
+
+/* CIA interrupt control register bits */
+
+#define CIA_ICR_TA      0x01
+#define CIA_ICR_TB      0x02
+#define CIA_ICR_ALRM    0x04
+#define CIA_ICR_SP      0x08
+#define CIA_ICR_FLG     0x10
+#define CIA_ICR_ALL     0x1f
+#define CIA_ICR_SETCLR  0x80
+
+/* to access the interrupt control registers of CIA's use only
+** these functions, they behave exactly like the amiga os routines
+*/
+
+extern struct ciabase ciaa_base, ciab_base;
+
+extern unsigned char cia_set_irq(unsigned int irq, int set);
+extern unsigned char cia_able_irq(unsigned int irq, int enable);
+
+#endif /* asm-m68k/amigaints.h */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h
new file mode 100644
index 000000000000..35114ce5135f
--- /dev/null
+++ b/include/asm-ppc/amigappc.h
@@ -0,0 +1,85 @@
+/*
+** asm-ppc/amigappc.h -- This header defines some values and pointers for
+**                        the Phase 5 PowerUp card.
+**
+** Copyright 1997, 1998 by Phase5, Germany.
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License.  See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 7/22/97 by Jesper Skov
+*/
+
+#ifdef __KERNEL__
+#ifndef _M68K_AMIGAPPC_H
+#define _M68K_AMIGAPPC_H
+
+#ifndef __ASSEMBLY__
+
+/* #include <asm/system.h> */
+#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
+
+#define APUS_WRITE(_a_, _v_)                            \
+do {                                                    \
+        (*((volatile unsigned char *)(_a_)) = (_v_));   \
+        mb();                                           \
+} while (0)
+
+#define APUS_READ(_a_, _v_)                             \
+do {                                                    \
+        (_v_) = (*((volatile unsigned char *)(_a_)));   \
+        mb();                                           \
+} while (0)
+#endif /* ndef __ASSEMBLY__ */
+
+/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
+#define zTwoBase (0x80000000)
+
+#define APUS_IPL_BASE           (zTwoBase + 0x00f60000)
+#define APUS_REG_RESET          (APUS_IPL_BASE + 0x00)
+#define APUS_REG_WAITSTATE      (APUS_IPL_BASE + 0x10)
+#define APUS_REG_SHADOW         (APUS_IPL_BASE + 0x18)
+#define APUS_REG_LOCK           (APUS_IPL_BASE + 0x20)
+#define APUS_REG_INT            (APUS_IPL_BASE + 0x28)
+#define APUS_IPL_EMU            (APUS_IPL_BASE + 0x30)
+#define APUS_INT_LVL            (APUS_IPL_BASE + 0x38)
+
+#define REGSHADOW_SETRESET      (0x80)
+#define REGSHADOW_SELFRESET     (0x40)
+
+#define REGLOCK_SETRESET        (0x80)
+#define REGLOCK_BLACKMAGICK1    (0x40)
+#define REGLOCK_BLACKMAGICK2    (0x20)
+#define REGLOCK_BLACKMAGICK3    (0x10)
+
+#define REGWAITSTATE_SETRESET   (0x80)
+#define REGWAITSTATE_PPCW       (0x08)
+#define REGWAITSTATE_PPCR       (0x04)
+
+#define REGRESET_SETRESET       (0x80)
+#define REGRESET_PPCRESET       (0x10)
+#define REGRESET_M68KRESET      (0x08)
+#define REGRESET_AMIGARESET     (0x04)
+#define REGRESET_AUXRESET       (0x02)
+#define REGRESET_SCSIRESET      (0x01)
+
+#define REGINT_SETRESET         (0x80)
+#define REGINT_ENABLEIPL        (0x02)
+#define REGINT_INTMASTER        (0x01)
+
+#define IPLEMU_SETRESET         (0x80)
+#define IPLEMU_DISABLEINT       (0x40)
+#define IPLEMU_IPL2             (0x20)
+#define IPLEMU_IPL1             (0x10)
+#define IPLEMU_IPL0             (0x08)
+#define IPLEMU_PPCIPL2          (0x04)
+#define IPLEMU_PPCIPL1          (0x02)
+#define IPLEMU_PPCIPL0          (0x01)
+#define IPLEMU_IPLMASK          (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
+
+#define INTLVL_SETRESET         (0x80)
+#define INTLVL_MASK             (0x7f)
+
+#endif /* _M68k_AMIGAPPC_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h
new file mode 100644
index 000000000000..1fe0b87859b0
--- /dev/null
+++ b/include/asm-ppc/amigayle.h
@@ -0,0 +1 @@
+#include <asm-m68k/amigayle.h>
diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h
new file mode 100644
index 000000000000..3f65f63f508f
--- /dev/null
+++ b/include/asm-ppc/amipcmcia.h
@@ -0,0 +1 @@
+#include <asm-m68k/amipcmcia.h>
diff --git a/include/asm-ppc/ans-lcd.h b/include/asm-ppc/ans-lcd.h
new file mode 100644
index 000000000000..d795b9fd2db6
--- /dev/null
+++ b/include/asm-ppc/ans-lcd.h
@@ -0,0 +1,11 @@
+#ifndef _PPC_ANS_LCD_H
+#define _PPC_ANS_LCD_H
+
+#define ANSLCD_MINOR            156
+
+#define ANSLCD_CLEAR            0x01
+#define ANSLCD_SENDCTRL         0x02
+#define ANSLCD_SETSHORTDELAY    0x03
+#define ANSLCD_SETLONGDELAY     0x04
+
+#endif
diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h
new file mode 100644
index 000000000000..eeafd505836e
--- /dev/null
+++ b/include/asm-ppc/atomic.h
@@ -0,0 +1,214 @@
+/*
+ * PowerPC atomic operations
+ */
+
+#ifndef _ASM_PPC_ATOMIC_H_
+#define _ASM_PPC_ATOMIC_H_
+
+typedef struct { volatile int counter; } atomic_t;
+
+#ifdef __KERNEL__
+
+#define ATOMIC_INIT(i)  { (i) }
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic_set(v,i)         (((v)->counter) = (i))
+
+extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
+
+#ifdef CONFIG_SMP
+#define SMP_SYNC        "sync"
+#define SMP_ISYNC       "\n\tisync"
+#else
+#define SMP_SYNC        ""
+#define SMP_ISYNC
+#endif
+
+/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
+ * The old ATOMIC_SYNC_FIX covered some but not all of this.
+ */
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb)     "dcbt " #ra "," #rb ";"
+#else
+#define PPC405_ERR77(ra,rb)
+#endif
+
+static __inline__ void atomic_add(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%3         # atomic_add\n\
+        add     %0,%2,%0\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "=m" (v->counter)
+        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_add_return\n\
+        add     %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        SMP_ISYNC
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+
+static __inline__ void atomic_sub(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%3         # atomic_sub\n\
+        subf    %0,%2,%0\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (t), "=m" (v->counter)
+        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_sub_return\n\
+        subf    %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        SMP_ISYNC
+        : "=&r" (t)
+        : "r" (a), "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+static __inline__ void atomic_inc(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_inc\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t), "=m" (v->counter)
+        : "r" (&v->counter), "m" (v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%1         # atomic_inc_return\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1 \n\
+        bne-    1b"
+        SMP_ISYNC
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+static __inline__ void atomic_dec(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2         # atomic_dec\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%2)\
+"       stwcx.  %0,0,%2\n\
+        bne-    1b"
+        : "=&r" (t), "=m" (v->counter)
+        : "r" (&v->counter), "m" (v->counter)
+        : "cc");
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%1         # atomic_dec_return\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    1b"
+        SMP_ISYNC
+        : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define atomic_sub_and_test(a, v)       (atomic_sub_return((a), (v)) == 0)
+#define atomic_dec_and_test(v)          (atomic_dec_return((v)) == 0)
+
+/*
+ * Atomically test *v and decrement if it is greater than 0.
+ * The function returns the old value of *v minus 1.
+ */
+static __inline__ int atomic_dec_if_positive(atomic_t *v)
+{
+        int t;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
+        addic.  %0,%0,-1\n\
+        blt-    2f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    1b"
+        SMP_ISYNC
+        "\n\
+2:"     : "=&r" (t)
+        : "r" (&v->counter)
+        : "cc", "memory");
+
+        return t;
+}
+
+#define __MB    __asm__ __volatile__ (SMP_SYNC : : : "memory")
+#define smp_mb__before_atomic_dec()     __MB
+#define smp_mb__after_atomic_dec()      __MB
+#define smp_mb__before_atomic_inc()     __MB
+#define smp_mb__after_atomic_inc()      __MB
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_PPC_ATOMIC_H_ */
diff --git a/include/asm-ppc/backlight.h b/include/asm-ppc/backlight.h
new file mode 100644
index 000000000000..3a1c3dede2a0
--- /dev/null
+++ b/include/asm-ppc/backlight.h
@@ -0,0 +1,30 @@
+/*
+ * Routines for handling backlight control on PowerBooks
+ *
+ * For now, implementation resides in arch/ppc/kernel/pmac_support.c
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_BACKLIGHT_H
+#define __ASM_PPC_BACKLIGHT_H
+
+/* Abstract values */
+#define BACKLIGHT_OFF   0
+#define BACKLIGHT_MIN   1
+#define BACKLIGHT_MAX   0xf
+
+struct backlight_controller {
+        int (*set_enable)(int enable, int level, void *data);
+        int (*set_level)(int level, void *data);
+};
+
+extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type);
+extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data);
+
+extern int set_backlight_enable(int enable);
+extern int get_backlight_enable(void);
+extern int set_backlight_level(int level);
+extern int get_backlight_level(void);
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h
new file mode 100644
index 000000000000..e30f536fd830
--- /dev/null
+++ b/include/asm-ppc/bitops.h
@@ -0,0 +1,460 @@
+/*
+ * bitops.h: Bit string operations on the ppc
+ */
+
+#ifdef __KERNEL__
+#ifndef _PPC_BITOPS_H
+#define _PPC_BITOPS_H
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+#include <asm/atomic.h>
+
+/*
+ * The test_and_*_bit operations are taken to imply a memory barrier
+ * on SMP systems.
+ */
+#ifdef CONFIG_SMP
+#define SMP_WMB         "eieio\n"
+#define SMP_MB          "\nsync"
+#else
+#define SMP_WMB
+#define SMP_MB
+#endif /* CONFIG_SMP */
+
+static __inline__ void set_bit(int nr, volatile unsigned long * addr)
+{
+        unsigned long old;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+        
+        __asm__ __volatile__("\n\
+1:      lwarx   %0,0,%3 \n\
+        or      %0,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (old), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc" );
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+        *p |= mask;
+}
+
+/*
+ * clear_bit doesn't imply a memory barrier
+ */
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+
+static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+        __asm__ __volatile__("\n\
+1:      lwarx   %0,0,%3 \n\
+        andc    %0,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (old), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc");
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+        *p &= ~mask;
+}
+
+static __inline__ void change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long old;
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+        __asm__ __volatile__("\n\
+1:      lwarx   %0,0,%3 \n\
+        xor     %0,%0,%2 \n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %0,0,%3 \n\
+        bne-    1b"
+        : "=&r" (old), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc");
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+        *p ^= mask;
+}
+
+/*
+ * test_and_*_bit do imply a memory barrier (?)
+ */
+static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned int old, t;
+        unsigned int mask = 1 << (nr & 0x1f);
+        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+        __asm__ __volatile__(SMP_WMB "\n\
+1:      lwarx   %0,0,%4 \n\
+        or      %1,%0,%3 \n"
+        PPC405_ERR77(0,%4)
+"       stwcx.  %1,0,%4 \n\
+        bne     1b"
+        SMP_MB
+        : "=&r" (old), "=&r" (t), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long old = *p;
+
+        *p = old | mask;
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned int old, t;
+        unsigned int mask = 1 << (nr & 0x1f);
+        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+        __asm__ __volatile__(SMP_WMB "\n\
+1:      lwarx   %0,0,%4 \n\
+        andc    %1,%0,%3 \n"
+        PPC405_ERR77(0,%4)
+"       stwcx.  %1,0,%4 \n\
+        bne     1b"
+        SMP_MB
+        : "=&r" (old), "=&r" (t), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long old = *p;
+
+        *p = old & ~mask;
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned int old, t;
+        unsigned int mask = 1 << (nr & 0x1f);
+        volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+        __asm__ __volatile__(SMP_WMB "\n\
+1:      lwarx   %0,0,%4 \n\
+        xor     %1,%0,%3 \n"
+        PPC405_ERR77(0,%4)
+"       stwcx.  %1,0,%4 \n\
+        bne     1b"
+        SMP_MB
+        : "=&r" (old), "=&r" (t), "=m" (*p)
+        : "r" (mask), "r" (p), "m" (*p)
+        : "cc", "memory");
+
+        return (old & mask) != 0;
+}
+
+/*
+ * non-atomic version
+ */
+static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = 1 << (nr & 0x1f);
+        unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+        unsigned long old = *p;
+
+        *p = old ^ mask;
+        return (old & mask) != 0;
+}
+
+static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr)
+{
+        return ((addr[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
+}
+
+/* Return the bit position of the most significant 1 bit in a word */
+static __inline__ int __ilog2(unsigned long x)
+{
+        int lz;
+
+        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+        return 31 - lz;
+}
+
+static __inline__ int ffz(unsigned long x)
+{
+        if ((x = ~x) == 0)
+                return 32;
+        return __ilog2(x & -x);
+}
+
+static inline int __ffs(unsigned long x)
+{
+        return __ilog2(x & -x);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+        return __ilog2(x & -x) + 1;
+}
+
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __inline__ int fls(unsigned int x)
+{
+        int lz;
+
+        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+        return 32 - lz;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+/*
+ * Find the first bit set in a 140-bit bitmap.
+ * The first 100 bits are unlikely to be set.
+ */
+static inline int sched_find_first_bit(const unsigned long *b)
+{
+        if (unlikely(b[0]))
+                return __ffs(b[0]);
+        if (unlikely(b[1]))
+                return __ffs(b[1]) + 32;
+        if (unlikely(b[2]))
+                return __ffs(b[2]) + 64;
+        if (b[3])
+                return __ffs(b[3]) + 96;
+        return __ffs(b[4]) + 128;
+}
+
+/**
+ * find_next_bit - find the next set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static __inline__ unsigned long find_next_bit(const unsigned long *addr,
+        unsigned long size, unsigned long offset)
+{
+        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+        unsigned int result = offset & ~31UL;
+        unsigned int tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if (offset) {
+                tmp = *p++;
+                tmp &= ~0UL << offset;
+                if (size < 32)
+                        goto found_first;
+                if (tmp)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while (size >= 32) {
+                if ((tmp = *p++) != 0)
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+
+found_first:
+        tmp &= ~0UL >> (32 - size);
+        if (tmp == 0UL)        /* Are any bits set? */
+                return result + size; /* Nope. */
+found_middle:
+        return result + __ffs(tmp);
+}
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first set bit, not the number of the byte
+ * containing a bit.
+ */
+#define find_first_bit(addr, size) \
+        find_next_bit((addr), (size), 0)
+
+/*
+ * This implementation of find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h.
+ */
+#define find_first_zero_bit(addr, size) \
+        find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long find_next_zero_bit(const unsigned long *addr,
+        unsigned long size, unsigned long offset)
+{
+        unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
+        unsigned int result = offset & ~31UL;
+        unsigned int tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if (offset) {
+                tmp = *p++;
+                tmp |= ~0UL >> (32-offset);
+                if (size < 32)
+                        goto found_first;
+                if (tmp != ~0U)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while (size >= 32) {
+                if ((tmp = *p++) != ~0U)
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if (!size)
+                return result;
+        tmp = *p;
+found_first:
+        tmp |= ~0UL << size;
+        if (tmp == ~0UL)        /* Are any bits zero? */
+                return result + size; /* Nope. */
+found_middle:
+        return result + ffz(tmp);
+}
+
+
+#define ext2_set_bit(nr, addr)  __test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
+#define ext2_set_bit_atomic(lock, nr, addr)  test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
+#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
+
+static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
+{
+        __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
+
+        return (ADDR[nr >> 3] >> (nr & 7)) & 1;
+}
+
+/*
+ * This implementation of ext2_find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
+ */
+
+#define ext2_find_first_zero_bit(addr, size) \
+        ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(const void *addr,
+        unsigned long size, unsigned long offset)
+{
+        unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+        unsigned int result = offset & ~31UL;
+        unsigned int tmp;
+
+        if (offset >= size)
+                return size;
+        size -= result;
+        offset &= 31UL;
+        if (offset) {
+                tmp = cpu_to_le32p(p++);
+                tmp |= ~0UL >> (32-offset);
+                if (size < 32)
+                        goto found_first;
+                if (tmp != ~0U)
+                        goto found_middle;
+                size -= 32;
+                result += 32;
+        }
+        while (size >= 32) {
+                if ((tmp = cpu_to_le32p(p++)) != ~0U)
+                        goto found_middle;
+                result += 32;
+                size -= 32;
+        }
+        if (!size)
+                return result;
+        tmp = cpu_to_le32p(p);
+found_first:
+        tmp |= ~0U << size;
+        if (tmp == ~0UL)        /* Are any bits zero? */
+                return result + size; /* Nope. */
+found_middle:
+        return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
+#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
+
+#endif /* _PPC_BITOPS_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h
new file mode 100644
index 000000000000..93d955c70d65
--- /dev/null
+++ b/include/asm-ppc/bootinfo.h
@@ -0,0 +1,52 @@
+/*
+ * Non-machine dependent bootinfo structure.  Basic idea
+ * borrowed from the m68k.
+ *
+ * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
+ */
+
+#ifdef __KERNEL__
+#ifndef _PPC_BOOTINFO_H
+#define _PPC_BOOTINFO_H
+
+#include <linux/config.h>
+#include <asm/page.h>
+
+#if defined(CONFIG_APUS) && !defined(__BOOTER__)
+#include <asm-m68k/bootinfo.h>
+#else
+
+struct bi_record {
+        unsigned long tag;              /* tag ID */
+        unsigned long size;             /* size of record (in bytes) */
+        unsigned long data[0];          /* data */
+};
+
+#define BI_FIRST                0x1010  /* first record - marker */
+#define BI_LAST                 0x1011  /* last record - marker */
+#define BI_CMD_LINE             0x1012
+#define BI_BOOTLOADER_ID        0x1013
+#define BI_INITRD               0x1014
+#define BI_SYSMAP               0x1015
+#define BI_MACHTYPE             0x1016
+#define BI_MEMSIZE              0x1017
+#define BI_BOARD_INFO           0x1018
+
+extern struct bi_record *find_bootinfo(void);
+extern void bootinfo_init(struct bi_record *rec);
+extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
+extern void parse_bootinfo(struct bi_record *rec);
+extern unsigned long boot_mem_size;
+
+static inline struct bi_record *
+bootinfo_addr(unsigned long offset)
+{
+
+        return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
+                                          (1 << 20));
+}
+#endif /* CONFIG_APUS */
+
+
+#endif /* _PPC_BOOTINFO_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h
new file mode 100644
index 000000000000..b0c51b45d7a2
--- /dev/null
+++ b/include/asm-ppc/bootx.h
@@ -0,0 +1,135 @@
+/*
+ * This file describes the structure passed from the BootX application
+ * (for MacOS) when it is used to boot Linux.
+ *
+ * Written by Benjamin Herrenschmidt.
+ */
+
+
+#ifndef __ASM_BOOTX_H__
+#define __ASM_BOOTX_H__
+
+#ifdef macintosh
+#include <Types.h>
+#include "linux_type_defs.h"
+#endif
+
+#ifdef macintosh
+/* All this requires PowerPC alignment */
+#pragma options align=power
+#endif
+
+/* On kernel entry:
+ *
+ * r3 = 0x426f6f58    ('BooX')
+ * r4 = pointer to boot_infos
+ * r5 = NULL
+ *
+ * Data and instruction translation disabled, interrupts
+ * disabled, kernel loaded at physical 0x00000000 on PCI
+ * machines (will be different on NuBus).
+ */
+
+#define BOOT_INFO_VERSION               5
+#define BOOT_INFO_COMPATIBLE_VERSION    1
+
+/* Bit in the architecture flag mask. More to be defined in
+   future versions. Note that either BOOT_ARCH_PCI or
+   BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
+   set additionally when BOOT_ARCH_NUBUS is set.
+ */
+#define BOOT_ARCH_PCI                   0x00000001UL
+#define BOOT_ARCH_NUBUS                 0x00000002UL
+#define BOOT_ARCH_NUBUS_PDM             0x00000010UL
+#define BOOT_ARCH_NUBUS_PERFORMA        0x00000020UL
+#define BOOT_ARCH_NUBUS_POWERBOOK       0x00000040UL
+
+/*  Maximum number of ranges in phys memory map */
+#define MAX_MEM_MAP_SIZE                                26
+
+/* This is the format of an element in the physical memory map. Note that
+   the map is optional and current BootX will only build it for pre-PCI
+   machines */
+typedef struct boot_info_map_entry
+{
+    __u32       physAddr;                /* Physical starting address */
+    __u32       size;                    /* Size in bytes */
+} boot_info_map_entry_t;
+
+
+/* Here are the boot informations that are passed to the bootstrap
+ * Note that the kernel arguments and the device tree are appended
+ * at the end of this structure. */
+typedef struct boot_infos
+{
+    /* Version of this structure */
+    __u32       version;
+    /* backward compatible down to version: */
+    __u32       compatible_version;
+
+    /* NEW (vers. 2) this holds the current _logical_ base addr of
+       the frame buffer (for use by early boot message) */
+    __u8*       logicalDisplayBase;
+
+    /* NEW (vers. 4) Apple's machine identification */
+    __u32       machineID;
+
+    /* NEW (vers. 4) Detected hw architecture */
+    __u32       architecture;
+
+    /* The device tree (internal addresses relative to the beginning of the tree,
+     * device tree offset relative to the beginning of this structure).
+     * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
+     * field is 0.
+     */
+    __u32       deviceTreeOffset;        /* Device tree offset */
+    __u32       deviceTreeSize;          /* Size of the device tree */
+
+    /* Some infos about the current MacOS display */
+    __u32       dispDeviceRect[4];       /* left,top,right,bottom */
+    __u32       dispDeviceDepth;         /* (8, 16 or 32) */
+    __u8*       dispDeviceBase;          /* base address (physical) */
+    __u32       dispDeviceRowBytes;      /* rowbytes (in bytes) */
+    __u32       dispDeviceColorsOffset;  /* Colormap (8 bits only) or 0 (*) */
+    /* Optional offset in the registry to the current
+     * MacOS display. (Can be 0 when not detected) */
+     __u32      dispDeviceRegEntryOffset;
+
+    /* Optional pointer to boot ramdisk (offset from this structure) */
+    __u32       ramDisk;
+    __u32       ramDiskSize;             /* size of ramdisk image */
+
+    /* Kernel command line arguments (offset from this structure) */
+    __u32       kernelParamsOffset;
+
+    /* ALL BELOW NEW (vers. 4) */
+
+    /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
+       (non-PCI) only. On PCI, memory is contiguous and it's size is in the
+       device-tree. */
+    boot_info_map_entry_t
+                physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
+    __u32       physMemoryMapSize;               /* How many entries in map */
+
+
+    /* The framebuffer size (optional, currently 0) */
+    __u32       frameBufferSize;         /* Represents a max size, can be 0. */
+
+    /* NEW (vers. 5) */
+
+    /* Total params size (args + colormap + device tree + ramdisk) */
+    __u32       totalParamsSize;
+
+} boot_infos_t;
+
+/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented
+ * by 3 short words containing a 16 bits (unsigned) color component.
+ * Later versions may contain the gamma table for direct-color devices here.
+ */
+#define BOOTX_COLORTABLE_SIZE    (256UL*3UL*2UL)
+
+#ifdef macintosh
+#pragma options align=reset
+#endif
+
+#endif
diff --git a/include/asm-ppc/bseip.h b/include/asm-ppc/bseip.h
new file mode 100644
index 000000000000..691f4a52b0a5
--- /dev/null
+++ b/include/asm-ppc/bseip.h
@@ -0,0 +1,38 @@
+/*
+ * A collection of structures, addresses, and values associated with
+ * the Bright Star Engineering ip-Engine board.  Copied from the MBX stuff.
+ *
+ * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+ */
+#ifndef __MACH_BSEIP_DEFS
+#define __MACH_BSEIP_DEFS
+
+#ifndef __ASSEMBLY__
+/* A Board Information structure that is given to a program when
+ * prom starts it up.
+ */
+typedef struct bd_info {
+        unsigned int    bi_memstart;    /* Memory start address */
+        unsigned int    bi_memsize;     /* Memory (end) size in bytes */
+        unsigned int    bi_intfreq;     /* Internal Freq, in Hz */
+        unsigned int    bi_busfreq;     /* Bus Freq, in Hz */
+        unsigned char   bi_enetaddr[6];
+        unsigned int    bi_baudrate;
+} bd_t;
+
+extern bd_t m8xx_board_info;
+
+/* Memory map is configured by the PROM startup.
+ * All we need to get started is the IMMR.
+ */
+#define IMAP_ADDR               ((uint)0xff000000)
+#define IMAP_SIZE               ((uint)(64 * 1024))
+#define PCMCIA_MEM_ADDR         ((uint)0x04000000)
+#define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
+#endif  /* !__ASSEMBLY__ */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS    0
+
+#endif
diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h
new file mode 100644
index 000000000000..36c7640d00f2
--- /dev/null
+++ b/include/asm-ppc/btext.h
@@ -0,0 +1,34 @@
+/*
+ * Definitions for using the procedures in btext.c.
+ *
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ */
+#ifndef __PPC_BTEXT_H
+#define __PPC_BTEXT_H
+#ifdef __KERNEL__
+
+#include <asm/bootx.h>
+
+extern void btext_clearscreen(void);
+extern void btext_flushscreen(void);
+
+extern unsigned long disp_BAT[2];
+
+extern boot_infos_t disp_bi;
+extern int boot_text_mapped;
+
+void btext_init(boot_infos_t *bi);
+void btext_welcome(void);
+void btext_prepare_BAT(void);
+void btext_setup_display(int width, int height, int depth, int pitch,
+                         unsigned long address);
+void map_boot_text(void);
+void btext_update_display(unsigned long phys, int width, int height,
+                          int depth, int pitch);
+
+void btext_drawchar(char c);
+void btext_drawstring(const char *str);
+void btext_drawhex(unsigned long v);
+
+#endif /* __KERNEL__ */
+#endif /* __PPC_BTEXT_H */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
new file mode 100644
index 000000000000..e99c6cb9d618
--- /dev/null
+++ b/include/asm-ppc/bug.h
@@ -0,0 +1,55 @@
+#ifndef _PPC_BUG_H
+#define _PPC_BUG_H
+
+struct bug_entry {
+        unsigned long   bug_addr;
+        int             line;
+        const char      *file;
+        const char      *function;
+};
+
+/*
+ * If this bit is set in the line number it means that the trap
+ * is for WARN_ON rather than BUG or BUG_ON.
+ */
+#define BUG_WARNING_TRAP        0x1000000
+
+#define BUG() do {                                                       \
+        __asm__ __volatile__(                                            \
+                "1:     twi 31,0,0\n"                                    \
+                ".section __bug_table,\"a\"\n\t"                         \
+                "       .long 1b,%0,%1,%2\n"                             \
+                ".previous"                                              \
+                : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
+} while (0)
+
+#define BUG_ON(x) do {                                                  \
+        if (!__builtin_constant_p(x) || (x)) {                          \
+                __asm__ __volatile__(                                   \
+                        "1:     twnei %0,0\n"                           \
+                        ".section __bug_table,\"a\"\n\t"                \
+                        "       .long 1b,%1,%2,%3\n"                    \
+                        ".previous"                                     \
+                        : : "r" (x), "i" (__LINE__), "i" (__FILE__),    \
+                            "i" (__FUNCTION__));                        \
+        }                                                               \
+} while (0)
+
+#define WARN_ON(x) do {                                                 \
+        if (!__builtin_constant_p(x) || (x)) {                          \
+                __asm__ __volatile__(                                   \
+                        "1:     twnei %0,0\n"                           \
+                        ".section __bug_table,\"a\"\n\t"                \
+                        "       .long 1b,%1,%2,%3\n"                    \
+                        ".previous"                                     \
+                        : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
+                            "i" (__FILE__), "i" (__FUNCTION__));        \
+        }                                                               \
+} while (0)
+
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_BUG_ON
+#define HAVE_ARCH_WARN_ON
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/include/asm-ppc/bugs.h b/include/asm-ppc/bugs.h
new file mode 100644
index 000000000000..8dce1e290fd0
--- /dev/null
+++ b/include/asm-ppc/bugs.h
@@ -0,0 +1,6 @@
+/*
+ * This file is included by 'init/main.c'
+ */
+
+extern void
+check_bugs(void);
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h
new file mode 100644
index 000000000000..c63c81ec7968
--- /dev/null
+++ b/include/asm-ppc/byteorder.h
@@ -0,0 +1,76 @@
+#ifndef _PPC_BYTEORDER_H
+#define _PPC_BYTEORDER_H
+
+#include <asm/types.h>
+#include <linux/compiler.h>
+
+#ifdef __GNUC__
+#ifdef __KERNEL__
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+        unsigned val;
+
+        __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+        return val;
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
+{
+        __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+        unsigned val;
+
+        __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+        return val;
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+        __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
+{
+        __u16 result;
+
+        __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value));
+        return result;
+}
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
+{
+        __u32 result;
+
+        __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value));
+        __asm__("rlwimi %0,%2,8,8,15"   : "=&r" (result) : "0" (result),    "r" (value));
+        __asm__("rlwimi %0,%2,24,0,7"   : "=&r" (result) : "0" (result),    "r" (value));
+
+        return result;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+
+#endif /* __KERNEL__ */
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _PPC_BYTEORDER_H */
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
new file mode 100644
index 000000000000..38f2f1be4a87
--- /dev/null
+++ b/include/asm-ppc/cache.h
@@ -0,0 +1,87 @@
+/*
+ * include/asm-ppc/cache.h
+ */
+#ifdef __KERNEL__
+#ifndef __ARCH_PPC_CACHE_H
+#define __ARCH_PPC_CACHE_H
+
+#include <linux/config.h>
+
+/* bytes per L1 cache line */
+#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
+#define L1_CACHE_LINE_SIZE      16
+#define LG_L1_CACHE_LINE_SIZE   4
+#define MAX_COPY_PREFETCH       1
+#elif defined(CONFIG_PPC64BRIDGE)
+#define L1_CACHE_LINE_SIZE      128
+#define LG_L1_CACHE_LINE_SIZE   7
+#define MAX_COPY_PREFETCH       1
+#else
+#define L1_CACHE_LINE_SIZE      32
+#define LG_L1_CACHE_LINE_SIZE   5
+#define MAX_COPY_PREFETCH       4
+#endif
+
+#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE
+#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
+
+#define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define L1_CACHE_PAGES          8
+
+#ifndef __ASSEMBLY__
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache_all(void);
+#endif /* __ASSEMBLY__ */
+
+/* prep registers for L2 */
+#define CACHECRBA       0x80000823      /* Cache configuration register address */
+#define L2CACHE_MASK    0x03    /* Mask for 2 L2 Cache bits */
+#define L2CACHE_512KB   0x00    /* 512KB */
+#define L2CACHE_256KB   0x01    /* 256KB */
+#define L2CACHE_1MB     0x02    /* 1MB */
+#define L2CACHE_NONE    0x03    /* NONE */
+#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
+
+#ifdef CONFIG_8xx
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define SPRN_IC_CST     560     /* Instruction cache control/status */
+#define SPRN_IC_ADR     561     /* Address needed for some commands */
+#define SPRN_IC_DAT     562     /* Read-only data register */
+#define SPRN_DC_CST     568     /* Data cache control/status */
+#define SPRN_DC_ADR     569     /* Address needed for some commands */
+#define SPRN_DC_DAT     570     /* Read-only data register */
+
+/* Commands.  Only the first few are available to the instruction cache.
+*/
+#define IDC_ENABLE      0x02000000      /* Cache enable */
+#define IDC_DISABLE     0x04000000      /* Cache disable */
+#define IDC_LDLCK       0x06000000      /* Load and lock */
+#define IDC_UNLINE      0x08000000      /* Unlock line */
+#define IDC_UNALL       0x0a000000      /* Unlock all */
+#define IDC_INVALL      0x0c000000      /* Invalidate all */
+
+#define DC_FLINE        0x0e000000      /* Flush data cache line */
+#define DC_SFWT         0x01000000      /* Set forced writethrough mode */
+#define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
+#define DC_SLES         0x05000000      /* Set little endian swap mode */
+#define DC_CLES         0x07000000      /* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED     0x80000000      /* Cache is enabled */
+#define IDC_CERR1       0x00200000      /* Cache error 1 */
+#define IDC_CERR2       0x00100000      /* Cache error 2 */
+#define IDC_CERR3       0x00080000      /* Cache error 3 */
+
+#define DC_DFWT         0x40000000      /* Data cache is forced write through */
+#define DC_LES          0x20000000      /* Caches are little endian mode */
+#endif /* CONFIG_8xx */
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cacheflush.h b/include/asm-ppc/cacheflush.h
new file mode 100644
index 000000000000..6a243efb3317
--- /dev/null
+++ b/include/asm-ppc/cacheflush.h
@@ -0,0 +1,49 @@
+/*
+ * include/asm-ppc/cacheflush.h
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_CACHEFLUSH_H
+#define _PPC_CACHEFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * No cache flushing is required when address mappings are
+ * changed, because the caches on PowerPCs are physically
+ * addressed.  -- paulus
+ * Also, when SMP we use the coherency (M) bit of the
+ * BATs and PTEs.  -- Cort
+ */
+#define flush_cache_all()               do { } while (0)
+#define flush_cache_mm(mm)              do { } while (0)
+#define flush_cache_range(vma, a, b)    do { } while (0)
+#define flush_cache_page(vma, p, pfn)   do { } while (0)
+#define flush_icache_page(vma, page)    do { } while (0)
+#define flush_cache_vmap(start, end)    do { } while (0)
+#define flush_cache_vunmap(start, end)  do { } while (0)
+
+extern void flush_dcache_page(struct page *page);
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+extern void flush_icache_range(unsigned long, unsigned long);
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+                struct page *page, unsigned long addr, int len);
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do { memcpy(dst, src, len); \
+     flush_icache_user_range(vma, page, vaddr, len); \
+} while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        memcpy(dst, src, len)
+
+extern void __flush_dcache_icache(void *page_va);
+extern void __flush_dcache_icache_phys(unsigned long physaddr);
+extern void flush_dcache_icache_page(struct page *page);
+#endif /* _PPC_CACHEFLUSH_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/checksum.h b/include/asm-ppc/checksum.h
new file mode 100644
index 000000000000..cf953a92c7ab
--- /dev/null
+++ b/include/asm-ppc/checksum.h
@@ -0,0 +1,107 @@
+#ifdef __KERNEL__
+#ifndef _PPC_CHECKSUM_H
+#define _PPC_CHECKSUM_H
+
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+extern unsigned int csum_partial(const unsigned char * buff, int len,
+                                 unsigned int sum);
+
+/*
+ * Computes the checksum of a memory block at src, length len,
+ * and adds in "sum" (32-bit), while copying the block to dst.
+ * If an access exception occurs on src or dst, it stores -EFAULT
+ * to *src_err or *dst_err respectively (if that pointer is not
+ * NULL), and, for an error on src, zeroes the rest of dst.
+ *
+ * Like csum_partial, this must be called with even lengths,
+ * except for the last fragment.
+ */
+extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
+                                              int len, unsigned int sum,
+                                              int *src_err, int *dst_err);
+
+#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
+        csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL)
+
+/* FIXME: this needs to be written to really do no check -- Cort */
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
+
+/*
+ * turns a 32-bit partial checksum (e.g. from csum_partial) into a
+ * 1's complement 16-bit checksum.
+ */
+static inline unsigned int csum_fold(unsigned int sum)
+{
+        unsigned int tmp;
+
+        /* swap the two 16-bit halves of sum */
+        __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
+        /* if there is a carry from adding the two 16-bit halves,
+           it will carry from the lower half into the upper half,
+           giving us the correct sum in the upper half. */
+        sum = ~(sum + tmp) >> 16;
+        return sum;
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+/*
+ * FIXME: I swiped this one from the sparc and made minor modifications.
+ * It may not be correct.  -- Cort
+ */
+static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
+                                                   unsigned long daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   unsigned int sum)
+{
+    __asm__("\n\
+        addc %0,%0,%1 \n\
+        adde %0,%0,%2 \n\
+        adde %0,%0,%3 \n\
+        addze %0,%0 \n\
+        "
+        : "=r" (sum)
+        : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
+    return sum;
+}
+
+/*
+ * This is a version of ip_compute_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.  ihl is the number
+ * of 32-bit words and is always >= 5.
+ */
+extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl);
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+extern unsigned short csum_tcpudp_magic(unsigned long saddr,
+                                        unsigned long daddr,
+                                        unsigned short len,
+                                        unsigned short proto,
+                                        unsigned int sum);
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h
new file mode 100644
index 000000000000..5bbb8e2c1c6d
--- /dev/null
+++ b/include/asm-ppc/commproc.h
@@ -0,0 +1,695 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
+ * bytes of the DP RAM and relocates the I2C parameter area to the
+ * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
+ * or other use.
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <linux/config.h>
+#include <asm/8xx_immap.h>
+#include <asm/ptrace.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST      ((ushort)0x8000)
+#define CPM_CR_OPCODE   ((ushort)0x0f00)
+#define CPM_CR_CHAN     ((ushort)0x00f0)
+#define CPM_CR_FLG      ((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX         ((ushort)0x0000)
+#define CPM_CR_INIT_RX          ((ushort)0x0001)
+#define CPM_CR_INIT_TX          ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
+#define CPM_CR_STOP_TX          ((ushort)0x0004)
+#define CPM_CR_RESTART_TX       ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
+#define CPM_CR_SET_GADDR        ((ushort)0x0008)
+#define CPM_CR_SET_TIMER        CPM_CR_SET_GADDR
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1          ((ushort)0x0000)
+#define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2          ((ushort)0x0004)
+#define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
+#define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
+#define CPM_CR_CH_SCC3          ((ushort)0x0008)
+#define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4          ((ushort)0x000c)
+#define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
+
+/* The dual ported RAM is multi-functional.  Some areas can be (and are
+ * being) used for microcode.  There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+#define CPM_DATAONLY_BASE       ((uint)0x0800)
+#define CPM_DATAONLY_SIZE       ((uint)0x0700)
+#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
+
+static inline long IS_DPERR(const uint offset)
+{
+        return (uint)offset > (uint)-1000L;
+}
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
+extern uint cpm_dpalloc(uint size, uint align);
+extern int cpm_dpfree(uint offset);
+extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
+extern void cpm_dpdump(void);
+extern void *cpm_dpram_addr(uint offset);
+extern void cpm_setbrg(uint brg, uint rate);
+
+extern uint m8xx_cpm_hostalloc(uint size);
+extern int  m8xx_cpm_hostfree(uint start);
+extern void m8xx_cpm_hostdump(void);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+        ushort  cbd_sc;         /* Status and Control */
+        ushort  cbd_datlen;     /* Data length in buffer */
+        uint    cbd_bufaddr;    /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
+#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
+#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
+#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
+#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
+#define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
+#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
+#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
+#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
+#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
+#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
+#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
+#define BD_SC_NAK       ((ushort)0x0004)        /* NAK - did not respond */
+#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
+#define BD_SC_UN        ((ushort)0x0002)        /* Underrun */
+#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
+#define BD_SC_CL        ((ushort)0x0001)        /* Collision */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1      ((uint)0x0000)
+#define PROFF_IIC       ((uint)0x0080)
+#define PROFF_SCC2      ((uint)0x0100)
+#define PROFF_SPI       ((uint)0x0180)
+#define PROFF_SCC3      ((uint)0x0200)
+#define PROFF_SMC1      ((uint)0x0280)
+#define PROFF_SCC4      ((uint)0x0300)
+#define PROFF_SMC2      ((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ * The MBX uses SMC1 as the host serial port.
+ */
+typedef struct smc_uart {
+        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  smc_rfcr;       /* Rx function code */
+        u_char  smc_tfcr;       /* Tx function code */
+        ushort  smc_mrblr;      /* Max receive buffer length */
+        uint    smc_rstate;     /* Internal */
+        uint    smc_idp;        /* Internal */
+        ushort  smc_rbptr;      /* Internal */
+        ushort  smc_ibc;        /* Internal */
+        uint    smc_rxtmp;      /* Internal */
+        uint    smc_tstate;     /* Internal */
+        uint    smc_tdp;        /* Internal */
+        ushort  smc_tbptr;      /* Internal */
+        ushort  smc_tbc;        /* Internal */
+        uint    smc_txtmp;      /* Internal */
+        ushort  smc_maxidl;     /* Maximum idle characters */
+        ushort  smc_tmpidl;     /* Temporary idle counter */
+        ushort  smc_brklen;     /* Last received break length */
+        ushort  smc_brkec;      /* rcv'd break condition counter */
+        ushort  smc_brkcr;      /* xmt break count register */
+        ushort  smc_rmask;      /* Temporary bit mask */
+        char    res1[8];        /* Reserved */
+        ushort  smc_rpbase;     /* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define SMCMR_REN       ((ushort)0x0001)
+#define SMCMR_TEN       ((ushort)0x0002)
+#define SMCMR_DM        ((ushort)0x000c)
+#define SMCMR_SM_GCI    ((ushort)0x0000)
+#define SMCMR_SM_UART   ((ushort)0x0020)
+#define SMCMR_SM_TRANS  ((ushort)0x0030)
+#define SMCMR_SM_MASK   ((ushort)0x0030)
+#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
+#define SMCMR_REVD      SMCMR_PM_EVEN
+#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
+#define SMCMR_BS        SMCMR_PEN
+#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
+#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+        ushort  scent_rbase;
+        ushort  scent_tbase;
+        u_char  scent_cfcr;
+        u_char  scent_smask;
+        ushort  scent_mrblr;
+        uint    scent_rstate;
+        uint    scent_r_ptr;
+        ushort  scent_rbptr;
+        ushort  scent_r_cnt;
+        uint    scent_rtemp;
+        uint    scent_tstate;
+        uint    scent_t_ptr;
+        ushort  scent_tbptr;
+        ushort  scent_t_cnt;
+        uint    scent_ttemp;
+        ushort  scent_max_sl;
+        ushort  scent_sl_cnt;
+        ushort  scent_character1;
+        ushort  scent_character2;
+        ushort  scent_character3;
+        ushort  scent_character4;
+        ushort  scent_character5;
+        ushort  scent_character6;
+        ushort  scent_character7;
+        ushort  scent_character8;
+        ushort  scent_rccm;
+        ushort  scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F      ((u_char)0x08)
+#define SMC_CENT_PE     ((u_char)0x04)
+#define SMC_CENT_S      ((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
+#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
+#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
+#define SMCM_BSY        ((unsigned char)0x04)
+#define SMCM_TX         ((unsigned char)0x02)
+#define SMCM_RX         ((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST             ((uint)0x00020000)
+#define CPM_BRG_EN              ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
+#define CPM_BRG_ATB             ((uint)0x00002000)
+#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
+#define CPM_BRG_DIV16           ((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP           ((uint)0x00040000)
+#define SCC_GSMRH_GDE           ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
+#define SCC_GSMRH_REVD          ((uint)0x00002000)
+#define SCC_GSMRH_TRX           ((uint)0x00001000)
+#define SCC_GSMRH_TTX           ((uint)0x00000800)
+#define SCC_GSMRH_CDP           ((uint)0x00000400)
+#define SCC_GSMRH_CTSP          ((uint)0x00000200)
+#define SCC_GSMRH_CDS           ((uint)0x00000100)
+#define SCC_GSMRH_CTSS          ((uint)0x00000080)
+#define SCC_GSMRH_TFL           ((uint)0x00000040)
+#define SCC_GSMRH_RFW           ((uint)0x00000020)
+#define SCC_GSMRH_TXSY          ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
+#define SCC_GSMRH_RTSM          ((uint)0x00000002)
+#define SCC_GSMRH_RSYN          ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
+#define SCC_GSMRL_TCI           ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
+#define SCC_GSMRL_RINV          ((uint)0x02000000)
+#define SCC_GSMRL_TINV          ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
+#define SCC_GSMRL_TEND          ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
+#define SCC_GSMRL_ENR           ((uint)0x00000020)
+#define SCC_GSMRL_ENT           ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
+#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
+
+#define SCC_TODR_TOD            ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE        ((unsigned char)0x10)
+#define SCCM_BSY        ((unsigned char)0x04)
+#define SCCM_TX         ((unsigned char)0x02)
+#define SCCM_RX         ((unsigned char)0x01)
+
+typedef struct scc_param {
+        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  scc_rfcr;       /* Rx function code */
+        u_char  scc_tfcr;       /* Tx function code */
+        ushort  scc_mrblr;      /* Max receive buffer length */
+        uint    scc_rstate;     /* Internal */
+        uint    scc_idp;        /* Internal */
+        ushort  scc_rbptr;      /* Internal */
+        ushort  scc_ibc;        /* Internal */
+        uint    scc_rxtmp;      /* Internal */
+        uint    scc_tstate;     /* Internal */
+        uint    scc_tdp;        /* Internal */
+        ushort  scc_tbptr;      /* Internal */
+        ushort  scc_tbc;        /* Internal */
+        uint    scc_txtmp;      /* Internal */
+        uint    scc_rcrc;       /* Internal */
+        uint    scc_tcrc;       /* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+        sccp_t  sen_genscc;
+        uint    sen_cpres;      /* Preset CRC */
+        uint    sen_cmask;      /* Constant mask for CRC */
+        uint    sen_crcec;      /* CRC Error counter */
+        uint    sen_alec;       /* alignment error counter */
+        uint    sen_disfc;      /* discard frame counter */
+        ushort  sen_pads;       /* Tx short frame pad character */
+        ushort  sen_retlim;     /* Retry limit threshold */
+        ushort  sen_retcnt;     /* Retry limit counter */
+        ushort  sen_maxflr;     /* maximum frame length register */
+        ushort  sen_minflr;     /* minimum frame length register */
+        ushort  sen_maxd1;      /* maximum DMA1 length */
+        ushort  sen_maxd2;      /* maximum DMA2 length */
+        ushort  sen_maxd;       /* Rx max DMA */
+        ushort  sen_dmacnt;     /* Rx DMA counter */
+        ushort  sen_maxb;       /* Max BD byte count */
+        ushort  sen_gaddr1;     /* Group address filter */
+        ushort  sen_gaddr2;
+        ushort  sen_gaddr3;
+        ushort  sen_gaddr4;
+        uint    sen_tbuf0data0; /* Save area 0 - current frame */
+        uint    sen_tbuf0data1; /* Save area 1 - current frame */
+        uint    sen_tbuf0rba;   /* Internal */
+        uint    sen_tbuf0crc;   /* Internal */
+        ushort  sen_tbuf0bcnt;  /* Internal */
+        ushort  sen_paddrh;     /* physical address (MSB) */
+        ushort  sen_paddrm;
+        ushort  sen_paddrl;     /* physical address (LSB) */
+        ushort  sen_pper;       /* persistence */
+        ushort  sen_rfbdptr;    /* Rx first BD pointer */
+        ushort  sen_tfbdptr;    /* Tx first BD pointer */
+        ushort  sen_tlbdptr;    /* Tx last BD pointer */
+        uint    sen_tbuf1data0; /* Save area 0 - current frame */
+        uint    sen_tbuf1data1; /* Save area 1 - current frame */
+        uint    sen_tbuf1rba;   /* Internal */
+        uint    sen_tbuf1crc;   /* Internal */
+        ushort  sen_tbuf1bcnt;  /* Internal */
+        ushort  sen_txlen;      /* Tx Frame length counter */
+        ushort  sen_iaddr1;     /* Individual address filter */
+        ushort  sen_iaddr2;
+        ushort  sen_iaddr3;
+        ushort  sen_iaddr4;
+        ushort  sen_boffcnt;    /* Backoff counter */
+
+        /* NOTE: Some versions of the manual have the following items
+         * incorrectly documented.  Below is the proper order.
+         */
+        ushort  sen_taddrh;     /* temp address (MSB) */
+        ushort  sen_taddrm;
+        ushort  sen_taddrl;     /* temp address (LSB) */
+} scc_enet_t;
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
+#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
+#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
+#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
+#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
+#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
+
+/* SCC Mode Register (PMSR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
+#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
+#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
+#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
+#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
+#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
+#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
+#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
+#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
+#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
+#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
+#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
+#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
+#define BD_ENET_RX_WRAP         ((ushort)0x2000)
+#define BD_ENET_RX_INTR         ((ushort)0x1000)
+#define BD_ENET_RX_LAST         ((ushort)0x0800)
+#define BD_ENET_RX_FIRST        ((ushort)0x0400)
+#define BD_ENET_RX_MISS         ((ushort)0x0100)
+#define BD_ENET_RX_LG           ((ushort)0x0020)
+#define BD_ENET_RX_NO           ((ushort)0x0010)
+#define BD_ENET_RX_SH           ((ushort)0x0008)
+#define BD_ENET_RX_CR           ((ushort)0x0004)
+#define BD_ENET_RX_OV           ((ushort)0x0002)
+#define BD_ENET_RX_CL           ((ushort)0x0001)
+#define BD_ENET_RX_BC           ((ushort)0x0080)        /* DA is Broadcast */
+#define BD_ENET_RX_MC           ((ushort)0x0040)        /* DA is Multicast */
+#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY        ((ushort)0x8000)
+#define BD_ENET_TX_PAD          ((ushort)0x4000)
+#define BD_ENET_TX_WRAP         ((ushort)0x2000)
+#define BD_ENET_TX_INTR         ((ushort)0x1000)
+#define BD_ENET_TX_LAST         ((ushort)0x0800)
+#define BD_ENET_TX_TC           ((ushort)0x0400)
+#define BD_ENET_TX_DEF          ((ushort)0x0200)
+#define BD_ENET_TX_HB           ((ushort)0x0100)
+#define BD_ENET_TX_LC           ((ushort)0x0080)
+#define BD_ENET_TX_RL           ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
+#define BD_ENET_TX_UN           ((ushort)0x0002)
+#define BD_ENET_TX_CSL          ((ushort)0x0001)
+#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+        sccp_t  scc_genscc;
+        char    res1[8];        /* Reserved */
+        ushort  scc_maxidl;     /* Maximum idle chars */
+        ushort  scc_idlc;       /* temp idle counter */
+        ushort  scc_brkcr;      /* Break count register */
+        ushort  scc_parec;      /* receive parity error counter */
+        ushort  scc_frmec;      /* receive framing error counter */
+        ushort  scc_nosec;      /* receive noise counter */
+        ushort  scc_brkec;      /* receive break condition counter */
+        ushort  scc_brkln;      /* last received break length */
+        ushort  scc_uaddr1;     /* UART address character 1 */
+        ushort  scc_uaddr2;     /* UART address character 2 */
+        ushort  scc_rtemp;      /* Temp storage */
+        ushort  scc_toseq;      /* Transmit out of sequence char */
+        ushort  scc_char1;      /* control character 1 */
+        ushort  scc_char2;      /* control character 2 */
+        ushort  scc_char3;      /* control character 3 */
+        ushort  scc_char4;      /* control character 4 */
+        ushort  scc_char5;      /* control character 5 */
+        ushort  scc_char6;      /* control character 6 */
+        ushort  scc_char7;      /* control character 7 */
+        ushort  scc_char8;      /* control character 8 */
+        ushort  scc_rccm;       /* receive control character mask */
+        ushort  scc_rccr;       /* receive control character register */
+        ushort  scc_rlbc;       /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR           ((ushort)0x1000)
+#define UART_SCCM_GLT           ((ushort)0x0800)
+#define UART_SCCM_AB            ((ushort)0x0200)
+#define UART_SCCM_IDL           ((ushort)0x0100)
+#define UART_SCCM_GRA           ((ushort)0x0080)
+#define UART_SCCM_BRKE          ((ushort)0x0040)
+#define UART_SCCM_BRKS          ((ushort)0x0020)
+#define UART_SCCM_CCR           ((ushort)0x0008)
+#define UART_SCCM_BSY           ((ushort)0x0004)
+#define UART_SCCM_TX            ((ushort)0x0002)
+#define UART_SCCM_RX            ((ushort)0x0001)
+
+/* The SCC PMSR when used as a UART.
+*/
+#define SCU_PSMR_FLC            ((ushort)0x8000)
+#define SCU_PSMR_SL             ((ushort)0x4000)
+#define SCU_PSMR_CL             ((ushort)0x3000)
+#define SCU_PSMR_UM             ((ushort)0x0c00)
+#define SCU_PSMR_FRZ            ((ushort)0x0200)
+#define SCU_PSMR_RZS            ((ushort)0x0100)
+#define SCU_PSMR_SYN            ((ushort)0x0080)
+#define SCU_PSMR_DRT            ((ushort)0x0040)
+#define SCU_PSMR_PEN            ((ushort)0x0010)
+#define SCU_PSMR_RPM            ((ushort)0x000c)
+#define SCU_PSMR_REVP           ((ushort)0x0008)
+#define SCU_PSMR_TPM            ((ushort)0x0003)
+#define SCU_PSMR_TEVP           ((ushort)0x0002)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+        sccp_t  st_genscc;
+        uint    st_cpres;       /* Preset CRC */
+        uint    st_cmask;       /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST          ((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
+        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
+        u_char  iic_rfcr;       /* Rx function code */
+        u_char  iic_tfcr;       /* Tx function code */
+        ushort  iic_mrblr;      /* Max receive buffer length */
+        uint    iic_rstate;     /* Internal */
+        uint    iic_rdp;        /* Internal */
+        ushort  iic_rbptr;      /* Internal */
+        ushort  iic_rbc;        /* Internal */
+        uint    iic_rxtmp;      /* Internal */
+        uint    iic_tstate;     /* Internal */
+        uint    iic_tdp;        /* Internal */
+        ushort  iic_tbptr;      /* Internal */
+        ushort  iic_tbc;        /* Internal */
+        uint    iic_txtmp;      /* Internal */
+        char    res1[4];        /* Reserved */
+        ushort  iic_rpbase;     /* Relocation pointer */
+        char    res2[2];        /* Reserved */
+} iic_t;
+
+#define BD_IIC_START            ((ushort)0x0400)
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
+        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
+        u_char  spi_rfcr;       /* Rx function code */
+        u_char  spi_tfcr;       /* Tx function code */
+        ushort  spi_mrblr;      /* Max receive buffer length */
+        uint    spi_rstate;     /* Internal */
+        uint    spi_rdp;        /* Internal */
+        ushort  spi_rbptr;      /* Internal */
+        ushort  spi_rbc;        /* Internal */
+        uint    spi_rxtmp;      /* Internal */
+        uint    spi_tstate;     /* Internal */
+        uint    spi_tdp;        /* Internal */
+        ushort  spi_tbptr;      /* Internal */
+        ushort  spi_tbc;        /* Internal */
+        uint    spi_txtmp;      /* Internal */
+        uint    spi_res;
+        ushort  spi_rpbase;     /* Relocation pointer */
+        ushort  spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
+#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
+#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
+#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
+#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
+#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
+#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
+#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
+#define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
+#define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
+#define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
+#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
+
+/* SPIE fields */
+#define SPIE_MME        0x20
+#define SPIE_TXE        0x10
+#define SPIE_BSY        0x04
+#define SPIE_TXB        0x02
+#define SPIE_RXB        0x01
+
+/*
+ * RISC Controller Configuration Register definitons
+ */
+#define RCCR_TIME       0x8000                  /* RISC Timer Enable */
+#define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
+#define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
+
+/* RISC Timer Parameter RAM offset */
+#define PROFF_RTMR      ((uint)0x01B0)
+
+typedef struct risc_timer_pram {
+        unsigned short  tm_base;        /* RISC Timer Table Base Address */
+        unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
+        unsigned short  r_tmr;          /* RISC Timer Mode Register */
+        unsigned short  r_tmv;          /* RISC Timer Valid Register */
+        unsigned long   tm_cmd;         /* RISC Timer Command Register */
+        unsigned long   tm_cnt;         /* RISC Timer Internal Count */
+} rt_pram_t;
+
+/* Bits in RISC Timer Command Register */
+#define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
+#define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
+#define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
+#define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
+#define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR               32
+#define CPMVEC_PIO_PC15         ((ushort)0x1f)
+#define CPMVEC_SCC1             ((ushort)0x1e)
+#define CPMVEC_SCC2             ((ushort)0x1d)
+#define CPMVEC_SCC3             ((ushort)0x1c)
+#define CPMVEC_SCC4             ((ushort)0x1b)
+#define CPMVEC_PIO_PC14         ((ushort)0x1a)
+#define CPMVEC_TIMER1           ((ushort)0x19)
+#define CPMVEC_PIO_PC13         ((ushort)0x18)
+#define CPMVEC_PIO_PC12         ((ushort)0x17)
+#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
+#define CPMVEC_IDMA1            ((ushort)0x15)
+#define CPMVEC_IDMA2            ((ushort)0x14)
+#define CPMVEC_TIMER2           ((ushort)0x12)
+#define CPMVEC_RISCTIMER        ((ushort)0x11)
+#define CPMVEC_I2C              ((ushort)0x10)
+#define CPMVEC_PIO_PC11         ((ushort)0x0f)
+#define CPMVEC_PIO_PC10         ((ushort)0x0e)
+#define CPMVEC_TIMER3           ((ushort)0x0c)
+#define CPMVEC_PIO_PC9          ((ushort)0x0b)
+#define CPMVEC_PIO_PC8          ((ushort)0x0a)
+#define CPMVEC_PIO_PC7          ((ushort)0x09)
+#define CPMVEC_TIMER4           ((ushort)0x07)
+#define CPMVEC_PIO_PC6          ((ushort)0x06)
+#define CPMVEC_SPI              ((ushort)0x05)
+#define CPMVEC_SMC1             ((ushort)0x04)
+#define CPMVEC_SMC2             ((ushort)0x03)
+#define CPMVEC_PIO_PC5          ((ushort)0x02)
+#define CPMVEC_PIO_PC4          ((ushort)0x01)
+#define CPMVEC_ERROR            ((ushort)0x00)
+
+/* CPM interrupt configuration vector.
+*/
+#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
+#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
+#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
+#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
+#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
+#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
+#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
+#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
+
+extern void cpm_install_handler(int vec,
+                void (*handler)(void *, struct pt_regs *regs), void *dev_id);
+extern void cpm_free_handler(int vec);
+
+#endif /* __CPM_8XX__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
new file mode 100644
index 000000000000..42fd1068cf2a
--- /dev/null
+++ b/include/asm-ppc/cpm2.h
@@ -0,0 +1,1045 @@
+/*
+ * Communication Processor Module v2.
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the CPM2 internal
+ * memory map.  See immap_cpm2.h for details.
+ */
+#ifdef __KERNEL__
+#ifndef __CPM2__
+#define __CPM2__
+
+#include <asm/immap_cpm2.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST      ((uint)0x80000000)
+#define CPM_CR_PAGE     ((uint)0x7c000000)
+#define CPM_CR_SBLOCK   ((uint)0x03e00000)
+#define CPM_CR_FLG      ((uint)0x00010000)
+#define CPM_CR_MCN      ((uint)0x00003fc0)
+#define CPM_CR_OPCODE   ((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK      (0x04)
+#define CPM_CR_SCC2_SBLOCK      (0x05)
+#define CPM_CR_SCC3_SBLOCK      (0x06)
+#define CPM_CR_SCC4_SBLOCK      (0x07)
+#define CPM_CR_SMC1_SBLOCK      (0x08)
+#define CPM_CR_SMC2_SBLOCK      (0x09)
+#define CPM_CR_SPI_SBLOCK       (0x0a)
+#define CPM_CR_I2C_SBLOCK       (0x0b)
+#define CPM_CR_TIMER_SBLOCK     (0x0f)
+#define CPM_CR_RAND_SBLOCK      (0x0e)
+#define CPM_CR_FCC1_SBLOCK      (0x10)
+#define CPM_CR_FCC2_SBLOCK      (0x11)
+#define CPM_CR_FCC3_SBLOCK      (0x12)
+#define CPM_CR_IDMA1_SBLOCK     (0x14)
+#define CPM_CR_IDMA2_SBLOCK     (0x15)
+#define CPM_CR_IDMA3_SBLOCK     (0x16)
+#define CPM_CR_IDMA4_SBLOCK     (0x17)
+#define CPM_CR_MCC1_SBLOCK      (0x1c)
+
+#define CPM_CR_SCC1_PAGE        (0x00)
+#define CPM_CR_SCC2_PAGE        (0x01)
+#define CPM_CR_SCC3_PAGE        (0x02)
+#define CPM_CR_SCC4_PAGE        (0x03)
+#define CPM_CR_SMC1_PAGE        (0x07)
+#define CPM_CR_SMC2_PAGE        (0x08)
+#define CPM_CR_SPI_PAGE         (0x09)
+#define CPM_CR_I2C_PAGE         (0x0a)
+#define CPM_CR_TIMER_PAGE       (0x0a)
+#define CPM_CR_RAND_PAGE        (0x0a)
+#define CPM_CR_FCC1_PAGE        (0x04)
+#define CPM_CR_FCC2_PAGE        (0x05)
+#define CPM_CR_FCC3_PAGE        (0x06)
+#define CPM_CR_IDMA1_PAGE       (0x07)
+#define CPM_CR_IDMA2_PAGE       (0x08)
+#define CPM_CR_IDMA3_PAGE       (0x09)
+#define CPM_CR_IDMA4_PAGE       (0x0a)
+#define CPM_CR_MCC1_PAGE        (0x07)
+#define CPM_CR_MCC2_PAGE        (0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX         ((ushort)0x0000)
+#define CPM_CR_INIT_RX          ((ushort)0x0001)
+#define CPM_CR_INIT_TX          ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
+#define CPM_CR_STOP_TX          ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
+#define CPM_CR_RESTART_TX       ((ushort)0x0006)
+#define CPM_CR_SET_GADDR        ((ushort)0x0008)
+#define CPM_CR_START_IDMA       ((ushort)0x0009)
+#define CPM_CR_STOP_IDMA        ((ushort)0x000b)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+        ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses.  The first 16K is available for almost
+ * any CPM use, so we put the BDs there.  The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that.  All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE       ((uint)128)
+#define CPM_DP_NOSPACE          ((uint)0x7fffffff)
+#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
+#define CPM_DATAONLY_SIZE       ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_FCC_SPECIAL_BASE    ((uint)0x00009000)
+#else
+#define CPM_DATAONLY_SIZE       ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_FCC_SPECIAL_BASE    ((uint)0x0000b000)
+#endif
+
+/* The number of pages of host memory we allocate for CPM.  This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES      2
+
+static inline long IS_DPERR(const uint offset)
+{
+        return (uint)offset > (uint)-1000L;
+}
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern          cpm_cpm2_t      *cpmp;   /* Pointer to comm processor */
+extern uint cpm_dpalloc(uint size, uint align);
+extern int cpm_dpfree(uint offset);
+extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
+extern void cpm_dpdump(void);
+extern void *cpm_dpram_addr(uint offset);
+extern void cpm_setbrg(uint brg, uint rate);
+extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+        ushort  cbd_sc;         /* Status and Control */
+        ushort  cbd_datlen;     /* Data length in buffer */
+        uint    cbd_bufaddr;    /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
+#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
+#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
+#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
+#define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
+#define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
+#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
+#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
+#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
+#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
+#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
+#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
+#define BD_SC_CD        ((ushort)0x0001)        /* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL      ((u_char)0x20)  /* Set memory snooping */
+#define CPMFCR_EB       ((u_char)0x10)  /* Set big endian byte order */
+#define CPMFCR_TC2      ((u_char)0x04)  /* Transfer code 2 value */
+#define CPMFCR_DTB      ((u_char)0x02)  /* Use local bus for data when set */
+#define CPMFCR_BDB      ((u_char)0x01)  /* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define PROFF_SCC1              ((uint)0x8000)
+#define PROFF_SCC2              ((uint)0x8100)
+#define PROFF_SCC3              ((uint)0x8200)
+#define PROFF_SCC4              ((uint)0x8300)
+#define PROFF_FCC1              ((uint)0x8400)
+#define PROFF_FCC2              ((uint)0x8500)
+#define PROFF_FCC3              ((uint)0x8600)
+#define PROFF_MCC1              ((uint)0x8700)
+#define PROFF_SMC1_BASE         ((uint)0x87fc)
+#define PROFF_IDMA1_BASE        ((uint)0x87fe)
+#define PROFF_MCC2              ((uint)0x8800)
+#define PROFF_SMC2_BASE         ((uint)0x88fc)
+#define PROFF_IDMA2_BASE        ((uint)0x88fe)
+#define PROFF_SPI_BASE          ((uint)0x89fc)
+#define PROFF_IDMA3_BASE        ((uint)0x89fe)
+#define PROFF_TIMERS            ((uint)0x8ae0)
+#define PROFF_REVNUM            ((uint)0x8af0)
+#define PROFF_RAND              ((uint)0x8af8)
+#define PROFF_I2C_BASE          ((uint)0x8afc)
+#define PROFF_IDMA4_BASE        ((uint)0x8afe)
+
+/* The SMCs are relocated to any of the first eight DPRAM pages.
+ * We will fix these at the first locations of DPRAM, until we
+ * get some microcode patches :-).
+ * The parameter ram space for the SMCs is fifty-some bytes, and
+ * they are required to start on a 64 byte boundary.
+ */
+#define PROFF_SMC1      (0)
+#define PROFF_SMC2      (64)
+
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  smc_rfcr;       /* Rx function code */
+        u_char  smc_tfcr;       /* Tx function code */
+        ushort  smc_mrblr;      /* Max receive buffer length */
+        uint    smc_rstate;     /* Internal */
+        uint    smc_idp;        /* Internal */
+        ushort  smc_rbptr;      /* Internal */
+        ushort  smc_ibc;        /* Internal */
+        uint    smc_rxtmp;      /* Internal */
+        uint    smc_tstate;     /* Internal */
+        uint    smc_tdp;        /* Internal */
+        ushort  smc_tbptr;      /* Internal */
+        ushort  smc_tbc;        /* Internal */
+        uint    smc_txtmp;      /* Internal */
+        ushort  smc_maxidl;     /* Maximum idle characters */
+        ushort  smc_tmpidl;     /* Temporary idle counter */
+        ushort  smc_brklen;     /* Last received break length */
+        ushort  smc_brkec;      /* rcv'd break condition counter */
+        ushort  smc_brkcr;      /* xmt break count register */
+        ushort  smc_rmask;      /* Temporary bit mask */
+        uint    smc_stmp;       /* SDMA Temp */
+} smc_uart_t;
+
+/* SMC uart mode register (Internal memory map).
+*/
+#define SMCMR_REN       ((ushort)0x0001)
+#define SMCMR_TEN       ((ushort)0x0002)
+#define SMCMR_DM        ((ushort)0x000c)
+#define SMCMR_SM_GCI    ((ushort)0x0000)
+#define SMCMR_SM_UART   ((ushort)0x0020)
+#define SMCMR_SM_TRANS  ((ushort)0x0030)
+#define SMCMR_SM_MASK   ((ushort)0x0030)
+#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
+#define SMCMR_REVD      SMCMR_PM_EVEN
+#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
+#define SMCMR_BS        SMCMR_PEN
+#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
+#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
+#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC Event and Mask register.
+*/
+#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
+#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
+#define SMCM_TXE        ((unsigned char)0x10)
+#define SMCM_BSY        ((unsigned char)0x04)
+#define SMCM_TX         ((unsigned char)0x02)
+#define SMCM_RX         ((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST             ((uint)0x00020000)
+#define CPM_BRG_EN              ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9     ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
+#define CPM_BRG_ATB             ((uint)0x00002000)
+#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
+#define CPM_BRG_DIV16           ((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP           ((uint)0x00040000)
+#define SCC_GSMRH_GDE           ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
+#define SCC_GSMRH_REVD          ((uint)0x00002000)
+#define SCC_GSMRH_TRX           ((uint)0x00001000)
+#define SCC_GSMRH_TTX           ((uint)0x00000800)
+#define SCC_GSMRH_CDP           ((uint)0x00000400)
+#define SCC_GSMRH_CTSP          ((uint)0x00000200)
+#define SCC_GSMRH_CDS           ((uint)0x00000100)
+#define SCC_GSMRH_CTSS          ((uint)0x00000080)
+#define SCC_GSMRH_TFL           ((uint)0x00000040)
+#define SCC_GSMRH_RFW           ((uint)0x00000020)
+#define SCC_GSMRH_TXSY          ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
+#define SCC_GSMRH_RTSM          ((uint)0x00000002)
+#define SCC_GSMRH_RSYN          ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
+#define SCC_GSMRL_TCI           ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
+#define SCC_GSMRL_RINV          ((uint)0x02000000)
+#define SCC_GSMRL_TINV          ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
+#define SCC_GSMRL_TEND          ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
+#define SCC_GSMRL_ENR           ((uint)0x00000020)
+#define SCC_GSMRL_ENT           ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
+
+#define SCC_TODR_TOD            ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE        ((unsigned char)0x10)
+#define SCCM_BSY        ((unsigned char)0x04)
+#define SCCM_TX         ((unsigned char)0x02)
+#define SCCM_RX         ((unsigned char)0x01)
+
+typedef struct scc_param {
+        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
+        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
+        u_char  scc_rfcr;       /* Rx function code */
+        u_char  scc_tfcr;       /* Tx function code */
+        ushort  scc_mrblr;      /* Max receive buffer length */
+        uint    scc_rstate;     /* Internal */
+        uint    scc_idp;        /* Internal */
+        ushort  scc_rbptr;      /* Internal */
+        ushort  scc_ibc;        /* Internal */
+        uint    scc_rxtmp;      /* Internal */
+        uint    scc_tstate;     /* Internal */
+        uint    scc_tdp;        /* Internal */
+        ushort  scc_tbptr;      /* Internal */
+        ushort  scc_tbc;        /* Internal */
+        uint    scc_txtmp;      /* Internal */
+        uint    scc_rcrc;       /* Internal */
+        uint    scc_tcrc;       /* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+        sccp_t  sen_genscc;
+        uint    sen_cpres;      /* Preset CRC */
+        uint    sen_cmask;      /* Constant mask for CRC */
+        uint    sen_crcec;      /* CRC Error counter */
+        uint    sen_alec;       /* alignment error counter */
+        uint    sen_disfc;      /* discard frame counter */
+        ushort  sen_pads;       /* Tx short frame pad character */
+        ushort  sen_retlim;     /* Retry limit threshold */
+        ushort  sen_retcnt;     /* Retry limit counter */
+        ushort  sen_maxflr;     /* maximum frame length register */
+        ushort  sen_minflr;     /* minimum frame length register */
+        ushort  sen_maxd1;      /* maximum DMA1 length */
+        ushort  sen_maxd2;      /* maximum DMA2 length */
+        ushort  sen_maxd;       /* Rx max DMA */
+        ushort  sen_dmacnt;     /* Rx DMA counter */
+        ushort  sen_maxb;       /* Max BD byte count */
+        ushort  sen_gaddr1;     /* Group address filter */
+        ushort  sen_gaddr2;
+        ushort  sen_gaddr3;
+        ushort  sen_gaddr4;
+        uint    sen_tbuf0data0; /* Save area 0 - current frame */
+        uint    sen_tbuf0data1; /* Save area 1 - current frame */
+        uint    sen_tbuf0rba;   /* Internal */
+        uint    sen_tbuf0crc;   /* Internal */
+        ushort  sen_tbuf0bcnt;  /* Internal */
+        ushort  sen_paddrh;     /* physical address (MSB) */
+        ushort  sen_paddrm;
+        ushort  sen_paddrl;     /* physical address (LSB) */
+        ushort  sen_pper;       /* persistence */
+        ushort  sen_rfbdptr;    /* Rx first BD pointer */
+        ushort  sen_tfbdptr;    /* Tx first BD pointer */
+        ushort  sen_tlbdptr;    /* Tx last BD pointer */
+        uint    sen_tbuf1data0; /* Save area 0 - current frame */
+        uint    sen_tbuf1data1; /* Save area 1 - current frame */
+        uint    sen_tbuf1rba;   /* Internal */
+        uint    sen_tbuf1crc;   /* Internal */
+        ushort  sen_tbuf1bcnt;  /* Internal */
+        ushort  sen_txlen;      /* Tx Frame length counter */
+        ushort  sen_iaddr1;     /* Individual address filter */
+        ushort  sen_iaddr2;
+        ushort  sen_iaddr3;
+        ushort  sen_iaddr4;
+        ushort  sen_boffcnt;    /* Backoff counter */
+
+        /* NOTE: Some versions of the manual have the following items
+         * incorrectly documented.  Below is the proper order.
+         */
+        ushort  sen_taddrh;     /* temp address (MSB) */
+        ushort  sen_taddrm;
+        ushort  sen_taddrl;     /* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
+#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
+#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
+#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
+#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
+#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
+#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
+#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
+#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
+#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
+#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
+#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
+#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
+#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
+#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
+#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
+#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
+#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
+#define BD_ENET_RX_WRAP         ((ushort)0x2000)
+#define BD_ENET_RX_INTR         ((ushort)0x1000)
+#define BD_ENET_RX_LAST         ((ushort)0x0800)
+#define BD_ENET_RX_FIRST        ((ushort)0x0400)
+#define BD_ENET_RX_MISS         ((ushort)0x0100)
+#define BD_ENET_RX_BC           ((ushort)0x0080)        /* FCC Only */
+#define BD_ENET_RX_MC           ((ushort)0x0040)        /* FCC Only */
+#define BD_ENET_RX_LG           ((ushort)0x0020)
+#define BD_ENET_RX_NO           ((ushort)0x0010)
+#define BD_ENET_RX_SH           ((ushort)0x0008)
+#define BD_ENET_RX_CR           ((ushort)0x0004)
+#define BD_ENET_RX_OV           ((ushort)0x0002)
+#define BD_ENET_RX_CL           ((ushort)0x0001)
+#define BD_ENET_RX_STATS        ((ushort)0x01ff)        /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY        ((ushort)0x8000)
+#define BD_ENET_TX_PAD          ((ushort)0x4000)
+#define BD_ENET_TX_WRAP         ((ushort)0x2000)
+#define BD_ENET_TX_INTR         ((ushort)0x1000)
+#define BD_ENET_TX_LAST         ((ushort)0x0800)
+#define BD_ENET_TX_TC           ((ushort)0x0400)
+#define BD_ENET_TX_DEF          ((ushort)0x0200)
+#define BD_ENET_TX_HB           ((ushort)0x0100)
+#define BD_ENET_TX_LC           ((ushort)0x0080)
+#define BD_ENET_TX_RL           ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
+#define BD_ENET_TX_UN           ((ushort)0x0002)
+#define BD_ENET_TX_CSL          ((ushort)0x0001)
+#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+        sccp_t  scc_genscc;
+        uint    scc_res1;       /* Reserved */
+        uint    scc_res2;       /* Reserved */
+        ushort  scc_maxidl;     /* Maximum idle chars */
+        ushort  scc_idlc;       /* temp idle counter */
+        ushort  scc_brkcr;      /* Break count register */
+        ushort  scc_parec;      /* receive parity error counter */
+        ushort  scc_frmec;      /* receive framing error counter */
+        ushort  scc_nosec;      /* receive noise counter */
+        ushort  scc_brkec;      /* receive break condition counter */
+        ushort  scc_brkln;      /* last received break length */
+        ushort  scc_uaddr1;     /* UART address character 1 */
+        ushort  scc_uaddr2;     /* UART address character 2 */
+        ushort  scc_rtemp;      /* Temp storage */
+        ushort  scc_toseq;      /* Transmit out of sequence char */
+        ushort  scc_char1;      /* control character 1 */
+        ushort  scc_char2;      /* control character 2 */
+        ushort  scc_char3;      /* control character 3 */
+        ushort  scc_char4;      /* control character 4 */
+        ushort  scc_char5;      /* control character 5 */
+        ushort  scc_char6;      /* control character 6 */
+        ushort  scc_char7;      /* control character 7 */
+        ushort  scc_char8;      /* control character 8 */
+        ushort  scc_rccm;       /* receive control character mask */
+        ushort  scc_rccr;       /* receive control character register */
+        ushort  scc_rlbc;       /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR           ((ushort)0x1000)
+#define UART_SCCM_GLT           ((ushort)0x0800)
+#define UART_SCCM_AB            ((ushort)0x0200)
+#define UART_SCCM_IDL           ((ushort)0x0100)
+#define UART_SCCM_GRA           ((ushort)0x0080)
+#define UART_SCCM_BRKE          ((ushort)0x0040)
+#define UART_SCCM_BRKS          ((ushort)0x0020)
+#define UART_SCCM_CCR           ((ushort)0x0008)
+#define UART_SCCM_BSY           ((ushort)0x0004)
+#define UART_SCCM_TX            ((ushort)0x0002)
+#define UART_SCCM_RX            ((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC            ((ushort)0x8000)
+#define SCU_PSMR_SL             ((ushort)0x4000)
+#define SCU_PSMR_CL             ((ushort)0x3000)
+#define SCU_PSMR_UM             ((ushort)0x0c00)
+#define SCU_PSMR_FRZ            ((ushort)0x0200)
+#define SCU_PSMR_RZS            ((ushort)0x0100)
+#define SCU_PSMR_SYN            ((ushort)0x0080)
+#define SCU_PSMR_DRT            ((ushort)0x0040)
+#define SCU_PSMR_PEN            ((ushort)0x0010)
+#define SCU_PSMR_RPM            ((ushort)0x000c)
+#define SCU_PSMR_REVP           ((ushort)0x0008)
+#define SCU_PSMR_TPM            ((ushort)0x0003)
+#define SCU_PSMR_TEVP           ((ushort)0x0002)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+        sccp_t  st_genscc;
+        uint    st_cpres;       /* Preset CRC */
+        uint    st_cmask;       /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST          ((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM      ((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE        ((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE        ((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE       ((uint)0xc0000000)
+#define FCC_GFMR_TCI            ((uint)0x20000000)
+#define FCC_GFMR_TRX            ((uint)0x10000000)
+#define FCC_GFMR_TTX            ((uint)0x08000000)
+#define FCC_GFMR_TTX            ((uint)0x08000000)
+#define FCC_GFMR_CDP            ((uint)0x04000000)
+#define FCC_GFMR_CTSP           ((uint)0x02000000)
+#define FCC_GFMR_CDS            ((uint)0x01000000)
+#define FCC_GFMR_CTSS           ((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE      ((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO      ((uint)0x00004000)
+#define FCC_GFMR_SYNL_8         ((uint)0x00008000)
+#define FCC_GFMR_SYNL_16        ((uint)0x0000c000)
+#define FCC_GFMR_RTSM           ((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ       ((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI      ((uint)0x00000800)
+#define FCC_GFMR_REVD           ((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ       ((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI      ((uint)0x00000100)
+#define FCC_GFMR_TCRC_16        ((uint)0x00000000)
+#define FCC_GFMR_TCRC_32        ((uint)0x00000080)
+#define FCC_GFMR_ENR            ((uint)0x00000020)
+#define FCC_GFMR_ENT            ((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET      ((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM       ((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC      ((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+        ushort  fcc_riptr;      /* Rx Internal temp pointer */
+        ushort  fcc_tiptr;      /* Tx Internal temp pointer */
+        ushort  fcc_res1;
+        ushort  fcc_mrblr;      /* Max receive buffer length, mod 32 bytes */
+        uint    fcc_rstate;     /* Upper byte is Func code, must be set */
+        uint    fcc_rbase;      /* Receive BD base */
+        ushort  fcc_rbdstat;    /* RxBD status */
+        ushort  fcc_rbdlen;     /* RxBD down counter */
+        uint    fcc_rdptr;      /* RxBD internal data pointer */
+        uint    fcc_tstate;     /* Upper byte is Func code, must be set */
+        uint    fcc_tbase;      /* Transmit BD base */
+        ushort  fcc_tbdstat;    /* TxBD status */
+        ushort  fcc_tbdlen;     /* TxBD down counter */
+        uint    fcc_tdptr;      /* TxBD internal data pointer */
+        uint    fcc_rbptr;      /* Rx BD Internal buf pointer */
+        uint    fcc_tbptr;      /* Tx BD Internal buf pointer */
+        uint    fcc_rcrc;       /* Rx temp CRC */
+        uint    fcc_res2;
+        uint    fcc_tcrc;       /* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+        fccp_t  fen_genfcc;
+        uint    fen_statbuf;    /* Internal status buffer */
+        uint    fen_camptr;     /* CAM address */
+        uint    fen_cmask;      /* Constant mask for CRC */
+        uint    fen_cpres;      /* Preset CRC */
+        uint    fen_crcec;      /* CRC Error counter */
+        uint    fen_alec;       /* alignment error counter */
+        uint    fen_disfc;      /* discard frame counter */
+        ushort  fen_retlim;     /* Retry limit */
+        ushort  fen_retcnt;     /* Retry counter */
+        ushort  fen_pper;       /* Persistence */
+        ushort  fen_boffcnt;    /* backoff counter */
+        uint    fen_gaddrh;     /* Group address filter, high 32-bits */
+        uint    fen_gaddrl;     /* Group address filter, low 32-bits */
+        ushort  fen_tfcstat;    /* out of sequence TxBD */
+        ushort  fen_tfclen;
+        uint    fen_tfcptr;
+        ushort  fen_mflr;       /* Maximum frame length (1518) */
+        ushort  fen_paddrh;     /* MAC address */
+        ushort  fen_paddrm;
+        ushort  fen_paddrl;
+        ushort  fen_ibdcount;   /* Internal BD counter */
+        ushort  fen_ibdstart;   /* Internal BD start pointer */
+        ushort  fen_ibdend;     /* Internal BD end pointer */
+        ushort  fen_txlen;      /* Internal Tx frame length counter */
+        uint    fen_ibdbase[8]; /* Internal use */
+        uint    fen_iaddrh;     /* Individual address filter */
+        uint    fen_iaddrl;
+        ushort  fen_minflr;     /* Minimum frame length (64) */
+        ushort  fen_taddrh;     /* Filter transfer MAC address */
+        ushort  fen_taddrm;
+        ushort  fen_taddrl;
+        ushort  fen_padptr;     /* Pointer to pad byte buffer */
+        ushort  fen_cftype;     /* control frame type */
+        ushort  fen_cfrange;    /* control frame range */
+        ushort  fen_maxb;       /* maximum BD count */
+        ushort  fen_maxd1;      /* Max DMA1 length (1520) */
+        ushort  fen_maxd2;      /* Max DMA2 length (1520) */
+        ushort  fen_maxd;       /* internal max DMA count */
+        ushort  fen_dmacnt;     /* internal DMA counter */
+        uint    fen_octc;       /* Total octect counter */
+        uint    fen_colc;       /* Total collision counter */
+        uint    fen_broc;       /* Total broadcast packet counter */
+        uint    fen_mulc;       /* Total multicast packet count */
+        uint    fen_uspc;       /* Total packets < 64 bytes */
+        uint    fen_frgc;       /* Total packets < 64 bytes with errors */
+        uint    fen_ospc;       /* Total packets > 1518 */
+        uint    fen_jbrc;       /* Total packets > 1518 with errors */
+        uint    fen_p64c;       /* Total packets == 64 bytes */
+        uint    fen_p65c;       /* Total packets 64 < bytes <= 127 */
+        uint    fen_p128c;      /* Total packets 127 < bytes <= 255 */
+        uint    fen_p256c;      /* Total packets 256 < bytes <= 511 */
+        uint    fen_p512c;      /* Total packets 512 < bytes <= 1023 */
+        uint    fen_p1024c;     /* Total packets 1024 < bytes <= 1518 */
+        uint    fen_cambuf;     /* Internal CAM buffer poiner */
+        ushort  fen_rfthr;      /* Received frames threshold */
+        ushort  fen_rfcnt;      /* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA    ((ushort)0x0080)        /* Graceful stop complete */
+#define FCC_ENET_RXC    ((ushort)0x0040)        /* Control Frame Received */
+#define FCC_ENET_TXC    ((ushort)0x0020)        /* Out of seq. Tx sent */
+#define FCC_ENET_TXE    ((ushort)0x0010)        /* Transmit Error */
+#define FCC_ENET_RXF    ((ushort)0x0008)        /* Full frame received */
+#define FCC_ENET_BSY    ((ushort)0x0004)        /* Busy.  Rx Frame dropped */
+#define FCC_ENET_TXB    ((ushort)0x0002)        /* A buffer was transmitted */
+#define FCC_ENET_RXB    ((ushort)0x0001)        /* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC    ((uint)0x80000000)      /* Enable heartbeat */
+#define FCC_PSMR_FC     ((uint)0x40000000)      /* Force Collision */
+#define FCC_PSMR_SBT    ((uint)0x20000000)      /* Stop backoff timer */
+#define FCC_PSMR_LPB    ((uint)0x10000000)      /* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW    ((uint)0x08000000)      /* Late collision select */
+#define FCC_PSMR_FDE    ((uint)0x04000000)      /* Full Duplex Enable */
+#define FCC_PSMR_MON    ((uint)0x02000000)      /* RMON Enable */
+#define FCC_PSMR_PRO    ((uint)0x00400000)      /* Promiscuous Enable */
+#define FCC_PSMR_FCE    ((uint)0x00200000)      /* Flow Control Enable */
+#define FCC_PSMR_RSH    ((uint)0x00100000)      /* Receive Short Frames */
+#define FCC_PSMR_CAM    ((uint)0x00000400)      /* CAM enable */
+#define FCC_PSMR_BRO    ((uint)0x00000200)      /* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC  ((uint)0x00000080)      /* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
+        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
+        u_char  iic_rfcr;       /* Rx function code */
+        u_char  iic_tfcr;       /* Tx function code */
+        ushort  iic_mrblr;      /* Max receive buffer length */
+        uint    iic_rstate;     /* Internal */
+        uint    iic_rdp;        /* Internal */
+        ushort  iic_rbptr;      /* Internal */
+        ushort  iic_rbc;        /* Internal */
+        uint    iic_rxtmp;      /* Internal */
+        uint    iic_tstate;     /* Internal */
+        uint    iic_tdp;        /* Internal */
+        ushort  iic_tbptr;      /* Internal */
+        ushort  iic_tbc;        /* Internal */
+        uint    iic_txtmp;      /* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
+        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
+        u_char  spi_rfcr;       /* Rx function code */
+        u_char  spi_tfcr;       /* Tx function code */
+        ushort  spi_mrblr;      /* Max receive buffer length */
+        uint    spi_rstate;     /* Internal */
+        uint    spi_rdp;        /* Internal */
+        ushort  spi_rbptr;      /* Internal */
+        ushort  spi_rbc;        /* Internal */
+        uint    spi_rxtmp;      /* Internal */
+        uint    spi_tstate;     /* Internal */
+        uint    spi_tdp;        /* Internal */
+        ushort  spi_tbptr;      /* Internal */
+        ushort  spi_tbc;        /* Internal */
+        uint    spi_txtmp;      /* Internal */
+        uint    spi_res;        /* Tx temp. */
+        uint    spi_res1[4];    /* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
+#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
+#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
+#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
+#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
+#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
+#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
+#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
+#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
+
+#define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)    ((x) &0xF)
+
+#define SPI_EB          ((u_char)0x10)          /* big endian byte order */
+
+#define BD_IIC_START            ((ushort)0x0400)
+
+/* IDMA parameter RAM
+*/
+typedef struct idma {
+        ushort ibase;           /* IDMA buffer descriptor table base address */
+        ushort dcm;             /* DMA channel mode */
+        ushort ibdptr;          /* IDMA current buffer descriptor pointer */
+        ushort dpr_buf;         /* IDMA transfer buffer base address */
+        ushort buf_inv;         /* internal buffer inventory */
+        ushort ss_max;          /* steady-state maximum transfer size */
+        ushort dpr_in_ptr;      /* write pointer inside the internal buffer */
+        ushort sts;             /* source transfer size */
+        ushort dpr_out_ptr;     /* read pointer inside the internal buffer */
+        ushort seob;            /* source end of burst */
+        ushort deob;            /* destination end of burst */
+        ushort dts;             /* destination transfer size */
+        ushort ret_add;         /* return address when working in ERM=1 mode */
+        ushort res0;            /* reserved */
+        uint   bd_cnt;          /* internal byte count */
+        uint   s_ptr;           /* source internal data pointer */
+        uint   d_ptr;           /* destination internal data pointer */
+        uint   istate;          /* internal state */
+        u_char res1[20];        /* pad to 64-byte length */
+} idma_t;
+
+/* DMA channel mode bit fields
+*/
+#define IDMA_DCM_FB             ((ushort)0x8000) /* fly-by mode */
+#define IDMA_DCM_LP             ((ushort)0x4000) /* low priority */
+#define IDMA_DCM_TC2            ((ushort)0x0400) /* value driven on TC[2] */
+#define IDMA_DCM_DMA_WRAP_MASK  ((ushort)0x01c0) /* mask for DMA wrap */
+#define IDMA_DCM_DMA_WRAP_64    ((ushort)0x0000) /* 64-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_128   ((ushort)0x0040) /* 128-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_256   ((ushort)0x0080) /* 256-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_512   ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_1024  ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
+#define IDMA_DCM_DMA_WRAP_2048  ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
+#define IDMA_DCM_SINC           ((ushort)0x0020) /* source inc addr */
+#define IDMA_DCM_DINC           ((ushort)0x0010) /* destination inc addr */
+#define IDMA_DCM_ERM            ((ushort)0x0008) /* external request mode */
+#define IDMA_DCM_DT             ((ushort)0x0004) /* DONE treatment */
+#define IDMA_DCM_SD_MASK        ((ushort)0x0003) /* mask for SD bit field */
+#define IDMA_DCM_SD_MEM2MEM     ((ushort)0x0000) /* memory-to-memory xfer */
+#define IDMA_DCM_SD_PER2MEM     ((ushort)0x0002) /* peripheral-to-memory xfer */
+#define IDMA_DCM_SD_MEM2PER     ((ushort)0x0001) /* memory-to-peripheral xfer */
+
+/* IDMA Buffer Descriptors
+*/
+typedef struct idma_bd {
+        uint flags;
+        uint len;       /* data length */
+        uint src;       /* source data buffer pointer */
+        uint dst;       /* destination data buffer pointer */
+} idma_bd_t;
+
+/* IDMA buffer descriptor flag bit fields
+*/
+#define IDMA_BD_V       ((uint)0x80000000)      /* valid */
+#define IDMA_BD_W       ((uint)0x20000000)      /* wrap */
+#define IDMA_BD_I       ((uint)0x10000000)      /* interrupt */
+#define IDMA_BD_L       ((uint)0x08000000)      /* last */
+#define IDMA_BD_CM      ((uint)0x02000000)      /* continuous mode */
+#define IDMA_BD_SDN     ((uint)0x00400000)      /* source done */
+#define IDMA_BD_DDN     ((uint)0x00200000)      /* destination done */
+#define IDMA_BD_DGBL    ((uint)0x00100000)      /* destination global */
+#define IDMA_BD_DBO_LE  ((uint)0x00040000)      /* little-end dest byte order */
+#define IDMA_BD_DBO_BE  ((uint)0x00080000)      /* big-end dest byte order */
+#define IDMA_BD_DDTB    ((uint)0x00010000)      /* destination data bus */
+#define IDMA_BD_SGBL    ((uint)0x00002000)      /* source global */
+#define IDMA_BD_SBO_LE  ((uint)0x00000800)      /* little-end src byte order */
+#define IDMA_BD_SBO_BE  ((uint)0x00001000)      /* big-end src byte order */
+#define IDMA_BD_SDTB    ((uint)0x00000200)      /* source data bus */
+
+/* per-channel IDMA registers
+*/
+typedef struct im_idma {
+        u_char idsr;                    /* IDMAn event status register */
+        u_char res0[3];
+        u_char idmr;                    /* IDMAn event mask register */
+        u_char res1[3];
+} im_idma_t;
+
+/* IDMA event register bit fields
+*/
+#define IDMA_EVENT_SC   ((unsigned char)0x08)   /* stop completed */
+#define IDMA_EVENT_OB   ((unsigned char)0x04)   /* out of buffers */
+#define IDMA_EVENT_EDN  ((unsigned char)0x02)   /* external DONE asserted */
+#define IDMA_EVENT_BC   ((unsigned char)0x01)   /* buffer descriptor complete */
+
+/* RISC Controller Configuration Register (RCCR) bit fields
+*/
+#define RCCR_TIME       ((uint)0x80000000) /* timer enable */
+#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
+#define RCCR_DR0M       ((uint)0x00800000) /* IDMA0 request mode */
+#define RCCR_DR1M       ((uint)0x00400000) /* IDMA1 request mode */
+#define RCCR_DR2M       ((uint)0x00000080) /* IDMA2 request mode */
+#define RCCR_DR3M       ((uint)0x00000040) /* IDMA3 request mode */
+#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
+#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
+#define RCCR_DR0QP_MED  ((uint)0x00100000) /* IDMA0 has medium req priority */
+#define RCCR_DR0QP_LOW  ((uint)0x00200000) /* IDMA0 has low req priority */
+#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
+#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
+#define RCCR_DR1QP_MED  ((uint)0x00010000) /* IDMA1 has medium req priority */
+#define RCCR_DR1QP_LOW  ((uint)0x00020000) /* IDMA1 has low req priority */
+#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
+#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
+#define RCCR_DR2QP_MED  ((uint)0x00000010) /* IDMA2 has medium req priority */
+#define RCCR_DR2QP_LOW  ((uint)0x00000020) /* IDMA2 has low req priority */
+#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
+#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
+#define RCCR_DR3QP_MED  ((uint)0x00000001) /* IDMA3 has medium req priority */
+#define RCCR_DR3QP_LOW  ((uint)0x00000002) /* IDMA3 has low req priority */
+#define RCCR_EIE        ((uint)0x00080000) /* external interrupt enable */
+#define RCCR_SCD        ((uint)0x00040000) /* scheduler configuration */
+#define RCCR_ERAM_MASK  ((uint)0x0000e000) /* mask for enable RAM microcode */
+#define RCCR_ERAM_0KB   ((uint)0x00000000) /* use 0KB of dpram for microcode */
+#define RCCR_ERAM_2KB   ((uint)0x00002000) /* use 2KB of dpram for microcode */
+#define RCCR_ERAM_4KB   ((uint)0x00004000) /* use 4KB of dpram for microcode */
+#define RCCR_ERAM_6KB   ((uint)0x00006000) /* use 6KB of dpram for microcode */
+#define RCCR_ERAM_8KB   ((uint)0x00008000) /* use 8KB of dpram for microcode */
+#define RCCR_ERAM_10KB  ((uint)0x0000a000) /* use 10KB of dpram for microcode */
+#define RCCR_ERAM_12KB  ((uint)0x0000c000) /* use 12KB of dpram for microcode */
+#define RCCR_EDM0       ((uint)0x00000800) /* DREQ0 edge detect mode */
+#define RCCR_EDM1       ((uint)0x00000400) /* DREQ1 edge detect mode */
+#define RCCR_EDM2       ((uint)0x00000200) /* DREQ2 edge detect mode */
+#define RCCR_EDM3       ((uint)0x00000100) /* DREQ3 edge detect mode */
+#define RCCR_DEM01      ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
+#define RCCR_DEM23      ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register
+ */
+#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
+#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
+#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
+#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register
+ */
+#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
+#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
+#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
+#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
+#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
+#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
+#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
+#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
+#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
+
+#endif /* __CPM2__ */
+#endif /* __KERNEL__ */
+
+
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
new file mode 100644
index 000000000000..22de04fe1b4c
--- /dev/null
+++ b/include/asm-ppc/cputable.h
@@ -0,0 +1,127 @@
+/*
+ *  include/asm-ppc/cputable.h
+ *
+ *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_CPUTABLE_H
+#define __ASM_PPC_CPUTABLE_H
+
+/* Exposed to userland CPU features */
+#define PPC_FEATURE_32                  0x80000000
+#define PPC_FEATURE_64                  0x40000000
+#define PPC_FEATURE_601_INSTR           0x20000000
+#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
+#define PPC_FEATURE_HAS_FPU             0x08000000
+#define PPC_FEATURE_HAS_MMU             0x04000000
+#define PPC_FEATURE_HAS_4xxMAC          0x02000000
+#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
+#define PPC_FEATURE_HAS_SPE             0x00800000
+#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
+#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+/* This structure can grow, it's real size is used by head.S code
+ * via the mkdefs mecanism.
+ */
+struct cpu_spec;
+
+typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
+
+struct cpu_spec {
+        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
+        unsigned int    pvr_mask;
+        unsigned int    pvr_value;
+
+        char            *cpu_name;
+        unsigned int    cpu_features;           /* Kernel features */
+        unsigned int    cpu_user_features;      /* Userland features */
+
+        /* cache line sizes */
+        unsigned int    icache_bsize;
+        unsigned int    dcache_bsize;
+
+        /* number of performance monitor counters */
+        unsigned int    num_pmcs;
+
+        /* this is called to initialize various CPU bits like L1 cache,
+         * BHT, SPD, etc... from head.S before branching to identify_machine
+         */
+        cpu_setup_t     cpu_setup;
+};
+
+extern struct cpu_spec          cpu_specs[];
+extern struct cpu_spec          *cur_cpu_spec[];
+
+static inline unsigned int cpu_has_feature(unsigned int feature)
+{
+        return cur_cpu_spec[0]->cpu_features & feature;
+}
+
+#endif /* __ASSEMBLY__ */
+
+/* CPU kernel features */
+#define CPU_FTR_SPLIT_ID_CACHE          0x00000001
+#define CPU_FTR_L2CR                    0x00000002
+#define CPU_FTR_SPEC7450                0x00000004
+#define CPU_FTR_ALTIVEC                 0x00000008
+#define CPU_FTR_TAU                     0x00000010
+#define CPU_FTR_CAN_DOZE                0x00000020
+#define CPU_FTR_USE_TB                  0x00000040
+#define CPU_FTR_604_PERF_MON            0x00000080
+#define CPU_FTR_601                     0x00000100
+#define CPU_FTR_HPTE_TABLE              0x00000200
+#define CPU_FTR_CAN_NAP                 0x00000400
+#define CPU_FTR_L3CR                    0x00000800
+#define CPU_FTR_L3_DISABLE_NAP          0x00001000
+#define CPU_FTR_NAP_DISABLE_L2_PR       0x00002000
+#define CPU_FTR_DUAL_PLL_750FX          0x00004000
+#define CPU_FTR_NO_DPM                  0x00008000
+#define CPU_FTR_HAS_HIGH_BATS           0x00010000
+#define CPU_FTR_NEED_COHERENT           0x00020000
+#define CPU_FTR_NO_BTIC                 0x00040000
+
+#ifdef __ASSEMBLY__
+
+#define BEGIN_FTR_SECTION               98:
+
+#define END_FTR_SECTION(msk, val)               \
+99:                                             \
+        .section __ftr_fixup,"a";               \
+        .align 2;                               \
+        .long msk;                              \
+        .long val;                              \
+        .long 98b;                              \
+        .long 99b;                              \
+        .previous
+
+#else
+
+#define BEGIN_FTR_SECTION               "98:\n"
+#define END_FTR_SECTION(msk, val)               \
+"99:\n"                                         \
+"       .section __ftr_fixup,\"a\";\n"          \
+"       .align 2;\n"                            \
+"       .long "#msk";\n"                        \
+"       .long "#val";\n"                        \
+"       .long 98b;\n"                           \
+"       .long 99b;\n"                           \
+"       .previous\n"
+
+
+#endif /* __ASSEMBLY__ */
+
+#define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
+#define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
+
+#endif /* __ASM_PPC_CPUTABLE_H */
+#endif /* __KERNEL__ */
+
diff --git a/include/asm-ppc/cputime.h b/include/asm-ppc/cputime.h
new file mode 100644
index 000000000000..8e9faf5ce720
--- /dev/null
+++ b/include/asm-ppc/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __PPC_CPUTIME_H
+#define __PPC_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __PPC_CPUTIME_H */
diff --git a/include/asm-ppc/current.h b/include/asm-ppc/current.h
new file mode 100644
index 000000000000..8d41501ba10d
--- /dev/null
+++ b/include/asm-ppc/current.h
@@ -0,0 +1,11 @@
+#ifdef __KERNEL__
+#ifndef _PPC_CURRENT_H
+#define _PPC_CURRENT_H
+
+/*
+ * We keep `current' in r2 for speed.
+ */
+register struct task_struct *current asm ("r2");
+
+#endif /* !(_PPC_CURRENT_H) */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/dbdma.h b/include/asm-ppc/dbdma.h
new file mode 100644
index 000000000000..6047f288c70b
--- /dev/null
+++ b/include/asm-ppc/dbdma.h
@@ -0,0 +1,102 @@
+/*
+ * Definitions for using the Apple Descriptor-Based DMA controller
+ * in Power Macintosh computers.
+ *
+ * Copyright (C) 1996 Paul Mackerras.
+ */
+
+#ifdef __KERNEL__
+#ifndef _ASM_DBDMA_H_
+#define _ASM_DBDMA_H_
+/*
+ * DBDMA control/status registers.  All little-endian.
+ */
+struct dbdma_regs {
+    unsigned int control;       /* lets you change bits in status */
+    unsigned int status;        /* DMA and device status bits (see below) */
+    unsigned int cmdptr_hi;     /* upper 32 bits of command address */
+    unsigned int cmdptr;        /* (lower 32 bits of) command address (phys) */
+    unsigned int intr_sel;      /* select interrupt condition bit */
+    unsigned int br_sel;        /* select branch condition bit */
+    unsigned int wait_sel;      /* select wait condition bit */
+    unsigned int xfer_mode;
+    unsigned int data2ptr_hi;
+    unsigned int data2ptr;
+    unsigned int res1;
+    unsigned int address_hi;
+    unsigned int br_addr_hi;
+    unsigned int res2[3];
+};
+
+/* Bits in control and status registers */
+#define RUN     0x8000
+#define PAUSE   0x4000
+#define FLUSH   0x2000
+#define WAKE    0x1000
+#define DEAD    0x0800
+#define ACTIVE  0x0400
+#define BT      0x0100
+#define DEVSTAT 0x00ff
+
+/*
+ * DBDMA command structure.  These fields are all little-endian!
+ */
+struct dbdma_cmd {
+    unsigned short req_count;   /* requested byte transfer count */
+    unsigned short command;     /* command word (has bit-fields) */
+    unsigned int   phy_addr;    /* physical data address */
+    unsigned int   cmd_dep;     /* command-dependent field */
+    unsigned short res_count;   /* residual count after completion */
+    unsigned short xfer_status; /* transfer status */
+};
+
+/* DBDMA command values in command field */
+#define OUTPUT_MORE     0       /* transfer memory data to stream */
+#define OUTPUT_LAST     0x1000  /* ditto followed by end marker */
+#define INPUT_MORE      0x2000  /* transfer stream data to memory */
+#define INPUT_LAST      0x3000  /* ditto, expect end marker */
+#define STORE_WORD      0x4000  /* write word (4 bytes) to device reg */
+#define LOAD_WORD       0x5000  /* read word (4 bytes) from device reg */
+#define DBDMA_NOP       0x6000  /* do nothing */
+#define DBDMA_STOP      0x7000  /* suspend processing */
+
+/* Key values in command field */
+#define KEY_STREAM0     0       /* usual data stream */
+#define KEY_STREAM1     0x100   /* control/status stream */
+#define KEY_STREAM2     0x200   /* device-dependent stream */
+#define KEY_STREAM3     0x300   /* device-dependent stream */
+#define KEY_REGS        0x500   /* device register space */
+#define KEY_SYSTEM      0x600   /* system memory-mapped space */
+#define KEY_DEVICE      0x700   /* device memory-mapped space */
+
+/* Interrupt control values in command field */
+#define INTR_NEVER      0       /* don't interrupt */
+#define INTR_IFSET      0x10    /* intr if condition bit is 1 */
+#define INTR_IFCLR      0x20    /* intr if condition bit is 0 */
+#define INTR_ALWAYS     0x30    /* always interrupt */
+
+/* Branch control values in command field */
+#define BR_NEVER        0       /* don't branch */
+#define BR_IFSET        0x4     /* branch if condition bit is 1 */
+#define BR_IFCLR        0x8     /* branch if condition bit is 0 */
+#define BR_ALWAYS       0xc     /* always branch */
+
+/* Wait control values in command field */
+#define WAIT_NEVER      0       /* don't wait */
+#define WAIT_IFSET      1       /* wait if condition bit is 1 */
+#define WAIT_IFCLR      2       /* wait if condition bit is 0 */
+#define WAIT_ALWAYS     3       /* always wait */
+
+/* Align an address for a DBDMA command structure */
+#define DBDMA_ALIGN(x)  (((unsigned)(x) + sizeof(struct dbdma_cmd) - 1) \
+                         & -sizeof(struct dbdma_cmd))
+
+/* Useful macros */
+#define DBDMA_DO_STOP(regs) do {                                \
+        out_le32(&((regs)->control), (RUN|FLUSH)<<16);          \
+        while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))      \
+                ;                                               \
+} while(0)
+
+#endif /* _ASM_DBDMA_H_ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h
new file mode 100644
index 000000000000..badde6845af2
--- /dev/null
+++ b/include/asm-ppc/delay.h
@@ -0,0 +1,66 @@
+#ifdef __KERNEL__
+#ifndef _PPC_DELAY_H
+#define _PPC_DELAY_H
+
+#include <asm/param.h>
+
+/*
+ * Copyright 1996, Paul Mackerras.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+extern unsigned long loops_per_jiffy;
+
+extern void __delay(unsigned int loops);
+
+/*
+ * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
+ * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32.
+ *
+ * The mulhwu instruction gives us loops = (a * b) / 2^32.
+ * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
+ * because this lets us support a wide range of HZ and
+ * loops_per_jiffy values without either a or b overflowing 2^32.
+ * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
+ * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
+ * (which corresponds to ~3800 bogomips at HZ = 100).
+ *  -- paulus
+ */
+#define __MAX_UDELAY    (226050910UL/HZ)        /* maximum udelay argument */
+#define __MAX_NDELAY    (4294967295UL/HZ)       /* maximum ndelay argument */
+
+extern __inline__ void __udelay(unsigned int x)
+{
+        unsigned int loops;
+
+        __asm__("mulhwu %0,%1,%2" : "=r" (loops) :
+                "r" (x), "r" (loops_per_jiffy * 226));
+        __delay(loops);
+}
+
+extern __inline__ void __ndelay(unsigned int x)
+{
+        unsigned int loops;
+
+        __asm__("mulhwu %0,%1,%2" : "=r" (loops) :
+                "r" (x), "r" (loops_per_jiffy * 5));
+        __delay(loops);
+}
+
+extern void __bad_udelay(void);         /* deliberately undefined */
+extern void __bad_ndelay(void);         /* deliberately undefined */
+
+#define udelay(n) (__builtin_constant_p(n)? \
+        ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \
+        __udelay((n) * (19 * HZ)))
+
+#define ndelay(n) (__builtin_constant_p(n)? \
+        ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \
+        __ndelay((n) * HZ))
+
+#endif /* defined(_PPC_DELAY_H) */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/div64.h b/include/asm-ppc/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/include/asm-ppc/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
new file mode 100644
index 000000000000..7f0487afebbe
--- /dev/null
+++ b/include/asm-ppc/dma-mapping.h
@@ -0,0 +1,236 @@
+/*
+ * This is based on both include/asm-sh/dma-mapping.h and
+ * include/asm-ppc/pci.h
+ */
+#ifndef __ASM_PPC_DMA_MAPPING_H
+#define __ASM_PPC_DMA_MAPPING_H
+
+#include <linux/config.h>
+/* need struct page definitions */
+#include <linux/mm.h>
+#include <asm/scatterlist.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/*
+ * DMA-consistent mapping functions for PowerPCs that don't support
+ * cache snooping.  These allocate/free a region of uncached mapped
+ * memory space for use with DMA devices.  Alternatively, you could
+ * allocate the space "normally" and use the cache management functions
+ * to ensure it is consistent.
+ */
+extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp);
+extern void __dma_free_coherent(size_t size, void *vaddr);
+extern void __dma_sync(void *vaddr, size_t size, int direction);
+extern void __dma_sync_page(struct page *page, unsigned long offset,
+                                 size_t size, int direction);
+#define dma_cache_inv(_start,_size) \
+        invalidate_dcache_range(_start, (_start + _size))
+#define dma_cache_wback(_start,_size) \
+        clean_dcache_range(_start, (_start + _size))
+#define dma_cache_wback_inv(_start,_size) \
+        flush_dcache_range(_start, (_start + _size))
+
+#else /* ! CONFIG_NOT_COHERENT_CACHE */
+/*
+ * Cache coherent cores.
+ */
+
+#define dma_cache_inv(_start,_size)             do { } while (0)
+#define dma_cache_wback(_start,_size)           do { } while (0)
+#define dma_cache_wback_inv(_start,_size)       do { } while (0)
+
+#define __dma_alloc_coherent(gfp, size, handle) NULL
+#define __dma_free_coherent(size, addr)         do { } while (0)
+#define __dma_sync(addr, size, rw)              do { } while (0)
+#define __dma_sync_page(pg, off, sz, rw)        do { } while (0)
+
+#endif /* ! CONFIG_NOT_COHERENT_CACHE */
+
+#define dma_supported(dev, mask)        (1)
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
+        return 0;
+}
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t * dma_handle, int gfp)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+        return __dma_alloc_coherent(size, dma_handle, gfp);
+#else
+        void *ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+
+        if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
+                gfp |= GFP_DMA;
+
+        ret = (void *)__get_free_pages(gfp, get_order(size));
+
+        if (ret != NULL) {
+                memset(ret, 0, size);
+                *dma_handle = virt_to_bus(ret);
+        }
+
+        return ret;
+#endif
+}
+
+static inline void
+dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+                  dma_addr_t dma_handle)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+        __dma_free_coherent(size, vaddr);
+#else
+        free_pages((unsigned long)vaddr, get_order(size));
+#endif
+}
+
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+               enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync(ptr, size, direction);
+
+        return virt_to_bus(ptr);
+}
+
+/* We do nothing. */
+#define dma_unmap_single(dev, addr, size, dir)  do { } while (0)
+
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size,
+             enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync_page(page, offset, size, direction);
+
+        return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
+}
+
+/* We do nothing. */
+#define dma_unmap_page(dev, handle, size, dir)  do { } while (0)
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+           enum dma_data_direction direction)
+{
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for (i = 0; i < nents; i++, sg++) {
+                BUG_ON(!sg->page);
+                __dma_sync_page(sg->page, sg->offset, sg->length, direction);
+                sg->dma_address = page_to_bus(sg->page) + sg->offset;
+        }
+
+        return nents;
+}
+
+/* We don't do anything here. */
+#define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
+
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                        size_t size,
+                        enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync(bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
+                        size_t size,
+                        enum dma_data_direction direction)
+{
+        BUG_ON(direction == DMA_NONE);
+
+        __dma_sync(bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
+                    enum dma_data_direction direction)
+{
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for (i = 0; i < nents; i++, sg++)
+                __dma_sync_page(sg->page, sg->offset, sg->length, direction);
+}
+
+static inline void
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
+                    enum dma_data_direction direction)
+{
+        int i;
+
+        BUG_ON(direction == DMA_NONE);
+
+        for (i = 0; i < nents; i++, sg++)
+                __dma_sync_page(sg->page, sg->offset, sg->length, direction);
+}
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define dma_is_consistent(d)    (0)
+#else
+#define dma_is_consistent(d)    (1)
+#endif
+
+static inline int dma_get_cache_alignment(void)
+{
+        /*
+         * Each processor family will define its own L1_CACHE_SHIFT,
+         * L1_CACHE_BYTES wraps to this, so this is always safe.
+         */
+        return L1_CACHE_BYTES;
+}
+
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+                              unsigned long offset, size_t size,
+                              enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
+}
+
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
+}
+
+static inline void dma_cache_sync(void *vaddr, size_t size,
+                                  enum dma_data_direction direction)
+{
+        __dma_sync(vaddr, size, (int)direction);
+}
+
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+#endif                          /* __ASM_PPC_DMA_MAPPING_H */
diff --git a/include/asm-ppc/dma.h b/include/asm-ppc/dma.h
new file mode 100644
index 000000000000..cc8e5cd8c9d2
--- /dev/null
+++ b/include/asm-ppc/dma.h
@@ -0,0 +1,371 @@
+/*
+ * include/asm-ppc/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ * Changes for ppc sound by Christoph Nadig
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <asm/io.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
+
+/*
+ * Note: Adapted for PowerPC by Gary Thomas
+ * Modified by Cort Dougan <cort@cs.nmt.edu>
+ *
+ * None of this really applies for Power Macintoshes.  There is
+ * basically just enough here to get kernel/dma.c to compile.
+ *
+ * There may be some comments or restrictions made here which are
+ * not valid for the PReP platform.  Take what you read
+ * with a grain of salt.
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#ifndef MAX_DMA_CHANNELS
+#define MAX_DMA_CHANNELS        8
+#endif
+
+/* The maximum address that we can perform a DMA transfer to on this platform */
+/* Doesn't really apply... */
+#define MAX_DMA_ADDRESS         0xFFFFFFFF
+
+/* in arch/ppc/kernel/setup.c -- Cort */
+extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
+extern unsigned long ISA_DMA_THRESHOLD;
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb        outb_p
+#else
+#define dma_outb        outb
+#endif
+
+#define dma_inb         inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+/* see prep_setup_arch() for detailed informations */
+#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
+extern long ppc_cs4232_dma, ppc_cs4232_dma2;
+#define SND_DMA1 ppc_cs4232_dma
+#define SND_DMA2 ppc_cs4232_dma2
+#else
+#define SND_DMA1 -1
+#define SND_DMA2 -1
+#endif
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            0x08    /* command register (w) */
+#define DMA1_STAT_REG           0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG           0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            0xD0    /* command register (w) */
+#define DMA2_STAT_REG           0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG           0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_LO_PAGE_0           0x87    /* DMA page registers */
+#define DMA_LO_PAGE_1           0x83
+#define DMA_LO_PAGE_2           0x81
+#define DMA_LO_PAGE_3           0x82
+#define DMA_LO_PAGE_5           0x8B
+#define DMA_LO_PAGE_6           0x89
+#define DMA_LO_PAGE_7           0x8A
+
+#define DMA_HI_PAGE_0           0x487   /* DMA page registers */
+#define DMA_HI_PAGE_1           0x483
+#define DMA_HI_PAGE_2           0x481
+#define DMA_HI_PAGE_3           0x482
+#define DMA_HI_PAGE_5           0x48B
+#define DMA_HI_PAGE_6           0x489
+#define DMA_HI_PAGE_7           0x48A
+
+#define DMA1_EXT_REG            0x40B
+#define DMA2_EXT_REG            0x4D6
+
+#define DMA_MODE_CASCADE        0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
+#define DMA_AUTOINIT            0x10
+
+extern spinlock_t dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        unsigned char ucDmaCmd = 0x00;
+
+        if (dmanr != 4) {
+                dma_outb(0, DMA2_MASK_REG);     /* This may not be enabled */
+                dma_outb(ucDmaCmd, DMA2_CMD_REG);       /* Enable group */
+        }
+        if (dmanr <= 3) {
+                dma_outb(dmanr, DMA1_MASK_REG);
+                dma_outb(ucDmaCmd, DMA1_CMD_REG);       /* Enable group */
+        } else
+                dma_outb(dmanr & 3, DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr <= 3)
+                dma_outb(dmanr | 4, DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr <= 3)
+                dma_outb(0, DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0, DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr <= 3)
+                dma_outb(mode | dmanr, DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
+{
+        switch (dmanr) {
+        case 0:
+                dma_outb(pagenr, DMA_LO_PAGE_0);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
+                break;
+        case 1:
+                dma_outb(pagenr, DMA_LO_PAGE_1);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
+                break;
+        case 2:
+                dma_outb(pagenr, DMA_LO_PAGE_2);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
+                break;
+        case 3:
+                dma_outb(pagenr, DMA_LO_PAGE_3);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
+                break;
+        case 5:
+                if (SND_DMA1 == 5 || SND_DMA2 == 5)
+                        dma_outb(pagenr, DMA_LO_PAGE_5);
+                else
+                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
+                break;
+        case 6:
+                if (SND_DMA1 == 6 || SND_DMA2 == 6)
+                        dma_outb(pagenr, DMA_LO_PAGE_6);
+                else
+                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
+                break;
+        case 7:
+                if (SND_DMA1 == 7 || SND_DMA2 == 7)
+                        dma_outb(pagenr, DMA_LO_PAGE_7);
+                else
+                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
+                dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
+                break;
+        }
+}
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
+{
+        if (dmanr <= 3) {
+                dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
+                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
+        } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
+                dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((dmanr & 3), DMA2_EXT_REG);
+        } else {
+                dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+                dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
+        }
+        set_dma_page(dmanr, phys >> 16);
+}
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3) {
+                dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
+                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
+                         IO_DMA1_BASE);
+        } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
+                dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
+                dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
+                         IO_DMA2_BASE);
+        } else {
+                dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
+                         IO_DMA2_BASE);
+                dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
+                         IO_DMA2_BASE);
+        }
+}
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr <= 3) ?
+            ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
+            : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
+            ? count : (count << 1);
+
+}
+
+/* These are in kernel/dma.c: */
+
+/* reserve a DMA channel */
+extern int request_dma(unsigned int dmanr, const char *device_id);
+/* release it again */
+extern void free_dma(unsigned int dmanr);
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+#endif                          /* _ASM_DMA_H */
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
new file mode 100644
index 000000000000..2c056966efd3
--- /dev/null
+++ b/include/asm-ppc/elf.h
@@ -0,0 +1,160 @@
+#ifndef __PPC_ELF_H
+#define __PPC_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/cputable.h>
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE              0
+#define R_PPC_ADDR32            1       /* 32bit absolute address */
+#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16            3       /* 16bit absolute address */
+#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
+#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN    8
+#define R_PPC_ADDR14_BRNTAKEN   9
+#define R_PPC_REL24             10      /* PC relative 26 bit */
+#define R_PPC_REL14             11      /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN     12
+#define R_PPC_REL14_BRNTAKEN    13
+#define R_PPC_GOT16             14
+#define R_PPC_GOT16_LO          15
+#define R_PPC_GOT16_HI          16
+#define R_PPC_GOT16_HA          17
+#define R_PPC_PLTREL24          18
+#define R_PPC_COPY              19
+#define R_PPC_GLOB_DAT          20
+#define R_PPC_JMP_SLOT          21
+#define R_PPC_RELATIVE          22
+#define R_PPC_LOCAL24PC         23
+#define R_PPC_UADDR32           24
+#define R_PPC_UADDR16           25
+#define R_PPC_REL32             26
+#define R_PPC_PLT32             27
+#define R_PPC_PLTREL32          28
+#define R_PPC_PLT16_LO          29
+#define R_PPC_PLT16_HI          30
+#define R_PPC_PLT16_HA          31
+#define R_PPC_SDAREL16          32
+#define R_PPC_SECTOFF           33
+#define R_PPC_SECTOFF_LO        34
+#define R_PPC_SECTOFF_HI        35
+#define R_PPC_SECTOFF_HA        36
+/* Keep this the last entry.  */
+#define R_PPC_NUM               37
+
+#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
+#define ELF_NFPREG      33      /* includes fpscr */
+#define ELF_NVRREG      33      /* includes vscr */
+#define ELF_NEVRREG     34      /* includes acc (as 2) */
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_ARCH        EM_PPC
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2MSB
+
+/* General registers */
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Floating point registers */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+/* Altivec registers */
+typedef __vector128 elf_vrreg_t;
+typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+
+#ifdef __KERNEL__
+
+struct task_struct;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+
+#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         (0x08000000)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
+
+#define ELF_CORE_COPY_REGS(gregs, regs)                         \
+        memcpy((gregs), (regs), sizeof(struct pt_regs));        \
+        memset((char *)(gregs) + sizeof(struct pt_regs), 0,     \
+               sizeof(elf_gregset_t) - sizeof(struct pt_regs));
+
+#define ELF_CORE_COPY_TASK_REGS(t, elfregs)                     \
+        ((t)->thread.regs?                                      \
+         ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
+
+extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
+#define ELF_CORE_COPY_FPREGS(t, fpu)    dump_task_fpu((t), (fpu))
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This could be done in userspace,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (cur_cpu_spec[0]->cpu_user_features)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM    (NULL)
+
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+
+/*
+ * We need to put in some extra aux table entries to tell glibc what
+ * the cache block size is, so it can use the dcbz instruction safely.
+ */
+#define AT_DCACHEBSIZE          19
+#define AT_ICACHEBSIZE          20
+#define AT_UCACHEBSIZE          21
+/* A special ignored type value for PPC, for glibc compatibility.  */
+#define AT_IGNOREPPC            22
+
+extern int dcache_bsize;
+extern int icache_bsize;
+extern int ucache_bsize;
+
+/*
+ * The requirements here are:
+ * - keep the final alignment of sp (sp & 0xf)
+ * - make sure the 32-bit value at the first 16 byte aligned position of
+ *   AUXV is greater than 16 for glibc compatibility.
+ *   AT_IGNOREPPC is used for that.
+ * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
+ *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
+ */
+#define ARCH_DLINFO                                                     \
+do {                                                                    \
+        /* Handle glibc compatibility. */                               \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        /* Cache size items */                                          \
+        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
+        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
+        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
+ } while (0)
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h
new file mode 100644
index 000000000000..19f20bd41ae6
--- /dev/null
+++ b/include/asm-ppc/errno.h
@@ -0,0 +1,11 @@
+#ifndef _PPC_ERRNO_H
+#define _PPC_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#undef  EDEADLOCK
+#define EDEADLOCK       58      /* File locking deadlock error */
+
+#define _LAST_ERRNO     516
+
+#endif
diff --git a/include/asm-ppc/fcntl.h b/include/asm-ppc/fcntl.h
new file mode 100644
index 000000000000..5e28e41fb29f
--- /dev/null
+++ b/include/asm-ppc/fcntl.h
@@ -0,0 +1,93 @@
+#ifndef _PPC_FCNTL_H
+#define _PPC_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_ACCMODE          0003
+#define O_RDONLY             00
+#define O_WRONLY             01
+#define O_RDWR               02
+#define O_CREAT            0100 /* not fcntl */
+#define O_EXCL             0200 /* not fcntl */
+#define O_NOCTTY           0400 /* not fcntl */
+#define O_TRUNC           01000 /* not fcntl */
+#define O_APPEND          02000
+#define O_NONBLOCK        04000
+#define O_NDELAY        O_NONBLOCK
+#define O_SYNC           010000
+#define FASYNC           020000 /* fcntl, for BSD compatibility */
+#define O_DIRECTORY      040000 /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_LARGEFILE     0200000
+#define O_DIRECT        0400000 /* direct disk access hint */
+#define O_NOATIME       01000000
+
+#define F_DUPFD         0       /* dup */
+#define F_GETFD         1       /* get close_on_exec */
+#define F_SETFD         2       /* set/clear close_on_exec */
+#define F_GETFL         3       /* get file->f_flags */
+#define F_SETFL         4       /* set file->f_flags */
+#define F_GETLK         5
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        8       /*  for sockets. */
+#define F_GETOWN        9       /*  for sockets. */
+#define F_SETSIG        10      /*  for sockets. */
+#define F_GETSIG        11      /*  for sockets. */
+
+#define F_GETLK64       12      /*  using 'struct flock64' */
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         0
+#define F_WRLCK         1
+#define F_UNLCK         2
+
+/* for old implementation of bsd flock () */
+#define F_EXLCK         4       /* or 3 */
+#define F_SHLCK         8       /* or 4 */
+
+/* for leases */
+#define F_INPROGRESS    16
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH         1       /* shared lock */
+#define LOCK_EX         2       /* exclusive lock */
+#define LOCK_NB         4       /* or'd with one of the above to prevent
+                                   blocking */
+#define LOCK_UN         8       /* remove lock */
+
+#define LOCK_MAND       32      /* This is a mandatory flock */
+#define LOCK_READ       64      /* ... Which allows concurrent read operations */
+#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
+#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
+
+#ifdef __KERNEL__
+#define F_POSIX         1
+#define F_FLOCK         2
+#define F_BROKEN        4       /* broken flock() emulation */
+#endif /* __KERNEL__ */
+
+struct flock {
+        short l_type;
+        short l_whence;
+        off_t l_start;
+        off_t l_len;
+        pid_t l_pid;
+};
+
+struct flock64 {
+        short  l_type;
+        short  l_whence;
+        loff_t l_start;
+        loff_t l_len;
+        pid_t  l_pid;
+};
+
+#define F_LINUX_SPECIFIC_BASE   1024
+#endif
diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h
new file mode 100644
index 000000000000..8ccd4a276fe9
--- /dev/null
+++ b/include/asm-ppc/floppy.h
@@ -0,0 +1,182 @@
+/*
+ * Architecture specific parts of the Floppy driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_FLOPPY_H
+#define __ASM_PPC_FLOPPY_H
+
+#define fd_inb(port)            inb_p(port)
+#define fd_outb(value,port)     outb_p(value,port)
+
+#define fd_disable_dma()        fd_ops->_disable_dma(FLOPPY_DMA)
+#define fd_free_dma()           fd_ops->_free_dma(FLOPPY_DMA)
+#define fd_get_dma_residue()    fd_ops->_get_dma_residue(FLOPPY_DMA)
+#define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io)
+#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
+#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
+#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+
+static int fd_request_dma(void);
+
+struct fd_dma_ops {
+        void (*_disable_dma)(unsigned int dmanr);
+        void (*_free_dma)(unsigned int dmanr);
+        int (*_get_dma_residue)(unsigned int dummy);
+        int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
+};
+
+static int virtual_dma_count;
+static int virtual_dma_residue;
+static char *virtual_dma_addr;
+static int virtual_dma_mode;
+static int doing_vdma;
+static struct fd_dma_ops *fd_ops;
+
+static irqreturn_t floppy_hardint(int irq, void *dev_id, struct pt_regs * regs)
+{
+        unsigned char st;
+        int lcount;
+        char *lptr;
+
+        if (!doing_vdma)
+                return floppy_interrupt(irq, dev_id, regs);
+
+
+        st = 1;
+        for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
+             lcount; lcount--, lptr++) {
+                st=inb(virtual_dma_port+4) & 0xa0 ;
+                if (st != 0xa0)
+                        break;
+                if (virtual_dma_mode)
+                        outb_p(*lptr, virtual_dma_port+5);
+                else
+                        *lptr = inb_p(virtual_dma_port+5);
+        }
+        virtual_dma_count = lcount;
+        virtual_dma_addr = lptr;
+        st = inb(virtual_dma_port+4);
+
+        if (st == 0x20)
+                return IRQ_HANDLED;
+        if (!(st & 0x20)) {
+                virtual_dma_residue += virtual_dma_count;
+                virtual_dma_count=0;
+                doing_vdma = 0;
+                floppy_interrupt(irq, dev_id, regs);
+                return IRQ_HANDLED;
+        }
+        return IRQ_HANDLED;
+}
+
+static void vdma_disable_dma(unsigned int dummy)
+{
+        doing_vdma = 0;
+        virtual_dma_residue += virtual_dma_count;
+        virtual_dma_count=0;
+}
+
+static void vdma_nop(unsigned int dummy)
+{
+}
+
+
+static int vdma_get_dma_residue(unsigned int dummy)
+{
+        return virtual_dma_count + virtual_dma_residue;
+}
+
+
+static int fd_request_irq(void)
+{
+        if (can_use_virtual_dma)
+                return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT,
+                                                   "floppy", NULL);
+        else
+                return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                                                   SA_INTERRUPT|SA_SAMPLE_RANDOM,
+                                                   "floppy", NULL);
+
+}
+
+static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+        doing_vdma = 1;
+        virtual_dma_port = io;
+        virtual_dma_mode = (mode  == DMA_MODE_WRITE);
+        virtual_dma_addr = addr;
+        virtual_dma_count = size;
+        virtual_dma_residue = 0;
+        return 0;
+}
+
+static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+        /* actual, physical DMA */
+        doing_vdma = 0;
+        clear_dma_ff(FLOPPY_DMA);
+        set_dma_mode(FLOPPY_DMA,mode);
+        set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr));
+        set_dma_count(FLOPPY_DMA,size);
+        enable_dma(FLOPPY_DMA);
+        return 0;
+}
+
+static struct fd_dma_ops real_dma_ops =
+{
+        ._disable_dma = disable_dma,
+        ._free_dma = free_dma,
+        ._get_dma_residue = get_dma_residue,
+        ._dma_setup = hard_dma_setup
+};
+
+static struct fd_dma_ops virt_dma_ops =
+{
+        ._disable_dma = vdma_disable_dma,
+        ._free_dma = vdma_nop,
+        ._get_dma_residue = vdma_get_dma_residue,
+        ._dma_setup = vdma_dma_setup
+};
+
+static int fd_request_dma()
+{
+        if (can_use_virtual_dma & 1) {
+                fd_ops = &virt_dma_ops;
+                return 0;
+        }
+        else {
+                fd_ops = &real_dma_ops;
+                return request_dma(FLOPPY_DMA, "floppy");
+        }
+}
+
+static int FDC1 = 0x3f0;
+static int FDC2 = -1;
+
+/*
+ * Again, the CMOS information not available
+ */
+#define FLOPPY0_TYPE 6
+#define FLOPPY1_TYPE 0
+
+#define N_FDC 2                 /* Don't change this! */
+#define N_DRIVE 8
+
+#define FLOPPY_MOTOR_MASK 0xf0
+
+/*
+ * The PowerPC has no problems with floppy DMA crossing 64k borders.
+ */
+#define CROSS_64KB(a,s) (0)
+
+#endif /* __ASM_PPC_FLOPPY_H */
+
+#define EXTRA_FLOPPY_PARAMS
+
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/fsl_ocp.h b/include/asm-ppc/fsl_ocp.h
new file mode 100644
index 000000000000..050fbba8d049
--- /dev/null
+++ b/include/asm-ppc/fsl_ocp.h
@@ -0,0 +1,54 @@
+/*
+ * include/asm-ppc/fsl_ocp.h
+ *
+ * Definitions for the on-chip peripherals on Freescale PPC processors
+ *
+ * Maintainer: Kumar Gala (kumar.gala@freescale.com)
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_FS_OCP_H__
+#define __ASM_FS_OCP_H__
+
+/* A table of information for supporting the Gianfar Ethernet Controller
+ * This helps identify which enet controller we are dealing with,
+ * and what type of enet controller it is
+ */
+struct ocp_gfar_data {
+        uint interruptTransmit;
+        uint interruptError;
+        uint interruptReceive;
+        uint interruptPHY;
+        uint flags;
+        uint phyid;
+        uint phyregidx;
+        unsigned char mac_addr[6];
+};
+
+/* Flags in the flags field */
+#define GFAR_HAS_COALESCE               0x20
+#define GFAR_HAS_RMON                   0x10
+#define GFAR_HAS_MULTI_INTR             0x08
+#define GFAR_FIRM_SET_MACADDR           0x04
+#define GFAR_HAS_PHY_INTR               0x02    /* if not set use a timer */
+#define GFAR_HAS_GIGABIT                0x01
+
+/* Data structure for I2C support.  Just contains a couple flags
+ * to distinguish various I2C implementations*/
+struct ocp_fs_i2c_data {
+        uint flags;
+};
+
+/* Flags for I2C */
+#define FS_I2C_SEPARATE_DFSRR   0x02
+#define FS_I2C_CLOCK_5200       0x01
+
+#endif  /* __ASM_FS_OCP_H__ */
+#endif  /* __KERNEL__ */
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h
new file mode 100644
index 000000000000..341ae55b99fb
--- /dev/null
+++ b/include/asm-ppc/gg2.h
@@ -0,0 +1,61 @@
+/*
+ *  include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
+ *
+ *  Copyright (C) 1997 Geert Uytterhoeven
+ *
+ *  This file is based on the following documentation:
+ *
+ *      The VAS96011/12 Chipset, Data Book, Edition 1.0
+ *      VLSI Technology, Inc.
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License.  See the file COPYING in the main directory of this archive
+ *  for more details.
+ */
+
+#ifndef _ASMPPC_GG2_H
+#define _ASMPPC_GG2_H
+
+    /*
+     *  Memory Map (CHRP mode)
+     */
+
+#define GG2_PCI_MEM_BASE        0xc0000000      /* Peripheral memory space */
+#define GG2_ISA_MEM_BASE        0xf7000000      /* Peripheral memory alias */
+#define GG2_ISA_IO_BASE         0xf8000000      /* Peripheral I/O space */
+#define GG2_PCI_CONFIG_BASE     0xfec00000      /* PCI configuration space */
+#define GG2_INT_ACK_SPECIAL     0xfec80000      /* Interrupt acknowledge and */
+                                                /* special PCI cycles */
+#define GG2_ROM_BASE0           0xff000000      /* ROM bank 0 */
+#define GG2_ROM_BASE1           0xff800000      /* ROM bank 1 */
+
+
+    /*
+     *  GG2 specific PCI Registers
+     */
+
+extern void __iomem *gg2_pci_config_base;       /* kernel virtual address */
+
+#define GG2_PCI_BUSNO           0x40    /* Bus number */
+#define GG2_PCI_SUBBUSNO        0x41    /* Subordinate bus number */
+#define GG2_PCI_DISCCTR         0x42    /* Disconnect counter */
+#define GG2_PCI_PPC_CTRL        0x50    /* PowerPC interface control register */
+#define GG2_PCI_ADDR_MAP        0x5c    /* Address map */
+#define GG2_PCI_PCI_CTRL        0x60    /* PCI interface control register */
+#define GG2_PCI_ROM_CTRL        0x70    /* ROM interface control register */
+#define GG2_PCI_ROM_TIME        0x74    /* ROM timing */
+#define GG2_PCI_CC_CTRL         0x80    /* Cache controller control register */
+#define GG2_PCI_DRAM_BANK0      0x90    /* Control register for DRAM bank #0 */
+#define GG2_PCI_DRAM_BANK1      0x94    /* Control register for DRAM bank #1 */
+#define GG2_PCI_DRAM_BANK2      0x98    /* Control register for DRAM bank #2 */
+#define GG2_PCI_DRAM_BANK3      0x9c    /* Control register for DRAM bank #3 */
+#define GG2_PCI_DRAM_BANK4      0xa0    /* Control register for DRAM bank #4 */
+#define GG2_PCI_DRAM_BANK5      0xa4    /* Control register for DRAM bank #5 */
+#define GG2_PCI_DRAM_TIME0      0xb0    /* Timing parameters set #0 */
+#define GG2_PCI_DRAM_TIME1      0xb4    /* Timing parameters set #1 */
+#define GG2_PCI_DRAM_CTRL       0xc0    /* DRAM control */
+#define GG2_PCI_ERR_CTRL        0xd0    /* Error control register */
+#define GG2_PCI_ERR_STATUS      0xd4    /* Error status register */
+                                        /* Cleared when read */
+
+#endif /* _ASMPPC_GG2_H */
diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h
new file mode 100644
index 000000000000..cd0ef644943d
--- /dev/null
+++ b/include/asm-ppc/gt64260.h
@@ -0,0 +1,322 @@
+/*
+ * include/asm-ppc/gt64260.h
+ *
+ * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASMPPC_GT64260_H
+#define __ASMPPC_GT64260_H
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/gt64260_defs.h>
+
+
+extern u32     gt64260_base;
+extern u32     gt64260_irq_base;     /* We handle the next 96 IRQs from here */
+extern u32     gt64260_revision;
+extern u8      gt64260_pci_exclude_bridge;
+
+#ifndef TRUE
+#define TRUE    1
+#endif
+
+#ifndef FALSE
+#define FALSE   0
+#endif
+
+/* IRQs defined by the 64260 */
+#define GT64260_IRQ_MPSC0               40
+#define GT64260_IRQ_MPSC1               42
+#define GT64260_IRQ_SDMA                36
+
+/*
+ * Define a default physical memory map to be set up on the bridge.
+ * Also define a struct to pass that info from board-specific routines to
+ * GT64260 generic set up routines.  By passing this info in, the board
+ * support developer can modify it at will.
+ */
+
+/*
+ * This is the default memory map:
+ *                      CPU                     PCI
+ *                      ---                     ---
+ * PCI 0 I/O:   0xfa000000-0xfaffffff   0x00000000-0x00ffffff
+ * PCI 1 I/O:   0xfb000000-0xfbffffff   0x01000000-0x01ffffff
+ * PCI 0 MEM:   0x80000000-0x8fffffff   0x80000000-0x8fffffff
+ * PCI 1 MEM:   0x90000000-0x9fffffff   0x90000000-0x9fffffff
+ */
+
+/* Default physical memory map for the GT64260 bridge */
+
+/*
+ * PCI Bus 0 Definitions
+ */
+#define GT64260_PCI_0_IO_SIZE           0x01000000U
+#define GT64260_PCI_0_MEM_SIZE          0x10000000U
+
+/* Processor Physical addresses */
+#define GT64260_PCI_0_IO_START_PROC     0xfa000000U
+#define GT64260_PCI_0_IO_END_PROC       (GT64260_PCI_0_IO_START_PROC + \
+                                         GT64260_PCI_0_IO_SIZE - 1)
+
+/* PCI 0 addresses */
+#define GT64260_PCI_0_IO_START          0x00000000U
+#define GT64260_PCI_0_IO_END            (GT64260_PCI_0_IO_START + \
+                                         GT64260_PCI_0_IO_SIZE - 1)
+
+/* Processor Physical addresses */
+#define GT64260_PCI_0_MEM_START_PROC    0x80000000U
+#define GT64260_PCI_0_MEM_END_PROC      (GT64260_PCI_0_MEM_START_PROC + \
+                                         GT64260_PCI_0_MEM_SIZE - 1)
+
+/* PCI 0 addresses */
+#define GT64260_PCI_0_MEM_START         0x80000000U
+#define GT64260_PCI_0_MEM_END           (GT64260_PCI_0_MEM_START + \
+                                         GT64260_PCI_0_MEM_SIZE - 1)
+
+/*
+ * PCI Bus 1 Definitions
+ */
+#define GT64260_PCI_1_IO_SIZE           0x01000000U
+#define GT64260_PCI_1_MEM_SIZE          0x10000000U
+
+/* PCI 1 addresses */
+#define GT64260_PCI_1_IO_START          0x01000000U
+#define GT64260_PCI_1_IO_END            (GT64260_PCI_1_IO_START + \
+                                         GT64260_PCI_1_IO_SIZE - 1)
+
+/* Processor Physical addresses */
+#define GT64260_PCI_1_IO_START_PROC     0xfb000000U
+#define GT64260_PCI_1_IO_END_PROC       (GT64260_PCI_1_IO_START_PROC + \
+                                         GT64260_PCI_1_IO_SIZE - 1)
+
+/* PCI 1 addresses */
+#define GT64260_PCI_1_MEM_START         0x90000000U
+#define GT64260_PCI_1_MEM_END           (GT64260_PCI_1_MEM_START + \
+                                         GT64260_PCI_1_MEM_SIZE - 1)
+
+/* Processor Physical addresses */
+#define GT64260_PCI_1_MEM_START_PROC    0x90000000U
+#define GT64260_PCI_1_MEM_END_PROC      (GT64260_PCI_1_MEM_START_PROC + \
+                                         GT64260_PCI_1_MEM_SIZE - 1)
+
+/* Define struct to pass mem-map info into gt64260_common.c code */
+typedef struct {
+        struct pci_controller   *hose_a;
+        struct pci_controller   *hose_b;
+
+        u32     mem_size;
+
+        u32     pci_0_io_start_proc;
+        u32     pci_0_io_start_pci;
+        u32     pci_0_io_size;
+        u32     pci_0_io_swap;
+
+        u32     pci_0_mem_start_proc;
+        u32     pci_0_mem_start_pci_hi;
+        u32     pci_0_mem_start_pci_lo;
+        u32     pci_0_mem_size;
+        u32     pci_0_mem_swap;
+
+        u32     pci_1_io_start_proc;
+        u32     pci_1_io_start_pci;
+        u32     pci_1_io_size;
+        u32     pci_1_io_swap;
+
+        u32     pci_1_mem_start_proc;
+        u32     pci_1_mem_start_pci_hi;
+        u32     pci_1_mem_start_pci_lo;
+        u32     pci_1_mem_size;
+        u32     pci_1_mem_swap;
+} gt64260_bridge_info_t;
+
+#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) {                           \
+        (ip)->mem_size = (ms);                                          \
+                                                                        \
+        (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC;        \
+        (ip)->pci_0_io_start_pci  = GT64260_PCI_0_IO_START;             \
+        (ip)->pci_0_io_size       = GT64260_PCI_0_IO_SIZE;              \
+        (ip)->pci_0_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
+                                                                        \
+        (ip)->pci_0_mem_start_proc   = GT64260_PCI_0_MEM_START_PROC;    \
+        (ip)->pci_0_mem_start_pci_hi = 0x00000000;                      \
+        (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START;         \
+        (ip)->pci_0_mem_size         = GT64260_PCI_0_MEM_SIZE;          \
+        (ip)->pci_0_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
+                                                                        \
+        (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC;        \
+        (ip)->pci_1_io_start_pci  = GT64260_PCI_1_IO_START;             \
+        (ip)->pci_1_io_size       = GT64260_PCI_1_IO_SIZE;              \
+        (ip)->pci_1_io_swap       = GT64260_CPU_PCI_SWAP_NONE;          \
+                                                                        \
+        (ip)->pci_1_mem_start_proc   = GT64260_PCI_1_MEM_START_PROC;    \
+        (ip)->pci_1_mem_start_pci_hi = 0x00000000;                      \
+        (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START;         \
+        (ip)->pci_1_mem_size         = GT64260_PCI_1_MEM_SIZE;          \
+        (ip)->pci_1_mem_swap         = GT64260_CPU_PCI_SWAP_NONE;       \
+}
+
+/*
+ *****************************************************************************
+ *
+ *      I/O macros to access the 64260's registers
+ *
+ *****************************************************************************
+ */
+
+extern inline uint32_t gt_read(uint32_t offs){
+        return (in_le32((volatile uint *)(gt64260_base + offs)));
+}
+extern inline void gt_write(uint32_t offs, uint32_t d){
+        out_le32((volatile uint *)(gt64260_base + offs), d);
+}
+
+#if 0 /* paranoid SMP version */
+extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
+{
+        uint32_t reg;
+        spin_lock(&gt64260_lock);
+        reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
+        reg |= data & mask; /* set bits from the data */
+        gt_write(offs, reg);
+        spin_unlock(&gt64260_lock);
+}
+#else
+extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
+{
+        uint32_t reg;
+        reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
+        reg |= (data) & (mask); /* set bits from the data */
+        gt_write(offs, reg);
+}
+#endif
+#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
+
+#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
+
+
+/*
+ *****************************************************************************
+ *
+ *      Function Prototypes
+ *
+ *****************************************************************************
+ */
+
+int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
+        int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
+int gt64260_bridge_init(gt64260_bridge_info_t *info);
+int gt64260_cpu_scs_set_window(u32 window,
+                               u32 base_addr,
+                               u32 size);
+int gt64260_cpu_cs_set_window(u32 window,
+                              u32 base_addr,
+                              u32 size);
+int gt64260_cpu_boot_set_window(u32 base_addr,
+                                u32 size);
+int gt64260_cpu_set_pci_io_window(u32 pci_bus,
+                                  u32 cpu_base_addr,
+                                  u32 pci_base_addr,
+                                  u32 size,
+                                  u32 swap);
+int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
+                                   u32 window,
+                                   u32 cpu_base_addr,
+                                   u32 pci_base_addr_hi,
+                                   u32 pci_base_addr_lo,
+                                   u32 size,
+                                   u32 swap_64bit);
+int gt64260_cpu_prot_set_window(u32 window,
+                                u32 base_addr,
+                                u32 size,
+                                u32 access_bits);
+int gt64260_cpu_snoop_set_window(u32 window,
+                                 u32 base_addr,
+                                 u32 size,
+                                 u32  snoop_type);
+void gt64260_cpu_disable_all_windows(void);
+int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
+int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
+                                     u32 window,
+                                     u32 pci_base_addr,
+                                     u32 cpu_base_addr,
+                                     u32 size);
+int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
+                                    u32 window,
+                                    u32 pci_base_addr,
+                                    u32 cpu_base_addr,
+                                    u32 size);
+int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
+                                      u32 pci_base_addr,
+                                      u32 cpu_base_addr,
+                                      u32 size);
+int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
+                                         u32 window,
+                                         u32 pci_base_addr,
+                                         u32 other_bus_base_addr,
+                                         u32 size);
+int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
+                                        u32 pci_base_addr,
+                                        u32 other_bus_base_addr,
+                                        u32 size);
+int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
+                                         u32 window,
+                                         u32 pci_base_addr_hi,
+                                         u32 pci_base_addr_lo,
+                                         u32 cpu_base_addr,
+                                         u32 size);
+int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
+                                        u32 window,
+                                        u32 pci_base_addr_hi,
+                                        u32 pci_base_addr_lo,
+                                        u32 cpu_base_addr,
+                                        u32 size);
+int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
+                                          u32 pci_base_addr_hi,
+                                          u32 pci_base_addr_lo,
+                                          u32 cpu_base_addr,
+                                          u32 size);
+int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
+                                             u32 window,
+                                             u32 pci_base_addr_hi,
+                                             u32 pci_base_addr_lo,
+                                             u32 other_bus_base_addr,
+                                             u32 size);
+int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
+                                    u32 window,
+                                    u32 base_addr_hi,
+                                    u32 base_addr_lo,
+                                    u32 size,
+                                    u32 features);
+int gt64260_pci_snoop_set_window(u32 pci_bus,
+                                 u32 window,
+                                 u32 base_addr_hi,
+                                 u32 base_addr_lo,
+                                 u32 size,
+                                 u32 snoop_type);
+int gt64260_set_base(u32 new_base);
+int gt64260_get_base(u32 *base);
+int gt64260_pci_exclude_device(u8 bus, u8 devfn);
+
+void gt64260_init_irq(void);
+int gt64260_get_irq(struct pt_regs *regs);
+
+void gt64260_mpsc_progress(char *s, unsigned short hex);
+
+#endif /* __ASMPPC_GT64260_H */
diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h
new file mode 100644
index 000000000000..6ffd01a5373e
--- /dev/null
+++ b/include/asm-ppc/gt64260_defs.h
@@ -0,0 +1,1010 @@
+/*
+ * include/asm-ppc/gt64260_defs.h
+ *
+ * Register definitions for the Marvell/Galileo GT64260 host bridge.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASMPPC_GT64260_DEFS_H
+#define __ASMPPC_GT64260_DEFS_H
+
+/*
+ * Define a macro to represent the supported version of the 64260.
+ */
+#define GT64260                 0x01
+#define GT64260A                0x10
+
+/*
+ *****************************************************************************
+ *
+ *      CPU Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* CPU physical address of 64260's registers */
+#define GT64260_INTERNAL_SPACE_DECODE                   0x0068
+#define GT64260_INTERNAL_SPACE_SIZE                     0x10000
+#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR             0x14000000
+
+/* CPU Memory Controller Window Registers (4 windows) */
+#define GT64260_CPU_SCS_DECODE_WINDOWS                  4
+
+#define GT64260_CPU_SCS_DECODE_0_BOT                    0x0008
+#define GT64260_CPU_SCS_DECODE_0_TOP                    0x0010
+#define GT64260_CPU_SCS_DECODE_1_BOT                    0x0208
+#define GT64260_CPU_SCS_DECODE_1_TOP                    0x0210
+#define GT64260_CPU_SCS_DECODE_2_BOT                    0x0018
+#define GT64260_CPU_SCS_DECODE_2_TOP                    0x0020
+#define GT64260_CPU_SCS_DECODE_3_BOT                    0x0218
+#define GT64260_CPU_SCS_DECODE_3_TOP                    0x0220
+
+/* CPU Device Controller Window Registers (4 windows) */
+#define GT64260_CPU_CS_DECODE_WINDOWS                   4
+
+#define GT64260_CPU_CS_DECODE_0_BOT                     0x0028
+#define GT64260_CPU_CS_DECODE_0_TOP                     0x0030
+#define GT64260_CPU_CS_DECODE_1_BOT                     0x0228
+#define GT64260_CPU_CS_DECODE_1_TOP                     0x0230
+#define GT64260_CPU_CS_DECODE_2_BOT                     0x0248
+#define GT64260_CPU_CS_DECODE_2_TOP                     0x0250
+#define GT64260_CPU_CS_DECODE_3_BOT                     0x0038
+#define GT64260_CPU_CS_DECODE_3_TOP                     0x0040
+
+#define GT64260_CPU_BOOT_CS_DECODE_0_BOT                0x0238
+#define GT64260_CPU_BOOT_CS_DECODE_0_TOP                0x0240
+
+/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
+#define GT64260_PCI_BUSES                               2
+#define GT64260_PCI_IO_WINDOWS_PER_BUS                  1
+#define GT64260_PCI_MEM_WINDOWS_PER_BUS                 4
+
+#define GT64260_CPU_PCI_SWAP_BYTE                       0x00000000
+#define GT64260_CPU_PCI_SWAP_NONE                       0x01000000
+#define GT64260_CPU_PCI_SWAP_BYTE_WORD                  0x02000000
+#define GT64260_CPU_PCI_SWAP_WORD                       0x03000000
+#define GT64260_CPU_PCI_SWAP_MASK                       0x07000000
+
+#define GT64260_CPU_PCI_MEM_REQ64                       (1<<27)
+
+#define GT64260_CPU_PCI_0_IO_DECODE_BOT                 0x0048
+#define GT64260_CPU_PCI_0_IO_DECODE_TOP                 0x0050
+#define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT              0x0058
+#define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP              0x0060
+#define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT              0x0080
+#define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP              0x0088
+#define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT              0x0258
+#define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP              0x0260
+#define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT              0x0280
+#define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP              0x0288
+
+#define GT64260_CPU_PCI_0_IO_REMAP                      0x00f0
+#define GT64260_CPU_PCI_0_MEM_0_REMAP_LO                0x00f8
+#define GT64260_CPU_PCI_0_MEM_0_REMAP_HI                0x0320
+#define GT64260_CPU_PCI_0_MEM_1_REMAP_LO                0x0100
+#define GT64260_CPU_PCI_0_MEM_1_REMAP_HI                0x0328
+#define GT64260_CPU_PCI_0_MEM_2_REMAP_LO                0x02f8
+#define GT64260_CPU_PCI_0_MEM_2_REMAP_HI                0x0330
+#define GT64260_CPU_PCI_0_MEM_3_REMAP_LO                0x0300
+#define GT64260_CPU_PCI_0_MEM_3_REMAP_HI                0x0338
+
+#define GT64260_CPU_PCI_1_IO_DECODE_BOT                 0x0090
+#define GT64260_CPU_PCI_1_IO_DECODE_TOP                 0x0098
+#define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT              0x00a0
+#define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP              0x00a8
+#define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT              0x00b0
+#define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP              0x00b8
+#define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT              0x02a0
+#define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP              0x02a8
+#define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT              0x02b0
+#define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP              0x02b8
+
+#define GT64260_CPU_PCI_1_IO_REMAP                      0x0108
+#define GT64260_CPU_PCI_1_MEM_0_REMAP_LO                0x0110
+#define GT64260_CPU_PCI_1_MEM_0_REMAP_HI                0x0340
+#define GT64260_CPU_PCI_1_MEM_1_REMAP_LO                0x0118
+#define GT64260_CPU_PCI_1_MEM_1_REMAP_HI                0x0348
+#define GT64260_CPU_PCI_1_MEM_2_REMAP_LO                0x0310
+#define GT64260_CPU_PCI_1_MEM_2_REMAP_HI                0x0350
+#define GT64260_CPU_PCI_1_MEM_3_REMAP_LO                0x0318
+#define GT64260_CPU_PCI_1_MEM_3_REMAP_HI                0x0358
+
+/* CPU Control Registers */
+#define GT64260_CPU_CONFIG                              0x0000
+#define GT64260_CPU_MODE                                0x0120
+#define GT64260_CPU_MASTER_CNTL                         0x0160
+#define GT64260_CPU_XBAR_CNTL_LO                        0x0150
+#define GT64260_CPU_XBAR_CNTL_HI                        0x0158
+#define GT64260_CPU_XBAR_TO                             0x0168
+#define GT64260_CPU_RR_XBAR_CNTL_LO                     0x0170
+#define GT64260_CPU_RR_XBAR_CNTL_HI                     0x0178
+
+/* CPU Sync Barrier Registers */
+#define GT64260_CPU_SYNC_BARRIER_PCI_0                  0x00c0
+#define GT64260_CPU_SYNC_BARRIER_PCI_1                  0x00c8
+
+/* CPU Access Protection Registers */
+#define GT64260_CPU_PROT_WINDOWS                        8
+
+#define GT64260_CPU_PROT_ACCPROTECT                     (1<<16)
+#define GT64260_CPU_PROT_WRPROTECT                      (1<<17)
+#define GT64260_CPU_PROT_CACHEPROTECT                   (1<<18)
+
+#define GT64260_CPU_PROT_BASE_0                         0x0180
+#define GT64260_CPU_PROT_TOP_0                          0x0188
+#define GT64260_CPU_PROT_BASE_1                         0x0190
+#define GT64260_CPU_PROT_TOP_1                          0x0198
+#define GT64260_CPU_PROT_BASE_2                         0x01a0
+#define GT64260_CPU_PROT_TOP_2                          0x01a8
+#define GT64260_CPU_PROT_BASE_3                         0x01b0
+#define GT64260_CPU_PROT_TOP_3                          0x01b8
+#define GT64260_CPU_PROT_BASE_4                         0x01c0
+#define GT64260_CPU_PROT_TOP_4                          0x01c8
+#define GT64260_CPU_PROT_BASE_5                         0x01d0
+#define GT64260_CPU_PROT_TOP_5                          0x01d8
+#define GT64260_CPU_PROT_BASE_6                         0x01e0
+#define GT64260_CPU_PROT_TOP_6                          0x01e8
+#define GT64260_CPU_PROT_BASE_7                         0x01f0
+#define GT64260_CPU_PROT_TOP_7                          0x01f8
+
+/* CPU Snoop Control Registers */
+#define GT64260_CPU_SNOOP_WINDOWS                       4
+
+#define GT64260_CPU_SNOOP_NONE                          0x00000000
+#define GT64260_CPU_SNOOP_WT                            0x00010000
+#define GT64260_CPU_SNOOP_WB                            0x00020000
+#define GT64260_CPU_SNOOP_MASK                          0x00030000
+#define GT64260_CPU_SNOOP_ALL_BITS                      GT64260_CPU_SNOOP_MASK
+
+#define GT64260_CPU_SNOOP_BASE_0                        0x0380
+#define GT64260_CPU_SNOOP_TOP_0                         0x0388
+#define GT64260_CPU_SNOOP_BASE_1                        0x0390
+#define GT64260_CPU_SNOOP_TOP_1                         0x0398
+#define GT64260_CPU_SNOOP_BASE_2                        0x03a0
+#define GT64260_CPU_SNOOP_TOP_2                         0x03a8
+#define GT64260_CPU_SNOOP_BASE_3                        0x03b0
+#define GT64260_CPU_SNOOP_TOP_3                         0x03b8
+
+/* CPU Error Report Registers */
+#define GT64260_CPU_ERR_ADDR_LO                         0x0070
+#define GT64260_CPU_ERR_ADDR_HI                         0x0078
+#define GT64260_CPU_ERR_DATA_LO                         0x0128
+#define GT64260_CPU_ERR_DATA_HI                         0x0130
+#define GT64260_CPU_ERR_PARITY                          0x0138
+#define GT64260_CPU_ERR_CAUSE                           0x0140
+#define GT64260_CPU_ERR_MASK                            0x0148
+
+
+/*
+ *****************************************************************************
+ *
+ *      SDRAM Cotnroller Registers
+ *
+ *****************************************************************************
+ */
+
+/* SDRAM Config Registers */
+#define GT64260_SDRAM_CONFIG                            0x0448
+#define GT64260_SDRAM_OPERATION_MODE                    0x0474
+#define GT64260_SDRAM_ADDR_CNTL                         0x047c
+#define GT64260_SDRAM_TIMING_PARAMS                     0x04b4
+#define GT64260_SDRAM_UMA_CNTL                          0x04a4
+#define GT64260_SDRAM_XBAR_CNTL_LO                      0x04a8
+#define GT64260_SDRAM_XBAR_CNTL_HI                      0x04ac
+#define GT64260_SDRAM_XBAR_CNTL_TO                      0x04b0
+
+/* SDRAM Banks Parameters Registers */
+#define GT64260_SDRAM_BANK_PARAMS_0                     0x044c
+#define GT64260_SDRAM_BANK_PARAMS_1                     0x0450
+#define GT64260_SDRAM_BANK_PARAMS_2                     0x0454
+#define GT64260_SDRAM_BANK_PARAMS_3                     0x0458
+
+/* SDRAM Error Report Registers */
+#define GT64260_SDRAM_ERR_DATA_LO                       0x0484
+#define GT64260_SDRAM_ERR_DATA_HI                       0x0480
+#define GT64260_SDRAM_ERR_ADDR                          0x0490
+#define GT64260_SDRAM_ERR_ECC_RCVD                      0x0488
+#define GT64260_SDRAM_ERR_ECC_CALC                      0x048c
+#define GT64260_SDRAM_ERR_ECC_CNTL                      0x0494
+#define GT64260_SDRAM_ERR_ECC_ERR_CNT                   0x0498
+
+
+/*
+ *****************************************************************************
+ *
+ *      Device/BOOT Cotnroller Registers
+ *
+ *****************************************************************************
+ */
+
+/* Device Control Registers */
+#define GT64260_DEV_BANK_PARAMS_0                       0x045c
+#define GT64260_DEV_BANK_PARAMS_1                       0x0460
+#define GT64260_DEV_BANK_PARAMS_2                       0x0464
+#define GT64260_DEV_BANK_PARAMS_3                       0x0468
+#define GT64260_DEV_BOOT_PARAMS                         0x046c
+#define GT64260_DEV_IF_CNTL                             0x04c0
+#define GT64260_DEV_IF_XBAR_CNTL_LO                     0x04c8
+#define GT64260_DEV_IF_XBAR_CNTL_HI                     0x04cc
+#define GT64260_DEV_IF_XBAR_CNTL_TO                     0x04c4
+
+/* Device Interrupt Registers */
+#define GT64260_DEV_INTR_CAUSE                          0x04d0
+#define GT64260_DEV_INTR_MASK                           0x04d4
+#define GT64260_DEV_INTR_ERR_ADDR                       0x04d8
+
+
+/*
+ *****************************************************************************
+ *
+ *      PCI Bridge Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* PCI Configuration Access Registers */
+#define GT64260_PCI_0_CONFIG_ADDR                       0x0cf8
+#define GT64260_PCI_0_CONFIG_DATA                       0x0cfc
+#define GT64260_PCI_0_IACK                              0x0c34
+
+#define GT64260_PCI_1_CONFIG_ADDR                       0x0c78
+#define GT64260_PCI_1_CONFIG_DATA                       0x0c7c
+#define GT64260_PCI_1_IACK                              0x0cb4
+
+/* PCI Control Registers */
+#define GT64260_PCI_0_CMD                               0x0c00
+#define GT64260_PCI_0_MODE                              0x0d00
+#define GT64260_PCI_0_TO_RETRY                          0x0c04
+#define GT64260_PCI_0_RD_BUF_DISCARD_TIMER              0x0d04
+#define GT64260_PCI_0_MSI_TRIGGER_TIMER                 0x0c38
+#define GT64260_PCI_0_ARBITER_CNTL                      0x1d00
+#define GT64260_PCI_0_XBAR_CNTL_LO                      0x1d08
+#define GT64260_PCI_0_XBAR_CNTL_HI                      0x1d0c
+#define GT64260_PCI_0_XBAR_CNTL_TO                      0x1d04
+#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO              0x1d18
+#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI              0x1d1c
+#define GT64260_PCI_0_SYNC_BARRIER                      0x1d10
+#define GT64260_PCI_0_P2P_CONFIG                        0x1d14
+#define GT64260_PCI_0_P2P_SWAP_CNTL                     0x1d54
+
+#define GT64260_PCI_1_CMD                               0x0c80
+#define GT64260_PCI_1_MODE                              0x0d80
+#define GT64260_PCI_1_TO_RETRY                          0x0c84
+#define GT64260_PCI_1_RD_BUF_DISCARD_TIMER              0x0d84
+#define GT64260_PCI_1_MSI_TRIGGER_TIMER                 0x0cb8
+#define GT64260_PCI_1_ARBITER_CNTL                      0x1d80
+#define GT64260_PCI_1_XBAR_CNTL_LO                      0x1d88
+#define GT64260_PCI_1_XBAR_CNTL_HI                      0x1d8c
+#define GT64260_PCI_1_XBAR_CNTL_TO                      0x1d84
+#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO              0x1d98
+#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI              0x1d9c
+#define GT64260_PCI_1_SYNC_BARRIER                      0x1d90
+#define GT64260_PCI_1_P2P_CONFIG                        0x1d94
+#define GT64260_PCI_1_P2P_SWAP_CNTL                     0x1dd4
+
+/* PCI Access Control Regions Registers */
+#define GT64260_PCI_ACC_CNTL_WINDOWS                    8
+
+#define GT64260_PCI_ACC_CNTL_PREFETCHEN                 (1<<12)
+#define GT64260_PCI_ACC_CNTL_DREADEN                    (1<<13)
+#define GT64260_PCI_ACC_CNTL_RDPREFETCH                 (1<<16)
+#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH             (1<<17)
+#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH              (1<<18)
+#define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS             0x00000000
+#define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS             0x00100000
+#define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS            0x00200000
+#define GT64260_PCI_ACC_CNTL_MBURST_MASK                0x00300000
+#define GT64260_PCI_ACC_CNTL_SWAP_BYTE                  0x00000000
+#define GT64260_PCI_ACC_CNTL_SWAP_NONE                  0x01000000
+#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD             0x02000000
+#define GT64260_PCI_ACC_CNTL_SWAP_WORD                  0x03000000
+#define GT64260_PCI_ACC_CNTL_SWAP_MASK                  0x03000000
+#define GT64260_PCI_ACC_CNTL_ACCPROT                    (1<<28)
+#define GT64260_PCI_ACC_CNTL_WRPROT                     (1<<29)
+
+#define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
+                                         GT64260_PCI_ACC_CNTL_DREADEN |       \
+                                         GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
+                                         GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
+                                         GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
+                                         GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
+                                         GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
+                                         GT64260_PCI_ACC_CNTL_ACCPROT|        \
+                                         GT64260_PCI_ACC_CNTL_WRPROT)
+
+#define GT64260_PCI_0_ACC_CNTL_0_BASE_LO                0x1e00
+#define GT64260_PCI_0_ACC_CNTL_0_BASE_HI                0x1e04
+#define GT64260_PCI_0_ACC_CNTL_0_TOP                    0x1e08
+#define GT64260_PCI_0_ACC_CNTL_1_BASE_LO                0x1e10
+#define GT64260_PCI_0_ACC_CNTL_1_BASE_HI                0x1e14
+#define GT64260_PCI_0_ACC_CNTL_1_TOP                    0x1e18
+#define GT64260_PCI_0_ACC_CNTL_2_BASE_LO                0x1e20
+#define GT64260_PCI_0_ACC_CNTL_2_BASE_HI                0x1e24
+#define GT64260_PCI_0_ACC_CNTL_2_TOP                    0x1e28
+#define GT64260_PCI_0_ACC_CNTL_3_BASE_LO                0x1e30
+#define GT64260_PCI_0_ACC_CNTL_3_BASE_HI                0x1e34
+#define GT64260_PCI_0_ACC_CNTL_3_TOP                    0x1e38
+#define GT64260_PCI_0_ACC_CNTL_4_BASE_LO                0x1e40
+#define GT64260_PCI_0_ACC_CNTL_4_BASE_HI                0x1e44
+#define GT64260_PCI_0_ACC_CNTL_4_TOP                    0x1e48
+#define GT64260_PCI_0_ACC_CNTL_5_BASE_LO                0x1e50
+#define GT64260_PCI_0_ACC_CNTL_5_BASE_HI                0x1e54
+#define GT64260_PCI_0_ACC_CNTL_5_TOP                    0x1e58
+#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO                0x1e60
+#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI                0x1e64
+#define GT64260_PCI_0_ACC_CNTL_6_TOP                    0x1e68
+#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO                0x1e70
+#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI                0x1e74
+#define GT64260_PCI_0_ACC_CNTL_7_TOP                    0x1e78
+
+#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO                0x1e80
+#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI                0x1e84
+#define GT64260_PCI_1_ACC_CNTL_0_TOP                    0x1e88
+#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO                0x1e90
+#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI                0x1e94
+#define GT64260_PCI_1_ACC_CNTL_1_TOP                    0x1e98
+#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO                0x1ea0
+#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI                0x1ea4
+#define GT64260_PCI_1_ACC_CNTL_2_TOP                    0x1ea8
+#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO                0x1eb0
+#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI                0x1eb4
+#define GT64260_PCI_1_ACC_CNTL_3_TOP                    0x1eb8
+#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO                0x1ec0
+#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI                0x1ec4
+#define GT64260_PCI_1_ACC_CNTL_4_TOP                    0x1ec8
+#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO                0x1ed0
+#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI                0x1ed4
+#define GT64260_PCI_1_ACC_CNTL_5_TOP                    0x1ed8
+#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO                0x1ee0
+#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI                0x1ee4
+#define GT64260_PCI_1_ACC_CNTL_6_TOP                    0x1ee8
+#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO                0x1ef0
+#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI                0x1ef4
+#define GT64260_PCI_1_ACC_CNTL_7_TOP                    0x1ef8
+
+/* PCI Snoop Control Registers */
+#define GT64260_PCI_SNOOP_WINDOWS                       4
+
+#define GT64260_PCI_SNOOP_NONE                          0x00000000
+#define GT64260_PCI_SNOOP_WT                            0x00001000
+#define GT64260_PCI_SNOOP_WB                            0x00002000
+
+#define GT64260_PCI_0_SNOOP_0_BASE_LO                   0x1f00
+#define GT64260_PCI_0_SNOOP_0_BASE_HI                   0x1f04
+#define GT64260_PCI_0_SNOOP_0_TOP                       0x1f08
+#define GT64260_PCI_0_SNOOP_1_BASE_LO                   0x1f10
+#define GT64260_PCI_0_SNOOP_1_BASE_HI                   0x1f14
+#define GT64260_PCI_0_SNOOP_1_TOP                       0x1f18
+#define GT64260_PCI_0_SNOOP_2_BASE_LO                   0x1f20
+#define GT64260_PCI_0_SNOOP_2_BASE_HI                   0x1f24
+#define GT64260_PCI_0_SNOOP_2_TOP                       0x1f28
+#define GT64260_PCI_0_SNOOP_3_BASE_LO                   0x1f30
+#define GT64260_PCI_0_SNOOP_3_BASE_HI                   0x1f34
+#define GT64260_PCI_0_SNOOP_3_TOP                       0x1f38
+
+#define GT64260_PCI_1_SNOOP_0_BASE_LO                   0x1f80
+#define GT64260_PCI_1_SNOOP_0_BASE_HI                   0x1f84
+#define GT64260_PCI_1_SNOOP_0_TOP                       0x1f88
+#define GT64260_PCI_1_SNOOP_1_BASE_LO                   0x1f90
+#define GT64260_PCI_1_SNOOP_1_BASE_HI                   0x1f94
+#define GT64260_PCI_1_SNOOP_1_TOP                       0x1f98
+#define GT64260_PCI_1_SNOOP_2_BASE_LO                   0x1fa0
+#define GT64260_PCI_1_SNOOP_2_BASE_HI                   0x1fa4
+#define GT64260_PCI_1_SNOOP_2_TOP                       0x1fa8
+#define GT64260_PCI_1_SNOOP_3_BASE_LO                   0x1fb0
+#define GT64260_PCI_1_SNOOP_3_BASE_HI                   0x1fb4
+#define GT64260_PCI_1_SNOOP_3_TOP                       0x1fb8
+
+/* PCI Error Report Registers */
+#define GT64260_PCI_0_ERR_SERR_MASK                     0x0c28
+#define GT64260_PCI_0_ERR_ADDR_LO                       0x1d40
+#define GT64260_PCI_0_ERR_ADDR_HI                       0x1d44
+#define GT64260_PCI_0_ERR_DATA_LO                       0x1d48
+#define GT64260_PCI_0_ERR_DATA_HI                       0x1d4c
+#define GT64260_PCI_0_ERR_CMD                           0x1d50
+#define GT64260_PCI_0_ERR_CAUSE                         0x1d58
+#define GT64260_PCI_0_ERR_MASK                          0x1d5c
+
+#define GT64260_PCI_1_ERR_SERR_MASK                     0x0ca8
+#define GT64260_PCI_1_ERR_ADDR_LO                       0x1dc0
+#define GT64260_PCI_1_ERR_ADDR_HI                       0x1dc4
+#define GT64260_PCI_1_ERR_DATA_LO                       0x1dc8
+#define GT64260_PCI_1_ERR_DATA_HI                       0x1dcc
+#define GT64260_PCI_1_ERR_CMD                           0x1dd0
+#define GT64260_PCI_1_ERR_CAUSE                         0x1dd8
+#define GT64260_PCI_1_ERR_MASK                          0x1ddc
+
+/* PCI Slave Address Decoding Registers */
+#define GT64260_PCI_SCS_WINDOWS                         4
+#define GT64260_PCI_CS_WINDOWS                          4
+#define GT64260_PCI_BOOT_WINDOWS                        1
+#define GT64260_PCI_P2P_MEM_WINDOWS                     2
+#define GT64260_PCI_P2P_IO_WINDOWS                      1
+#define GT64260_PCI_DAC_SCS_WINDOWS                     4
+#define GT64260_PCI_DAC_CS_WINDOWS                      4
+#define GT64260_PCI_DAC_BOOT_WINDOWS                    1
+#define GT64260_PCI_DAC_P2P_MEM_WINDOWS                 2
+
+#define GT64260_PCI_0_SLAVE_SCS_0_SIZE                  0x0c08
+#define GT64260_PCI_0_SLAVE_SCS_1_SIZE                  0x0d08
+#define GT64260_PCI_0_SLAVE_SCS_2_SIZE                  0x0c0c
+#define GT64260_PCI_0_SLAVE_SCS_3_SIZE                  0x0d0c
+#define GT64260_PCI_0_SLAVE_CS_0_SIZE                   0x0c10
+#define GT64260_PCI_0_SLAVE_CS_1_SIZE                   0x0d10
+#define GT64260_PCI_0_SLAVE_CS_2_SIZE                   0x0d18
+#define GT64260_PCI_0_SLAVE_CS_3_SIZE                   0x0c14
+#define GT64260_PCI_0_SLAVE_BOOT_SIZE                   0x0d14
+#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE              0x0d1c
+#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE              0x0d20
+#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE                 0x0d24
+#define GT64260_PCI_0_SLAVE_CPU_SIZE                    0x0d28
+
+#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE              0x0e00
+#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE              0x0e04
+#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE              0x0e08
+#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE              0x0e0c
+#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE               0x0e10
+#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE               0x0e14
+#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE               0x0e18
+#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE               0x0e1c
+#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE               0x0e20
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE          0x0e24
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE          0x0e28
+#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE                0x0e2c
+
+#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE                0x0d2c
+
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0         (1<<0)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1         (1<<1)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2         (1<<2)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3         (1<<3)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0          (1<<4)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1          (1<<5)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2          (1<<6)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3          (1<<7)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT          (1<<8)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM       (1<<9)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO        (1<<10)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0     (1<<11)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1     (1<<12)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO        (1<<13)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU           (1<<14)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0     (1<<15)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1     (1<<16)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2     (1<<17)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3     (1<<18)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0      (1<<19)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1      (1<<20)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2      (1<<21)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3      (1<<22)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT      (1<<23)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25)
+#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU       (1<<26)
+
+#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES             0x0c3c
+#define GT64260_PCI_0_SLAVE_SCS_0_REMAP                 0x0c48
+#define GT64260_PCI_0_SLAVE_SCS_1_REMAP                 0x0d48
+#define GT64260_PCI_0_SLAVE_SCS_2_REMAP                 0x0c4c
+#define GT64260_PCI_0_SLAVE_SCS_3_REMAP                 0x0d4c
+#define GT64260_PCI_0_SLAVE_CS_0_REMAP                  0x0c50
+#define GT64260_PCI_0_SLAVE_CS_1_REMAP                  0x0d50
+#define GT64260_PCI_0_SLAVE_CS_2_REMAP                  0x0d58
+#define GT64260_PCI_0_SLAVE_CS_3_REMAP                  0x0c54
+#define GT64260_PCI_0_SLAVE_BOOT_REMAP                  0x0d54
+#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO          0x0d5c
+#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI          0x0d60
+#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO          0x0d64
+#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI          0x0d68
+#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP                0x0d6c
+#define GT64260_PCI_0_SLAVE_CPU_REMAP                   0x0d70
+
+#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP             0x0f00
+#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP             0x0f04
+#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP             0x0f08
+#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP             0x0f0c
+#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP              0x0f10
+#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP              0x0f14
+#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP              0x0f18
+#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP              0x0f1c
+#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP              0x0f20
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0f24
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0f28
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0f2c
+#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0f30
+#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP               0x0f34
+
+#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP               0x0f38
+#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL             0x0d3c
+
+#define GT64260_PCI_1_SLAVE_SCS_0_SIZE                  0x0c88
+#define GT64260_PCI_1_SLAVE_SCS_1_SIZE                  0x0d88
+#define GT64260_PCI_1_SLAVE_SCS_2_SIZE                  0x0c8c
+#define GT64260_PCI_1_SLAVE_SCS_3_SIZE                  0x0d8c
+#define GT64260_PCI_1_SLAVE_CS_0_SIZE                   0x0c90
+#define GT64260_PCI_1_SLAVE_CS_1_SIZE                   0x0d90
+#define GT64260_PCI_1_SLAVE_CS_2_SIZE                   0x0d98
+#define GT64260_PCI_1_SLAVE_CS_3_SIZE                   0x0c94
+#define GT64260_PCI_1_SLAVE_BOOT_SIZE                   0x0d94
+#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE              0x0d9c
+#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE              0x0da0
+#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE                 0x0da4
+#define GT64260_PCI_1_SLAVE_CPU_SIZE                    0x0da8
+
+#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE              0x0e80
+#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE              0x0e84
+#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE              0x0e88
+#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE              0x0e8c
+#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE               0x0e90
+#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE               0x0e94
+#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE               0x0e98
+#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE               0x0e9c
+#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE               0x0ea0
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE          0x0ea4
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE          0x0ea8
+#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE                0x0eac
+
+#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE                0x0dac
+
+#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES             0x0cbc
+#define GT64260_PCI_1_SLAVE_SCS_0_REMAP                 0x0cc8
+#define GT64260_PCI_1_SLAVE_SCS_1_REMAP                 0x0dc8
+#define GT64260_PCI_1_SLAVE_SCS_2_REMAP                 0x0ccc
+#define GT64260_PCI_1_SLAVE_SCS_3_REMAP                 0x0dcc
+#define GT64260_PCI_1_SLAVE_CS_0_REMAP                  0x0cd0
+#define GT64260_PCI_1_SLAVE_CS_1_REMAP                  0x0dd0
+#define GT64260_PCI_1_SLAVE_CS_2_REMAP                  0x0dd8
+#define GT64260_PCI_1_SLAVE_CS_3_REMAP                  0x0cd4
+#define GT64260_PCI_1_SLAVE_BOOT_REMAP                  0x0dd4
+#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO          0x0ddc
+#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI          0x0de0
+#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO          0x0de4
+#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI          0x0de8
+#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP                0x0dec
+#define GT64260_PCI_1_SLAVE_CPU_REMAP                   0x0df0
+
+#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP             0x0f80
+#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP             0x0f84
+#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP             0x0f88
+#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP             0x0f8c
+#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP              0x0f90
+#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP              0x0f94
+#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP              0x0f98
+#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP              0x0f9c
+#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP              0x0fa0
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO      0x0fa4
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI      0x0fa8
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO      0x0fac
+#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI      0x0fb0
+#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP               0x0fb4
+
+#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP               0x0fb8
+#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL             0x0dbc
+
+
+/*
+ *****************************************************************************
+ *
+ *      I2O Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* FIXME: fill in */
+
+
+
+/*
+ *****************************************************************************
+ *
+ *      DMA Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* FIXME: fill in */
+
+
+/*
+ *****************************************************************************
+ *
+ *      Timer/Counter Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* FIXME: fill in */
+
+
+/*
+ *****************************************************************************
+ *
+ *      Communications Controller (Enet, Serial, etc.) Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_ENET_0_CNTL_LO                          0xf200
+#define GT64260_ENET_0_CNTL_HI                          0xf204
+#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI               0xf208
+#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI               0xf20c
+#define GT64260_ENET_0_RX_DESC_ADDR_HI                  0xf210
+#define GT64260_ENET_0_TX_DESC_ADDR_HI                  0xf214
+#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI             0xf218
+#define GT64260_ENET_1_CNTL_LO                          0xf220
+#define GT64260_ENET_1_CNTL_HI                          0xf224
+#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI               0xf228
+#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI               0xf22c
+#define GT64260_ENET_1_RX_DESC_ADDR_HI                  0xf230
+#define GT64260_ENET_1_TX_DESC_ADDR_HI                  0xf234
+#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI             0xf238
+#define GT64260_ENET_2_CNTL_LO                          0xf240
+#define GT64260_ENET_2_CNTL_HI                          0xf244
+#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI               0xf248
+#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI               0xf24c
+#define GT64260_ENET_2_RX_DESC_ADDR_HI                  0xf250
+#define GT64260_ENET_2_TX_DESC_ADDR_HI                  0xf254
+#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI             0xf258
+
+#define GT64260_MPSC_0_CNTL_LO                          0xf280
+#define GT64260_MPSC_0_CNTL_HI                          0xf284
+#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI               0xf288
+#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI               0xf28c
+#define GT64260_MPSC_0_RX_DESC_ADDR_HI                  0xf290
+#define GT64260_MPSC_0_TX_DESC_ADDR_HI                  0xf294
+#define GT64260_MPSC_1_CNTL_LO                          0xf2c0
+#define GT64260_MPSC_1_CNTL_HI                          0xf2c4
+#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI               0xf2c8
+#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI               0xf2cc
+#define GT64260_MPSC_1_RX_DESC_ADDR_HI                  0xf2d0
+#define GT64260_MPSC_1_TX_DESC_ADDR_HI                  0xf2d4
+
+#define GT64260_SER_INIT_PCI_ADDR_HI                    0xf320
+#define GT64260_SER_INIT_LAST_DATA                      0xf324
+#define GT64260_SER_INIT_CONTROL                        0xf328
+#define GT64260_SER_INIT_STATUS                         0xf32c
+
+#define GT64260_COMM_ARBITER_CNTL                       0xf300
+#define GT64260_COMM_CONFIG                             0xb40c
+#define GT64260_COMM_XBAR_TO                            0xf304
+#define GT64260_COMM_INTR_CAUSE                         0xf310
+#define GT64260_COMM_INTR_MASK                          0xf314
+#define GT64260_COMM_ERR_ADDR                           0xf318
+
+
+/*
+ *****************************************************************************
+ *
+ *      Fast Ethernet Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_ENET_PHY_ADDR                           0x2000
+#define GT64260_ENET_ESMIR                              0x2010
+
+#define GT64260_ENET_E0PCR                              0x2400
+#define GT64260_ENET_E0PCXR                             0x2408
+#define GT64260_ENET_E0PCMR                             0x2410
+#define GT64260_ENET_E0PSR                              0x2418
+#define GT64260_ENET_E0SPR                              0x2420
+#define GT64260_ENET_E0HTPR                             0x2428
+#define GT64260_ENET_E0FCSAL                            0x2430
+#define GT64260_ENET_E0FCSAH                            0x2438
+#define GT64260_ENET_E0SDCR                             0x2440
+#define GT64260_ENET_E0SDCMR                            0x2448
+#define GT64260_ENET_E0ICR                              0x2450
+#define GT64260_ENET_E0IMR                              0x2458
+#define GT64260_ENET_E0FRDP0                            0x2480
+#define GT64260_ENET_E0FRDP1                            0x2484
+#define GT64260_ENET_E0FRDP2                            0x2488
+#define GT64260_ENET_E0FRDP3                            0x248c
+#define GT64260_ENET_E0CRDP0                            0x24a0
+#define GT64260_ENET_E0CRDP1                            0x24a4
+#define GT64260_ENET_E0CRDP2                            0x24a8
+#define GT64260_ENET_E0CRDP3                            0x24ac
+#define GT64260_ENET_E0CTDP0                            0x24e0
+#define GT64260_ENET_E0CTDP1                            0x24e4
+#define GT64260_ENET_0_DSCP2P0L                         0x2460
+#define GT64260_ENET_0_DSCP2P0H                         0x2464
+#define GT64260_ENET_0_DSCP2P1L                         0x2468
+#define GT64260_ENET_0_DSCP2P1H                         0x246c
+#define GT64260_ENET_0_VPT2P                            0x2470
+#define GT64260_ENET_0_MIB_CTRS                         0x2500
+
+#define GT64260_ENET_E1PCR                              0x2800
+#define GT64260_ENET_E1PCXR                             0x2808
+#define GT64260_ENET_E1PCMR                             0x2810
+#define GT64260_ENET_E1PSR                              0x2818
+#define GT64260_ENET_E1SPR                              0x2820
+#define GT64260_ENET_E1HTPR                             0x2828
+#define GT64260_ENET_E1FCSAL                            0x2830
+#define GT64260_ENET_E1FCSAH                            0x2838
+#define GT64260_ENET_E1SDCR                             0x2840
+#define GT64260_ENET_E1SDCMR                            0x2848
+#define GT64260_ENET_E1ICR                              0x2850
+#define GT64260_ENET_E1IMR                              0x2858
+#define GT64260_ENET_E1FRDP0                            0x2880
+#define GT64260_ENET_E1FRDP1                            0x2884
+#define GT64260_ENET_E1FRDP2                            0x2888
+#define GT64260_ENET_E1FRDP3                            0x288c
+#define GT64260_ENET_E1CRDP0                            0x28a0
+#define GT64260_ENET_E1CRDP1                            0x28a4
+#define GT64260_ENET_E1CRDP2                            0x28a8
+#define GT64260_ENET_E1CRDP3                            0x28ac
+#define GT64260_ENET_E1CTDP0                            0x28e0
+#define GT64260_ENET_E1CTDP1                            0x28e4
+#define GT64260_ENET_1_DSCP2P0L                         0x2860
+#define GT64260_ENET_1_DSCP2P0H                         0x2864
+#define GT64260_ENET_1_DSCP2P1L                         0x2868
+#define GT64260_ENET_1_DSCP2P1H                         0x286c
+#define GT64260_ENET_1_VPT2P                            0x2870
+#define GT64260_ENET_1_MIB_CTRS                         0x2900
+
+#define GT64260_ENET_E2PCR                              0x2c00
+#define GT64260_ENET_E2PCXR                             0x2c08
+#define GT64260_ENET_E2PCMR                             0x2c10
+#define GT64260_ENET_E2PSR                              0x2c18
+#define GT64260_ENET_E2SPR                              0x2c20
+#define GT64260_ENET_E2HTPR                             0x2c28
+#define GT64260_ENET_E2FCSAL                            0x2c30
+#define GT64260_ENET_E2FCSAH                            0x2c38
+#define GT64260_ENET_E2SDCR                             0x2c40
+#define GT64260_ENET_E2SDCMR                            0x2c48
+#define GT64260_ENET_E2ICR                              0x2c50
+#define GT64260_ENET_E2IMR                              0x2c58
+#define GT64260_ENET_E2FRDP0                            0x2c80
+#define GT64260_ENET_E2FRDP1                            0x2c84
+#define GT64260_ENET_E2FRDP2                            0x2c88
+#define GT64260_ENET_E2FRDP3                            0x2c8c
+#define GT64260_ENET_E2CRDP0                            0x2ca0
+#define GT64260_ENET_E2CRDP1                            0x2ca4
+#define GT64260_ENET_E2CRDP2                            0x2ca8
+#define GT64260_ENET_E2CRDP3                            0x2cac
+#define GT64260_ENET_E2CTDP0                            0x2ce0
+#define GT64260_ENET_E2CTDP1                            0x2ce4
+#define GT64260_ENET_2_DSCP2P0L                         0x2c60
+#define GT64260_ENET_2_DSCP2P0H                         0x2c64
+#define GT64260_ENET_2_DSCP2P1L                         0x2c68
+#define GT64260_ENET_2_DSCP2P1H                         0x2c6c
+#define GT64260_ENET_2_VPT2P                            0x2c70
+#define GT64260_ENET_2_MIB_CTRS                         0x2d00
+
+
+/*
+ *****************************************************************************
+ *
+ *      Multi-Protocol Serial Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* Signal Routing */
+#define GT64260_MPSC_MRR                                0xb400
+#define GT64260_MPSC_RCRR                               0xb404
+#define GT64260_MPSC_TCRR                               0xb408
+
+/* Main Configuratino Registers */
+#define GT64260_MPSC_0_MMCRL                            0x8000
+#define GT64260_MPSC_0_MMCRH                            0x8004
+#define GT64260_MPSC_0_MPCR                             0x8008
+#define GT64260_MPSC_0_CHR_1                            0x800c
+#define GT64260_MPSC_0_CHR_2                            0x8010
+#define GT64260_MPSC_0_CHR_3                            0x8014
+#define GT64260_MPSC_0_CHR_4                            0x8018
+#define GT64260_MPSC_0_CHR_5                            0x801c
+#define GT64260_MPSC_0_CHR_6                            0x8020
+#define GT64260_MPSC_0_CHR_7                            0x8024
+#define GT64260_MPSC_0_CHR_8                            0x8028
+#define GT64260_MPSC_0_CHR_9                            0x802c
+#define GT64260_MPSC_0_CHR_10                           0x8030
+#define GT64260_MPSC_0_CHR_11                           0x8034
+
+#define GT64260_MPSC_1_MMCRL                            0x9000
+#define GT64260_MPSC_1_MMCRH                            0x9004
+#define GT64260_MPSC_1_MPCR                             0x9008
+#define GT64260_MPSC_1_CHR_1                            0x900c
+#define GT64260_MPSC_1_CHR_2                            0x9010
+#define GT64260_MPSC_1_CHR_3                            0x9014
+#define GT64260_MPSC_1_CHR_4                            0x9018
+#define GT64260_MPSC_1_CHR_5                            0x901c
+#define GT64260_MPSC_1_CHR_6                            0x9020
+#define GT64260_MPSC_1_CHR_7                            0x9024
+#define GT64260_MPSC_1_CHR_8                            0x9028
+#define GT64260_MPSC_1_CHR_9                            0x902c
+#define GT64260_MPSC_1_CHR_10                           0x9030
+#define GT64260_MPSC_1_CHR_11                           0x9034
+
+#define GT64260_MPSC_0_INTR_CAUSE                       0xb804
+#define GT64260_MPSC_0_INTR_MASK                        0xb884
+#define GT64260_MPSC_1_INTR_CAUSE                       0xb80c
+#define GT64260_MPSC_1_INTR_MASK                        0xb88c
+
+#define GT64260_MPSC_UART_CR_TEV                        (1<<1)
+#define GT64260_MPSC_UART_CR_TA                         (1<<7)
+#define GT64260_MPSC_UART_CR_TTCS                       (1<<9)
+#define GT64260_MPSC_UART_CR_REV                        (1<<17)
+#define GT64260_MPSC_UART_CR_RA                         (1<<23)
+#define GT64260_MPSC_UART_CR_CRD                        (1<<25)
+#define GT64260_MPSC_UART_CR_EH                         (1<<31)
+
+#define GT64260_MPSC_UART_ESR_CTS                       (1<<0)
+#define GT64260_MPSC_UART_ESR_CD                        (1<<1)
+#define GT64260_MPSC_UART_ESR_TIDLE                     (1<<3)
+#define GT64260_MPSC_UART_ESR_RHS                       (1<<5)
+#define GT64260_MPSC_UART_ESR_RLS                       (1<<7)
+#define GT64260_MPSC_UART_ESR_RLIDL                     (1<<11)
+
+
+/*
+ *****************************************************************************
+ *
+ *      Serial DMA Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_SDMA_0_SDC                              0x4000
+#define GT64260_SDMA_0_SDCM                             0x4008
+#define GT64260_SDMA_0_RX_DESC                          0x4800
+#define GT64260_SDMA_0_RX_BUF_PTR                       0x4808
+#define GT64260_SDMA_0_SCRDP                            0x4810
+#define GT64260_SDMA_0_TX_DESC                          0x4c00
+#define GT64260_SDMA_0_SCTDP                            0x4c10
+#define GT64260_SDMA_0_SFTDP                            0x4c14
+
+#define GT64260_SDMA_1_SDC                              0x6000
+#define GT64260_SDMA_1_SDCM                             0x6008
+#define GT64260_SDMA_1_RX_DESC                          0x6800
+#define GT64260_SDMA_1_RX_BUF_PTR                       0x6808
+#define GT64260_SDMA_1_SCRDP                            0x6810
+#define GT64260_SDMA_1_TX_DESC                          0x6c00
+#define GT64260_SDMA_1_SCTDP                            0x6c10
+#define GT64260_SDMA_1_SFTDP                            0x6c14
+
+#define GT64260_SDMA_INTR_CAUSE                         0xb800
+#define GT64260_SDMA_INTR_MASK                          0xb880
+
+#define GT64260_SDMA_DESC_CMDSTAT_PE                    (1<<0)
+#define GT64260_SDMA_DESC_CMDSTAT_CDL                   (1<<1)
+#define GT64260_SDMA_DESC_CMDSTAT_FR                    (1<<3)
+#define GT64260_SDMA_DESC_CMDSTAT_OR                    (1<<6)
+#define GT64260_SDMA_DESC_CMDSTAT_BR                    (1<<9)
+#define GT64260_SDMA_DESC_CMDSTAT_MI                    (1<<10)
+#define GT64260_SDMA_DESC_CMDSTAT_A                     (1<<11)
+#define GT64260_SDMA_DESC_CMDSTAT_AM                    (1<<12)
+#define GT64260_SDMA_DESC_CMDSTAT_CT                    (1<<13)
+#define GT64260_SDMA_DESC_CMDSTAT_C                     (1<<14)
+#define GT64260_SDMA_DESC_CMDSTAT_ES                    (1<<15)
+#define GT64260_SDMA_DESC_CMDSTAT_L                     (1<<16)
+#define GT64260_SDMA_DESC_CMDSTAT_F                     (1<<17)
+#define GT64260_SDMA_DESC_CMDSTAT_P                     (1<<18)
+#define GT64260_SDMA_DESC_CMDSTAT_EI                    (1<<23)
+#define GT64260_SDMA_DESC_CMDSTAT_O                     (1<<31)
+
+#define GT64260_SDMA_SDC_RFT                            (1<<0)
+#define GT64260_SDMA_SDC_SFM                            (1<<1)
+#define GT64260_SDMA_SDC_BLMR                           (1<<6)
+#define GT64260_SDMA_SDC_BLMT                           (1<<7)
+#define GT64260_SDMA_SDC_POVR                           (1<<8)
+#define GT64260_SDMA_SDC_RIFB                           (1<<9)
+
+#define GT64260_SDMA_SDCM_ERD                           (1<<7)
+#define GT64260_SDMA_SDCM_AR                            (1<<15)
+#define GT64260_SDMA_SDCM_STD                           (1<<16)
+#define GT64260_SDMA_SDCM_TXD                           (1<<23)
+#define GT64260_SDMA_SDCM_AT                            (1<<31)
+
+#define GT64260_SDMA_0_CAUSE_RXBUF                      (1<<0)
+#define GT64260_SDMA_0_CAUSE_RXERR                      (1<<1)
+#define GT64260_SDMA_0_CAUSE_TXBUF                      (1<<2)
+#define GT64260_SDMA_0_CAUSE_TXEND                      (1<<3)
+#define GT64260_SDMA_1_CAUSE_RXBUF                      (1<<8)
+#define GT64260_SDMA_1_CAUSE_RXERR                      (1<<9)
+#define GT64260_SDMA_1_CAUSE_TXBUF                      (1<<10)
+#define GT64260_SDMA_1_CAUSE_TXEND                      (1<<11)
+
+
+/*
+ *****************************************************************************
+ *
+ *      Baud Rate Generator Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_BRG_0_BCR                               0xb200
+#define GT64260_BRG_0_BTR                               0xb204
+#define GT64260_BRG_1_BCR                               0xb208
+#define GT64260_BRG_1_BTR                               0xb20c
+#define GT64260_BRG_2_BCR                               0xb210
+#define GT64260_BRG_2_BTR                               0xb214
+
+#define GT64260_BRG_INTR_CAUSE                          0xb834
+#define GT64260_BRG_INTR_MASK                           0xb8b4
+
+
+/*
+ *****************************************************************************
+ *
+ *      Watchdog Timer Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_WDT_WDC                                 0xb410
+#define GT64260_WDT_WDV                                 0xb414
+
+
+/*
+ *****************************************************************************
+ *
+ *       General Purpose Pins Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_GPP_IO_CNTL                             0xf100
+#define GT64260_GPP_LEVEL_CNTL                          0xf110
+#define GT64260_GPP_VALUE                               0xf104
+#define GT64260_GPP_INTR_CAUSE                          0xf108
+#define GT64260_GPP_INTR_MASK                           0xf10c
+
+
+/*
+ *****************************************************************************
+ *
+ *      Multi-Purpose Pins Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_MPP_CNTL_0                              0xf000
+#define GT64260_MPP_CNTL_1                              0xf004
+#define GT64260_MPP_CNTL_2                              0xf008
+#define GT64260_MPP_CNTL_3                              0xf00c
+#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX              0xf010
+
+
+/*
+ *****************************************************************************
+ *
+ *      I2C Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* FIXME: fill in */
+
+
+/*
+ *****************************************************************************
+ *
+ *      Interrupt Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_IC_MAIN_CAUSE_LO                        0x0c18
+#define GT64260_IC_MAIN_CAUSE_HI                        0x0c68
+#define GT64260_IC_CPU_INTR_MASK_LO                     0x0c1c
+#define GT64260_IC_CPU_INTR_MASK_HI                     0x0c6c
+#define GT64260_IC_CPU_SELECT_CAUSE                     0x0c70
+#define GT64260_IC_PCI_0_INTR_MASK_LO                   0x0c24
+#define GT64260_IC_PCI_0_INTR_MASK_HI                   0x0c64
+#define GT64260_IC_PCI_0_SELECT_CAUSE                   0x0c74
+#define GT64260_IC_PCI_1_INTR_MASK_LO                   0x0ca4
+#define GT64260_IC_PCI_1_INTR_MASK_HI                   0x0ce4
+#define GT64260_IC_PCI_1_SELECT_CAUSE                   0x0cf4
+#define GT64260_IC_CPU_INT_0_MASK                       0x0e60
+#define GT64260_IC_CPU_INT_1_MASK                       0x0e64
+#define GT64260_IC_CPU_INT_2_MASK                       0x0e68
+#define GT64260_IC_CPU_INT_3_MASK                       0x0e6c
+
+
+#endif /* __ASMPPC_GT64260_DEFS_H */
diff --git a/include/asm-ppc/hardirq.h b/include/asm-ppc/hardirq.h
new file mode 100644
index 000000000000..94f1411b1a93
--- /dev/null
+++ b/include/asm-ppc/hardirq.h
@@ -0,0 +1,31 @@
+#ifdef __KERNEL__
+#ifndef __ASM_HARDIRQ_H
+#define __ASM_HARDIRQ_H
+
+#include <linux/config.h>
+#include <linux/cache.h>
+#include <linux/smp_lock.h>
+#include <asm/irq.h>
+
+/* The __last_jiffy_stamp field is needed to ensure that no decrementer
+ * interrupt is lost on SMP machines. Since on most CPUs it is in the same
+ * cache line as local_irq_count, it is cheap to access and is also used on UP
+ * for uniformity.
+ */
+typedef struct {
+        unsigned long __softirq_pending;        /* set_bit is used on this */
+        unsigned int __last_jiffy_stamp;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
+
+static inline void ack_bad_irq(int irq)
+{
+        printk(KERN_CRIT "illegal vector %d received!\n", irq);
+        BUG();
+}
+
+#endif /* __ASM_HARDIRQ_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h
new file mode 100644
index 000000000000..36c73ab7e43e
--- /dev/null
+++ b/include/asm-ppc/harrier.h
@@ -0,0 +1,45 @@
+/*
+ * arch/ppc/kernel/harrier.h
+ *
+ * Definitions for Motorola MCG Harrier North Bridge & Memory controller
+ *
+ * Author: Dale Farnsworth
+ *         dale.farnsworth@mvista.com
+ *
+ * Modified by: Randy Vinson
+ *         rvinson@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASMPPC_HARRIER_H
+#define __ASMPPC_HARRIER_H
+
+#include <linux/types.h>
+#include <asm/pci-bridge.h>
+
+struct pci_controller;
+int harrier_init(struct pci_controller *hose,
+                 uint ppc_reg_base,
+                 ulong processor_pci_mem_start,
+                 ulong processor_pci_mem_end,
+                 ulong processor_pci_io_start,
+                 ulong processor_pci_io_end,
+                 ulong processor_mpic_base);
+
+unsigned long harrier_get_mem_size(uint smc_base);
+
+int harrier_mpic_init(unsigned int pci_mem_offset);
+
+void harrier_setup_nonmonarch(uint ppc_reg_base,
+                              uint in0_size);
+void harrier_release_eready(uint ppc_reg_base);
+
+void harrier_wait_eready(uint ppc_reg_base);
+
+#endif /* __ASMPPC_HARRIER_H */
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h
new file mode 100644
index 000000000000..f347007d22af
--- /dev/null
+++ b/include/asm-ppc/hawk.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-ppc/hawk.h
+ *
+ * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * Modified by Randy Vinson (rvinson@mvista.com)
+ *
+ * 2001,2004 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASMPPC_HAWK_H
+#define __ASMPPC_HAWK_H
+
+#include <asm/pci-bridge.h>
+#include <asm/hawk_defs.h>
+
+extern int hawk_init(struct pci_controller *hose,
+              unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
+              unsigned long processor_pci_mem_end,
+              unsigned long processor_pci_io_start,
+              unsigned long processor_pci_io_end,
+              unsigned long processor_mpic_base);
+extern unsigned long hawk_get_mem_size(unsigned int smc_base);
+extern int hawk_mpic_init(unsigned int pci_mem_offset);
+
+#endif  /* __ASMPPC_HAWK_H */
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h
new file mode 100644
index 000000000000..6d1d2baf648c
--- /dev/null
+++ b/include/asm-ppc/hawk_defs.h
@@ -0,0 +1,76 @@
+/*
+ * include/asm-ppc/hawk_defs.h
+ *
+ * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * Modified by Randy Vinson (rvinson@mvista.com)
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASMPPC_HAWK_DEFS_H
+#define __ASMPPC_HAWK_DEFS_H
+
+#include <asm/pci-bridge.h>
+
+/*
+ * The Falcon/Raven and HAWK have 4 sets of registers:
+ *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
+ *      etc.
+ *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
+ *      MPIC base address.
+ *   3) MPIC registers
+ *   4) System Memory Controller (SMC) registers.
+ */
+
+#define HAWK_PCI_CONFIG_ADDR_OFF        0x00000cf8
+#define HAWK_PCI_CONFIG_DATA_OFF        0x00000cfc
+
+#define HAWK_MPIC_SIZE                  0x00040000U
+#define HAWK_SMC_SIZE                   0x00001000U
+
+/*
+ * Define PPC register offsets.
+ */
+#define HAWK_PPC_XSADD0_OFF                     0x40
+#define HAWK_PPC_XSOFF0_OFF                     0x44
+#define HAWK_PPC_XSADD1_OFF                     0x48
+#define HAWK_PPC_XSOFF1_OFF                     0x4c
+#define HAWK_PPC_XSADD2_OFF                     0x50
+#define HAWK_PPC_XSOFF2_OFF                     0x54
+#define HAWK_PPC_XSADD3_OFF                     0x58
+#define HAWK_PPC_XSOFF3_OFF                     0x5c
+
+/*
+ * Define PCI register offsets.
+ */
+#define HAWK_PCI_PSADD0_OFF                     0x80
+#define HAWK_PCI_PSOFF0_OFF                     0x84
+#define HAWK_PCI_PSADD1_OFF                     0x88
+#define HAWK_PCI_PSOFF1_OFF                     0x8c
+#define HAWK_PCI_PSADD2_OFF                     0x90
+#define HAWK_PCI_PSOFF2_OFF                     0x94
+#define HAWK_PCI_PSADD3_OFF                     0x98
+#define HAWK_PCI_PSOFF3_OFF                     0x9c
+
+/*
+ * Define the System Memory Controller (SMC) register offsets.
+ */
+#define HAWK_SMC_RAM_A_SIZE_REG_OFF             0x10
+#define HAWK_SMC_RAM_B_SIZE_REG_OFF             0x11
+#define HAWK_SMC_RAM_C_SIZE_REG_OFF             0x12
+#define HAWK_SMC_RAM_D_SIZE_REG_OFF             0x13
+#define HAWK_SMC_RAM_E_SIZE_REG_OFF             0xc0    /* HAWK Only */
+#define HAWK_SMC_RAM_F_SIZE_REG_OFF             0xc1    /* HAWK Only */
+#define HAWK_SMC_RAM_G_SIZE_REG_OFF             0xc2    /* HAWK Only */
+#define HAWK_SMC_RAM_H_SIZE_REG_OFF             0xc3    /* HAWK Only */
+
+#define FALCON_SMC_REG_COUNT                    4
+#define HAWK_SMC_REG_COUNT                      8
+#endif                          /* __ASMPPC_HAWK_DEFS_H */
diff --git a/include/asm-ppc/hdreg.h b/include/asm-ppc/hdreg.h
new file mode 100644
index 000000000000..7f7fd1af0af3
--- /dev/null
+++ b/include/asm-ppc/hdreg.h
@@ -0,0 +1 @@
+#include <asm-generic/hdreg.h>
diff --git a/include/asm-ppc/heathrow.h b/include/asm-ppc/heathrow.h
new file mode 100644
index 000000000000..22ac179856b9
--- /dev/null
+++ b/include/asm-ppc/heathrow.h
@@ -0,0 +1,62 @@
+/*
+ * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
+ *
+ * Grabbed from Open Firmware definitions on a PowerBook G3 Series
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ */
+
+/* Front light color on Yikes/B&W G3. 32 bits */
+#define HEATHROW_FRONT_LIGHT            0x32 /* (set to 0 or 0xffffffff) */
+
+/* Brightness/contrast (gossamer iMac ?). 8 bits */
+#define HEATHROW_BRIGHTNESS_CNTL        0x32
+#define HEATHROW_CONTRAST_CNTL          0x33
+
+/* offset from ohare base for feature control register */
+#define HEATHROW_MBCR                   0x34    /* Media bay control */
+#define HEATHROW_FCR                    0x38    /* Feature control */
+#define HEATHROW_AUX_CNTL_REG           0x3c    /* Aux control */
+
+/*
+ * Bits in feature control register.
+ * Bits postfixed with a _N are in inverse logic
+ */
+#define HRW_SCC_TRANS_EN_N      0x00000001      /* Also controls modem power */
+#define HRW_BAY_POWER_N         0x00000002
+#define HRW_BAY_PCI_ENABLE      0x00000004
+#define HRW_BAY_IDE_ENABLE      0x00000008
+#define HRW_BAY_FLOPPY_ENABLE   0x00000010
+#define HRW_IDE0_ENABLE         0x00000020
+#define HRW_IDE0_RESET_N        0x00000040
+#define HRW_BAY_DEV_MASK        0x0000001c
+#define HRW_BAY_RESET_N         0x00000080
+#define HRW_IOBUS_ENABLE        0x00000100      /* Internal IDE ? */
+#define HRW_SCC_ENABLE          0x00000200
+#define HRW_MESH_ENABLE         0x00000400
+#define HRW_SWIM_ENABLE         0x00000800
+#define HRW_SOUND_POWER_N       0x00001000
+#define HRW_SOUND_CLK_ENABLE    0x00002000
+#define HRW_SCCA_IO             0x00004000
+#define HRW_SCCB_IO             0x00008000
+#define HRW_PORT_OR_DESK_VIA_N  0x00010000      /* This one is 0 on PowerBook */
+#define HRW_PWM_MON_ID_N        0x00020000      /* ??? (0) */
+#define HRW_HOOK_MB_CNT_N       0x00040000      /* ??? (0) */
+#define HRW_SWIM_CLONE_FLOPPY   0x00080000      /* ??? (0) */
+#define HRW_AUD_RUN22           0x00100000      /* ??? (1) */
+#define HRW_SCSI_LINK_MODE      0x00200000      /* Read ??? (1) */
+#define HRW_ARB_BYPASS          0x00400000      /* Disable internal PCI arbitrer */
+#define HRW_IDE1_RESET_N        0x00800000      /* Media bay */
+#define HRW_SLOW_SCC_PCLK       0x01000000      /* ??? (0) */
+#define HRW_RESET_SCC           0x02000000
+#define HRW_MFDC_CELL_ENABLE    0x04000000      /* ??? (0) */
+#define HRW_USE_MFDC            0x08000000      /* ??? (0) */
+#define HRW_BMAC_IO_ENABLE      0x60000000      /* two bits, not documented in OF */
+#define HRW_BMAC_RESET          0x80000000      /* not documented in OF */
+
+/* We OR those features at boot on desktop G3s */
+#define HRW_DEFAULTS            (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
+
+/* Looks like Heathrow has some sort of GPIOs as well... */
+#define HRW_GPIO_MODEM_RESET    0x6d
+
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h
new file mode 100644
index 000000000000..1d2c4ef81c22
--- /dev/null
+++ b/include/asm-ppc/highmem.h
@@ -0,0 +1,137 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * PowerPC version, stolen from the i386 version.
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terrabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/kmap_types.h>
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+
+/* undef for production */
+#define HIGHMEM_DEBUG 1
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define PKMAP_BASE      CONFIG_HIGHMEM_START
+#define LAST_PKMAP      (1 << PTE_SHIFT)
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+#define KMAP_FIX_BEGIN  (PKMAP_BASE + 0x00400000UL)
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+static inline void *kmap(struct page *page)
+{
+        might_sleep();
+        if (!PageHighMem(page))
+                return page_address(page);
+        return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+        BUG_ON(in_interrupt());
+        if (!PageHighMem(page))
+                return;
+        kunmap_high(page);
+}
+
+/*
+ * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
+ * gives a more generic (and caching) interface. But kmap_atomic can
+ * be used in IRQ contexts, so in some (very limited) cases we need
+ * it.
+ */
+static inline void *kmap_atomic(struct page *page, enum km_type type)
+{
+        unsigned int idx;
+        unsigned long vaddr;
+
+        /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
+        inc_preempt_count();
+        if (!PageHighMem(page))
+                return page_address(page);
+
+        idx = type + KM_TYPE_NR*smp_processor_id();
+        vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
+#ifdef HIGHMEM_DEBUG
+        BUG_ON(!pte_none(*(kmap_pte+idx)));
+#endif
+        set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
+        flush_tlb_page(NULL, vaddr);
+
+        return (void*) vaddr;
+}
+
+static inline void kunmap_atomic(void *kvaddr, enum km_type type)
+{
+#ifdef HIGHMEM_DEBUG
+        unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
+        unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
+
+        if (vaddr < KMAP_FIX_BEGIN) { // FIXME
+                dec_preempt_count();
+                preempt_check_resched();
+                return;
+        }
+
+        BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
+
+        /*
+         * force other mappings to Oops if they'll try to access
+         * this pte without first remap it
+         */
+        pte_clear(&init_mm, vaddr, kmap_pte+idx);
+        flush_tlb_page(NULL, vaddr);
+#endif
+        dec_preempt_count();
+        preempt_check_resched();
+}
+
+static inline struct page *kmap_atomic_to_page(void *ptr)
+{
+        unsigned long idx, vaddr = (unsigned long) ptr;
+
+        if (vaddr < KMAP_FIX_BEGIN)
+                return virt_to_page(ptr);
+
+        idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
+        return pte_page(kmap_pte[idx]);
+}
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h
new file mode 100644
index 000000000000..47dc7990fb26
--- /dev/null
+++ b/include/asm-ppc/hw_irq.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_HW_IRQ_H
+#define _PPC_HW_IRQ_H
+
+#include <asm/ptrace.h>
+#include <asm/reg.h>
+
+extern void timer_interrupt(struct pt_regs *);
+
+#define INLINE_IRQS
+
+#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
+
+#ifdef INLINE_IRQS
+
+static inline void local_irq_disable(void)
+{
+        unsigned long msr;
+        msr = mfmsr();
+        mtmsr(msr & ~MSR_EE);
+        __asm__ __volatile__("": : :"memory");
+}
+
+static inline void local_irq_enable(void)
+{
+        unsigned long msr;
+        __asm__ __volatile__("": : :"memory");
+        msr = mfmsr();
+        mtmsr(msr | MSR_EE);
+}
+
+static inline void local_irq_save_ptr(unsigned long *flags)
+{
+        unsigned long msr;
+        msr = mfmsr();
+        *flags = msr;
+        mtmsr(msr & ~MSR_EE);
+        __asm__ __volatile__("": : :"memory");
+}
+
+#define local_save_flags(flags)         ((flags) = mfmsr())
+#define local_irq_save(flags)           local_irq_save_ptr(&flags)
+#define local_irq_restore(flags)        mtmsr(flags)
+
+#else
+
+extern void local_irq_enable(void);
+extern void local_irq_disable(void);
+extern void local_irq_restore(unsigned long);
+extern void local_save_flags_ptr(unsigned long *);
+
+#define local_save_flags(flags) local_save_flags_ptr(&flags)
+#define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();})
+
+#endif
+
+extern void do_lost_interrupts(unsigned long);
+
+#define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);})
+#define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);})
+#define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);})
+
+/* Should we handle this via lost interrupts and IPIs or should we don't care like
+ * we do now ? --BenH.
+ */
+struct hw_interrupt_type;
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
+
+
+#endif /* _PPC_HW_IRQ_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h
new file mode 100644
index 000000000000..1134431431da
--- /dev/null
+++ b/include/asm-ppc/hydra.h
@@ -0,0 +1,102 @@
+/*
+ *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
+ *
+ *  Copyright (C) 1997 Geert Uytterhoeven
+ *
+ *  This file is based on the following documentation:
+ *
+ *      Macintosh Technology in the Common Hardware Reference Platform
+ *      Apple Computer, Inc.
+ *
+ *      © Copyright 1995 Apple Computer, Inc. All rights reserved.
+ *
+ *  It's available online from http://chrp.apple.com/MacTech.pdf.
+ *  You can obtain paper copies of this book from computer bookstores or by
+ *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
+ *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License.  See the file COPYING in the main directory of this archive
+ *  for more details.
+ */
+
+#ifndef _ASMPPC_HYDRA_H
+#define _ASMPPC_HYDRA_H
+
+#ifdef __KERNEL__
+
+struct Hydra {
+    /* DBDMA Controller Register Space */
+    char Pad1[0x30];
+    u_int CachePD;
+    u_int IDs;
+    u_int Feature_Control;
+    char Pad2[0x7fc4];
+    /* DBDMA Channel Register Space */
+    char SCSI_DMA[0x100];
+    char Pad3[0x300];
+    char SCCA_Tx_DMA[0x100];
+    char SCCA_Rx_DMA[0x100];
+    char SCCB_Tx_DMA[0x100];
+    char SCCB_Rx_DMA[0x100];
+    char Pad4[0x7800];
+    /* Device Register Space */
+    char SCSI[0x1000];
+    char ADB[0x1000];
+    char SCC_Legacy[0x1000];
+    char SCC[0x1000];
+    char Pad9[0x2000];
+    char VIA[0x2000];
+    char Pad10[0x28000];
+    char OpenPIC[0x40000];
+};
+
+extern volatile struct Hydra *Hydra;
+
+
+    /*
+     *  Feature Control Register
+     */
+
+#define HYDRA_FC_SCC_CELL_EN    0x00000001      /* Enable SCC Clock */
+#define HYDRA_FC_SCSI_CELL_EN   0x00000002      /* Enable SCSI Clock */
+#define HYDRA_FC_SCCA_ENABLE    0x00000004      /* Enable SCC A Lines */
+#define HYDRA_FC_SCCB_ENABLE    0x00000008      /* Enable SCC B Lines */
+#define HYDRA_FC_ARB_BYPASS     0x00000010      /* Bypass Internal Arbiter */
+#define HYDRA_FC_RESET_SCC      0x00000020      /* Reset SCC */
+#define HYDRA_FC_MPIC_ENABLE    0x00000040      /* Enable OpenPIC */
+#define HYDRA_FC_SLOW_SCC_PCLK  0x00000080      /* 1=15.6672, 0=25 MHz */
+#define HYDRA_FC_MPIC_IS_MASTER 0x00000100      /* OpenPIC Master Mode */
+
+
+    /*
+     *  OpenPIC Interrupt Sources
+     */
+
+#define HYDRA_INT_SIO           0
+#define HYDRA_INT_SCSI_DMA      1
+#define HYDRA_INT_SCCA_TX_DMA   2
+#define HYDRA_INT_SCCA_RX_DMA   3
+#define HYDRA_INT_SCCB_TX_DMA   4
+#define HYDRA_INT_SCCB_RX_DMA   5
+#define HYDRA_INT_SCSI          6
+#define HYDRA_INT_SCCA          7
+#define HYDRA_INT_SCCB          8
+#define HYDRA_INT_VIA           9
+#define HYDRA_INT_ADB           10
+#define HYDRA_INT_ADB_NMI       11
+#define HYDRA_INT_EXT1          12      /* PCI IRQW */
+#define HYDRA_INT_EXT2          13      /* PCI IRQX */
+#define HYDRA_INT_EXT3          14      /* PCI IRQY */
+#define HYDRA_INT_EXT4          15      /* PCI IRQZ */
+#define HYDRA_INT_EXT5          16      /* IDE Primay/Secondary */
+#define HYDRA_INT_EXT6          17      /* IDE Secondary */
+#define HYDRA_INT_EXT7          18      /* Power Off Request */
+#define HYDRA_INT_SPARE         19
+
+extern int hydra_init(void);
+extern void macio_adb_init(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASMPPC_HYDRA_H */
diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h
new file mode 100644
index 000000000000..091b71295de4
--- /dev/null
+++ b/include/asm-ppc/i8259.h
@@ -0,0 +1,11 @@
+#ifndef _PPC_KERNEL_i8259_H
+#define _PPC_KERNEL_i8259_H
+
+#include <linux/irq.h>
+
+extern struct hw_interrupt_type i8259_pic;
+
+extern void i8259_init(long intack_addr);
+extern int i8259_irq(struct pt_regs *regs);
+
+#endif /* _PPC_KERNEL_i8259_H */
diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h
new file mode 100644
index 000000000000..bf6efa0417ab
--- /dev/null
+++ b/include/asm-ppc/ibm403.h
@@ -0,0 +1,479 @@
+/*
+ * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com>
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM403_H__
+#define __ASM_IBM403_H__
+
+#include <linux/config.h>
+
+#if defined(CONFIG_403GCX)
+
+#define DCRN_BE_BASE            0x090
+#define DCRN_DMA0_BASE          0x0C0
+#define DCRN_DMA1_BASE          0x0C8
+#define DCRN_DMA2_BASE          0x0D0
+#define DCRN_DMA3_BASE          0x0D8
+#define DCRNCAP_DMA_CC          1       /* have DMA chained count capability */
+#define DCRN_DMASR_BASE         0x0E0
+
+#define DCRN_EXIER_BASE         0x042
+#define DCRN_EXISR_BASE         0x040
+#define DCRN_IOCR_BASE          0x0A0
+
+
+/* ------------------------------------------------------------------------- */
+#endif
+
+
+
+#ifdef DCRN_BE_BASE
+#define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
+#define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register*/
+#endif
+/* DCRN_BESR */
+#define BESR_DSES       0x80000000      /* Data-Side Error Status */
+#define BESR_DMES       0x40000000      /* DMA Error Status */
+#define BESR_RWS        0x20000000      /* Read/Write Status */
+#define BESR_ETMASK     0x1C000000      /* Error Type */
+#define ET_PROT 0
+#define ET_PARITY       1
+#define ET_NCFG 2
+#define ET_BUSERR       4
+#define ET_BUSTO        6
+
+#ifdef DCRN_CHCR_BASE
+#define DCRN_CHCR0      (DCRN_CHCR_BASE + 0x0)  /* Chip Control Register 1 */
+#define DCRN_CHCR1      (DCRN_CHCR_BASE + 0x1)  /* Chip Control Register 2 */
+#endif
+#define CHR1_CETE       0x00800000               /* CPU external timer enable */
+#define CHR1_PCIPW      0x00008000 /* PCI Int enable/Peripheral Write enable */
+
+#ifdef DCRN_CHPSR_BASE
+#define DCRN_CHPSR      (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
+#endif
+
+#ifdef DCRN_CIC_BASE
+#define DCRN_CICCR      (DCRN_CIC_BASE + 0x0)   /* CIC Control Register */
+#define DCRN_DMAS1      (DCRN_CIC_BASE + 0x1)   /* DMA Select1 Register */
+#define DCRN_DMAS2      (DCRN_CIC_BASE + 0x2)   /* DMA Select2 Register */
+#define DCRN_CICVCR     (DCRN_CIC_BASE + 0x3)   /* CIC Video COntro Register */
+#define DCRN_CICSEL3    (DCRN_CIC_BASE + 0x5)   /* CIC Select 3 Register */
+#define DCRN_SGPO       (DCRN_CIC_BASE + 0x6)   /* CIC GPIO Output Register */
+#define DCRN_SGPOD      (DCRN_CIC_BASE + 0x7)   /* CIC GPIO OD Register */
+#define DCRN_SGPTC      (DCRN_CIC_BASE + 0x8)   /* CIC GPIO Tristate Ctrl Reg */
+#define DCRN_SGPI       (DCRN_CIC_BASE + 0x9)   /* CIC GPIO Input Reg */
+#endif
+
+#ifdef DCRN_CPMFR_BASE
+#define DCRN_CPMFR      (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
+#endif
+
+#ifndef CPM_AUD
+#define CPM_AUD         0x00000000
+#endif
+#ifndef CPM_BRG
+#define CPM_BRG         0x00000000
+#endif
+#ifndef CPM_CBS
+#define CPM_CBS         0x00000000
+#endif
+#ifndef CPM_CPU
+#define CPM_CPU         0x00000000
+#endif
+#ifndef CPM_DCP
+#define CPM_DCP         0x00000000
+#endif
+#ifndef CPM_DCRX
+#define CPM_DCRX        0x00000000
+#endif
+#ifndef CPM_DENC
+#define CPM_DENC        0x00000000
+#endif
+#ifndef CPM_DMA
+#define CPM_DMA         0x00000000
+#endif
+#ifndef CPM_DSCR
+#define CPM_DSCR        0x00000000
+#endif
+#ifndef CPM_EBC
+#define CPM_EBC         0x00000000
+#endif
+#ifndef CPM_EBIU
+#define CPM_EBIU        0x00000000
+#endif
+#ifndef CPM_EMAC_MM
+#define CPM_EMAC_MM     0x00000000
+#endif
+#ifndef CPM_EMAC_RM
+#define CPM_EMAC_RM     0x00000000
+#endif
+#ifndef CPM_EMAC_TM
+#define CPM_EMAC_TM     0x00000000
+#endif
+#ifndef CPM_GPIO0
+#define CPM_GPIO0       0x00000000
+#endif
+#ifndef CPM_GPT
+#define CPM_GPT         0x00000000
+#endif
+#ifndef CPM_I1284
+#define CPM_I1284       0x00000000
+#endif
+#ifndef CPM_IIC0
+#define CPM_IIC0        0x00000000
+#endif
+#ifndef CPM_IIC1
+#define CPM_IIC1        0x00000000
+#endif
+#ifndef CPM_MSI
+#define CPM_MSI         0x00000000
+#endif
+#ifndef CPM_PCI
+#define CPM_PCI         0x00000000
+#endif
+#ifndef CPM_PLB
+#define CPM_PLB         0x00000000
+#endif
+#ifndef CPM_SC0
+#define CPM_SC0         0x00000000
+#endif
+#ifndef CPM_SC1
+#define CPM_SC1         0x00000000
+#endif
+#ifndef CPM_SDRAM0
+#define CPM_SDRAM0      0x00000000
+#endif
+#ifndef CPM_SDRAM1
+#define CPM_SDRAM1      0x00000000
+#endif
+#ifndef CPM_TMRCLK
+#define CPM_TMRCLK      0x00000000
+#endif
+#ifndef CPM_UART0
+#define CPM_UART0       0x00000000
+#endif
+#ifndef CPM_UART1
+#define CPM_UART1       0x00000000
+#endif
+#ifndef CPM_UART2
+#define CPM_UART2       0x00000000
+#endif
+#ifndef CPM_UIC
+#define CPM_UIC         0x00000000
+#endif
+#ifndef CPM_VID2
+#define CPM_VID2        0x00000000
+#endif
+#ifndef CPM_XPT27
+#define CPM_XPT27       0x00000000
+#endif
+#ifndef CPM_XPT54
+#define CPM_XPT54       0x00000000
+#endif
+
+#ifdef DCRN_CPMSR_BASE
+#define DCRN_CPMSR      (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
+#define DCRN_CPMER      (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
+#endif
+
+#ifdef DCRN_DCP0_BASE
+#define DCRN_DCP0_CFGADDR       (DCRN_DCP0_BASE + 0x0)  /* Decompression Controller Address */
+#define DCRN_DCP0_CFGDATA       (DCRN_DCP0_BASE + 0x1)  /* Decompression Controller Data */
+#endif
+
+#ifdef DCRN_DCRX_BASE
+#define DCRN_DCRXICR    (DCRN_DCRX_BASE + 0x0)  /* Internal Control Register */
+#define DCRN_DCRXISR    (DCRN_DCRX_BASE + 0x1)  /* Internal Status Register */
+#define DCRN_DCRXECR    (DCRN_DCRX_BASE + 0x2)  /* External Control Register */
+#define DCRN_DCRXESR    (DCRN_DCRX_BASE + 0x3)  /* External Status Register */
+#define DCRN_DCRXTAR    (DCRN_DCRX_BASE + 0x4)  /* Target Address Register */
+#define DCRN_DCRXTDR    (DCRN_DCRX_BASE + 0x5)  /* Target Data Register */
+#define DCRN_DCRXIGR    (DCRN_DCRX_BASE + 0x6)  /* Interrupt Generation Register */
+#define DCRN_DCRXBCR    (DCRN_DCRX_BASE + 0x7)  /* Line Buffer Control Register */
+#endif
+
+#ifdef DCRN_DMA0_BASE
+#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)  /* DMA Channel Control Register 0 */
+#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count Register 0 */
+#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x2)  /* DMA Destination Address Register 0 */
+#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)  /* DMA Source Address Register 0 */
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC0     (DCRN_DMA0_BASE + 0x4)  /* DMA Chained Count Register 0 */
+#endif
+
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 0 */
+#endif
+#endif
+
+#ifdef DCRN_DMA1_BASE
+#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)  /* DMA Channel Control Register 1 */
+#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count Register 1 */
+#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x2)  /* DMA Destination Address Register 1 */
+#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Source Address Register 1 */
+
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC1     (DCRN_DMA1_BASE + 0x4)  /* DMA Chained Count Register 1 */
+#endif
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 1 */
+#endif
+#endif
+
+#ifdef DCRN_DMA2_BASE
+#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control Register 2 */
+#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count Register 2 */
+#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x2)  /* DMA Destination Address Register 2 */
+#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Source Address Register 2 */
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC2     (DCRN_DMA2_BASE + 0x4)  /* DMA Chained Count Register 2 */
+#endif
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 2 */
+#endif
+#endif
+
+#ifdef DCRN_DMA3_BASE
+#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control Register 3 */
+#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count Register 3 */
+#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x2)  /* DMA Destination Address Register 3 */
+#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Source Address Register 3 */
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC3     (DCRN_DMA3_BASE + 0x4)  /* DMA Chained Count Register 3 */
+#endif
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 3 */
+#endif
+#endif
+
+#ifdef DCRN_DMASR_BASE
+#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
+/* don't know if these two registers always exist if scatter/gather exists */
+#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
+#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
+#endif
+#endif
+
+#ifdef DCRN_EBC_BASE
+#define DCRN_EBCCFGADR  (DCRN_EBC_BASE + 0x0)   /* Peripheral Controller Address */
+#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1)   /* Peripheral Controller Data */
+#endif
+
+#ifdef DCRN_EXIER_BASE
+#define DCRN_EXIER      (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
+#endif
+
+#ifdef DCRN_EBIMC_BASE
+#define DCRN_BRCRH0     (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
+#define DCRN_BRCRH1     (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
+#define DCRN_BRCRH2     (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
+#define DCRN_BRCRH3     (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
+#define DCRN_BRCRH4     (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
+#define DCRN_BRCRH5     (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
+#define DCRN_BRCRH6     (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
+#define DCRN_BRCRH7     (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
+#define DCRN_BRCR0      (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */
+#define DCRN_BRCR1      (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */
+#define DCRN_BRCR2      (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */
+#define DCRN_BRCR3      (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */
+#define DCRN_BRCR4      (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */
+#define DCRN_BRCR5      (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */
+#define DCRN_BRCR6      (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */
+#define DCRN_BRCR7      (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */
+#define DCRN_BEAR0      (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */
+#define DCRN_BESR0      (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */
+#define DCRN_BIUCR      (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */
+#endif
+
+#ifdef DCRN_EXISR_BASE
+#define DCRN_EXISR      (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
+#endif
+#define EXIER_CIE       0x80000000      /* Critical Interrupt Enable */
+#define EXIER_SRIE      0x08000000      /* Serial Port Rx Int. Enable */
+#define EXIER_STIE      0x04000000      /* Serial Port Tx Int. Enable */
+#define EXIER_JRIE      0x02000000      /* JTAG Serial Port Rx Int. Enable */
+#define EXIER_JTIE      0x01000000      /* JTAG Serial Port Tx Int. Enable */
+#define EXIER_D0IE      0x00800000      /* DMA Channel 0 Interrupt Enable */
+#define EXIER_D1IE      0x00400000      /* DMA Channel 1 Interrupt Enable */
+#define EXIER_D2IE      0x00200000      /* DMA Channel 2 Interrupt Enable */
+#define EXIER_D3IE      0x00100000      /* DMA Channel 3 Interrupt Enable */
+#define EXIER_E0IE      0x00000010      /* External Interrupt 0 Enable */
+#define EXIER_E1IE      0x00000008      /* External Interrupt 1 Enable */
+#define EXIER_E2IE      0x00000004      /* External Interrupt 2 Enable */
+#define EXIER_E3IE      0x00000002      /* External Interrupt 3 Enable */
+#define EXIER_E4IE      0x00000001      /* External Interrupt 4 Enable */
+
+#ifdef DCRN_IOCR_BASE
+#define DCRN_IOCR       (DCRN_IOCR_BASE + 0x0)  /* Input/Output Configuration Register */
+#endif
+#define IOCR_E0TE       0x80000000
+#define IOCR_E0LP       0x40000000
+#define IOCR_E1TE       0x20000000
+#define IOCR_E1LP       0x10000000
+#define IOCR_E2TE       0x08000000
+#define IOCR_E2LP       0x04000000
+#define IOCR_E3TE       0x02000000
+#define IOCR_E3LP       0x01000000
+#define IOCR_E4TE       0x00800000
+#define IOCR_E4LP       0x00400000
+#define IOCR_EDT        0x00080000
+#define IOCR_SOR        0x00040000
+#define IOCR_EDO        0x00008000
+#define IOCR_2XC        0x00004000
+#define IOCR_ATC        0x00002000
+#define IOCR_SPD        0x00001000
+#define IOCR_BEM        0x00000800
+#define IOCR_PTD        0x00000400
+#define IOCR_ARE        0x00000080
+#define IOCR_DRC        0x00000020
+#define IOCR_RDM(x)     (((x) & 0x3) << 3)
+#define IOCR_TCS        0x00000004
+#define IOCR_SCS        0x00000002
+#define IOCR_SPC        0x00000001
+
+#ifdef DCRN_MAL_BASE
+#define DCRN_MALCR              (DCRN_MAL_BASE + 0x0) /* MAL Configuration */
+#define DCRN_MALDBR             (DCRN_MAL_BASE + 0x3) /* Debug Register */
+#define DCRN_MALESR             (DCRN_MAL_BASE + 0x1) /* Error Status */
+#define DCRN_MALIER             (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
+#define DCRN_MALTXCARR          (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
+#define DCRN_MALTXCASR          (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
+#define DCRN_MALTXDEIR          (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
+#define DCRN_MALTXEOBISR        (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status  */
+#define DCRN_MALRXCARR          (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */
+#define DCRN_MALRXCASR          (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */
+#define DCRN_MALRXDEIR          (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */
+#define DCRN_MALRXEOBISR        (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status  */
+#define DCRN_MALRXCTP0R         (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP0R         (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R         (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALRCBS0           (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */
+#endif
+/* DCRN_MALCR */
+#define MALCR_MMSR              0x80000000/* MAL Software reset */
+#define MALCR_PLBP_1            0x00400000 /* MAL reqest priority: */
+#define MALCR_PLBP_2            0x00800000 /* lowsest is 00 */
+#define MALCR_PLBP_3            0x00C00000 /* highest */
+#define MALCR_GA                0x00200000 /* Guarded Active Bit */
+#define MALCR_OA                0x00100000 /* Ordered Active Bit */
+#define MALCR_PLBLE             0x00080000 /* PLB Lock Error Bit */
+#define MALCR_PLBLT_1           0x00040000 /* PLB Latency Timer */
+#define MALCR_PLBLT_2           0x00020000
+#define MALCR_PLBLT_3           0x00010000
+#define MALCR_PLBLT_4           0x00008000
+#define MALCR_PLBLT_DEFAULT     0x00078000 /* JSP: Is this a valid default?? */
+#define MALCR_PLBB              0x00004000 /* PLB Burst Deactivation Bit */
+#define MALCR_OPBBL             0x00000080 /* OPB Lock Bit */
+#define MALCR_EOPIE             0x00000004 /* End Of Packet Interrupt Enable */
+#define MALCR_LEA               0x00000002 /* Locked Error Active */
+#define MALCR_MSD               0x00000001 /* MAL Scroll Descriptor Bit */
+/* DCRN_MALESR */
+#define MALESR_EVB              0x80000000 /* Error Valid Bit */
+#define MALESR_CIDRX            0x40000000 /* Channel ID Receive */
+#define MALESR_DE               0x00100000 /* Descriptor Error */
+#define MALESR_OEN              0x00080000 /* OPB Non-Fullword Error */
+#define MALESR_OTE              0x00040000 /* OPB Timeout Error */
+#define MALESR_OSE              0x00020000 /* OPB Slave Error */
+#define MALESR_PEIN             0x00010000 /* PLB Bus Error Indication */
+#define MALESR_DEI              0x00000010 /* Descriptor Error Interrupt */
+#define MALESR_ONEI             0x00000008 /* OPB Non-Fullword Error Interrupt */
+#define MALESR_OTEI             0x00000004 /* OPB Timeout Error Interrupt */
+#define MALESR_OSEI             0x00000002 /* OPB Slace Error Interrupt */
+#define MALESR_PBEI             0x00000001 /* PLB Bus Error Interrupt */
+/* DCRN_MALIER */
+#define MALIER_DE               0x00000010 /* Descriptor Error Interrupt Enable */
+#define MALIER_NE               0x00000008 /* OPB Non-word Transfer Int Enable */
+#define MALIER_TE               0x00000004 /* OPB Time Out Error Interrupt Enable  */
+#define MALIER_OPBE             0x00000002 /* OPB Slave Error Interrupt Enable */
+#define MALIER_PLBE             0x00000001 /* PLB Error Interrupt Enable */
+/* DCRN_MALTXEOBISR */
+#define MALOBISR_CH0            0x80000000 /* EOB channel 1 bit */
+#define MALOBISR_CH2            0x40000000 /* EOB channel 2 bit */
+
+#ifdef DCRN_OCM0_BASE
+#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0)  /* OCM Instr Side Addr Range Compare */
+#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1)  /* OCM Instr Side Control */
+#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2)  /* OCM Data Side Addr Range Compare */
+#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3)  /* OCM Data Side Control */
+#endif
+
+#ifdef DCRN_PLB0_BASE
+#define DCRN_PLB0_BESR  (DCRN_PLB0_BASE + 0x0)
+#define DCRN_PLB0_BEAR  (DCRN_PLB0_BASE + 0x2)
+/* doesn't exist on stb03xxx? */
+#define DCRN_PLB0_ACR   (DCRN_PLB0_BASE + 0x3)
+#endif
+
+#ifdef DCRN_PLB1_BASE
+#define DCRN_PLB1_BESR  (DCRN_PLB1_BASE + 0x0)
+#define DCRN_PLB1_BEAR  (DCRN_PLB1_BASE + 0x1)
+/* doesn't exist on stb03xxx? */
+#define DCRN_PLB1_ACR   (DCRN_PLB1_BASE + 0x2)
+#endif
+
+#ifdef DCRN_PLLMR_BASE
+#define DCRN_PLLMR      (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
+#endif
+
+#ifdef DCRN_POB0_BASE
+#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
+#define DCRN_POB0_BEAR  (DCRN_POB0_BASE + 0x2)
+#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
+#endif
+
+#ifdef DCRN_SCCR_BASE
+#define DCRN_SCCR       (DCRN_SCCR_BASE + 0x0)
+#endif
+
+#ifdef DCRN_SDRAM0_BASE
+#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */
+#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */
+#endif
+
+#ifdef DCRN_UIC0_BASE
+#define DCRN_UIC0_SR    (DCRN_UIC0_BASE + 0x0)
+#define DCRN_UIC0_ER    (DCRN_UIC0_BASE + 0x2)
+#define DCRN_UIC0_CR    (DCRN_UIC0_BASE + 0x3)
+#define DCRN_UIC0_PR    (DCRN_UIC0_BASE + 0x4)
+#define DCRN_UIC0_TR    (DCRN_UIC0_BASE + 0x5)
+#define DCRN_UIC0_MSR   (DCRN_UIC0_BASE + 0x6)
+#define DCRN_UIC0_VR    (DCRN_UIC0_BASE + 0x7)
+#define DCRN_UIC0_VCR   (DCRN_UIC0_BASE + 0x8)
+#endif
+
+#ifdef DCRN_UIC1_BASE
+#define DCRN_UIC1_SR    (DCRN_UIC1_BASE + 0x0)
+#define DCRN_UIC1_SRS   (DCRN_UIC1_BASE + 0x1)
+#define DCRN_UIC1_ER    (DCRN_UIC1_BASE + 0x2)
+#define DCRN_UIC1_CR    (DCRN_UIC1_BASE + 0x3)
+#define DCRN_UIC1_PR    (DCRN_UIC1_BASE + 0x4)
+#define DCRN_UIC1_TR    (DCRN_UIC1_BASE + 0x5)
+#define DCRN_UIC1_MSR   (DCRN_UIC1_BASE + 0x6)
+#define DCRN_UIC1_VR    (DCRN_UIC1_BASE + 0x7)
+#define DCRN_UIC1_VCR   (DCRN_UIC1_BASE + 0x8)
+#endif
+
+#ifdef DCRN_SDRAM0_BASE
+#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
+#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
+#endif
+
+#ifdef DCRN_OCM0_BASE
+#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
+#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
+#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
+#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
+#endif
+
+#endif /* __ASM_IBM403_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h
new file mode 100644
index 000000000000..4e5be9e2c153
--- /dev/null
+++ b/include/asm-ppc/ibm405.h
@@ -0,0 +1,299 @@
+/*
+ * Author: Armin Kuster <akuster@mvista.com>
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM405_H__
+#define __ASM_IBM405_H__
+
+#ifdef DCRN_BE_BASE
+#define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
+#define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register */
+#endif
+/* DCRN_BESR */
+#define BESR_DSES       0x80000000      /* Data-Side Error Status */
+#define BESR_DMES       0x40000000      /* DMA Error Status */
+#define BESR_RWS        0x20000000      /* Read/Write Status */
+#define BESR_ETMASK     0x1C000000      /* Error Type */
+#define ET_PROT 0
+#define ET_PARITY       1
+#define ET_NCFG 2
+#define ET_BUSERR       4
+#define ET_BUSTO        6
+
+/* Clock and power management shifts for emacs */
+#define IBM_CPM_EMMII   0       /* Shift value for MII */
+#define IBM_CPM_EMRX    1       /* Shift value for recv */
+#define IBM_CPM_EMTX    2       /* Shift value for MAC */
+
+#ifdef DCRN_CHCR_BASE
+#define DCRN_CHCR0      (DCRN_CHCR_BASE + 0x0)  /* Chip Control Register 1 */
+#define DCRN_CHCR1      (DCRN_CHCR_BASE + 0x1)  /* Chip Control Register 2 */
+#endif
+#define CHR1_PCIPW      0x00008000      /* PCI Int enable/Peripheral Write enable */
+
+#ifdef DCRN_CHPSR_BASE
+#define DCRN_CHPSR      (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
+#endif
+
+#ifdef DCRN_CPMFR_BASE
+#define DCRN_CPMFR      (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
+#endif
+
+#ifdef DCRN_CPMSR_BASE
+#define DCRN_CPMSR      (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
+#define DCRN_CPMER      (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
+#endif
+
+#ifdef DCRN_DCP0_BASE
+/* Decompression Controller Address */
+#define DCRN_DCP0_CFGADDR       (DCRN_DCP0_BASE + 0x0)
+/* Decompression Controller Data */
+#define DCRN_DCP0_CFGDATA       (DCRN_DCP0_BASE + 0x1)
+#else
+#define DCRN_DCP0_CFGADDR       0x0
+#define DCRN_DCP0_CFGDATA       0x0
+#endif
+
+#ifdef DCRN_DMA0_BASE
+/* DMA Channel Control Register 0 */
+#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)
+#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count Register 0 */
+/* DMA Destination Address Register 0 */
+#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x2)
+/* DMA Source Address Register 0 */
+#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)
+#ifdef DCRNCAP_DMA_CC
+/* DMA Chained Count Register 0 */
+#define DCRN_DMACC0     (DCRN_DMA0_BASE + 0x4)
+#endif
+#ifdef DCRNCAP_DMA_SG
+/* DMA Scatter/Gather Descriptor Addr 0 */
+#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x4)
+#endif
+#endif
+
+#ifdef DCRN_DMA1_BASE
+/* DMA Channel Control Register 1 */
+#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)
+#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count Register 1 */
+/* DMA Destination Address Register 1 */
+#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x2)
+/* DMA Source Address Register 1 */
+#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Source Address Register 1 */
+#ifdef DCRNCAP_DMA_CC
+/* DMA Chained Count Register 1 */
+#define DCRN_DMACC1     (DCRN_DMA1_BASE + 0x4)
+#endif
+#ifdef DCRNCAP_DMA_SG
+/* DMA Scatter/Gather Descriptor Addr 1 */
+#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x4)
+#endif
+#endif
+
+#ifdef DCRN_DMA2_BASE
+#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control Register 2 */
+#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count Register 2 */
+#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x2)  /* DMA Destination Address Register 2 */
+#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Source Address Register 2 */
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC2     (DCRN_DMA2_BASE + 0x4)  /* DMA Chained Count Register 2 */
+#endif
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 2 */
+#endif
+#endif
+
+#ifdef DCRN_DMA3_BASE
+#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control Register 3 */
+#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count Register 3 */
+#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x2)  /* DMA Destination Address Register 3 */
+#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Source Address Register 3 */
+#ifdef DCRNCAP_DMA_CC
+#define DCRN_DMACC3     (DCRN_DMA3_BASE + 0x4)  /* DMA Chained Count Register 3 */
+#endif
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 3 */
+#endif
+#endif
+
+#ifdef DCRN_DMASR_BASE
+#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
+#ifdef DCRNCAP_DMA_SG
+#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
+/* don't know if these two registers always exist if scatter/gather exists */
+#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
+#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
+#endif
+#endif
+
+#ifdef DCRN_EBC_BASE
+#define DCRN_EBCCFGADR  (DCRN_EBC_BASE + 0x0)   /* Peripheral Controller Address */
+#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1)   /* Peripheral Controller Data */
+#endif
+
+#ifdef DCRN_EXIER_BASE
+#define DCRN_EXIER      (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
+#endif
+
+#ifdef DCRN_EXISR_BASE
+#define DCRN_EXISR      (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
+#endif
+
+#define EXIER_CIE       0x80000000      /* Critical Interrupt Enable */
+#define EXIER_SRIE      0x08000000      /* Serial Port Rx Int. Enable */
+#define EXIER_STIE      0x04000000      /* Serial Port Tx Int. Enable */
+#define EXIER_JRIE      0x02000000      /* JTAG Serial Port Rx Int. Enable */
+#define EXIER_JTIE      0x01000000      /* JTAG Serial Port Tx Int. Enable */
+#define EXIER_D0IE      0x00800000      /* DMA Channel 0 Interrupt Enable */
+#define EXIER_D1IE      0x00400000      /* DMA Channel 1 Interrupt Enable */
+#define EXIER_D2IE      0x00200000      /* DMA Channel 2 Interrupt Enable */
+#define EXIER_D3IE      0x00100000      /* DMA Channel 3 Interrupt Enable */
+#define EXIER_E0IE      0x00000010      /* External Interrupt 0 Enable */
+#define EXIER_E1IE      0x00000008      /* External Interrupt 1 Enable */
+#define EXIER_E2IE      0x00000004      /* External Interrupt 2 Enable */
+#define EXIER_E3IE      0x00000002      /* External Interrupt 3 Enable */
+#define EXIER_E4IE      0x00000001      /* External Interrupt 4 Enable */
+
+#ifdef DCRN_IOCR_BASE
+#define DCRN_IOCR       (DCRN_IOCR_BASE + 0x0)  /* Input/Output Configuration Register */
+#endif
+#define IOCR_E0TE       0x80000000
+#define IOCR_E0LP       0x40000000
+#define IOCR_E1TE       0x20000000
+#define IOCR_E1LP       0x10000000
+#define IOCR_E2TE       0x08000000
+#define IOCR_E2LP       0x04000000
+#define IOCR_E3TE       0x02000000
+#define IOCR_E3LP       0x01000000
+#define IOCR_E4TE       0x00800000
+#define IOCR_E4LP       0x00400000
+#define IOCR_EDT        0x00080000
+#define IOCR_SOR        0x00040000
+#define IOCR_EDO        0x00008000
+#define IOCR_2XC        0x00004000
+#define IOCR_ATC        0x00002000
+#define IOCR_SPD        0x00001000
+#define IOCR_BEM        0x00000800
+#define IOCR_PTD        0x00000400
+#define IOCR_ARE        0x00000080
+#define IOCR_DRC        0x00000020
+#define IOCR_RDM(x)     (((x) & 0x3) << 3)
+#define IOCR_TCS        0x00000004
+#define IOCR_SCS        0x00000002
+#define IOCR_SPC        0x00000001
+
+#define DCRN_MALCR(base)        (base + 0x0)    /* MAL Configuration */
+#define DCRN_MALDBR(base)       ((base) + 0x3)  /* Debug Register */
+#define DCRN_MALESR(base)       ((base) + 0x1)  /* Error Status */
+#define DCRN_MALIER(base)       ((base) + 0x2)  /* Interrupt Enable */
+#define DCRN_MALTXCARR(base)    ((base) + 0x5)  /* TX Channed Active Reset Register */
+#define DCRN_MALTXCASR(base)    ((base) + 0x4)  /* TX Channel Active Set Register */
+#define DCRN_MALTXDEIR(base)    ((base) + 0x7)  /* Tx Descriptor Error Interrupt */
+#define DCRN_MALTXEOBISR(base)  ((base) + 0x6)  /* Tx End of Buffer Interrupt Status */
+#define DCRN_MALRXCARR(base)    ((base) + 0x11) /* RX Channed Active Reset Register */
+#define DCRN_MALRXCASR(base)    ((base) + 0x10) /* RX Channel Active Set Register */
+#define DCRN_MALRXDEIR(base)    ((base) + 0x13) /* Rx Descriptor Error Interrupt */
+#define DCRN_MALRXEOBISR(base)  ((base) + 0x12) /* Rx End of Buffer Interrupt Status */
+#define DCRN_MALRXCTP0R(base)   ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base)   ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP0R(base)   ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R(base)   ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP2R(base)   ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */
+#define DCRN_MALTXCTP3R(base)   ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */
+#define DCRN_MALRCBS0(base)     ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base)     ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */
+
+ /* DCRN_MALCR */
+#define MALCR_MMSR              0x80000000      /* MAL Software reset */
+#define MALCR_PLBP_1            0x00400000      /* MAL reqest priority: */
+#define MALCR_PLBP_2            0x00800000      /* lowsest is 00 */
+#define MALCR_PLBP_3            0x00C00000      /* highest */
+#define MALCR_GA                0x00200000      /* Guarded Active Bit */
+#define MALCR_OA                0x00100000      /* Ordered Active Bit */
+#define MALCR_PLBLE             0x00080000      /* PLB Lock Error Bit */
+#define MALCR_PLBLT_1           0x00040000      /* PLB Latency Timer */
+#define MALCR_PLBLT_2           0x00020000
+#define MALCR_PLBLT_3           0x00010000
+#define MALCR_PLBLT_4           0x00008000
+#define MALCR_PLBLT_DEFAULT     0x00078000      /* JSP: Is this a valid default?? */
+#define MALCR_PLBB              0x00004000      /* PLB Burst Deactivation Bit */
+#define MALCR_OPBBL             0x00000080      /* OPB Lock Bit */
+#define MALCR_EOPIE             0x00000004      /* End Of Packet Interrupt Enable */
+#define MALCR_LEA               0x00000002      /* Locked Error Active */
+#define MALCR_MSD               0x00000001      /* MAL Scroll Descriptor Bit */
+/* DCRN_MALESR */
+#define MALESR_EVB              0x80000000      /* Error Valid Bit */
+#define MALESR_CIDRX            0x40000000      /* Channel ID Receive */
+#define MALESR_DE               0x00100000      /* Descriptor Error */
+#define MALESR_OEN              0x00080000      /* OPB Non-Fullword Error */
+#define MALESR_OTE              0x00040000      /* OPB Timeout Error */
+#define MALESR_OSE              0x00020000      /* OPB Slave Error */
+#define MALESR_PEIN             0x00010000      /* PLB Bus Error Indication */
+#define MALESR_DEI              0x00000010      /* Descriptor Error Interrupt */
+#define MALESR_ONEI             0x00000008      /* OPB Non-Fullword Error Interrupt */
+#define MALESR_OTEI             0x00000004      /* OPB Timeout Error Interrupt */
+#define MALESR_OSEI             0x00000002      /* OPB Slace Error Interrupt */
+#define MALESR_PBEI             0x00000001      /* PLB Bus Error Interrupt */
+/* DCRN_MALIER */
+#define MALIER_DE               0x00000010      /* Descriptor Error Interrupt Enable */
+#define MALIER_NE               0x00000008      /* OPB Non-word Transfer Int Enable */
+#define MALIER_TE               0x00000004      /* OPB Time Out Error Interrupt Enable */
+#define MALIER_OPBE             0x00000002      /* OPB Slave Error Interrupt Enable */
+#define MALIER_PLBE             0x00000001      /* PLB Error Interrupt Enable */
+/* DCRN_MALTXEOBISR */
+#define MALOBISR_CH0            0x80000000      /* EOB channel 1 bit */
+#define MALOBISR_CH2            0x40000000      /* EOB channel 2 bit */
+
+#ifdef DCRN_PLB0_BASE
+#define DCRN_PLB0_BESR  (DCRN_PLB0_BASE + 0x0)
+#define DCRN_PLB0_BEAR  (DCRN_PLB0_BASE + 0x2)
+/* doesn't exist on stb03xxx? */
+#define DCRN_PLB0_ACR   (DCRN_PLB0_BASE + 0x3)
+#endif
+
+#ifdef DCRN_PLB1_BASE
+#define DCRN_PLB1_BESR  (DCRN_PLB1_BASE + 0x0)
+#define DCRN_PLB1_BEAR  (DCRN_PLB1_BASE + 0x1)
+/* doesn't exist on stb03xxx? */
+#define DCRN_PLB1_ACR   (DCRN_PLB1_BASE + 0x2)
+#endif
+
+#ifdef DCRN_PLLMR_BASE
+#define DCRN_PLLMR      (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
+#endif
+
+#ifdef DCRN_POB0_BASE
+#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
+#define DCRN_POB0_BEAR  (DCRN_POB0_BASE + 0x2)
+#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
+#endif
+
+#define DCRN_UIC_SR(base)       (base + 0x0)
+#define DCRN_UIC_ER(base)       (base + 0x2)
+#define DCRN_UIC_CR(base)       (base + 0x3)
+#define DCRN_UIC_PR(base)       (base + 0x4)
+#define DCRN_UIC_TR(base)       (base + 0x5)
+#define DCRN_UIC_MSR(base)      (base + 0x6)
+#define DCRN_UIC_VR(base)       (base + 0x7)
+#define DCRN_UIC_VCR(base)      (base + 0x8)
+
+#ifdef DCRN_SDRAM0_BASE
+#define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0)        /* Memory Controller Address */
+#define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1)        /* Memory Controller Data */
+#endif
+
+#ifdef DCRN_OCM0_BASE
+#define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0)  /* OCM Instr Side Addr Range Compare */
+#define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1)  /* OCM Instr Side Control */
+#define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2)  /* OCM Data Side Addr Range Compare */
+#define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3)  /* OCM Data Side Control */
+#endif
+
+#endif                          /* __ASM_IBM405_H__ */
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
new file mode 100644
index 000000000000..87f051138b9d
--- /dev/null
+++ b/include/asm-ppc/ibm44x.h
@@ -0,0 +1,599 @@
+/*
+ * include/asm-ppc/ibm44x.h
+ *
+ * PPC44x definitions
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ *
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM44x_H__
+#define __ASM_IBM44x_H__
+
+#include <linux/config.h>
+
+#ifndef NR_BOARD_IRQS
+#define NR_BOARD_IRQS 0
+#endif
+
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+
+/* TLB entry offset/size used for pinning kernel lowmem */
+#define PPC44x_PIN_SHIFT        28
+#define PPC44x_PIN_SIZE         (1 << PPC44x_PIN_SHIFT)
+
+/* Lowest TLB slot consumed by the default pinned TLBs */
+#define PPC44x_LOW_SLOT         63
+
+/* LS 32-bits of UART0 physical address location for early serial text debug */
+#ifdef CONFIG_440SP
+#define UART0_PHYS_IO_BASE      0xf0000200
+#else
+#define UART0_PHYS_IO_BASE      0x40000200
+#endif
+
+/*
+ * XXX This 36-bit trap stuff will move somewhere in syslib/
+ * when we rework/abstract the PPC44x PCI-X handling -mdp
+ */
+
+/*
+ * Standard 4GB "page" definitions
+ */
+#ifdef CONFIG_440SP
+#define PPC44x_IO_PAGE          0x0000000100000000ULL
+#define PPC44x_PCICFG_PAGE      0x0000000900000000ULL
+#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE      0x0000000a00000000ULL
+#else
+#define PPC44x_IO_PAGE          0x0000000100000000ULL
+#define PPC44x_PCICFG_PAGE      0x0000000200000000ULL
+#define PPC44x_PCIIO_PAGE       PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE      0x0000000300000000ULL
+#endif
+
+/*
+ * 36-bit trap ranges
+ */
+#ifdef CONFIG_440SP
+#define PPC44x_IO_LO            0xf0000000UL
+#define PPC44x_IO_HI            0xf0000fffUL
+#define PPC44x_PCI0CFG_LO       0x0ec00000UL
+#define PPC44x_PCI0CFG_HI       0x0ec00007UL
+#define PPC44x_PCI1CFG_LO       0x1ec00000UL
+#define PPC44x_PCI1CFG_HI       0x1ec00007UL
+#define PPC44x_PCI2CFG_LO       0x2ec00000UL
+#define PPC44x_PCI2CFG_HI       0x2ec00007UL
+#define PPC44x_PCIMEM_LO        0x80000000UL
+#define PPC44x_PCIMEM_HI        0xdfffffffUL
+#else
+#define PPC44x_IO_LO            0x40000000UL
+#define PPC44x_IO_HI            0x40000fffUL
+#define PPC44x_PCI0CFG_LO       0x0ec00000UL
+#define PPC44x_PCI0CFG_HI       0x0ec00007UL
+#define PPC44x_PCIMEM_LO        0x80002000UL
+#define PPC44x_PCIMEM_HI        0xffffffffUL
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+#ifndef __ASSEMBLY__
+
+/*
+ * DCRN definitions
+ */
+
+
+/* CPRs (440GX and 440SP) */
+#define DCRN_CPR_CONFIG_ADDR    0xc
+#define DCRN_CPR_CONFIG_DATA    0xd
+
+#define DCRN_CPR_CLKUPD         0x0020
+#define DCRN_CPR_PLLC           0x0040
+#define DCRN_CPR_PLLD           0x0060
+#define DCRN_CPR_PRIMAD         0x0080
+#define DCRN_CPR_PRIMBD         0x00a0
+#define DCRN_CPR_OPBD           0x00c0
+#define DCRN_CPR_PERD           0x00e0
+#define DCRN_CPR_MALD           0x0100
+
+/* CPRs read/write helper macros */
+#define CPR_READ(offset) ({\
+        mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+        mfdcr(DCRN_CPR_CONFIG_DATA);})
+#define CPR_WRITE(offset, data) ({\
+        mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+        mtdcr(DCRN_CPR_CONFIG_DATA, data);})
+
+/* SDRs (440GX and 440SP) */
+#define DCRN_SDR_CONFIG_ADDR    0xe
+#define DCRN_SDR_CONFIG_DATA    0xf
+#define DCRN_SDR_PFC0           0x4100
+#define DCRN_SDR_PFC1           0x4101
+#define DCRN_SDR_PFC1_EPS       0x1c00000
+#define DCRN_SDR_PFC1_EPS_SHIFT 22
+#define DCRN_SDR_PFC1_RMII      0x02000000
+#define DCRN_SDR_MFR            0x4300
+#define DCRN_SDR_MFR_TAH0       0x80000000      /* TAHOE0 Enable */
+#define DCRN_SDR_MFR_TAH1       0x40000000      /* TAHOE1 Enable */
+#define DCRN_SDR_MFR_PCM        0x10000000      /* PPC440GP irq compat mode */
+#define DCRN_SDR_MFR_ECS        0x08000000      /* EMAC int clk */
+#define DCRN_SDR_MFR_T0TXFL     0x00080000
+#define DCRN_SDR_MFR_T0TXFH     0x00040000
+#define DCRN_SDR_MFR_T1TXFL     0x00020000
+#define DCRN_SDR_MFR_T1TXFH     0x00010000
+#define DCRN_SDR_MFR_E0TXFL     0x00008000
+#define DCRN_SDR_MFR_E0TXFH     0x00004000
+#define DCRN_SDR_MFR_E0RXFL     0x00002000
+#define DCRN_SDR_MFR_E0RXFH     0x00001000
+#define DCRN_SDR_MFR_E1TXFL     0x00000800
+#define DCRN_SDR_MFR_E1TXFH     0x00000400
+#define DCRN_SDR_MFR_E1RXFL     0x00000200
+#define DCRN_SDR_MFR_E1RXFH     0x00000100
+#define DCRN_SDR_MFR_E2TXFL     0x00000080
+#define DCRN_SDR_MFR_E2TXFH     0x00000040
+#define DCRN_SDR_MFR_E2RXFL     0x00000020
+#define DCRN_SDR_MFR_E2RXFH     0x00000010
+#define DCRN_SDR_MFR_E3TXFL     0x00000008
+#define DCRN_SDR_MFR_E3TXFH     0x00000004
+#define DCRN_SDR_MFR_E3RXFL     0x00000002
+#define DCRN_SDR_MFR_E3RXFH     0x00000001
+#define DCRN_SDR_UART0          0x0120
+#define DCRN_SDR_UART1          0x0121
+
+/* SDR read/write helper macros */
+#define SDR_READ(offset) ({\
+        mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
+        mfdcr(DCRN_SDR_CONFIG_DATA);})
+#define SDR_WRITE(offset, data) ({\
+        mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
+        mtdcr(DCRN_SDR_CONFIG_DATA,data);})
+
+/* DMA (excluding 440SP) */
+#define DCRN_DMA0_BASE          0x100
+#define DCRN_DMA1_BASE          0x108
+#define DCRN_DMA2_BASE          0x110
+#define DCRN_DMA3_BASE          0x118
+#define DCRN_DMASR_BASE         0x120
+#define DCRNCAP_DMA_SG          1       /* have DMA scatter/gather capability */
+#define DCRN_MAL_BASE           0x180
+
+/* UIC */
+#define DCRN_UIC0_BASE  0xc0
+#define DCRN_UIC1_BASE  0xd0
+#define DCRN_UIC2_BASE  0x210
+#define DCRN_UICB_BASE  0x200
+#define UIC0            DCRN_UIC0_BASE
+#define UIC1            DCRN_UIC1_BASE
+#define UIC2            DCRN_UIC2_BASE
+#define UICB            DCRN_UICB_BASE
+
+#define DCRN_UIC_SR(base)       (base + 0x0)
+#define DCRN_UIC_ER(base)       (base + 0x2)
+#define DCRN_UIC_CR(base)       (base + 0x3)
+#define DCRN_UIC_PR(base)       (base + 0x4)
+#define DCRN_UIC_TR(base)       (base + 0x5)
+#define DCRN_UIC_MSR(base)      (base + 0x6)
+#define DCRN_UIC_VR(base)       (base + 0x7)
+#define DCRN_UIC_VCR(base)      (base + 0x8)
+
+#define UIC0_UIC1NC             0x00000002
+
+#define UICB_UIC0NC             0x40000000
+#define UICB_UIC1NC             0x10000000
+#define UICB_UIC2NC             0x04000000
+
+/* 440 MAL DCRs */
+#define DCRN_MALCR(base)                (base + 0x0)    /* Configuration */
+#define DCRN_MALESR(base)               (base + 0x1)    /* Error Status */
+#define DCRN_MALIER(base)               (base + 0x2)    /* Interrupt Enable */
+#define DCRN_MALTXCASR(base)            (base + 0x4)    /* Tx Channel Active Set */
+#define DCRN_MALTXCARR(base)            (base + 0x5)    /* Tx Channel Active Reset */
+#define DCRN_MALTXEOBISR(base)          (base + 0x6)    /* Tx End of Buffer Interrupt Status */
+#define DCRN_MALTXDEIR(base)            (base + 0x7)    /* Tx Descriptor Error Interrupt */
+#define DCRN_MALRXCASR(base)            (base + 0x10)   /* Rx Channel Active Set */
+#define DCRN_MALRXCARR(base)            (base + 0x11)   /* Rx Channel Active Reset */
+#define DCRN_MALRXEOBISR(base)          (base + 0x12)   /* Rx End of Buffer Interrupt Status */
+#define DCRN_MALRXDEIR(base)            (base + 0x13)   /* Rx Descriptor Error Interrupt */
+#define DCRN_MALTXCTP0R(base)           (base + 0x20)   /* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R(base)           (base + 0x21)   /* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP2R(base)           (base + 0x22)   /* Channel Tx 2 Channel Table Pointer */
+#define DCRN_MALTXCTP3R(base)           (base + 0x23)   /* Channel Tx 3 Channel Table Pointer */
+#define DCRN_MALRXCTP0R(base)           (base + 0x40)   /* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base)           (base + 0x41)   /* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALRCBS0(base)             (base + 0x60)   /* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base)             (base + 0x61)   /* Channel Rx 1 Channel Buffer Size */
+
+/* Compatibility DCRN's */
+#define DCRN_MALRXCTP2R(base)   ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
+#define DCRN_MALRXCTP3R(base)   ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
+#define DCRN_MALTXCTP4R(base)   ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
+#define DCRN_MALTXCTP5R(base)   ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
+#define DCRN_MALTXCTP6R(base)   ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
+#define DCRN_MALTXCTP7R(base)   ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
+#define DCRN_MALRCBS2(base)     ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
+#define DCRN_MALRCBS3(base)     ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
+
+#define MALCR_MMSR              0x80000000      /* MAL Software reset */
+#define MALCR_PLBP_1            0x00400000      /* MAL reqest priority: */
+#define MALCR_PLBP_2            0x00800000      /* lowsest is 00 */
+#define MALCR_PLBP_3            0x00C00000      /* highest */
+#define MALCR_GA                0x00200000      /* Guarded Active Bit */
+#define MALCR_OA                0x00100000      /* Ordered Active Bit */
+#define MALCR_PLBLE             0x00080000      /* PLB Lock Error Bit */
+#define MALCR_PLBLT_1           0x00040000      /* PLB Latency Timer */
+#define MALCR_PLBLT_2           0x00020000
+#define MALCR_PLBLT_3           0x00010000
+#define MALCR_PLBLT_4           0x00008000
+#ifdef CONFIG_440GP
+#define MALCR_PLBLT_DEFAULT     0x00330000      /* PLB Latency Timer default */
+#else
+#define MALCR_PLBLT_DEFAULT     0x00ff0000      /* PLB Latency Timer default */
+#endif
+#define MALCR_PLBB              0x00004000      /* PLB Burst Deactivation Bit */
+#define MALCR_OPBBL             0x00000080      /* OPB Lock Bit */
+#define MALCR_EOPIE             0x00000004      /* End Of Packet Interrupt Enable */
+#define MALCR_LEA               0x00000002      /* Locked Error Active */
+#define MALCR_MSD               0x00000001      /* MAL Scroll Descriptor Bit */
+/* DCRN_MALESR */
+#define MALESR_EVB              0x80000000      /* Error Valid Bit */
+#define MALESR_CIDRX            0x40000000      /* Channel ID Receive */
+#define MALESR_DE               0x00100000      /* Descriptor Error */
+#define MALESR_OEN              0x00080000      /* OPB Non-Fullword Error */
+#define MALESR_OTE              0x00040000      /* OPB Timeout Error */
+#define MALESR_OSE              0x00020000      /* OPB Slave Error */
+#define MALESR_PEIN             0x00010000      /* PLB Bus Error Indication */
+#define MALESR_DEI              0x00000010      /* Descriptor Error Interrupt */
+#define MALESR_ONEI             0x00000008      /* OPB Non-Fullword Error Interrupt */
+#define MALESR_OTEI             0x00000004      /* OPB Timeout Error Interrupt */
+#define MALESR_OSEI             0x00000002      /* OPB Slace Error Interrupt */
+#define MALESR_PBEI             0x00000001      /* PLB Bus Error Interrupt */
+/* DCRN_MALIER */
+#define MALIER_DE               0x00000010      /* Descriptor Error Interrupt Enable */
+#define MALIER_NE               0x00000008      /* OPB Non-word Transfer Int Enable */
+#define MALIER_TE               0x00000004      /* OPB Time Out Error Interrupt Enable */
+#define MALIER_OPBE             0x00000002      /* OPB Slave Error Interrupt Enable */
+#define MALIER_PLBE             0x00000001      /* PLB Error Interrupt Enable */
+/* DCRN_MALTXEOBISR */
+#define MALOBISR_CH0            0x80000000      /* EOB channel 1 bit */
+#define MALOBISR_CH2            0x40000000      /* EOB channel 2 bit */
+
+/* 440GP/GX PLB Arbiter DCRs */
+#define DCRN_PLB0_REVID         0x082           /* PLB Arbiter Revision ID */
+#define DCRN_PLB0_ACR           0x083           /* PLB Arbiter Control */
+#define DCRN_PLB0_BESR          0x084           /* PLB Error Status */
+#define DCRN_PLB0_BEARL         0x086           /* PLB Error Address Low */
+#define DCRN_PLB0_BEAR          DCRN_PLB0_BEARL /* 40x compatibility */
+#define DCRN_PLB0_BEARH         0x087           /* PLB Error Address High */
+
+/* 440GP/GX PLB to OPB bridge DCRs */
+#define DCRN_POB0_BESR0         0x090
+#define DCRN_POB0_BESR1         0x094
+#define DCRN_POB0_BEARL         0x092
+#define DCRN_POB0_BEARH         0x093
+
+/* 440GP/GX OPB to PLB bridge DCRs */
+#define DCRN_OPB0_BSTAT         0x0a9
+#define DCRN_OPB0_BEARL         0x0aa
+#define DCRN_OPB0_BEARH         0x0ab
+
+/* 440GP Clock, PM, chip control */
+#define DCRN_CPC0_SR            0x0b0
+#define DCRN_CPC0_ER            0x0b1
+#define DCRN_CPC0_FR            0x0b2
+#define DCRN_CPC0_SYS0          0x0e0
+#define DCRN_CPC0_SYS1          0x0e1
+#define DCRN_CPC0_CUST0         0x0e2
+#define DCRN_CPC0_CUST1         0x0e3
+#define DCRN_CPC0_STRP0         0x0e4
+#define DCRN_CPC0_STRP1         0x0e5
+#define DCRN_CPC0_STRP2         0x0e6
+#define DCRN_CPC0_STRP3         0x0e7
+#define DCRN_CPC0_GPIO          0x0e8
+#define DCRN_CPC0_PLB           0x0e9
+#define DCRN_CPC0_CR1           0x0ea
+#define DCRN_CPC0_CR0           0x0eb
+#define DCRN_CPC0_MIRQ0         0x0ec
+#define DCRN_CPC0_MIRQ1         0x0ed
+#define DCRN_CPC0_JTAGID        0x0ef
+
+/* 440GP DMA controller DCRs */
+#define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)  /* DMA Channel Control 0 */
+#define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count 0 */
+#define DCRN_DMASAH0    (DCRN_DMA0_BASE + 0x2)  /* DMA Src Addr High 0 */
+#define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)  /* DMA Src Addr Low 0 */
+#define DCRN_DMADAH0    (DCRN_DMA0_BASE + 0x4)  /* DMA Dest Addr High 0 */
+#define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x5)  /* DMA Dest Addr Low 0 */
+#define DCRN_ASGH0      (DCRN_DMA0_BASE + 0x6)  /* DMA SG Desc Addr High 0 */
+#define DCRN_ASG0       (DCRN_DMA0_BASE + 0x7)  /* DMA SG Desc Addr Low 0 */
+
+#define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)  /* DMA Channel Control 1 */
+#define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count 1 */
+#define DCRN_DMASAH1    (DCRN_DMA1_BASE + 0x2)  /* DMA Src Addr High 1 */
+#define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Src Addr Low 1 */
+#define DCRN_DMADAH1    (DCRN_DMA1_BASE + 0x4)  /* DMA Dest Addr High 1 */
+#define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x5)  /* DMA Dest Addr Low 1 */
+#define DCRN_ASGH1      (DCRN_DMA1_BASE + 0x6)  /* DMA SG Desc Addr High 1 */
+#define DCRN_ASG1       (DCRN_DMA1_BASE + 0x7)  /* DMA SG Desc Addr Low 1 */
+
+#define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control 2 */
+#define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count 2 */
+#define DCRN_DMASAH2    (DCRN_DMA2_BASE + 0x2)  /* DMA Src Addr High 2 */
+#define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Src Addr Low 2 */
+#define DCRN_DMADAH2    (DCRN_DMA2_BASE + 0x4)  /* DMA Dest Addr High 2 */
+#define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x5)  /* DMA Dest Addr Low 2 */
+#define DCRN_ASGH2      (DCRN_DMA2_BASE + 0x6)  /* DMA SG Desc Addr High 2 */
+#define DCRN_ASG2       (DCRN_DMA2_BASE + 0x7)  /* DMA SG Desc Addr Low 2 */
+
+#define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control 3 */
+#define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count 3 */
+#define DCRN_DMASAH3    (DCRN_DMA3_BASE + 0x2)  /* DMA Src Addr High 3 */
+#define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Src Addr Low 3 */
+#define DCRN_DMADAH3    (DCRN_DMA3_BASE + 0x4)  /* DMA Dest Addr High 3 */
+#define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x5)  /* DMA Dest Addr Low 3 */
+#define DCRN_ASGH3      (DCRN_DMA3_BASE + 0x6)  /* DMA SG Desc Addr High 3 */
+#define DCRN_ASG3       (DCRN_DMA3_BASE + 0x7)  /* DMA SG Desc Addr Low 3 */
+
+#define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
+#define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
+#define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
+#define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
+
+/* 440GP/440GX SDRAM controller DCRs */
+#define DCRN_SDRAM0_CFGADDR             0x010
+#define DCRN_SDRAM0_CFGDATA             0x011
+
+#define SDRAM0_B0CR     0x40
+#define SDRAM0_B1CR     0x44
+#define SDRAM0_B2CR     0x48
+#define SDRAM0_B3CR     0x4c
+
+#define SDRAM_CONFIG_BANK_ENABLE        0x00000001
+#define SDRAM_CONFIG_SIZE_MASK          0x000e0000
+#define SDRAM_CONFIG_BANK_SIZE(reg)     ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
+#define SDRAM_CONFIG_SIZE_8M            0x00000001
+#define SDRAM_CONFIG_SIZE_16M           0x00000002
+#define SDRAM_CONFIG_SIZE_32M           0x00000003
+#define SDRAM_CONFIG_SIZE_64M           0x00000004
+#define SDRAM_CONFIG_SIZE_128M          0x00000005
+#define SDRAM_CONFIG_SIZE_256M          0x00000006
+#define SDRAM_CONFIG_SIZE_512M          0x00000007
+#define PPC44x_MEM_SIZE_8M              0x00800000
+#define PPC44x_MEM_SIZE_16M             0x01000000
+#define PPC44x_MEM_SIZE_32M             0x02000000
+#define PPC44x_MEM_SIZE_64M             0x04000000
+#define PPC44x_MEM_SIZE_128M            0x08000000
+#define PPC44x_MEM_SIZE_256M            0x10000000
+#define PPC44x_MEM_SIZE_512M            0x20000000
+#define PPC44x_MEM_SIZE_1G              0x40000000
+#define PPC44x_MEM_SIZE_2G              0x80000000
+
+/* 440SP memory controller DCRs */
+#define DCRN_MQ0_BS0BAS                 0x40
+#define DCRN_MQ0_BS1BAS                 0x41
+
+#define MQ0_CONFIG_SIZE_MASK            0x0000fff0
+#define MQ0_CONFIG_SIZE_8M              0x0000ffc0
+#define MQ0_CONFIG_SIZE_16M             0x0000ff80
+#define MQ0_CONFIG_SIZE_32M             0x0000ff00
+#define MQ0_CONFIG_SIZE_64M             0x0000fe00
+#define MQ0_CONFIG_SIZE_128M            0x0000fc00
+#define MQ0_CONFIG_SIZE_256M            0x0000f800
+#define MQ0_CONFIG_SIZE_512M            0x0000f000
+#define MQ0_CONFIG_SIZE_1G              0x0000e000
+#define MQ0_CONFIG_SIZE_2G              0x0000c000
+
+/* Internal SRAM Controller 440GX/440SP */
+#ifdef CONFIG_440SP
+#define DCRN_SRAM0_BASE         0x100
+#else /* 440GX */
+#define DCRN_SRAM0_BASE         0x000
+#endif
+
+#define DCRN_SRAM0_SB0CR        (DCRN_SRAM0_BASE + 0x020)
+#define DCRN_SRAM0_SB1CR        (DCRN_SRAM0_BASE + 0x021)
+#define DCRN_SRAM0_SB2CR        (DCRN_SRAM0_BASE + 0x022)
+#define DCRN_SRAM0_SB3CR        (DCRN_SRAM0_BASE + 0x023)
+#define  SRAM_SBCR_BAS0         0x80000000
+#define  SRAM_SBCR_BAS1         0x80010000
+#define  SRAM_SBCR_BAS2         0x80020000
+#define  SRAM_SBCR_BAS3         0x80030000
+#define  SRAM_SBCR_BU_MASK      0x00000180
+#define  SRAM_SBCR_BS_64KB      0x00000800
+#define  SRAM_SBCR_BU_RO        0x00000080
+#define  SRAM_SBCR_BU_RW        0x00000180
+#define DCRN_SRAM0_BEAR         (DCRN_SRAM0_BASE + 0x024)
+#define DCRN_SRAM0_BESR0        (DCRN_SRAM0_BASE + 0x025)
+#define DCRN_SRAM0_BESR1        (DCRN_SRAM0_BASE + 0x026)
+#define DCRN_SRAM0_PMEG         (DCRN_SRAM0_BASE + 0x027)
+#define DCRN_SRAM0_CID          (DCRN_SRAM0_BASE + 0x028)
+#define DCRN_SRAM0_REVID        (DCRN_SRAM0_BASE + 0x029)
+#define DCRN_SRAM0_DPC          (DCRN_SRAM0_BASE + 0x02a)
+#define  SRAM_DPC_ENABLE        0x80000000
+
+/* L2 Cache Controller 440GX/440SP */
+#define DCRN_L2C0_CFG           0x030
+#define  L2C_CFG_L2M            0x80000000
+#define  L2C_CFG_ICU            0x40000000
+#define  L2C_CFG_DCU            0x20000000
+#define  L2C_CFG_DCW_MASK       0x1e000000
+#define  L2C_CFG_TPC            0x01000000
+#define  L2C_CFG_CPC            0x00800000
+#define  L2C_CFG_FRAN           0x00200000
+#define  L2C_CFG_SS_MASK        0x00180000
+#define  L2C_CFG_SS_256         0x00000000
+#define  L2C_CFG_CPIM           0x00040000
+#define  L2C_CFG_TPIM           0x00020000
+#define  L2C_CFG_LIM            0x00010000
+#define  L2C_CFG_PMUX_MASK      0x00007000
+#define  L2C_CFG_PMUX_SNP       0x00000000
+#define  L2C_CFG_PMUX_IF        0x00001000
+#define  L2C_CFG_PMUX_DF        0x00002000
+#define  L2C_CFG_PMUX_DS        0x00003000
+#define  L2C_CFG_PMIM           0x00000800
+#define  L2C_CFG_TPEI           0x00000400
+#define  L2C_CFG_CPEI           0x00000200
+#define  L2C_CFG_NAM            0x00000100
+#define  L2C_CFG_SMCM           0x00000080
+#define  L2C_CFG_NBRM           0x00000040
+#define DCRN_L2C0_CMD           0x031
+#define  L2C_CMD_CLR            0x80000000
+#define  L2C_CMD_DIAG           0x40000000
+#define  L2C_CMD_INV            0x20000000
+#define  L2C_CMD_CCP            0x10000000
+#define  L2C_CMD_CTE            0x08000000
+#define  L2C_CMD_STRC           0x04000000
+#define  L2C_CMD_STPC           0x02000000
+#define  L2C_CMD_RPMC           0x01000000
+#define  L2C_CMD_HCC            0x00800000
+#define DCRN_L2C0_ADDR          0x032
+#define DCRN_L2C0_DATA          0x033
+#define DCRN_L2C0_SR            0x034
+#define  L2C_SR_CC              0x80000000
+#define  L2C_SR_CPE             0x40000000
+#define  L2C_SR_TPE             0x20000000
+#define  L2C_SR_LRU             0x10000000
+#define  L2C_SR_PCS             0x08000000
+#define DCRN_L2C0_REVID         0x035
+#define DCRN_L2C0_SNP0          0x036
+#define DCRN_L2C0_SNP1          0x037
+#define  L2C_SNP_BA_MASK        0xffff0000
+#define  L2C_SNP_SSR_MASK       0x0000f000
+#define  L2C_SNP_SSR_32G        0x0000f000
+#define  L2C_SNP_ESR            0x00000800
+
+/*
+ * PCI-X definitions
+ */
+#define PCIX0_CFGA              0x0ec00000UL
+#define PCIX1_CFGA              0x1ec00000UL
+#define PCIX2_CFGA              0x2ec00000UL
+#define PCIX0_CFGD              0x0ec00004UL
+#define PCIX1_CFGD              0x1ec00004UL
+#define PCIX2_CFGD              0x2ec00004UL
+
+#define PCIX0_IO_BASE           0x0000000908000000ULL
+#define PCIX1_IO_BASE           0x0000000908000000ULL
+#define PCIX2_IO_BASE           0x0000000908000000ULL
+#define PCIX_IO_SIZE            0x00010000
+
+#ifdef CONFIG_440SP
+#define PCIX0_REG_BASE          0x000000090ec80000ULL
+#else
+#define PCIX0_REG_BASE          0x000000020ec80000ULL
+#endif
+#define PCIX_REG_OFFSET         0x10000000
+#define PCIX_REG_SIZE           0x200
+
+#define PCIX0_VENDID            0x000
+#define PCIX0_DEVID             0x002
+#define PCIX0_COMMAND           0x004
+#define PCIX0_STATUS            0x006
+#define PCIX0_REVID             0x008
+#define PCIX0_CLS               0x009
+#define PCIX0_CACHELS           0x00c
+#define PCIX0_LATTIM            0x00d
+#define PCIX0_HDTYPE            0x00e
+#define PCIX0_BIST              0x00f
+#define PCIX0_BAR0L             0x010
+#define PCIX0_BAR0H             0x014
+#define PCIX0_BAR1              0x018
+#define PCIX0_BAR2L             0x01c
+#define PCIX0_BAR2H             0x020
+#define PCIX0_BAR3              0x024
+#define PCIX0_CISPTR            0x028
+#define PCIX0_SBSYSVID          0x02c
+#define PCIX0_SBSYSID           0x02e
+#define PCIX0_EROMBA            0x030
+#define PCIX0_CAP               0x034
+#define PCIX0_RES0              0x035
+#define PCIX0_RES1              0x036
+#define PCIX0_RES2              0x038
+#define PCIX0_INTLN             0x03c
+#define PCIX0_INTPN             0x03d
+#define PCIX0_MINGNT            0x03e
+#define PCIX0_MAXLTNCY          0x03f
+#define PCIX0_BRDGOPT1          0x040
+#define PCIX0_BRDGOPT2          0x044
+#define PCIX0_ERREN             0x050
+#define PCIX0_ERRSTS            0x054
+#define PCIX0_PLBBESR           0x058
+#define PCIX0_PLBBEARL          0x05c
+#define PCIX0_PLBBEARH          0x060
+#define PCIX0_POM0LAL           0x068
+#define PCIX0_POM0LAH           0x06c
+#define PCIX0_POM0SA            0x070
+#define PCIX0_POM0PCIAL         0x074
+#define PCIX0_POM0PCIAH         0x078
+#define PCIX0_POM1LAL           0x07c
+#define PCIX0_POM1LAH           0x080
+#define PCIX0_POM1SA            0x084
+#define PCIX0_POM1PCIAL         0x088
+#define PCIX0_POM1PCIAH         0x08c
+#define PCIX0_POM2SA            0x090
+#define PCIX0_PIM0SAL           0x098
+#define PCIX0_PIM0SA            PCIX0_PIM0SAL
+#define PCIX0_PIM0LAL           0x09c
+#define PCIX0_PIM0LAH           0x0a0
+#define PCIX0_PIM1SA            0x0a4
+#define PCIX0_PIM1LAL           0x0a8
+#define PCIX0_PIM1LAH           0x0ac
+#define PCIX0_PIM2SAL           0x0b0
+#define PCIX0_PIM2SA            PCIX0_PIM2SAL
+#define PCIX0_PIM2LAL           0x0b4
+#define PCIX0_PIM2LAH           0x0b8
+#define PCIX0_OMCAPID           0x0c0
+#define PCIX0_OMNIPTR           0x0c1
+#define PCIX0_OMMC              0x0c2
+#define PCIX0_OMMA              0x0c4
+#define PCIX0_OMMUA             0x0c8
+#define PCIX0_OMMDATA           0x0cc
+#define PCIX0_OMMEOI            0x0ce
+#define PCIX0_PMCAPID           0x0d0
+#define PCIX0_PMNIPTR           0x0d1
+#define PCIX0_PMC               0x0d2
+#define PCIX0_PMCSR             0x0d4
+#define PCIX0_PMCSRBSE          0x0d6
+#define PCIX0_PMDATA            0x0d7
+#define PCIX0_PMSCRR            0x0d8
+#define PCIX0_CAPID             0x0dc
+#define PCIX0_NIPTR             0x0dd
+#define PCIX0_CMD               0x0de
+#define PCIX0_STS               0x0e0
+#define PCIX0_IDR               0x0e4
+#define PCIX0_CID               0x0e8
+#define PCIX0_RID               0x0ec
+#define PCIX0_PIM0SAH           0x0f8
+#define PCIX0_PIM2SAH           0x0fc
+#define PCIX0_MSGIL             0x100
+#define PCIX0_MSGIH             0x104
+#define PCIX0_MSGOL             0x108
+#define PCIX0_MSGOH             0x10c
+#define PCIX0_IM                0x1f8
+
+#define IIC_OWN                 0x55
+#define IIC_CLOCK               50
+
+#undef NR_UICS
+#ifdef CONFIG_440GX
+#define NR_UICS 3
+#else
+#define NR_UICS 2
+#endif
+
+#include <asm/ibm4xx.h>
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_IBM44x_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
new file mode 100644
index 000000000000..35260afa33a9
--- /dev/null
+++ b/include/asm-ppc/ibm4xx.h
@@ -0,0 +1,124 @@
+/*
+ *
+ *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ *
+ *    Module name: ibm4xx.h
+ *
+ *    Description:
+ *      A generic include file which pulls in appropriate include files
+ *      for specific board types based on configuration settings.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM4XX_H__
+#define __ASM_IBM4XX_H__
+
+#include <linux/config.h>
+#include <asm/types.h>
+
+#ifdef CONFIG_40x
+
+#if defined(CONFIG_ASH)
+#include <platforms/4xx/ash.h>
+#endif
+
+#if defined(CONFIG_BUBINGA)
+#include <platforms/4xx/bubinga.h>
+#endif
+
+#if defined(CONFIG_CPCI405)
+#include <platforms/4xx/cpci405.h>
+#endif
+
+#if defined(CONFIG_EP405)
+#include <platforms/4xx/ep405.h>
+#endif
+
+#if defined(CONFIG_OAK)
+#include <platforms/4xx/oak.h>
+#endif
+
+#if defined(CONFIG_REDWOOD_4)
+#include <platforms/4xx/redwood.h>
+#endif
+
+#if defined(CONFIG_REDWOOD_5)
+#include <platforms/4xx/redwood5.h>
+#endif
+
+#if defined(CONFIG_REDWOOD_6)
+#include <platforms/4xx/redwood6.h>
+#endif
+
+#if defined(CONFIG_SYCAMORE)
+#include <platforms/4xx/sycamore.h>
+#endif
+
+#if defined(CONFIG_WALNUT)
+#include <platforms/4xx/walnut.h>
+#endif
+
+#if defined(CONFIG_XILINX_ML300)
+#include <platforms/4xx/xilinx_ml300.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_40x
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern bd_t __res;
+#endif
+
+void ppc4xx_setup_arch(void);
+void ppc4xx_map_io(void);
+void ppc4xx_init_IRQ(void);
+void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
+                 unsigned long r6, unsigned long r7);
+#endif
+
+#ifndef PPC4xx_MACHINE_NAME
+#define PPC4xx_MACHINE_NAME     "Unidentified 4xx class"
+#endif
+
+
+/* IO_BASE is for PCI I/O.
+ * ISA not supported, just here to resolve copilation.
+ */
+
+#ifndef _IO_BASE
+#define _IO_BASE        0xe8000000      /* The PCI address window */
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#elif CONFIG_44x
+
+#if defined(CONFIG_EBONY)
+#include <platforms/4xx/ebony.h>
+#endif
+
+#if defined(CONFIG_LUAN)
+#include <platforms/4xx/luan.h>
+#endif
+
+#if defined(CONFIG_OCOTEA)
+#include <platforms/4xx/ocotea.h>
+#endif
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_40x
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern bd_t __res;
+#endif
+#endif
+#endif /* CONFIG_40x */
+
+#endif /* __ASM_IBM4XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
new file mode 100644
index 000000000000..8c61d93043af
--- /dev/null
+++ b/include/asm-ppc/ibm_ocp.h
@@ -0,0 +1,163 @@
+/*
+ * ibm_ocp.h
+ *
+ *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *          Mipsys - France
+ *
+ *          Derived from work (c) Armin Kuster akuster@pacbell.net
+ *
+ *          Additional support and port to 2.6 LDM/sysfs by
+ *          Matt Porter <mporter@kernel.crashing.org>
+ *          Copyright 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __IBM_OCP_H__
+#define __IBM_OCP_H__
+
+#include <asm/types.h>
+
+/*
+ * IBM 4xx OCP system information
+ */
+struct ocp_sys_info_data {
+        int     opb_bus_freq;   /* OPB Bus Frequency (Hz) */
+        int     ebc_bus_freq;   /* EBC Bus Frequency (Hz) */
+};
+
+extern struct ocp_sys_info_data ocp_sys_info;
+
+/*
+ * EMAC additional data and sysfs support
+ *
+ * Note about mdio_idx: When you have a zmii, it's usually
+ * not necessary, it covers the case of the 405EP which has
+ * the MDIO lines on EMAC0 only
+ *
+ * Note about phy_map: Per EMAC map of PHY ids which should
+ * be probed by emac_probe. Different EMACs can have
+ * overlapping maps.
+ *
+ * Note, this map uses inverse logic for bits:
+ *  0 - id should be probed
+ *  1 - id should be ignored
+ *
+ * Default value of 0x00000000 - will result in usual
+ * auto-detection logic.
+ *
+ */
+
+struct ocp_func_emac_data {
+        int     rgmii_idx;      /* RGMII device index or -1 */
+        int     rgmii_mux;      /* RGMII input of this EMAC */
+        int     zmii_idx;       /* ZMII device index or -1 */
+        int     zmii_mux;       /* ZMII input of this EMAC */
+        int     mal_idx;        /* MAL device index */
+        int     mal_rx_chan;    /* MAL rx channel number */
+        int     mal_tx_chan;    /* MAL tx channel number */
+        int     wol_irq;        /* WOL interrupt */
+        int     mdio_idx;       /* EMAC idx of MDIO master or -1 */
+        int     tah_idx;        /* TAH device index or -1 */
+        int     jumbo;          /* Jumbo frames capable flag */
+        int     phy_mode;       /* PHY type or configurable mode */
+        u8      mac_addr[6];    /* EMAC mac address */
+        u32     phy_map;        /* EMAC phy map */
+};
+
+/* Sysfs support */
+#define OCP_SYSFS_EMAC_DATA()                                           \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)      \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)      \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)       \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)   \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)   \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)       \
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)      \
+                                                                        \
+void ocp_show_emac_data(struct device *dev)                             \
+{                                                                       \
+        device_create_file(dev, &dev_attr_emac_zmii_idx);               \
+        device_create_file(dev, &dev_attr_emac_zmii_mux);               \
+        device_create_file(dev, &dev_attr_emac_mal_idx);                \
+        device_create_file(dev, &dev_attr_emac_mal_rx_chan);            \
+        device_create_file(dev, &dev_attr_emac_mal_tx_chan);            \
+        device_create_file(dev, &dev_attr_emac_wol_irq);                \
+        device_create_file(dev, &dev_attr_emac_mdio_idx);               \
+}
+
+#ifdef CONFIG_40x
+/*
+ * Helper function to copy MAC addresses from the bd_t to OCP EMAC
+ * additions.
+ *
+ * The range of EMAC indices (inclusive) to be copied are the arguments.
+ */
+static inline void ibm_ocp_set_emac(int start, int end)
+{
+        int i;
+        struct ocp_def *def;
+
+        /* Copy MAC addresses to EMAC additions */
+        for (i=start; i<=end; i++) {
+                def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
+                memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
+                                &__res.bi_enetaddr[i],
+                                6);
+        }
+}
+#endif
+
+/*
+ * MAL additional data and sysfs support
+ */
+struct ocp_func_mal_data {
+        int     num_tx_chans;   /* Number of TX channels */
+        int     num_rx_chans;   /* Number of RX channels */
+        int     txeob_irq;      /* TX End Of Buffer IRQ  */
+        int     rxeob_irq;      /* RX End Of Buffer IRQ  */
+        int     txde_irq;       /* TX Descriptor Error IRQ */
+        int     rxde_irq;       /* RX Descriptor Error IRQ */
+        int     serr_irq;       /* MAL System Error IRQ    */
+};
+
+#define OCP_SYSFS_MAL_DATA()                                            \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans)    \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans)    \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq)       \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq)       \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq)        \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq)        \
+OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq)        \
+                                                                        \
+void ocp_show_mal_data(struct device *dev)                              \
+{                                                                       \
+        device_create_file(dev, &dev_attr_mal_num_tx_chans);            \
+        device_create_file(dev, &dev_attr_mal_num_rx_chans);            \
+        device_create_file(dev, &dev_attr_mal_txeob_irq);               \
+        device_create_file(dev, &dev_attr_mal_rxeob_irq);               \
+        device_create_file(dev, &dev_attr_mal_txde_irq);                \
+        device_create_file(dev, &dev_attr_mal_rxde_irq);                \
+        device_create_file(dev, &dev_attr_mal_serr_irq);                \
+}
+
+/*
+ * IIC additional data and sysfs support
+ */
+struct ocp_func_iic_data {
+        int     fast_mode;      /* IIC fast mode enabled */
+};
+
+#define OCP_SYSFS_IIC_DATA()                                            \
+OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)       \
+                                                                        \
+void ocp_show_iic_data(struct device *dev)                              \
+{                                                                       \
+        device_create_file(dev, &dev_attr_iic_fast_mode);                       \
+}
+#endif /* __IBM_OCP_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h
new file mode 100644
index 000000000000..a81ab6144358
--- /dev/null
+++ b/include/asm-ppc/ibm_ocp_pci.h
@@ -0,0 +1,32 @@
+/*
+ * Author: Armin Kuster <akuster@mvista.com>
+ *
+ * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IBM_OCP_PCI_H__
+#define __ASM_IBM_OCP_PCI_H__
+
+/* PCI 32 */
+
+struct pmm_regs {
+        u32 la;
+        u32 ma;
+        u32 pcila;
+        u32 pciha;
+};
+
+typedef struct pcil0_regs {
+        struct pmm_regs pmm[3];
+        u32 ptm1ms;
+        u32 ptm1la;
+        u32 ptm2ms;
+        u32 ptm2la;
+} pci0_t;
+
+#endif                          /* __ASM_IBM_OCP_PCI_H__ */
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ide.h b/include/asm-ppc/ide.h
new file mode 100644
index 000000000000..7d6e6599fac4
--- /dev/null
+++ b/include/asm-ppc/ide.h
@@ -0,0 +1,78 @@
+/*
+ *  linux/include/asm-ppc/ide.h
+ *
+ *  Copyright (C) 1994-1996 Linus Torvalds & authors */
+
+/*
+ *  This file contains the ppc architecture specific IDE code.
+ */
+
+#ifndef __ASMPPC_IDE_H
+#define __ASMPPC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <linux/sched.h>
+#include <asm/mpc8xx.h>
+
+#ifndef MAX_HWIFS
+#define MAX_HWIFS       8
+#endif
+
+#include <linux/config.h>
+#include <linux/hdreg.h>
+#include <linux/ioport.h>
+#include <asm/io.h>
+
+extern void __ide_mm_insw(void __iomem *port, void *addr, u32 count);
+extern void __ide_mm_outsw(void __iomem *port, void *addr, u32 count);
+extern void __ide_mm_insl(void __iomem *port, void *addr, u32 count);
+extern void __ide_mm_outsl(void __iomem *port, void *addr, u32 count);
+
+struct ide_machdep_calls {
+        int         (*default_irq)(unsigned long base);
+        unsigned long (*default_io_base)(int index);
+        void        (*ide_init_hwif)(hw_regs_t *hw,
+                                     unsigned long data_port,
+                                     unsigned long ctrl_port,
+                                     int *irq);
+};
+
+extern struct ide_machdep_calls ppc_ide_md;
+
+#undef  SUPPORT_SLOW_DATA_PORTS
+#define SUPPORT_SLOW_DATA_PORTS 0
+
+#define IDE_ARCH_OBSOLETE_DEFAULTS
+
+static __inline__ int ide_default_irq(unsigned long base)
+{
+        if (ppc_ide_md.default_irq)
+                return ppc_ide_md.default_irq(base);
+        return 0;
+}
+
+static __inline__ unsigned long ide_default_io_base(int index)
+{
+        if (ppc_ide_md.default_io_base)
+                return ppc_ide_md.default_io_base(index);
+        return 0;
+}
+
+#define IDE_ARCH_OBSOLETE_INIT
+#define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
+
+#ifdef CONFIG_PCI
+#define ide_init_default_irq(base)      (0)
+#else
+#define ide_init_default_irq(base)      ide_default_irq(base)
+#endif
+
+#if (defined CONFIG_APUS || defined CONFIG_BLK_DEV_MPC8xx_IDE )
+#define IDE_ARCH_ACK_INTR  1
+#define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1)
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMPPC_IDE_H */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
new file mode 100644
index 000000000000..50fb5e47094a
--- /dev/null
+++ b/include/asm-ppc/immap_85xx.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-ppc/immap_85xx.h
+ *
+ * MPC85xx Internal Memory Map
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_IMMAP_85XX_H__
+#define __ASM_IMMAP_85XX_H__
+
+/* Eventually this should define all the IO block registers in 85xx */
+
+/* PCI Registers */
+typedef struct ccsr_pci {
+        uint    cfg_addr;       /* 0x.000 - PCI Configuration Address Register */
+        uint    cfg_data;       /* 0x.004 - PCI Configuration Data Register */
+        uint    int_ack;        /* 0x.008 - PCI Interrupt Acknowledge Register */
+        char    res1[3060];
+        uint    potar0;         /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
+        uint    potear0;        /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
+        uint    powbar0;        /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
+        char    res2[4];
+        uint    powar0;         /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
+        char    res3[12];
+        uint    potar1;         /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
+        uint    potear1;        /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
+        uint    powbar1;        /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
+        char    res4[4];
+        uint    powar1;         /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
+        char    res5[12];
+        uint    potar2;         /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
+        uint    potear2;        /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
+        uint    powbar2;        /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
+        char    res6[4];
+        uint    powar2;         /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
+        char    res7[12];
+        uint    potar3;         /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
+        uint    potear3;        /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
+        uint    powbar3;        /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
+        char    res8[4];
+        uint    powar3;         /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
+        char    res9[12];
+        uint    potar4;         /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
+        uint    potear4;        /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
+        uint    powbar4;        /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
+        char    res10[4];
+        uint    powar4;         /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
+        char    res11[268];
+        uint    pitar3;         /* 0x.da0 - PCI Inbound Translation Address Register 3  */
+        char    res12[4];
+        uint    piwbar3;        /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
+        uint    piwbear3;       /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
+        uint    piwar3;         /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
+        char    res13[12];
+        uint    pitar2;         /* 0x.dc0 - PCI Inbound Translation Address Register 2  */
+        char    res14[4];
+        uint    piwbar2;        /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
+        uint    piwbear2;       /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
+        uint    piwar2;         /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
+        char    res15[12];
+        uint    pitar1;         /* 0x.de0 - PCI Inbound Translation Address Register 1  */
+        char    res16[4];
+        uint    piwbar1;        /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
+        char    res17[4];
+        uint    piwar1;         /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
+        char    res18[12];
+        uint    err_dr;         /* 0x.e00 - PCI Error Detect Register */
+        uint    err_cap_dr;     /* 0x.e04 - PCI Error Capture Disable Register */
+        uint    err_en;         /* 0x.e08 - PCI Error Enable Register */
+        uint    err_attrib;     /* 0x.e0c - PCI Error Attributes Capture Register */
+        uint    err_addr;       /* 0x.e10 - PCI Error Address Capture Register */
+        uint    err_ext_addr;   /* 0x.e14 - PCI Error Extended Address Capture Register */
+        uint    err_dl;         /* 0x.e18 - PCI Error Data Low Capture Register */
+        uint    err_dh;         /* 0x.e1c - PCI Error Data High Capture Register */
+        uint    gas_timr;       /* 0x.e20 - PCI Gasket Timer Register */
+        uint    pci_timr;       /* 0x.e24 - PCI Timer Register */
+        char    res19[472];
+} ccsr_pci_t;
+
+/* Global Utility Registers */
+typedef struct ccsr_guts {
+        uint    porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
+        uint    porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
+        uint    porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
+        uint    pordevsr;       /* 0x.000c - POR I/O Device Status Register */
+        uint    pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
+        char    res1[12];
+        uint    gpporcr;        /* 0x.0020 - General-Purpose POR Configuration Register */
+        char    res2[12];
+        uint    gpiocr;         /* 0x.0030 - GPIO Control Register */
+        char    res3[12];
+        uint    gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
+        char    res4[12];
+        uint    gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
+        char    res5[12];
+        uint    pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
+        char    res6[12];
+        uint    devdisr;        /* 0x.0070 - Device Disable Control */
+        char    res7[12];
+        uint    powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
+        char    res8[12];
+        uint    mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
+        char    res9[12];
+        uint    pvr;            /* 0x.00a0 - Processor Version Register */
+        uint    svr;            /* 0x.00a4 - System Version Register */
+        char    res10[3416];
+        uint    clkocr;         /* 0x.0e00 - Clock Out Select Register */
+        char    res11[12];
+        uint    ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
+        char    res12[12];
+        uint    lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
+        char    res13[61916];
+} ccsr_guts_t;
+
+#endif /* __ASM_IMMAP_85XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h
new file mode 100644
index 000000000000..3c23d9cb47a6
--- /dev/null
+++ b/include/asm-ppc/immap_cpm2.h
@@ -0,0 +1,648 @@
+/*
+ * CPM2 Internal Memory Map
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * The Internal Memory Map for devices with CPM2 on them.  This
+ * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
+ * 8560). 
+ */
+#ifdef __KERNEL__
+#ifndef __IMMAP_CPM2__
+#define __IMMAP_CPM2__
+
+/* System configuration registers.
+*/
+typedef struct sys_82xx_conf {
+        u32     sc_siumcr;
+        u32     sc_sypcr;
+        u8      res1[6];
+        u16     sc_swsr;
+        u8      res2[20];
+        u32     sc_bcr;
+        u8      sc_ppc_acr;
+        u8      res3[3];
+        u32     sc_ppc_alrh;
+        u32     sc_ppc_alrl;
+        u8      sc_lcl_acr;
+        u8      res4[3];
+        u32     sc_lcl_alrh;
+        u32     sc_lcl_alrl;
+        u32     sc_tescr1;
+        u32     sc_tescr2;
+        u32     sc_ltescr1;
+        u32     sc_ltescr2;
+        u32     sc_pdtea;
+        u8      sc_pdtem;
+        u8      res5[3];
+        u32     sc_ldtea;
+        u8      sc_ldtem;
+        u8      res6[163];
+} sysconf_82xx_cpm2_t;
+
+typedef struct sys_85xx_conf {
+        u32     sc_cear;
+        u16     sc_ceer;
+        u16     sc_cemr;
+        u8      res1[70];
+        u32     sc_smaer;
+        u8      res2[4];
+        u32     sc_smevr;
+        u32     sc_smctr;
+        u32     sc_lmaer;
+        u8      res3[4];
+        u32     sc_lmevr;
+        u32     sc_lmctr;
+        u8      res4[144];
+} sysconf_85xx_cpm2_t;
+
+typedef union sys_conf {
+        sysconf_82xx_cpm2_t     siu_82xx;
+        sysconf_85xx_cpm2_t     siu_85xx;
+} sysconf_cpm2_t;
+
+
+
+/* Memory controller registers.
+*/
+typedef struct  mem_ctlr {
+        u32     memc_br0;
+        u32     memc_or0;
+        u32     memc_br1;
+        u32     memc_or1;
+        u32     memc_br2;
+        u32     memc_or2;
+        u32     memc_br3;
+        u32     memc_or3;
+        u32     memc_br4;
+        u32     memc_or4;
+        u32     memc_br5;
+        u32     memc_or5;
+        u32     memc_br6;
+        u32     memc_or6;
+        u32     memc_br7;
+        u32     memc_or7;
+        u32     memc_br8;
+        u32     memc_or8;
+        u32     memc_br9;
+        u32     memc_or9;
+        u32     memc_br10;
+        u32     memc_or10;
+        u32     memc_br11;
+        u32     memc_or11;
+        u8      res1[8];
+        u32     memc_mar;
+        u8      res2[4];
+        u32     memc_mamr;
+        u32     memc_mbmr;
+        u32     memc_mcmr;
+        u8      res3[8];
+        u16     memc_mptpr;
+        u8      res4[2];
+        u32     memc_mdr;
+        u8      res5[4];
+        u32     memc_psdmr;
+        u32     memc_lsdmr;
+        u8      memc_purt;
+        u8      res6[3];
+        u8      memc_psrt;
+        u8      res7[3];
+        u8      memc_lurt;
+        u8      res8[3];
+        u8      memc_lsrt;
+        u8      res9[3];
+        u32     memc_immr;
+        u32     memc_pcibr0;
+        u32     memc_pcibr1;
+        u8      res10[16];
+        u32     memc_pcimsk0;
+        u32     memc_pcimsk1;
+        u8      res11[52];
+} memctl_cpm2_t;
+
+/* System Integration Timers.
+*/
+typedef struct  sys_int_timers {
+        u8      res1[32];
+        u16     sit_tmcntsc;
+        u8      res2[2];
+        u32     sit_tmcnt;
+        u8      res3[4];
+        u32     sit_tmcntal;
+        u8      res4[16];
+        u16     sit_piscr;
+        u8      res5[2];
+        u32     sit_pitc;
+        u32     sit_pitr;
+        u8      res6[94];
+        u8      res7[390];
+} sit_cpm2_t;
+
+#define PISCR_PIRQ_MASK         ((u16)0xff00)
+#define PISCR_PS                ((u16)0x0080)
+#define PISCR_PIE               ((u16)0x0004)
+#define PISCR_PTF               ((u16)0x0002)
+#define PISCR_PTE               ((u16)0x0001)
+
+/* PCI Controller.
+*/
+typedef struct pci_ctlr {
+        u32     pci_omisr;
+        u32     pci_omimr;
+        u8      res1[8];
+        u32     pci_ifqpr;
+        u32     pci_ofqpr;
+        u8      res2[8];
+        u32     pci_imr0;
+        u32     pci_imr1;
+        u32     pci_omr0;
+        u32     pci_omr1;
+        u32     pci_odr;
+        u8      res3[4];
+        u32     pci_idr;
+        u8      res4[20];
+        u32     pci_imisr;
+        u32     pci_imimr;
+        u8      res5[24];
+        u32     pci_ifhpr;
+        u8      res6[4];
+        u32     pci_iftpr;
+        u8      res7[4];
+        u32     pci_iphpr;
+        u8      res8[4];
+        u32     pci_iptpr;
+        u8      res9[4];
+        u32     pci_ofhpr;
+        u8      res10[4];
+        u32     pci_oftpr;
+        u8      res11[4];
+        u32     pci_ophpr;
+        u8      res12[4];
+        u32     pci_optpr;
+        u8      res13[8];
+        u32     pci_mucr;
+        u8      res14[8];
+        u32     pci_qbar;
+        u8      res15[12];
+        u32     pci_dmamr0;
+        u32     pci_dmasr0;
+        u32     pci_dmacdar0;
+        u8      res16[4];
+        u32     pci_dmasar0;
+        u8      res17[4];
+        u32     pci_dmadar0;
+        u8      res18[4];
+        u32     pci_dmabcr0;
+        u32     pci_dmandar0;
+        u8      res19[86];
+        u32     pci_dmamr1;
+        u32     pci_dmasr1;
+        u32     pci_dmacdar1;
+        u8      res20[4];
+        u32     pci_dmasar1;
+        u8      res21[4];
+        u32     pci_dmadar1;
+        u8      res22[4];
+        u32     pci_dmabcr1;
+        u32     pci_dmandar1;
+        u8      res23[88];
+        u32     pci_dmamr2;
+        u32     pci_dmasr2;
+        u32     pci_dmacdar2;
+        u8      res24[4];
+        u32     pci_dmasar2;
+        u8      res25[4];
+        u32     pci_dmadar2;
+        u8      res26[4];
+        u32     pci_dmabcr2;
+        u32     pci_dmandar2;
+        u8      res27[88];
+        u32     pci_dmamr3;
+        u32     pci_dmasr3;
+        u32     pci_dmacdar3;
+        u8      res28[4];
+        u32     pci_dmasar3;
+        u8      res29[4];
+        u32     pci_dmadar3;
+        u8      res30[4];
+        u32     pci_dmabcr3;
+        u32     pci_dmandar3;
+        u8      res31[344];
+        u32     pci_potar0;
+        u8      res32[4];
+        u32     pci_pobar0;
+        u8      res33[4];
+        u32     pci_pocmr0;
+        u8      res34[4];
+        u32     pci_potar1;
+        u8      res35[4];
+        u32     pci_pobar1;
+        u8      res36[4];
+        u32     pci_pocmr1;
+        u8      res37[4];
+        u32     pci_potar2;
+        u8      res38[4];
+        u32     pci_pobar2;
+        u8      res39[4];
+        u32     pci_pocmr2;
+        u8      res40[50];
+        u32     pci_ptcr;
+        u32     pci_gpcr;
+        u32     pci_gcr;
+        u32     pci_esr;
+        u32     pci_emr;
+        u32     pci_ecr;
+        u32     pci_eacr;
+        u8      res41[4];
+        u32     pci_edcr;
+        u8      res42[4];
+        u32     pci_eccr;
+        u8      res43[44];
+        u32     pci_pitar1;
+        u8      res44[4];
+        u32     pci_pibar1;
+        u8      res45[4];
+        u32     pci_picmr1;
+        u8      res46[4];
+        u32     pci_pitar0;
+        u8      res47[4];
+        u32     pci_pibar0;
+        u8      res48[4];
+        u32     pci_picmr0;
+        u8      res49[4];
+        u32     pci_cfg_addr;
+        u32     pci_cfg_data;
+        u32     pci_int_ack;
+        u8      res50[756];
+} pci_cpm2_t;
+
+/* Interrupt Controller.
+*/
+typedef struct interrupt_controller {
+        u16     ic_sicr;
+        u8      res1[2];
+        u32     ic_sivec;
+        u32     ic_sipnrh;
+        u32     ic_sipnrl;
+        u32     ic_siprr;
+        u32     ic_scprrh;
+        u32     ic_scprrl;
+        u32     ic_simrh;
+        u32     ic_simrl;
+        u32     ic_siexr;
+        u8      res2[88];
+} intctl_cpm2_t;
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+        u32     car_sccr;
+        u8      res1[4];
+        u32     car_scmr;
+        u8      res2[4];
+        u32     car_rsr;
+        u32     car_rmr;
+        u8      res[104];
+} car_cpm2_t;
+
+/* Input/Output Port control/status registers.
+ * Names consistent with processor manual, although they are different
+ * from the original 8xx names.......
+ */
+typedef struct io_port {
+        u32     iop_pdira;
+        u32     iop_ppara;
+        u32     iop_psora;
+        u32     iop_podra;
+        u32     iop_pdata;
+        u8      res1[12];
+        u32     iop_pdirb;
+        u32     iop_pparb;
+        u32     iop_psorb;
+        u32     iop_podrb;
+        u32     iop_pdatb;
+        u8      res2[12];
+        u32     iop_pdirc;
+        u32     iop_pparc;
+        u32     iop_psorc;
+        u32     iop_podrc;
+        u32     iop_pdatc;
+        u8      res3[12];
+        u32     iop_pdird;
+        u32     iop_ppard;
+        u32     iop_psord;
+        u32     iop_podrd;
+        u32     iop_pdatd;
+        u8      res4[12];
+} iop_cpm2_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+        u8      cpmt_tgcr1;
+        u8      res1[3];
+        u8      cpmt_tgcr2;
+        u8      res2[11];
+        u16     cpmt_tmr1;
+        u16     cpmt_tmr2;
+        u16     cpmt_trr1;
+        u16     cpmt_trr2;
+        u16     cpmt_tcr1;
+        u16     cpmt_tcr2;
+        u16     cpmt_tcn1;
+        u16     cpmt_tcn2;
+        u16     cpmt_tmr3;
+        u16     cpmt_tmr4;
+        u16     cpmt_trr3;
+        u16     cpmt_trr4;
+        u16     cpmt_tcr3;
+        u16     cpmt_tcr4;
+        u16     cpmt_tcn3;
+        u16     cpmt_tcn4;
+        u16     cpmt_ter1;
+        u16     cpmt_ter2;
+        u16     cpmt_ter3;
+        u16     cpmt_ter4;
+        u8      res3[584];
+} cpmtimer_cpm2_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+        u8      res0[24];
+        u8      sdma_sdsr;
+        u8      res1[3];
+        u8      sdma_sdmr;
+        u8      res2[3];
+        u8      sdma_idsr1;
+        u8      res3[3];
+        u8      sdma_idmr1;
+        u8      res4[3];
+        u8      sdma_idsr2;
+        u8      res5[3];
+        u8      sdma_idmr2;
+        u8      res6[3];
+        u8      sdma_idsr3;
+        u8      res7[3];
+        u8      sdma_idmr3;
+        u8      res8[3];
+        u8      sdma_idsr4;
+        u8      res9[3];
+        u8      sdma_idmr4;
+        u8      res10[707];
+} sdma_cpm2_t;
+
+/* Fast controllers
+*/
+typedef struct fcc {
+        u32     fcc_gfmr;
+        u32     fcc_fpsmr;
+        u16     fcc_ftodr;
+        u8      res1[2];
+        u16     fcc_fdsr;
+        u8      res2[2];
+        u16     fcc_fcce;
+        u8      res3[2];
+        u16     fcc_fccm;
+        u8      res4[2];
+        u8      fcc_fccs;
+        u8      res5[3];
+        u8      fcc_ftirr_phy[4];
+} fcc_t;
+
+/* Fast controllers continued
+ */
+typedef struct fcc_c {
+        u32     fcc_firper;
+        u32     fcc_firer;
+        u32     fcc_firsr_hi;
+        u32     fcc_firsr_lo;
+        u8      fcc_gfemr;
+        u8      res1[15];
+} fcc_c_t;
+
+/* TC Layer
+ */
+typedef struct tclayer {
+        u16     tc_tcmode;
+        u16     tc_cdsmr;
+        u16     tc_tcer;
+        u16     tc_rcc;
+        u16     tc_tcmr;
+        u16     tc_fcc;
+        u16     tc_ccc;
+        u16     tc_icc;
+        u16     tc_tcc;
+        u16     tc_ecc;
+        u8      res1[12];
+} tclayer_t;
+
+
+/* I2C
+*/
+typedef struct i2c {
+        u8      i2c_i2mod;
+        u8      res1[3];
+        u8      i2c_i2add;
+        u8      res2[3];
+        u8      i2c_i2brg;
+        u8      res3[3];
+        u8      i2c_i2com;
+        u8      res4[3];
+        u8      i2c_i2cer;
+        u8      res5[3];
+        u8      i2c_i2cmr;
+        u8      res6[331];
+} i2c_cpm2_t;
+
+typedef struct scc {            /* Serial communication channels */
+        u32     scc_gsmrl;
+        u32     scc_gsmrh;
+        u16     scc_psmr;
+        u8      res1[2];
+        u16     scc_todr;
+        u16     scc_dsr;
+        u16     scc_scce;
+        u8      res2[2];
+        u16     scc_sccm;
+        u8      res3;
+        u8      scc_sccs;
+        u8      res4[8];
+} scc_t;
+
+typedef struct smc {            /* Serial management channels */
+        u8      res1[2];
+        u16     smc_smcmr;
+        u8      res2[2];
+        u8      smc_smce;
+        u8      res3[3];
+        u8      smc_smcm;
+        u8      res4[5];
+} smc_t;
+
+/* Serial Peripheral Interface.
+*/
+typedef struct spi_ctrl {
+        u16     spi_spmode;
+        u8      res1[4];
+        u8      spi_spie;
+        u8      res2[3];
+        u8      spi_spim;
+        u8      res3[2];
+        u8      spi_spcom;
+        u8      res4[82];
+} spictl_cpm2_t;
+
+/* CPM Mux.
+*/
+typedef struct cpmux {
+        u8      cmx_si1cr;
+        u8      res1;
+        u8      cmx_si2cr;
+        u8      res2;
+        u32     cmx_fcr;
+        u32     cmx_scr;
+        u8      cmx_smr;
+        u8      res3;
+        u16     cmx_uar;
+        u8      res4[16];
+} cpmux_t;
+
+/* SIRAM control
+*/
+typedef struct siram {
+        u16     si_amr;
+        u16     si_bmr;
+        u16     si_cmr;
+        u16     si_dmr;
+        u8      si_gmr;
+        u8      res1;
+        u8      si_cmdr;
+        u8      res2;
+        u8      si_str;
+        u8      res3;
+        u16     si_rsr;
+} siramctl_t;
+
+typedef struct mcc {
+        u16     mcc_mcce;
+        u8      res1[2];
+        u16     mcc_mccm;
+        u8      res2[2];
+        u8      mcc_mccf;
+        u8      res3[7];
+} mcc_t;
+
+typedef struct comm_proc {
+        u32     cp_cpcr;
+        u32     cp_rccr;
+        u8      res1[14];
+        u16     cp_rter;
+        u8      res2[2];
+        u16     cp_rtmr;
+        u16     cp_rtscr;
+        u8      res3[2];
+        u32     cp_rtsr;
+        u8      res4[12];
+} cpm_cpm2_t;
+
+/* USB Controller.
+*/
+typedef struct usb_ctlr {
+        u8      usb_usmod;
+        u8      usb_usadr;
+        u8      usb_uscom;
+        u8      res1[1];
+        u16     usb_usep1;
+        u16     usb_usep2;
+        u16     usb_usep3;
+        u16     usb_usep4;
+        u8      res2[4];
+        u16     usb_usber;
+        u8      res3[2];
+        u16     usb_usbmr;
+        u8      usb_usbs;
+        u8      res4[7];
+} usb_cpm2_t;
+
+/* ...and the whole thing wrapped up....
+*/
+
+typedef struct immap {
+        /* Some references are into the unique and known dpram spaces,
+         * others are from the generic base.
+         */
+#define im_dprambase    im_dpram1
+        u8              im_dpram1[16*1024];
+        u8              res1[16*1024];
+        u8              im_dpram2[4*1024];
+        u8              res2[8*1024];
+        u8              im_dpram3[4*1024];
+        u8              res3[16*1024];
+
+        sysconf_cpm2_t  im_siu_conf;    /* SIU Configuration */
+        memctl_cpm2_t   im_memctl;      /* Memory Controller */
+        sit_cpm2_t      im_sit;         /* System Integration Timers */
+        pci_cpm2_t      im_pci;         /* PCI Controller */
+        intctl_cpm2_t   im_intctl;      /* Interrupt Controller */
+        car_cpm2_t      im_clkrst;      /* Clocks and reset */
+        iop_cpm2_t      im_ioport;      /* IO Port control/status */
+        cpmtimer_cpm2_t im_cpmtimer;    /* CPM timers */
+        sdma_cpm2_t     im_sdma;        /* SDMA control/status */
+
+        fcc_t           im_fcc[3];      /* Three FCCs */
+        u8              res4z[32];
+        fcc_c_t         im_fcc_c[3];    /* Continued FCCs */
+
+        u8              res4[32];
+
+        tclayer_t       im_tclayer[8];  /* Eight TCLayers */
+        u16             tc_tcgsr;
+        u16             tc_tcger;
+        
+        /* First set of baud rate generators.
+        */
+        u8              res[236];
+        u32             im_brgc5;
+        u32             im_brgc6;
+        u32             im_brgc7;
+        u32             im_brgc8;
+
+        u8              res5[608];
+
+        i2c_cpm2_t      im_i2c;         /* I2C control/status */
+        cpm_cpm2_t      im_cpm;         /* Communication processor */
+
+        /* Second set of baud rate generators.
+        */
+        u32             im_brgc1;
+        u32             im_brgc2;
+        u32             im_brgc3;
+        u32             im_brgc4;
+
+        scc_t           im_scc[4];      /* Four SCCs */
+        smc_t           im_smc[2];      /* Couple of SMCs */
+        spictl_cpm2_t   im_spi;         /* A SPI */
+        cpmux_t         im_cpmux;       /* CPM clock route mux */
+        siramctl_t      im_siramctl1;   /* First SI RAM Control */
+        mcc_t           im_mcc1;        /* First MCC */
+        siramctl_t      im_siramctl2;   /* Second SI RAM Control */
+        mcc_t           im_mcc2;        /* Second MCC */
+        usb_cpm2_t      im_usb;         /* USB Controller */
+
+        u8              res6[1153];
+
+        u16             im_si1txram[256];
+        u8              res7[512];
+        u16             im_si1rxram[256];
+        u8              res8[512];
+        u16             im_si2txram[256];
+        u8              res9[512];
+        u16             im_si2rxram[256];
+        u8              res10[512];
+        u8              res11[4096];
+} cpm2_map_t;
+
+extern cpm2_map_t       *cpm2_immr;
+
+#endif /* __IMMAP_CPM2__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
new file mode 100644
index 000000000000..7eb7cf6360bd
--- /dev/null
+++ b/include/asm-ppc/io.h
@@ -0,0 +1,566 @@
+#ifdef __KERNEL__
+#ifndef _PPC_IO_H
+#define _PPC_IO_H
+
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <asm/page.h>
+#include <asm/byteorder.h>
+#include <asm/mmu.h>
+
+#define SIO_CONFIG_RA   0x398
+#define SIO_CONFIG_RD   0x399
+
+#define SLOW_DOWN_IO
+
+#define PMAC_ISA_MEM_BASE       0
+#define PMAC_PCI_DRAM_OFFSET    0
+#define CHRP_ISA_IO_BASE        0xf8000000
+#define CHRP_ISA_MEM_BASE       0xf7000000
+#define CHRP_PCI_DRAM_OFFSET    0
+#define PREP_ISA_IO_BASE        0x80000000
+#define PREP_ISA_MEM_BASE       0xc0000000
+#define PREP_PCI_DRAM_OFFSET    0x80000000
+
+#if defined(CONFIG_4xx)
+#include <asm/ibm4xx.h>
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
+#elif defined(CONFIG_8260)
+#include <asm/mpc8260.h>
+#elif defined(CONFIG_83xx)
+#include <asm/mpc83xx.h>
+#elif defined(CONFIG_85xx)
+#include <asm/mpc85xx.h>
+#elif defined(CONFIG_APUS)
+#define _IO_BASE        0
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#else /* Everyone else */
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#define PCI_DRAM_OFFSET pci_dram_offset
+#endif /* Platform-dependent I/O */
+
+#define ___IO_BASE ((void __iomem *)_IO_BASE)
+extern unsigned long isa_io_base;
+extern unsigned long isa_mem_base;
+extern unsigned long pci_dram_offset;
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
+ */
+extern inline int in_8(volatile unsigned char __iomem *addr)
+{
+        int ret;
+
+        __asm__ __volatile__(
+                "lbz%U1%X1 %0,%1;\n"
+                "twi 0,%0,0;\n"
+                "isync" : "=r" (ret) : "m" (*addr));
+        return ret;
+}
+
+extern inline void out_8(volatile unsigned char __iomem *addr, int val)
+{
+        __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline int in_le16(volatile unsigned short __iomem *addr)
+{
+        int ret;
+
+        __asm__ __volatile__("lhbrx %0,0,%1;\n"
+                             "twi 0,%0,0;\n"
+                             "isync" : "=r" (ret) :
+                              "r" (addr), "m" (*addr));
+        return ret;
+}
+
+extern inline int in_be16(volatile unsigned short __iomem *addr)
+{
+        int ret;
+
+        __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
+                             "twi 0,%0,0;\n"
+                             "isync" : "=r" (ret) : "m" (*addr));
+        return ret;
+}
+
+extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
+{
+        __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
+                              "r" (val), "r" (addr));
+}
+
+extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
+{
+        __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline unsigned in_le32(volatile unsigned __iomem *addr)
+{
+        unsigned ret;
+
+        __asm__ __volatile__("lwbrx %0,0,%1;\n"
+                             "twi 0,%0,0;\n"
+                             "isync" : "=r" (ret) :
+                             "r" (addr), "m" (*addr));
+        return ret;
+}
+
+extern inline unsigned in_be32(volatile unsigned __iomem *addr)
+{
+        unsigned ret;
+
+        __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
+                             "twi 0,%0,0;\n"
+                             "isync" : "=r" (ret) : "m" (*addr));
+        return ret;
+}
+
+extern inline void out_le32(volatile unsigned __iomem *addr, int val)
+{
+        __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
+                             "r" (val), "r" (addr));
+}
+
+extern inline void out_be32(volatile unsigned __iomem *addr, int val)
+{
+        __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#if defined (CONFIG_8260_PCI9)
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#else
+static inline __u8 readb(volatile void __iomem *addr)
+{
+        return in_8(addr);
+}
+static inline void writeb(__u8 b, volatile void __iomem *addr)
+{
+        out_8(addr, b);
+}
+#endif
+
+#if defined(CONFIG_APUS)
+static inline __u16 readw(volatile void __iomem *addr)
+{
+        return *(__force volatile __u16 *)(addr);
+}
+static inline __u32 readl(volatile void __iomem *addr)
+{
+        return *(__force volatile __u32 *)(addr);
+}
+static inline void writew(__u16 b, volatile void __iomem *addr)
+{
+        *(__force volatile __u16 *)(addr) = b;
+}
+static inline void writel(__u32 b, volatile void __iomem *addr)
+{
+        *(__force volatile __u32 *)(addr) = b;
+}
+#elif defined (CONFIG_8260_PCI9)
+/* Use macros if PCI9 workaround enabled */
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#else
+static inline __u16 readw(volatile void __iomem *addr)
+{
+        return in_le16(addr);
+}
+static inline __u32 readl(volatile void __iomem *addr)
+{
+        return in_le32(addr);
+}
+static inline void writew(__u16 b, volatile void __iomem *addr)
+{
+        out_le16(addr, b);
+}
+static inline void writel(__u32 b, volatile void __iomem *addr)
+{
+        out_le32(addr, b);
+}
+#endif /* CONFIG_APUS */
+
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+
+static inline __u8 __raw_readb(const volatile void __iomem *addr)
+{
+        return *(__force volatile __u8 *)(addr);
+}
+static inline __u16 __raw_readw(const volatile void __iomem *addr)
+{
+        return *(__force volatile __u16 *)(addr);
+}
+static inline __u32 __raw_readl(const volatile void __iomem *addr)
+{
+        return *(__force volatile __u32 *)(addr);
+}
+static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
+{
+        *(__force volatile __u8 *)(addr) = b;
+}
+static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
+{
+        *(__force volatile __u16 *)(addr) = b;
+}
+static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
+{
+        *(__force volatile __u32 *)(addr) = b;
+}
+
+#define mmiowb()
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns)     _insb((port)+___IO_BASE, (buf), (ns))
+#define outsb(port, buf, ns)    _outsb((port)+___IO_BASE, (buf), (ns))
+#define insw(port, buf, ns)     _insw_ns((port)+___IO_BASE, (buf), (ns))
+#define outsw(port, buf, ns)    _outsw_ns((port)+___IO_BASE, (buf), (ns))
+#define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
+#define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
+
+/*
+ * On powermacs, we will get a machine check exception if we
+ * try to read data from a non-existent I/O port.  Because the
+ * machine check is an asynchronous exception, it isn't
+ * well-defined which instruction SRR0 will point to when the
+ * exception occurs.
+ * With the sequence below (twi; isync; nop), we have found that
+ * the machine check occurs on one of the three instructions on
+ * all PPC implementations tested so far.  The twi and isync are
+ * needed on the 601 (in fact twi; sync works too), the isync and
+ * nop are needed on 604[e|r], and any of twi, sync or isync will
+ * work on 603[e], 750, 74xx.
+ * The twi creates an explicit data dependency on the returned
+ * value which seems to be needed to make the 601 wait for the
+ * load to finish.
+ */
+
+#define __do_in_asm(name, op)                           \
+extern __inline__ unsigned int name(unsigned int port)  \
+{                                                       \
+        unsigned int x;                                 \
+        __asm__ __volatile__(                           \
+                        op "    %0,0,%1\n"              \
+                "1:     twi     0,%0,0\n"               \
+                "2:     isync\n"                        \
+                "3:     nop\n"                          \
+                "4:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "5:     li      %0,-1\n"                \
+                "       b       4b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   1b,5b\n"                \
+                "       .long   2b,5b\n"                \
+                "       .long   3b,5b\n"                \
+                ".previous"                             \
+                : "=&r" (x)                             \
+                : "r" (port + ___IO_BASE));             \
+        return x;                                       \
+}
+
+#define __do_out_asm(name, op)                          \
+extern __inline__ void name(unsigned int val, unsigned int port) \
+{                                                       \
+        __asm__ __volatile__(                           \
+                op " %0,0,%1\n"                         \
+                "1:     sync\n"                         \
+                "2:\n"                                  \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align  2\n"                    \
+                "       .long   1b,2b\n"                \
+                ".previous"                             \
+                : : "r" (val), "r" (port + ___IO_BASE));        \
+}
+
+__do_out_asm(outb, "stbx")
+#ifdef CONFIG_APUS
+__do_in_asm(inb, "lbzx")
+__do_in_asm(inw, "lhz%U1%X1")
+__do_in_asm(inl, "lwz%U1%X1")
+__do_out_asm(outl,"stw%U0%X0")
+__do_out_asm(outw, "sth%U0%X0")
+#elif defined (CONFIG_8260_PCI9)
+/* in asm cannot be defined if PCI9 workaround is used */
+#define inb(port)               in_8((port)+___IO_BASE)
+#define inw(port)               in_le16((port)+___IO_BASE)
+#define inl(port)               in_le32((port)+___IO_BASE)
+__do_out_asm(outw, "sthbrx")
+__do_out_asm(outl, "stwbrx")
+#else
+__do_in_asm(inb, "lbzx")
+__do_in_asm(inw, "lhbrx")
+__do_in_asm(inl, "lwbrx")
+__do_out_asm(outw, "sthbrx")
+__do_out_asm(outl, "stwbrx")
+
+#endif
+
+#define inb_p(port)             inb((port))
+#define outb_p(val, port)       outb((val), (port))
+#define inw_p(port)             inw((port))
+#define outw_p(val, port)       outw((val), (port))
+#define inl_p(port)             inl((port))
+#define outl_p(val, port)       outl((val), (port))
+
+extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
+extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
+extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
+extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
+extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
+extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
+extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
+extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
+extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
+extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)  _insw_ns((port)+___IO_BASE, (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
+#define insl_ns(port, buf, nl)  _insl_ns((port)+___IO_BASE, (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
+
+
+#define IO_SPACE_LIMIT ~0
+
+#if defined (CONFIG_8260_PCI9)
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
+#else
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+        memset((void __force *)addr, val, count);
+}
+static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
+{
+        memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+        memcpy((void __force *) dst, src, count);
+}
+#endif
+
+#define eth_io_copy_and_sum(a,b,c,d)            eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
+
+/*
+ * Map in an area of physical address space, for accessing
+ * I/O devices etc.
+ */
+extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
+                       unsigned long flags);
+extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
+#ifdef CONFIG_44x
+extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
+#endif
+#define ioremap_nocache(addr, size)     ioremap((addr), (size))
+extern void iounmap(volatile void __iomem *addr);
+extern unsigned long iopa(unsigned long addr);
+extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
+extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
+                             unsigned int size, int flags);
+
+/*
+ * The PCI bus is inherently Little-Endian.  The PowerPC is being
+ * run Big-Endian.  Thus all values which cross the [PCI] barrier
+ * must be endian-adjusted.  Also, the local DRAM has a different
+ * address from the PCI point of view, thus buffer addresses also
+ * have to be modified [mapped] appropriately.
+ */
+extern inline unsigned long virt_to_bus(volatile void * address)
+{
+#ifndef CONFIG_APUS
+        if (address == (void *)0)
+                return 0;
+        return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
+#else
+        return iopa ((unsigned long) address);
+#endif
+}
+
+extern inline void * bus_to_virt(unsigned long address)
+{
+#ifndef CONFIG_APUS
+        if (address == 0)
+                return NULL;
+        return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
+#else
+        return (void*) mm_ptov (address);
+#endif
+}
+
+/*
+ * Change virtual addresses to physical addresses and vv, for
+ * addresses in the area where the kernel has the RAM mapped.
+ */
+extern inline unsigned long virt_to_phys(volatile void * address)
+{
+#ifndef CONFIG_APUS
+        return (unsigned long) address - KERNELBASE;
+#else
+        return iopa ((unsigned long) address);
+#endif
+}
+
+extern inline void * phys_to_virt(unsigned long address)
+{
+#ifndef CONFIG_APUS
+        return (void *) (address + KERNELBASE);
+#else
+        return (void*) mm_ptov (address);
+#endif
+}
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+#define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
+
+/*
+ * Enforce In-order Execution of I/O:
+ * Acts as a barrier to ensure all previous I/O accesses have
+ * completed before any further ones are issued.
+ */
+extern inline void eieio(void)
+{
+        __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
+
+static inline int check_signature(volatile void __iomem * io_addr,
+        const unsigned char *signature, int length)
+{
+        int retval = 0;
+        do {
+                if (readb(io_addr) != *signature)
+                        goto out;
+                io_addr++;
+                signature++;
+                length--;
+        } while (length);
+        retval = 1;
+out:
+        return retval;
+}
+
+/*
+ * Here comes the ppc implementation of the IOMAP 
+ * interfaces.
+ */
+static inline unsigned int ioread8(void __iomem *addr)
+{
+        return readb(addr);
+}
+
+static inline unsigned int ioread16(void __iomem *addr)
+{
+        return readw(addr);
+}
+
+static inline unsigned int ioread32(void __iomem *addr)
+{
+        return readl(addr);
+}
+
+static inline void iowrite8(u8 val, void __iomem *addr)
+{
+        writeb(val, addr);
+}
+
+static inline void iowrite16(u16 val, void __iomem *addr)
+{
+        writew(val, addr);
+}
+
+static inline void iowrite32(u32 val, void __iomem *addr)
+{
+        writel(val, addr);
+}
+
+static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        _insb(addr, dst, count);
+}
+
+static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        _insw_ns(addr, dst, count);
+}
+
+static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        _insl_ns(addr, dst, count);
+}
+
+static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        _outsb(addr, src, count);
+}
+
+static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        _outsw_ns(addr, src, count);
+}
+
+static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        _outsl_ns(addr, src, count);
+}
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+#endif /* _PPC_IO_H */
+
+#ifdef CONFIG_8260_PCI9
+#include <asm/mpc8260_pci9.h>
+#endif
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ioctl.h b/include/asm-ppc/ioctl.h
new file mode 100644
index 000000000000..93c6acfdd0fd
--- /dev/null
+++ b/include/asm-ppc/ioctl.h
@@ -0,0 +1,69 @@
+#ifndef _PPC_IOCTL_H
+#define _PPC_IOCTL_H
+
+
+/*
+ * this was copied from the alpha as it's a bit cleaner there.
+ *                         -- Cort
+ */
+
+#define _IOC_NRBITS     8
+#define _IOC_TYPEBITS   8
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT    0
+#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
+ * And this turns out useful to catch old ioctl numbers in header
+ * files for us.
+ */
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+        ((sizeof(t) == sizeof(t[1]) && \
+          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+          sizeof(t) : __invalid_size_argument_for_IOC)
+
+/* used to create numbers */
+#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size)  _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW_BAD(type,nr,size)  _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode them.. */
+#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* various drivers, such as the pcmcia stuff, need these... */
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif
diff --git a/include/asm-ppc/ioctls.h b/include/asm-ppc/ioctls.h
new file mode 100644
index 000000000000..f5b7f2b055e7
--- /dev/null
+++ b/include/asm-ppc/ioctls.h
@@ -0,0 +1,107 @@
+#ifndef _ASM_PPC_IOCTLS_H
+#define _ASM_PPC_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TIOCGETP        _IOR('t', 8, struct sgttyb)
+#define TIOCSETP        _IOW('t', 9, struct sgttyb)
+#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
+
+#define TIOCSETC        _IOW('t', 17, struct tchars)
+#define TIOCGETC        _IOR('t', 18, struct tchars)
+#define TCGETS          _IOR('t', 19, struct termios)
+#define TCSETS          _IOW('t', 20, struct termios)
+#define TCSETSW         _IOW('t', 21, struct termios)
+#define TCSETSF         _IOW('t', 22, struct termios)
+
+#define TCGETA          _IOR('t', 23, struct termio)
+#define TCSETA          _IOW('t', 24, struct termio)
+#define TCSETAW         _IOW('t', 25, struct termio)
+#define TCSETAF         _IOW('t', 28, struct termio)
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCGLTC        _IOR('t', 116, struct ltchars)
+#define TIOCSLTC        _IOW('t', 117, struct ltchars)
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+
+#define TIOCSTI         0x5412
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+# define TIOCM_LE       0x001
+# define TIOCM_DTR      0x002
+# define TIOCM_RTS      0x004
+# define TIOCM_ST       0x008
+# define TIOCM_SR       0x010
+# define TIOCM_CTS      0x020
+# define TIOCM_CAR      0x040
+# define TIOCM_RNG      0x080
+# define TIOCM_DSR      0x100
+# define TIOCM_CD       TIOCM_CAR
+# define TIOCM_RI       TIOCM_RNG
+
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+# define TIOCPKT_DATA            0
+# define TIOCPKT_FLUSHREAD       1
+# define TIOCPKT_FLUSHWRITE      2
+# define TIOCPKT_STOP            4
+# define TIOCPKT_START           8
+# define TIOCPKT_NOSTOP         16
+# define TIOCPKT_DOSTOP         32
+
+
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+#endif /* _ASM_PPC_IOCTLS_H */
diff --git a/include/asm-ppc/ipc.h b/include/asm-ppc/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-ppc/ipc.h
@@ -0,0 +1 @@
+#include <asm-generic/ipc.h>
diff --git a/include/asm-ppc/ipcbuf.h b/include/asm-ppc/ipcbuf.h
new file mode 100644
index 000000000000..fab6752c7480
--- /dev/null
+++ b/include/asm-ppc/ipcbuf.h
@@ -0,0 +1,29 @@
+#ifndef __PPC_IPCBUF_H__
+#define __PPC_IPCBUF_H__
+
+/*
+ * The ipc64_perm structure for PPC architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 1 32-bit value to fill up for 8-byte alignment
+ * - 2 miscellaneous 64-bit values (so that this structure matches
+ *                                  PPC64 ipc64_perm)
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid_t          uid;
+        __kernel_gid_t          gid;
+        __kernel_uid_t          cuid;
+        __kernel_gid_t          cgid;
+        __kernel_mode_t         mode;
+        unsigned long           seq;
+        unsigned int            __pad2;
+        unsigned long long      __unused1;
+        unsigned long long      __unused2;
+};
+
+#endif /* __PPC_IPCBUF_H__ */
diff --git a/include/asm-ppc/ipic.h b/include/asm-ppc/ipic.h
new file mode 100644
index 000000000000..9092b920997a
--- /dev/null
+++ b/include/asm-ppc/ipic.h
@@ -0,0 +1,85 @@
+/*
+ * include/asm-ppc/ipic.h
+ *
+ * IPIC external definitions and structure.
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_IPIC_H__
+#define __ASM_IPIC_H__
+
+#include <linux/irq.h>
+
+/* Flags when we init the IPIC */
+#define IPIC_SPREADMODE_GRP_A   0x00000001
+#define IPIC_SPREADMODE_GRP_D   0x00000002
+#define IPIC_SPREADMODE_MIX_A   0x00000004
+#define IPIC_SPREADMODE_MIX_B   0x00000008
+#define IPIC_DISABLE_MCP_OUT    0x00000010
+#define IPIC_IRQ0_MCP           0x00000020
+
+/* IPIC registers offsets */
+#define IPIC_SICFR      0x00    /* System Global Interrupt Configuration Register */
+#define IPIC_SIVCR      0x04    /* System Global Interrupt Vector Register */
+#define IPIC_SIPNR_H    0x08    /* System Internal Interrupt Pending Register (HIGH) */
+#define IPIC_SIPNR_L    0x0C    /* System Internal Interrupt Pending Register (LOW) */
+#define IPIC_SIPRR_A    0x10    /* System Internal Interrupt group A Priority Register */
+#define IPIC_SIPRR_B    0x14    /* System Internal Interrupt group B Priority Register */
+#define IPIC_SIPRR_C    0x18    /* System Internal Interrupt group C Priority Register */
+#define IPIC_SIPRR_D    0x1C    /* System Internal Interrupt group D Priority Register */
+#define IPIC_SIMSR_H    0x20    /* System Internal Interrupt Mask Register (HIGH) */
+#define IPIC_SIMSR_L    0x24    /* System Internal Interrupt Mask Register (LOW) */
+#define IPIC_SICNR      0x28    /* System Internal Interrupt Control Register */
+#define IPIC_SEPNR      0x2C    /* System External Interrupt Pending Register */
+#define IPIC_SMPRR_A    0x30    /* System Mixed Interrupt group A Priority Register */
+#define IPIC_SMPRR_B    0x34    /* System Mixed Interrupt group B Priority Register */
+#define IPIC_SEMSR      0x38    /* System External Interrupt Mask Register */
+#define IPIC_SECNR      0x3C    /* System External Interrupt Control Register */
+#define IPIC_SERSR      0x40    /* System Error Status Register */
+#define IPIC_SERMR      0x44    /* System Error Mask Register */
+#define IPIC_SERCR      0x48    /* System Error Control Register */
+#define IPIC_SIFCR_H    0x50    /* System Internal Interrupt Force Register (HIGH) */
+#define IPIC_SIFCR_L    0x54    /* System Internal Interrupt Force Register (LOW) */
+#define IPIC_SEFCR      0x58    /* System External Interrupt Force Register */
+#define IPIC_SERFR      0x5C    /* System Error Force Register */
+#define IPIC_SCVCR      0x60    /* System Critical Interrupt Vector Register */
+#define IPIC_SMVCR      0x64    /* System Management Interrupt Vector Register */
+
+enum ipic_prio_grp {
+        IPIC_INT_GRP_A = IPIC_SIPRR_A,
+        IPIC_INT_GRP_D = IPIC_SIPRR_D,
+        IPIC_MIX_GRP_A = IPIC_SMPRR_A,
+        IPIC_MIX_GRP_B = IPIC_SMPRR_B,
+};
+
+enum ipic_mcp_irq {
+        IPIC_MCP_IRQ0 = 0,
+        IPIC_MCP_WDT  = 1,
+        IPIC_MCP_SBA  = 2,
+        IPIC_MCP_PCI1 = 5,
+        IPIC_MCP_PCI2 = 6,
+        IPIC_MCP_MU   = 7,
+};
+
+extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
+                unsigned int irq_offset,
+                unsigned char *senses, unsigned int senses_count);
+extern int ipic_set_priority(unsigned int irq, unsigned int priority);
+extern void ipic_set_highest_priority(unsigned int irq);
+extern void ipic_set_default_priority(void);
+extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
+extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
+extern u32 ipic_get_mcp_status(void);
+extern void ipic_clear_mcp_status(u32 mask);
+extern int ipic_get_irq(struct pt_regs *regs);
+
+#endif /* __ASM_IPIC_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
new file mode 100644
index 000000000000..06b86be61ed1
--- /dev/null
+++ b/include/asm-ppc/irq.h
@@ -0,0 +1,400 @@
+#ifdef __KERNEL__
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#include <linux/config.h>
+#include <asm/machdep.h>                /* ppc_md */
+#include <asm/atomic.h>
+
+/*
+ * These constants are used for passing information about interrupt
+ * signal polarity and level/edge sensing to the low-level PIC chip
+ * drivers.
+ */
+#define IRQ_SENSE_MASK          0x1
+#define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
+#define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
+
+#define IRQ_POLARITY_MASK       0x2
+#define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
+#define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
+
+#if defined(CONFIG_40x)
+#include <asm/ibm4xx.h>
+
+#ifndef NR_BOARD_IRQS
+#define NR_BOARD_IRQS 0
+#endif
+
+#ifndef UIC_WIDTH /* Number of interrupts per device */
+#define UIC_WIDTH 32
+#endif
+
+#ifndef NR_UICS /* number  of UIC devices */
+#define NR_UICS 1
+#endif
+
+#if defined (CONFIG_403)
+/*
+ * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
+ * 32 possible interrupts, a majority of which are not implemented on
+ * all cores. There are six configurable, external interrupt pins and
+ * there are eight internal interrupts for the on-chip serial port
+ * (SPU), DMA controller, and JTAG controller.
+ *
+ */
+
+#define NR_AIC_IRQS 32
+#define NR_IRQS  (NR_AIC_IRQS + NR_BOARD_IRQS)
+
+#elif !defined (CONFIG_403)
+
+/*
+ *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
+ * possible interrupts as well. There are seven, configurable external
+ * interrupt pins and there are 17 internal interrupts for the on-chip
+ * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
+ *
+ */
+
+
+#define NR_UIC_IRQS UIC_WIDTH
+#define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
+#endif
+static __inline__ int
+irq_canonicalize(int irq)
+{
+        return (irq);
+}
+
+#elif defined(CONFIG_44x)
+#include <asm/ibm44x.h>
+
+#define NR_UIC_IRQS     32
+#define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
+
+static __inline__ int
+irq_canonicalize(int irq)
+{
+        return (irq);
+}
+
+#elif defined(CONFIG_8xx)
+
+/* Now include the board configuration specific associations.
+*/
+#include <asm/mpc8xx.h>
+
+/* The MPC8xx cores have 16 possible interrupts.  There are eight
+ * possible level sensitive interrupts assigned and generated internally
+ * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
+ * There are eight external interrupts (IRQs) that can be configured
+ * as either level or edge sensitive.
+ *
+ * On some implementations, there is also the possibility of an 8259
+ * through the PCI and PCI-ISA bridges.
+ *
+ * We are "flattening" the interrupt vectors of the cascaded CPM
+ * and 8259 interrupt controllers so that we can uniquely identify
+ * any interrupt source with a single integer.
+ */
+#define NR_SIU_INTS     16
+#define NR_CPM_INTS     32
+#ifndef NR_8259_INTS
+#define NR_8259_INTS 0
+#endif
+
+#define SIU_IRQ_OFFSET          0
+#define CPM_IRQ_OFFSET          (SIU_IRQ_OFFSET + NR_SIU_INTS)
+#define I8259_IRQ_OFFSET        (CPM_IRQ_OFFSET + NR_CPM_INTS)
+
+#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
+
+/* These values must be zero-based and map 1:1 with the SIU configuration.
+ * They are used throughout the 8xx I/O subsystem to generate
+ * interrupt masks, flags, and other control patterns.  This is why the
+ * current kernel assumption of the 8259 as the base controller is such
+ * a pain in the butt.
+ */
+#define SIU_IRQ0        (0)     /* Highest priority */
+#define SIU_LEVEL0      (1)
+#define SIU_IRQ1        (2)
+#define SIU_LEVEL1      (3)
+#define SIU_IRQ2        (4)
+#define SIU_LEVEL2      (5)
+#define SIU_IRQ3        (6)
+#define SIU_LEVEL3      (7)
+#define SIU_IRQ4        (8)
+#define SIU_LEVEL4      (9)
+#define SIU_IRQ5        (10)
+#define SIU_LEVEL5      (11)
+#define SIU_IRQ6        (12)
+#define SIU_LEVEL6      (13)
+#define SIU_IRQ7        (14)
+#define SIU_LEVEL7      (15)
+
+/* The internal interrupts we can configure as we see fit.
+ * My personal preference is CPM at level 2, which puts it above the
+ * MBX PCI/ISA/IDE interrupts.
+ */
+#ifndef PIT_INTERRUPT
+#define PIT_INTERRUPT           SIU_LEVEL0
+#endif
+#ifndef CPM_INTERRUPT
+#define CPM_INTERRUPT           SIU_LEVEL2
+#endif
+#ifndef PCMCIA_INTERRUPT
+#define PCMCIA_INTERRUPT        SIU_LEVEL6
+#endif
+#ifndef DEC_INTERRUPT
+#define DEC_INTERRUPT           SIU_LEVEL7
+#endif
+
+/* Some internal interrupt registers use an 8-bit mask for the interrupt
+ * level instead of a number.
+ */
+#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
+
+/* always the same on 8xx -- Cort */
+static __inline__ int irq_canonicalize(int irq)
+{
+        return irq;
+}
+
+#elif defined(CONFIG_83xx)
+#include <asm/mpc83xx.h>
+
+static __inline__ int irq_canonicalize(int irq)
+{
+        return irq;
+}
+
+#define NR_IRQS (NR_IPIC_INTS)
+
+#elif defined(CONFIG_85xx)
+/* Now include the board configuration specific associations.
+*/
+#include <asm/mpc85xx.h>
+
+/* The MPC8560 openpic has  32 internal interrupts and 12 external
+ * interrupts.
+ *
+ * We are "flattening" the interrupt vectors of the cascaded CPM
+ * so that we can uniquely identify any interrupt source with a
+ * single integer.
+ */
+#define NR_CPM_INTS     64
+#define NR_EPIC_INTS    44
+#ifndef NR_8259_INTS
+#define NR_8259_INTS    0
+#endif
+#define NUM_8259_INTERRUPTS NR_8259_INTS
+
+#ifndef CPM_IRQ_OFFSET
+#define CPM_IRQ_OFFSET  0
+#endif
+
+#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
+
+/* Internal IRQs on MPC85xx OpenPIC */
+
+#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
+#ifdef CONFIG_CPM2
+#define MPC85xx_OPENPIC_IRQ_OFFSET      (CPM_IRQ_OFFSET + NR_CPM_INTS)
+#else
+#define MPC85xx_OPENPIC_IRQ_OFFSET      0
+#endif
+#endif
+
+/* Not all of these exist on all MPC85xx implementations */
+#define MPC85xx_IRQ_L2CACHE     ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_ECM         ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DDR         ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_LBIU        ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DMA0        ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DMA1        ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DMA2        ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DMA3        ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_PCI1        ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_PCI2        ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_RIO_ERROR   ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_RIO_BELL    (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_RIO_TX      (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_IIC1        (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_PERFMON     (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_SEC2        (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_CPM         (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
+
+/* The 12 external interrupt lines */
+#define MPC85xx_IRQ_EXT0        (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT1        (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT2        (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT3        (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT4        (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT5        (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT6        (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT7        (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT8        (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT9        (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT10       (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_EXT11       (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
+
+/* CPM related interrupts */
+#define SIU_INT_ERROR           ((uint)0x00+CPM_IRQ_OFFSET)
+#define SIU_INT_I2C             ((uint)0x01+CPM_IRQ_OFFSET)
+#define SIU_INT_SPI             ((uint)0x02+CPM_IRQ_OFFSET)
+#define SIU_INT_RISC            ((uint)0x03+CPM_IRQ_OFFSET)
+#define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
+#define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
+#define SIU_INT_USB             ((uint)0x0b+CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER1          ((uint)0x0c+CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER2          ((uint)0x0d+CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER3          ((uint)0x0e+CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER4          ((uint)0x0f+CPM_IRQ_OFFSET)
+#define SIU_INT_FCC1            ((uint)0x20+CPM_IRQ_OFFSET)
+#define SIU_INT_FCC2            ((uint)0x21+CPM_IRQ_OFFSET)
+#define SIU_INT_FCC3            ((uint)0x22+CPM_IRQ_OFFSET)
+#define SIU_INT_MCC1            ((uint)0x24+CPM_IRQ_OFFSET)
+#define SIU_INT_MCC2            ((uint)0x25+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
+#define SIU_INT_PC15            ((uint)0x30+CPM_IRQ_OFFSET)
+#define SIU_INT_PC14            ((uint)0x31+CPM_IRQ_OFFSET)
+#define SIU_INT_PC13            ((uint)0x32+CPM_IRQ_OFFSET)
+#define SIU_INT_PC12            ((uint)0x33+CPM_IRQ_OFFSET)
+#define SIU_INT_PC11            ((uint)0x34+CPM_IRQ_OFFSET)
+#define SIU_INT_PC10            ((uint)0x35+CPM_IRQ_OFFSET)
+#define SIU_INT_PC9             ((uint)0x36+CPM_IRQ_OFFSET)
+#define SIU_INT_PC8             ((uint)0x37+CPM_IRQ_OFFSET)
+#define SIU_INT_PC7             ((uint)0x38+CPM_IRQ_OFFSET)
+#define SIU_INT_PC6             ((uint)0x39+CPM_IRQ_OFFSET)
+#define SIU_INT_PC5             ((uint)0x3a+CPM_IRQ_OFFSET)
+#define SIU_INT_PC4             ((uint)0x3b+CPM_IRQ_OFFSET)
+#define SIU_INT_PC3             ((uint)0x3c+CPM_IRQ_OFFSET)
+#define SIU_INT_PC2             ((uint)0x3d+CPM_IRQ_OFFSET)
+#define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
+#define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
+
+static __inline__ int irq_canonicalize(int irq)
+{
+        return irq;
+}
+
+#else /* CONFIG_40x + CONFIG_8xx */
+/*
+ * this is the # irq's for all ppc arch's (pmac/chrp/prep)
+ * so it is the max of them all
+ */
+#define NR_IRQS                 256
+
+#ifndef CONFIG_8260
+
+#define NUM_8259_INTERRUPTS     16
+
+#else /* CONFIG_8260 */
+
+/* The 8260 has an internal interrupt controller with a maximum of
+ * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
+ * Don't be confused by the 8260 documentation where they list an
+ * "interrupt number" and "interrupt vector".  We are only interested
+ * in the interrupt vector.  There are "reserved" holes where the
+ * vector number increases, but the interrupt number in the table does not.
+ * (Document errata updates have fixed this...make sure you have up to
+ * date processor documentation -- Dan).
+ */
+
+#ifndef CPM_IRQ_OFFSET
+#define CPM_IRQ_OFFSET  0
+#endif
+
+#define NR_CPM_INTS     64
+
+#define SIU_INT_ERROR           ((uint)0x00 + CPM_IRQ_OFFSET)
+#define SIU_INT_I2C             ((uint)0x01 + CPM_IRQ_OFFSET)
+#define SIU_INT_SPI             ((uint)0x02 + CPM_IRQ_OFFSET)
+#define SIU_INT_RISC            ((uint)0x03 + CPM_IRQ_OFFSET)
+#define SIU_INT_SMC1            ((uint)0x04 + CPM_IRQ_OFFSET)
+#define SIU_INT_SMC2            ((uint)0x05 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA1           ((uint)0x06 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA2           ((uint)0x07 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA3           ((uint)0x08 + CPM_IRQ_OFFSET)
+#define SIU_INT_IDMA4           ((uint)0x09 + CPM_IRQ_OFFSET)
+#define SIU_INT_SDMA            ((uint)0x0a + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER1          ((uint)0x0c + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER2          ((uint)0x0d + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER3          ((uint)0x0e + CPM_IRQ_OFFSET)
+#define SIU_INT_TIMER4          ((uint)0x0f + CPM_IRQ_OFFSET)
+#define SIU_INT_TMCNT           ((uint)0x10 + CPM_IRQ_OFFSET)
+#define SIU_INT_PIT             ((uint)0x11 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ1            ((uint)0x13 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ2            ((uint)0x14 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ3            ((uint)0x15 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ4            ((uint)0x16 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ5            ((uint)0x17 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ6            ((uint)0x18 + CPM_IRQ_OFFSET)
+#define SIU_INT_IRQ7            ((uint)0x19 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC1            ((uint)0x20 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC2            ((uint)0x21 + CPM_IRQ_OFFSET)
+#define SIU_INT_FCC3            ((uint)0x22 + CPM_IRQ_OFFSET)
+#define SIU_INT_MCC1            ((uint)0x24 + CPM_IRQ_OFFSET)
+#define SIU_INT_MCC2            ((uint)0x25 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC1            ((uint)0x28 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC2            ((uint)0x29 + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC3            ((uint)0x2a + CPM_IRQ_OFFSET)
+#define SIU_INT_SCC4            ((uint)0x2b + CPM_IRQ_OFFSET)
+#define SIU_INT_PC15            ((uint)0x30 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC14            ((uint)0x31 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC13            ((uint)0x32 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC12            ((uint)0x33 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC11            ((uint)0x34 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC10            ((uint)0x35 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC9             ((uint)0x36 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC8             ((uint)0x37 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC7             ((uint)0x38 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC6             ((uint)0x39 + CPM_IRQ_OFFSET)
+#define SIU_INT_PC5             ((uint)0x3a + CPM_IRQ_OFFSET)
+#define SIU_INT_PC4             ((uint)0x3b + CPM_IRQ_OFFSET)
+#define SIU_INT_PC3             ((uint)0x3c + CPM_IRQ_OFFSET)
+#define SIU_INT_PC2             ((uint)0x3d + CPM_IRQ_OFFSET)
+#define SIU_INT_PC1             ((uint)0x3e + CPM_IRQ_OFFSET)
+#define SIU_INT_PC0             ((uint)0x3f + CPM_IRQ_OFFSET)
+
+#endif /* CONFIG_8260 */
+
+/*
+ * This gets called from serial.c, which is now used on
+ * powermacs as well as prep/chrp boxes.
+ * Prep and chrp both have cascaded 8259 PICs.
+ */
+static __inline__ int irq_canonicalize(int irq)
+{
+        if (ppc_md.irq_canonicalize)
+                return ppc_md.irq_canonicalize(irq);
+        return irq;
+}
+
+#endif
+
+#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+/* pedantic: these are long because they are used with set_bit --RR */
+extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
+extern atomic_t ppc_n_lost_interrupts;
+
+struct irqaction;
+struct pt_regs;
+int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+
+#endif /* _ASM_IRQ_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h
new file mode 100644
index 000000000000..457c75a4622f
--- /dev/null
+++ b/include/asm-ppc/keylargo.h
@@ -0,0 +1,243 @@
+/*
+ * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
+ *
+ */
+
+/* "Pangea" chipset has keylargo device-id 0x25 while core99
+ * has device-id 0x22. The rev. of the pangea one is 0, so we
+ * fake an artificial rev. in keylargo_rev by oring 0x100
+ */
+#define KL_PANGEA_REV           0x100
+
+/* offset from base for feature control registers */
+#define KEYLARGO_MBCR           0x34    /* KL Only, Media bay control/status */
+#define KEYLARGO_FCR0           0x38
+#define KEYLARGO_FCR1           0x3c
+#define KEYLARGO_FCR2           0x40
+#define KEYLARGO_FCR3           0x44
+#define KEYLARGO_FCR4           0x48
+#define KEYLARGO_FCR5           0x4c    /* Pangea only */
+
+/* K2 aditional FCRs */
+#define K2_FCR6                 0x34
+#define K2_FCR7                 0x30
+#define K2_FCR8                 0x2c
+#define K2_FCR9                 0x28
+#define K2_FCR10                0x24
+
+/* GPIO registers */
+#define KEYLARGO_GPIO_LEVELS0           0x50
+#define KEYLARGO_GPIO_LEVELS1           0x54
+#define KEYLARGO_GPIO_EXTINT_0          0x58
+#define KEYLARGO_GPIO_EXTINT_CNT        18
+#define KEYLARGO_GPIO_0                 0x6A
+#define KEYLARGO_GPIO_CNT               17
+#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE  0x80
+#define KEYLARGO_GPIO_OUTPUT_ENABLE     0x04
+#define KEYLARGO_GPIO_OUTOUT_DATA       0x01
+#define KEYLARGO_GPIO_INPUT_DATA        0x02
+
+/* K2 does only extint GPIOs and does 51 of them */
+#define K2_GPIO_EXTINT_0                0x58
+#define K2_GPIO_EXTINT_CNT              51
+
+/* Specific GPIO regs */
+
+#define KL_GPIO_MODEM_RESET             (KEYLARGO_GPIO_0+0x03)
+#define KL_GPIO_MODEM_POWER             (KEYLARGO_GPIO_0+0x02) /* Pangea */
+
+#define KL_GPIO_SOUND_POWER             (KEYLARGO_GPIO_0+0x05)
+
+/* Hrm... this one is only to be used on Pismo. It seeem to also
+ * control the timebase enable on other machines. Still to be
+ * experimented... --BenH.
+ */
+#define KL_GPIO_FW_CABLE_POWER          (KEYLARGO_GPIO_0+0x09)
+#define KL_GPIO_TB_ENABLE               (KEYLARGO_GPIO_0+0x09)
+
+#define KL_GPIO_ETH_PHY_RESET           (KEYLARGO_GPIO_0+0x10)
+
+#define KL_GPIO_EXTINT_CPU1             (KEYLARGO_GPIO_0+0x0a)
+#define KL_GPIO_EXTINT_CPU1_ASSERT      0x04
+#define KL_GPIO_EXTINT_CPU1_RELEASE     0x38
+
+#define KL_GPIO_RESET_CPU0              (KEYLARGO_GPIO_EXTINT_0+0x03)
+#define KL_GPIO_RESET_CPU1              (KEYLARGO_GPIO_EXTINT_0+0x04)
+#define KL_GPIO_RESET_CPU2              (KEYLARGO_GPIO_EXTINT_0+0x0f)
+#define KL_GPIO_RESET_CPU3              (KEYLARGO_GPIO_EXTINT_0+0x10)
+
+#define KL_GPIO_PMU_MESSAGE_IRQ         (KEYLARGO_GPIO_EXTINT_0+0x09)
+#define KL_GPIO_PMU_MESSAGE_BIT         KEYLARGO_GPIO_INPUT_DATA
+
+#define KL_GPIO_MEDIABAY_IRQ            (KEYLARGO_GPIO_EXTINT_0+0x0e)
+
+#define KL_GPIO_AIRPORT_0               (KEYLARGO_GPIO_EXTINT_0+0x0a)
+#define KL_GPIO_AIRPORT_1               (KEYLARGO_GPIO_EXTINT_0+0x0d)
+#define KL_GPIO_AIRPORT_2               (KEYLARGO_GPIO_0+0x0d)
+#define KL_GPIO_AIRPORT_3               (KEYLARGO_GPIO_0+0x0e)
+#define KL_GPIO_AIRPORT_4               (KEYLARGO_GPIO_0+0x0f)
+
+/*
+ * Bits in feature control register. Those bits different for K2 are
+ * listed separately
+ */
+#define KL_MBCR_MB0_PCI_ENABLE          0x00000800      /* exist ? */
+#define KL_MBCR_MB0_IDE_ENABLE          0x00001000
+#define KL_MBCR_MB0_FLOPPY_ENABLE       0x00002000      /* exist ? */
+#define KL_MBCR_MB0_SOUND_ENABLE        0x00004000      /* hrm... */
+#define KL_MBCR_MB0_DEV_MASK            0x00007800
+#define KL_MBCR_MB0_DEV_POWER           0x00000400
+#define KL_MBCR_MB0_DEV_RESET           0x00000200
+#define KL_MBCR_MB0_ENABLE              0x00000100
+#define KL_MBCR_MB1_PCI_ENABLE          0x08000000      /* exist ? */
+#define KL_MBCR_MB1_IDE_ENABLE          0x10000000
+#define KL_MBCR_MB1_FLOPPY_ENABLE       0x20000000      /* exist ? */
+#define KL_MBCR_MB1_SOUND_ENABLE        0x40000000      /* hrm... */
+#define KL_MBCR_MB1_DEV_MASK            0x78000000
+#define KL_MBCR_MB1_DEV_POWER           0x04000000
+#define KL_MBCR_MB1_DEV_RESET           0x02000000
+#define KL_MBCR_MB1_ENABLE              0x01000000
+
+#define KL0_SCC_B_INTF_ENABLE           0x00000001      /* (KL Only) */
+#define KL0_SCC_A_INTF_ENABLE           0x00000002
+#define KL0_SCC_SLOWPCLK                0x00000004
+#define KL0_SCC_RESET                   0x00000008
+#define KL0_SCCA_ENABLE                 0x00000010
+#define KL0_SCCB_ENABLE                 0x00000020
+#define KL0_SCC_CELL_ENABLE             0x00000040
+#define KL0_IRDA_HIGH_BAND              0x00000100      /* (KL Only) */
+#define KL0_IRDA_SOURCE2_SEL            0x00000200      /* (KL Only) */
+#define KL0_IRDA_SOURCE1_SEL            0x00000400      /* (KL Only) */
+#define KL0_PG_USB0_PMI_ENABLE          0x00000400      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_RESET                  0x00000800      /* (KL Only) */
+#define KL0_PG_USB0_REF_SUSPEND_SEL     0x00000800      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_DEFAULT1               0x00001000      /* (KL Only) */
+#define KL0_PG_USB0_REF_SUSPEND         0x00001000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_DEFAULT0               0x00002000      /* (KL Only) */
+#define KL0_PG_USB0_PAD_SUSPEND         0x00002000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_FAST_CONNECT           0x00004000      /* (KL Only) */
+#define KL0_PG_USB1_PMI_ENABLE          0x00004000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_ENABLE                 0x00008000      /* (KL Only) */
+#define KL0_PG_USB1_REF_SUSPEND_SEL     0x00008000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_CLK32_ENABLE           0x00010000      /* (KL Only) */
+#define KL0_PG_USB1_REF_SUSPEND         0x00010000      /* (Pangea/Intrepid Only) */
+#define KL0_IRDA_CLK19_ENABLE           0x00020000      /* (KL Only) */
+#define KL0_PG_USB1_PAD_SUSPEND         0x00020000      /* (Pangea/Intrepid Only) */
+#define KL0_USB0_PAD_SUSPEND0           0x00040000
+#define KL0_USB0_PAD_SUSPEND1           0x00080000
+#define KL0_USB0_CELL_ENABLE            0x00100000
+#define KL0_USB1_PAD_SUSPEND0           0x00400000
+#define KL0_USB1_PAD_SUSPEND1           0x00800000
+#define KL0_USB1_CELL_ENABLE            0x01000000
+#define KL0_USB_REF_SUSPEND             0x10000000      /* (KL Only) */
+
+#define KL0_SERIAL_ENABLE               (KL0_SCC_B_INTF_ENABLE | \
+                                        KL0_SCC_SLOWPCLK | \
+                                        KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
+
+#define KL1_USB2_PMI_ENABLE             0x00000001      /* Intrepid only */
+#define KL1_AUDIO_SEL_22MCLK            0x00000002      /* KL/Pangea only */
+#define KL1_USB2_REF_SUSPEND_SEL        0x00000002      /* Intrepid only */
+#define KL1_USB2_REF_SUSPEND            0x00000004      /* Intrepid only */
+#define KL1_AUDIO_CLK_ENABLE_BIT        0x00000008      /* KL/Pangea only */
+#define KL1_USB2_PAD_SUSPEND_SEL        0x00000008      /* Intrepid only */
+#define KL1_USB2_PAD_SUSPEND0           0x00000010      /* Intrepid only */
+#define KL1_AUDIO_CLK_OUT_ENABLE        0x00000020      /* KL/Pangea only */
+#define KL1_USB2_PAD_SUSPEND1           0x00000020      /* Intrepid only */
+#define KL1_AUDIO_CELL_ENABLE           0x00000040      /* KL/Pangea only */
+#define KL1_USB2_CELL_ENABLE            0x00000040      /* Intrepid only */
+#define KL1_AUDIO_CHOOSE                0x00000080      /* KL/Pangea only */
+#define KL1_I2S0_CHOOSE                 0x00000200      /* KL Only */
+#define KL1_I2S0_CELL_ENABLE            0x00000400
+#define KL1_I2S0_CLK_ENABLE_BIT         0x00001000
+#define KL1_I2S0_ENABLE                 0x00002000
+#define KL1_I2S1_CELL_ENABLE            0x00020000
+#define KL1_I2S1_CLK_ENABLE_BIT         0x00080000
+#define KL1_I2S1_ENABLE                 0x00100000
+#define KL1_EIDE0_ENABLE                0x00800000      /* KL/Intrepid Only */
+#define KL1_EIDE0_RESET_N               0x01000000      /* KL/Intrepid Only */
+#define KL1_EIDE1_ENABLE                0x04000000      /* KL Only */
+#define KL1_EIDE1_RESET_N               0x08000000      /* KL Only */
+#define KL1_UIDE_ENABLE                 0x20000000      /* KL/Pangea Only */
+#define KL1_UIDE_RESET_N                0x40000000      /* KL/Pangea Only */
+
+#define KL2_IOBUS_ENABLE                0x00000002
+#define KL2_SLEEP_STATE_BIT             0x00000100      /* KL Only */
+#define KL2_PG_STOP_ALL_CLOCKS          0x00000100      /* Pangea Only */
+#define KL2_MPIC_ENABLE                 0x00020000
+#define KL2_CARDSLOT_RESET              0x00040000      /* Pangea/Intrepid Only */
+#define KL2_ALT_DATA_OUT                0x02000000      /* KL Only ??? */
+#define KL2_MEM_IS_BIG                  0x04000000
+#define KL2_CARDSEL_16                  0x08000000
+
+#define KL3_SHUTDOWN_PLL_TOTAL          0x00000001      /* KL/Pangea only */
+#define KL3_SHUTDOWN_PLLKW6             0x00000002      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL3            0x00000002      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW4             0x00000004      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL2            0x00000004      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW35            0x00000008      /* KL/Pangea only */
+#define KL3_IT_SHUTDOWN_PLL1            0x00000008      /* Intrepid only */
+#define KL3_SHUTDOWN_PLLKW12            0x00000010      /* KL Only */
+#define KL3_IT_ENABLE_PLL3_SHUTDOWN     0x00000010      /* Intrepid only */
+#define KL3_PLL_RESET                   0x00000020      /* KL/Pangea only */
+#define KL3_IT_ENABLE_PLL2_SHUTDOWN     0x00000020      /* Intrepid only */
+#define KL3_IT_ENABLE_PLL1_SHUTDOWN     0x00000010      /* Intrepid only */
+#define KL3_SHUTDOWN_PLL2X              0x00000080      /* KL Only */
+#define KL3_CLK66_ENABLE                0x00000100      /* KL Only */
+#define KL3_CLK49_ENABLE                0x00000200
+#define KL3_CLK45_ENABLE                0x00000400
+#define KL3_CLK31_ENABLE                0x00000800      /* KL/Pangea only */
+#define KL3_TIMER_CLK18_ENABLE          0x00001000
+#define KL3_I2S1_CLK18_ENABLE           0x00002000
+#define KL3_I2S0_CLK18_ENABLE           0x00004000
+#define KL3_VIA_CLK16_ENABLE            0x00008000      /* KL/Pangea only */
+#define KL3_IT_VIA_CLK32_ENABLE         0x00008000      /* Intrepid only */
+#define KL3_STOPPING33_ENABLED          0x00080000      /* KL Only */
+#define KL3_PG_PLL_ENABLE_TEST          0x00080000      /* Pangea Only */
+
+/* Intrepid USB bus 2, port 0,1 */
+#define KL3_IT_PORT_WAKEUP_ENABLE(p)            (0x00080000 << ((p)<<3))
+#define KL3_IT_PORT_RESUME_WAKE_EN(p)           (0x00040000 << ((p)<<3))
+#define KL3_IT_PORT_CONNECT_WAKE_EN(p)          (0x00020000 << ((p)<<3))
+#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)       (0x00010000 << ((p)<<3))
+#define KL3_IT_PORT_RESUME_STAT(p)              (0x00300000 << ((p)<<3))
+#define KL3_IT_PORT_CONNECT_STAT(p)             (0x00200000 << ((p)<<3))
+#define KL3_IT_PORT_DISCONNECT_STAT(p)          (0x00100000 << ((p)<<3))
+
+/* Port 0,1 : bus 0, port 2,3 : bus 1 */
+#define KL4_PORT_WAKEUP_ENABLE(p)       (0x00000008 << ((p)<<3))
+#define KL4_PORT_RESUME_WAKE_EN(p)      (0x00000004 << ((p)<<3))
+#define KL4_PORT_CONNECT_WAKE_EN(p)     (0x00000002 << ((p)<<3))
+#define KL4_PORT_DISCONNECT_WAKE_EN(p)  (0x00000001 << ((p)<<3))
+#define KL4_PORT_RESUME_STAT(p)         (0x00000040 << ((p)<<3))
+#define KL4_PORT_CONNECT_STAT(p)        (0x00000020 << ((p)<<3))
+#define KL4_PORT_DISCONNECT_STAT(p)     (0x00000010 << ((p)<<3))
+
+/* Pangea and Intrepid only */
+#define KL5_VIA_USE_CLK31               0000000001      /* Pangea Only */
+#define KL5_SCC_USE_CLK31               0x00000002      /* Pangea Only */
+#define KL5_PWM_CLK32_EN                0x00000004
+#define KL5_CLK3_68_EN                  0x00000010
+#define KL5_CLK32_EN                    0x00000020
+
+
+/* K2 definitions */
+#define K2_FCR0_USB0_SWRESET            0x00200000
+#define K2_FCR0_USB1_SWRESET            0x02000000
+#define K2_FCR0_RING_PME_DISABLE        0x08000000
+
+#define K2_FCR1_PCI1_BUS_RESET_N        0x00000010
+#define K2_FCR1_PCI1_SLEEP_RESET_EN     0x00000020
+#define K2_FCR1_PCI1_CLK_ENABLE         0x00004000
+#define K2_FCR1_FW_CLK_ENABLE           0x00008000
+#define K2_FCR1_FW_RESET_N              0x00010000
+#define K2_FCR1_GMAC_CLK_ENABLE         0x00400000
+#define K2_FCR1_GMAC_POWER_DOWN         0x00800000
+#define K2_FCR1_GMAC_RESET_N            0x01000000
+#define K2_FCR1_SATA_CLK_ENABLE         0x02000000
+#define K2_FCR1_SATA_POWER_DOWN         0x04000000
+#define K2_FCR1_SATA_RESET_N            0x08000000
+#define K2_FCR1_UATA_CLK_ENABLE         0x10000000
+#define K2_FCR1_UATA_RESET_N            0x40000000
+#define K2_FCR1_UATA_CHOOSE_CLK66       0x80000000
+
diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h
new file mode 100644
index 000000000000..1d3c927ce626
--- /dev/null
+++ b/include/asm-ppc/kgdb.h
@@ -0,0 +1,57 @@
+/*
+ * kgdb.h: Defines and declarations for serial line source level
+ *         remote debugging of the Linux kernel using gdb.
+ *
+ * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_KGDB_H
+#define _PPC_KGDB_H
+
+#ifndef __ASSEMBLY__
+
+/* Things specific to the gen550 backend. */
+struct uart_port;
+
+extern void gen550_progress(char *, unsigned short);
+extern void gen550_kgdb_map_scc(void);
+extern void gen550_init(int, struct uart_port *);
+
+/* Things specific to the pmac backend. */
+extern void zs_kgdb_hook(int tty_num);
+
+/* To init the kgdb engine. (called by serial hook)*/
+extern void set_debug_traps(void);
+
+/* To enter the debugger explicitly. */
+extern void breakpoint(void);
+
+/* For taking exceptions
+ * these are defined in traps.c
+ */
+extern void (*debugger)(struct pt_regs *regs);
+extern int (*debugger_bpt)(struct pt_regs *regs);
+extern int (*debugger_sstep)(struct pt_regs *regs);
+extern int (*debugger_iabr_match)(struct pt_regs *regs);
+extern int (*debugger_dabr_match)(struct pt_regs *regs);
+extern void (*debugger_fault_handler)(struct pt_regs *regs);
+
+/* What we bring to the party */
+int kgdb_bpt(struct pt_regs *regs);
+int kgdb_sstep(struct pt_regs *regs);
+void kgdb(struct pt_regs *regs);
+int kgdb_iabr_match(struct pt_regs *regs);
+int kgdb_dabr_match(struct pt_regs *regs);
+
+/*
+ * external low-level support routines (ie macserial.c)
+ */
+extern void kgdb_interruptible(int); /* control interrupts from serial */
+extern void putDebugChar(char);   /* write a single character      */
+extern char getDebugChar(void);   /* read and return a single char */
+
+#endif /* !(__ASSEMBLY__) */
+#endif /* !(_PPC_KGDB_H) */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
new file mode 100644
index 000000000000..2589f182a6ad
--- /dev/null
+++ b/include/asm-ppc/kmap_types.h
@@ -0,0 +1,24 @@
+#ifdef __KERNEL__
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_PPC_SYNC_PAGE,
+        KM_TYPE_NR
+};
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/linkage.h b/include/asm-ppc/linkage.h
new file mode 100644
index 000000000000..291c2d01c44f
--- /dev/null
+++ b/include/asm-ppc/linkage.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* Nothing to see here... */
+
+#endif
diff --git a/include/asm-ppc/local.h b/include/asm-ppc/local.h
new file mode 100644
index 000000000000..b08e3eced10e
--- /dev/null
+++ b/include/asm-ppc/local.h
@@ -0,0 +1,6 @@
+#ifndef __PPC_LOCAL_H
+#define __PPC_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif /* __PPC_LOCAL_H */
diff --git a/include/asm-ppc/m48t35.h b/include/asm-ppc/m48t35.h
new file mode 100644
index 000000000000..f3c5e5dfa986
--- /dev/null
+++ b/include/asm-ppc/m48t35.h
@@ -0,0 +1,77 @@
+/*
+ *  Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
+ *  and
+ *  Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
+ *  The 37 is the 35 plus alarm and century thus the offsets
+ *  are shifted by the extra registers.
+ */
+
+#ifndef __PPC_M48T35_H
+#define __PPC_M48T35_H
+
+/* RTC offsets */
+#define M48T35_RTC_FLAGS        (-8)    /* the negative regs are really T37 only */
+#define M48T35_RTC_CENTURY      (-7)
+#define M48T35_RTC_AL_SEC       (-6)
+#define M48T35_RTC_AL_MIN       (-5)
+#define M48T35_RTC_AL_HRS       (-4)
+#define M48T35_RTC_AL_DOM       (-3)
+#define M48T35_RTC_INTERRUPT    (-2)
+#define M48T35_RTC_WATCHDOG     (-1)
+#define M48T35_RTC_CONTROL      0       /* T35 starts here */
+#define M48T35_RTC_SECONDS      1
+#define M48T35_RTC_MINUTES      2
+#define M48T35_RTC_HOURS        3
+#define M48T35_RTC_DAY          4
+#define M48T35_RTC_DOM          5
+#define M48T35_RTC_MONTH        6
+#define M48T35_RTC_YEAR         7
+
+/* this way help us know which bits go with which regs */
+#define M48T35_RTC_FLAGS_BL           0x10
+#define M48T35_RTC_FLAGS_AF           0x40
+#define M48T35_RTC_FLAGS_WDF          0x80
+
+#define M48T35_RTC_INTERRUPT_AFE       0x80
+#define M48T35_RTC_INTERRUPT_ABE       0x20
+#define M48T35_RTC_INTERRUPT_ALL       (M48T35_RTC_INTERRUPT_AFE|M48T35_RTC_INTERRUPT_ABE)
+
+#define M48T35_RTC_WATCHDOG_RB         0x03
+#define M48T35_RTC_WATCHDOG_BMB        0x7c
+#define M48T35_RTC_WATCHDOG_WDS        0x80
+#define M48T35_RTC_WATCHDOG_ALL        (M48T35_RTC_WATCHDOG_RB|M48T35_RTC_WATCHDOG_BMB|M48T35_RTC_W
+
+#define M48T35_RTC_CONTROL_WRITE       0x80
+#define M48T35_RTC_CONTROL_READ        0x40
+#define M48T35_RTC_CONTROL_CAL_SIGN    0x20
+#define M48T35_RTC_CONTROL_CAL_VALUE   0x1f
+#define M48T35_RTC_CONTROL_LOCKED      (M48T35_RTC_WRITE|M48T35_RTC_READ)
+#define M48T35_RTC_CONTROL_CALIBRATION (M48T35_RTC_CONTROL_CAL_SIGN|M48T35_RTC_CONTROL_CAL_VALUE)
+
+#define M48T35_RTC_SECONDS_SEC_1       0x0f
+#define M48T35_RTC_SECONDS_SEC_10      0x70
+#define M48T35_RTC_SECONDS_ST          0x80
+#define M48T35_RTC_SECONDS_SEC_ALL     (M48T35_RTC_SECONDS_SEC_1|M48T35_RTC_SECONDS_SEC_10)
+
+#define M48T35_RTC_MINUTES_MIN_1       0x0f
+#define M48T35_RTC_MINUTES_MIN_10      0x70
+#define M48T35_RTC_MINUTES_MIN_ALL     (M48T35_RTC_MINUTES_MIN_1|M48T35_RTC_MINUTES_MIN_10)
+
+#define M48T35_RTC_HOURS_HRS_1         0x0f
+#define M48T35_RTC_HOURS_HRS_10        0x30
+#define M48T35_RTC_HOURS_HRS_ALL       (M48T35_RTC_HOURS_HRS_1|M48T35_RTC_HOURS_HRS_10)
+
+#define M48T35_RTC_DAY_DAY_1           0x03
+#define M48T35_RTC_DAY_FT              0x40
+
+#define M48T35_RTC_ALARM_OFF           0x00
+#define M48T35_RTC_WATCHDOG_OFF        0x00
+
+
+/* legacy */
+#define M48T35_RTC_SET      0x80
+#define M48T35_RTC_STOPPED  0x80
+#define M48T35_RTC_READ     0x40
+
+
+#endif
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
new file mode 100644
index 000000000000..163a6b91d5b2
--- /dev/null
+++ b/include/asm-ppc/m8260_pci.h
@@ -0,0 +1,186 @@
+/*
+ * include/asm-ppc/m8260_pci.h
+ *
+ * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __M8260_PCI_H
+#define __M8260_PCI_H
+
+#include <linux/pci_ids.h>
+
+/*
+ * Define the vendor/device ID for the MPC8265.
+ */
+#define PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+
+#define M8265_PCIBR0    0x101ac
+#define M8265_PCIBR1    0x101b0
+#define M8265_PCIMSK0   0x101c4
+#define M8265_PCIMSK1   0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KiB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KiB         0xFFFF0000
+#define PCIMSK_128KiB        0xFFFE0000
+#define PCIMSK_256KiB        0xFFFC0000
+#define PCIMSK_512KiB        0xFFF80000
+#define PCIMSK_1MiB          0xFFF00000
+#define PCIMSK_2MiB          0xFFE00000
+#define PCIMSK_4MiB          0xFFC00000
+#define PCIMSK_8MiB          0xFF800000
+#define PCIMSK_16MiB         0xFF000000
+#define PCIMSK_32MiB         0xFE000000
+#define PCIMSK_64MiB         0xFC000000
+#define PCIMSK_128MiB        0xF8000000
+#define PCIMSK_256MiB        0xF0000000
+#define PCIMSK_512MiB        0xE0000000
+#define PCIMSK_1GiB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus (local) 
+ * addresses are translated to PCI addresses when the MPC826x is a PCI bus 
+ * master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KiB      0x000FFFFF
+#define POCMR_MASK_8KiB      0x000FFFFE
+#define POCMR_MASK_16KiB     0x000FFFFC
+#define POCMR_MASK_32KiB     0x000FFFF8
+#define POCMR_MASK_64KiB     0x000FFFF0
+#define POCMR_MASK_128KiB    0x000FFFE0
+#define POCMR_MASK_256KiB    0x000FFFC0
+#define POCMR_MASK_512KiB    0x000FFF80
+#define POCMR_MASK_1MiB      0x000FFF00
+#define POCMR_MASK_2MiB      0x000FFE00
+#define POCMR_MASK_4MiB      0x000FFC00
+#define POCMR_MASK_8MiB      0x000FF800
+#define POCMR_MASK_16MiB     0x000FF000
+#define POCMR_MASK_32MiB     0x000FE000
+#define POCMR_MASK_64MiB     0x000FC000
+#define POCMR_MASK_128MiB    0x000F8000
+#define POCMR_MASK_256MiB    0x000F0000
+#define POCMR_MASK_512MiB    0x000E0000
+#define POCMR_MASK_1GiB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+#define PCI_EMR_REG         0x10888
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI addresses 
+ * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KiB       0x000FFFFF
+#define PICMR_MASK_8KiB       0x000FFFFE
+#define PICMR_MASK_16KiB      0x000FFFFC
+#define PICMR_MASK_32KiB      0x000FFFF8
+#define PICMR_MASK_64KiB      0x000FFFF0
+#define PICMR_MASK_128KiB     0x000FFFE0
+#define PICMR_MASK_256KiB     0x000FFFC0
+#define PICMR_MASK_512KiB     0x000FFF80
+#define PICMR_MASK_1MiB       0x000FFF00
+#define PICMR_MASK_2MiB       0x000FFE00
+#define PICMR_MASK_4MiB       0x000FFC00
+#define PICMR_MASK_8MiB       0x000FF800
+#define PICMR_MASK_16MiB      0x000FF000
+#define PICMR_MASK_32MiB      0x000FE000
+#define PICMR_MASK_64MiB      0x000FC000
+#define PICMR_MASK_128MiB     0x000F8000
+#define PICMR_MASK_256MiB     0x000F0000
+#define PICMR_MASK_512MiB     0x000E0000
+#define PICMR_MASK_1GiB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define PCI_ERROR_STATUS_REG            0x10884
+#define PCI_ERROR_MASK_REG              0x10888
+#define PCI_ERROR_CONTROL_REG           0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define PCI_ERROR_PCI_ADDR_PAR                  0x00000001
+#define PCI_ERROR_PCI_DATA_PAR_WR               0x00000002
+#define PCI_ERROR_PCI_DATA_PAR_RD               0x00000004
+#define PCI_ERROR_PCI_NO_RSP                    0x00000008
+#define PCI_ERROR_PCI_TAR_ABT                   0x00000010
+#define PCI_ERROR_PCI_SERR                      0x00000020
+#define PCI_ERROR_PCI_PERR_RD                   0x00000040
+#define PCI_ERROR_PCI_PERR_WR                   0x00000080
+#define PCI_ERROR_I2O_OFQO                      0x00000100
+#define PCI_ERROR_I2O_IPQO                      0x00000200
+#define PCI_ERROR_IRA                           0x00000400
+#define PCI_ERROR_NMI                           0x00000800
+#define PCI_ERROR_I2O_DBMC                      0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* __M8260_PCI_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
new file mode 100644
index 000000000000..b78d40870c95
--- /dev/null
+++ b/include/asm-ppc/machdep.h
@@ -0,0 +1,154 @@
+#ifdef __KERNEL__
+#ifndef _PPC_MACHDEP_H
+#define _PPC_MACHDEP_H
+
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+
+#ifdef CONFIG_APUS
+#include <asm-m68k/machdep.h>
+#endif
+
+struct pt_regs;
+struct pci_bus; 
+struct pci_dev;
+struct seq_file;
+struct file;
+
+/* We export this macro for external modules like Alsa to know if
+ * ppc_md.feature_call is implemented or not
+ */
+#define CONFIG_PPC_HAS_FEATURE_CALLS
+
+struct machdep_calls {
+        void            (*setup_arch)(void);
+        /* Optional, may be NULL. */
+        int             (*show_cpuinfo)(struct seq_file *m);
+        int             (*show_percpuinfo)(struct seq_file *m, int i);
+        /* Optional, may be NULL. */
+        unsigned int    (*irq_canonicalize)(unsigned int irq);
+        void            (*init_IRQ)(void);
+        int             (*get_irq)(struct pt_regs *);
+        
+        /* A general init function, called by ppc_init in init/main.c.
+           May be NULL. */
+        void            (*init)(void);
+
+        void            (*restart)(char *cmd);
+        void            (*power_off)(void);
+        void            (*halt)(void);
+
+        void            (*idle)(void);
+        void            (*power_save)(void);
+
+        long            (*time_init)(void); /* Optional, may be NULL */
+        int             (*set_rtc_time)(unsigned long nowtime);
+        unsigned long   (*get_rtc_time)(void);
+        unsigned char   (*rtc_read_val)(int addr);
+        void            (*rtc_write_val)(int addr, unsigned char val);
+        void            (*calibrate_decr)(void);
+
+        void            (*heartbeat)(void);
+        unsigned long   heartbeat_reset;
+        unsigned long   heartbeat_count;
+
+        unsigned long   (*find_end_of_memory)(void);
+        void            (*setup_io_mappings)(void);
+
+        void            (*early_serial_map)(void);
+        void            (*progress)(char *, unsigned short);
+        void            (*kgdb_map_scc)(void);
+
+        unsigned char   (*nvram_read_val)(int addr);
+        void            (*nvram_write_val)(int addr, unsigned char val);
+        void            (*nvram_sync)(void);
+
+        /*
+         * optional PCI "hooks"
+         */
+
+        /* Called after scanning the bus, before allocating resources */
+        void (*pcibios_fixup)(void);
+
+        /* Called after PPC generic resource fixup to perform
+           machine specific fixups */
+        void (*pcibios_fixup_resources)(struct pci_dev *);
+
+        /* Called for each PCI bus in the system when it's probed */
+        void (*pcibios_fixup_bus)(struct pci_bus *);
+
+        /* Called when pci_enable_device() is called (initial=0) or
+         * when a device with no assigned resource is found (initial=1).
+         * Returns 0 to allow assignment/enabling of the device. */
+        int  (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
+
+        /* For interrupt routing */
+        unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
+        int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
+
+        /* Called in indirect_* to avoid touching devices */
+        int (*pci_exclude_device)(unsigned char, unsigned char);
+
+        /* Called at then very end of pcibios_init() */
+        void (*pcibios_after_init)(void);
+
+        /* Get access protection for /dev/mem */
+        pgprot_t        (*phys_mem_access_prot)(struct file *file,
+                                                unsigned long offset,
+                                                unsigned long size,
+                                                pgprot_t vma_prot);
+
+        /* this is for modules, since _machine can be a define -- Cort */
+        int ppc_machine;
+
+        /* Motherboard/chipset features. This is a kind of general purpose
+         * hook used to control some machine specific features (like reset
+         * lines, chip power control, etc...).
+         */
+        long (*feature_call)(unsigned int feature, ...);
+
+#ifdef CONFIG_SMP
+        /* functions for dealing with other cpus */
+        struct smp_ops_t *smp_ops;
+#endif /* CONFIG_SMP */
+};
+
+extern struct machdep_calls ppc_md;
+extern char cmd_line[COMMAND_LINE_SIZE];
+
+extern void setup_pci_ptrs(void);
+
+/*
+ * Power macintoshes have either a CUDA or a PMU controlling
+ * system reset, power, NVRAM, RTC.
+ */
+typedef enum sys_ctrler_kind {
+        SYS_CTRLER_UNKNOWN = 0,
+        SYS_CTRLER_CUDA = 1,
+        SYS_CTRLER_PMU = 2,
+        SYS_CTRLER_SMU = 3,
+} sys_ctrler_t;
+
+extern sys_ctrler_t sys_ctrler;
+
+#ifdef CONFIG_SMP
+struct smp_ops_t {
+        void  (*message_pass)(int target, int msg, unsigned long data, int wait);
+        int   (*probe)(void);
+        void  (*kick_cpu)(int nr);
+        void  (*setup_cpu)(int nr);
+        void  (*space_timers)(int nr);
+        void  (*take_timebase)(void);
+        void  (*give_timebase)(void);
+};
+
+/* Poor default implementations */
+extern void __devinit smp_generic_give_timebase(void);
+extern void __devinit smp_generic_take_timebase(void);
+#endif /* CONFIG_SMP */
+
+#endif /* _PPC_MACHDEP_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/macio.h b/include/asm-ppc/macio.h
new file mode 100644
index 000000000000..00605bb88b2a
--- /dev/null
+++ b/include/asm-ppc/macio.h
@@ -0,0 +1,140 @@
+#ifndef __MACIO_ASIC_H__
+#define __MACIO_ASIC_H__
+
+#include <asm/of_device.h>
+
+extern struct bus_type macio_bus_type;
+
+/* MacIO device driver is defined later */
+struct macio_driver;
+struct macio_chip;
+
+#define MACIO_DEV_COUNT_RESOURCES       8
+#define MACIO_DEV_COUNT_IRQS            8
+
+/*
+ * the macio_bus structure is used to describe a "virtual" bus
+ * within a MacIO ASIC. It's typically provided by a macio_pci_asic
+ * PCI device, but could be provided differently as well (nubus
+ * machines using a fake OF tree).
+ *
+ * The pdev field can be NULL on non-PCI machines
+ */
+struct macio_bus
+{
+        struct macio_chip       *chip;          /* macio_chip (private use) */
+        int                     index;          /* macio chip index in system */
+#ifdef CONFIG_PCI
+        struct pci_dev          *pdev;          /* PCI device hosting this bus */
+#endif
+};
+
+/*
+ * the macio_dev structure is used to describe a device
+ * within an Apple MacIO ASIC.
+ */
+struct macio_dev
+{
+        struct macio_bus        *bus;           /* macio bus this device is on */
+        struct macio_dev        *media_bay;     /* Device is part of a media bay */
+        struct of_device        ofdev;
+        int                     n_resources;
+        struct resource         resource[MACIO_DEV_COUNT_RESOURCES];
+        int                     n_interrupts;
+        struct resource         interrupt[MACIO_DEV_COUNT_IRQS];
+};
+#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
+#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
+
+extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
+extern void macio_dev_put(struct macio_dev *dev);
+
+/*
+ * Accessors to resources & interrupts and other device
+ * fields
+ */
+
+static inline int macio_resource_count(struct macio_dev *dev)
+{
+        return dev->n_resources;
+}
+
+static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
+{
+        return dev->resource[resource_no].start;
+}
+
+static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
+{
+        return dev->resource[resource_no].end;
+}
+
+static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
+{
+        struct resource *res = &dev->resource[resource_no];
+        if (res->start == 0 || res->end == 0 || res->end < res->start)
+                return 0;
+        return res->end - res->start + 1;
+}
+
+extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
+extern void macio_release_resource(struct macio_dev *dev, int resource_no);
+extern int macio_request_resources(struct macio_dev *dev, const char *name);
+extern void macio_release_resources(struct macio_dev *dev);
+
+static inline int macio_irq_count(struct macio_dev *dev)
+{
+        return dev->n_interrupts;
+}
+
+static inline int macio_irq(struct macio_dev *dev, int irq_no)
+{
+        return dev->interrupt[irq_no].start;
+}
+
+static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
+{
+        dev_set_drvdata(&dev->ofdev.dev, data);
+}
+
+static inline void* macio_get_drvdata(struct macio_dev *dev)
+{
+        return dev_get_drvdata(&dev->ofdev.dev);
+}
+
+static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
+{
+        return mdev->ofdev.node;
+}
+
+#ifdef CONFIG_PCI
+static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
+{
+        return mdev->bus->pdev;
+}
+#endif
+
+/*
+ * A driver for a mac-io chip based device
+ */
+struct macio_driver
+{
+        char                    *name;
+        struct of_match         *match_table;
+        struct module           *owner;
+
+        int     (*probe)(struct macio_dev* dev, const struct of_match *match);
+        int     (*remove)(struct macio_dev* dev);
+
+        int     (*suspend)(struct macio_dev* dev, u32 state);
+        int     (*resume)(struct macio_dev* dev);
+        int     (*shutdown)(struct macio_dev* dev);
+
+        struct device_driver    driver;
+};
+#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
+
+extern int macio_register_driver(struct macio_driver *);
+extern void macio_unregister_driver(struct macio_driver *);
+
+#endif /* __MACIO_ASIC_H__ */
diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h
new file mode 100644
index 000000000000..227018b2fef8
--- /dev/null
+++ b/include/asm-ppc/mc146818rtc.h
@@ -0,0 +1,31 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_MC146818RTC_H
+#define __ASM_PPC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#define RTC_IRQ 8
+
+#endif /* __ASM_PPC_MC146818RTC_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h
new file mode 100644
index 000000000000..9a9b6b42b4b4
--- /dev/null
+++ b/include/asm-ppc/md.h
@@ -0,0 +1,15 @@
+/*
+ * md.h: High speed xor_block operation for RAID4/5
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_MD_H
+#define __ASM_MD_H
+
+/* #define HAVE_ARCH_XORBLOCK */
+
+#define MD_XORBLOCK_ALIGNMENT   sizeof(long)
+
+#endif /* __ASM_MD_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mediabay.h b/include/asm-ppc/mediabay.h
new file mode 100644
index 000000000000..9daa3252d7b6
--- /dev/null
+++ b/include/asm-ppc/mediabay.h
@@ -0,0 +1,31 @@
+/*
+ * mediabay.h: definitions for using the media bay
+ * on PowerBook 3400 and similar computers.
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ */
+#ifndef _PPC_MEDIABAY_H
+#define _PPC_MEDIABAY_H
+
+#ifdef __KERNEL__
+
+#define MB_FD           0       /* media bay contains floppy drive (automatic eject ?) */
+#define MB_FD1          1       /* media bay contains floppy drive (manual eject ?) */
+#define MB_SOUND        2       /* sound device ? */
+#define MB_CD           3       /* media bay contains ATA drive such as CD or ZIP */
+#define MB_PCI          5       /* media bay contains a PCI device */
+#define MB_POWER        6       /* media bay contains a Power device (???) */
+#define MB_NO           7       /* media bay contains nothing */
+
+int check_media_bay(struct device_node *which_bay, int what);
+int check_media_bay_by_base(unsigned long base, int what);
+
+/* Number of bays in the machine or 0 */
+extern int media_bay_count;
+
+/* called by pmac-ide.c to register IDE controller for media bay */
+extern int media_bay_set_ide_infos(struct device_node* which_bay,
+                        unsigned long base, int irq, int index);
+
+#endif /* __KERNEL__ */
+#endif /* _PPC_MEDIABAY_H */
diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h
new file mode 100644
index 000000000000..6a0ed6fc2d56
--- /dev/null
+++ b/include/asm-ppc/mk48t59.h
@@ -0,0 +1,27 @@
+/*
+ * Registers for the mk48t59 real-time-clock
+ */
+
+#ifndef _PPC_MK48T59_H
+#define _PPC_MK48T59_H
+
+/* RTC Offsets */
+
+#define MK48T59_RTC_SECONDS             0x1FF9
+#define MK48T59_RTC_MINUTES             0x1FFA
+#define MK48T59_RTC_HOURS               0x1FFB
+#define MK48T59_RTC_DAY_OF_WEEK         0x1FFC
+#define MK48T59_RTC_DAY_OF_MONTH        0x1FFD
+#define MK48T59_RTC_MONTH               0x1FFE
+#define MK48T59_RTC_YEAR                0x1FFF
+
+#define MK48T59_RTC_CONTROLA            0x1FF8
+#define MK48T59_RTC_CA_WRITE            0x80
+#define MK48T59_RTC_CA_READ             0x40
+#define MK48T59_RTC_CA_CALIB_SIGN       0x20
+#define MK48T59_RTC_CA_CALIB_MASK       0x1f
+
+#define MK48T59_RTC_CONTROLB            0x1FF9
+#define MK48T59_RTC_CB_STOP             0x80
+
+#endif /* _PPC_MK48T59_H */
diff --git a/include/asm-ppc/mman.h b/include/asm-ppc/mman.h
new file mode 100644
index 000000000000..5fd19fd4936c
--- /dev/null
+++ b/include/asm-ppc/mman.h
@@ -0,0 +1,44 @@
+#ifndef __PPC_MMAN_H__
+#define __PPC_MMAN_H__
+
+#define PROT_READ       0x1             /* page can be read */
+#define PROT_WRITE      0x2             /* page can be written */
+#define PROT_EXEC       0x4             /* page can be executed */
+#define PROT_SEM        0x8             /* page may be used for atomic ops */
+#define PROT_NONE       0x0             /* page can not be accessed */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+#define MAP_SHARED      0x01            /* Share changes */
+#define MAP_PRIVATE     0x02            /* Changes are private */
+#define MAP_TYPE        0x0f            /* Mask for type of mapping */
+#define MAP_FIXED       0x10            /* Interpret addr exactly */
+#define MAP_ANONYMOUS   0x20            /* don't use a file */
+#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
+#define MAP_NORESERVE   0x40            /* don't reserve swap pages */
+#define MAP_LOCKED      0x80
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MS_ASYNC        1               /* sync memory asynchronously */
+#define MS_INVALIDATE   2               /* invalidate the caches */
+#define MS_SYNC         4               /* synchronous memory sync */
+
+#define MCL_CURRENT     0x2000          /* lock all currently mapped pages */
+#define MCL_FUTURE      0x4000          /* lock all additions to address space */
+
+#define MADV_NORMAL     0x0             /* default page-in behavior */
+#define MADV_RANDOM     0x1             /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2             /* read-ahead aggressively */
+#define MADV_WILLNEED   0x3             /* pre-fault pages */
+#define MADV_DONTNEED   0x4             /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON        MAP_ANONYMOUS
+#define MAP_FILE        0
+
+#endif /* __PPC_MMAN_H__ */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
new file mode 100644
index 000000000000..4a0c67f672c2
--- /dev/null
+++ b/include/asm-ppc/mmu.h
@@ -0,0 +1,454 @@
+/*
+ * PowerPC memory management structures
+ */
+
+#ifdef __KERNEL__
+#ifndef _PPC_MMU_H_
+#define _PPC_MMU_H_
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Define physical address type.  Machines using split size
+ * virtual/physical addressing like 32-bit virtual / 36-bit
+ * physical need a larger than native word size type. -Matt
+ */
+#ifndef CONFIG_PTE_64BIT
+typedef unsigned long phys_addr_t;
+#else
+typedef unsigned long long phys_addr_t;
+extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+#endif
+
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+
+/* Hardware Page Table Entry */
+typedef struct _PTE {
+#ifdef CONFIG_PPC64BRIDGE
+        unsigned long long vsid:52;
+        unsigned long api:5;
+        unsigned long :5;
+        unsigned long h:1;
+        unsigned long v:1;
+        unsigned long long rpn:52;
+#else /* CONFIG_PPC64BRIDGE */
+        unsigned long v:1;      /* Entry is valid */
+        unsigned long vsid:24;  /* Virtual segment identifier */
+        unsigned long h:1;      /* Hash algorithm indicator */
+        unsigned long api:6;    /* Abbreviated page index */
+        unsigned long rpn:20;   /* Real (physical) page number */
+#endif /* CONFIG_PPC64BRIDGE */
+        unsigned long    :3;    /* Unused */
+        unsigned long r:1;      /* Referenced */
+        unsigned long c:1;      /* Changed */
+        unsigned long w:1;      /* Write-thru cache mode */
+        unsigned long i:1;      /* Cache inhibited */
+        unsigned long m:1;      /* Memory coherence */
+        unsigned long g:1;      /* Guarded */
+        unsigned long  :1;      /* Unused */
+        unsigned long pp:2;     /* Page protection */
+} PTE;
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+#define PP_RWXX 0       /* Supervisor read/write, User none */
+#define PP_RWRX 1       /* Supervisor read/write, User read */
+#define PP_RWRW 2       /* Supervisor read/write, User read/write */
+#define PP_RXRX 3       /* Supervisor read,       User read */
+
+/* Segment Register */
+typedef struct _SEGREG {
+        unsigned long t:1;      /* Normal or I/O  type */
+        unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
+        unsigned long kp:1;     /* User 'key' (normally 1) */
+        unsigned long n:1;      /* No-execute */
+        unsigned long :4;       /* Unused */
+        unsigned long vsid:24;  /* Virtual Segment Identifier */
+} SEGREG;
+
+/* Block Address Translation (BAT) Registers */
+typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
+        unsigned long bepi:15;  /* Effective page index (virtual address) */
+        unsigned long :8;       /* unused */
+        unsigned long w:1;
+        unsigned long i:1;      /* Cache inhibit */
+        unsigned long m:1;      /* Memory coherence */
+        unsigned long ks:1;     /* Supervisor key (normally 0) */
+        unsigned long kp:1;     /* User key (normally 1) */
+        unsigned long pp:2;     /* Page access protections */
+} P601_BATU;
+
+typedef struct _BATU {          /* Upper part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+        unsigned long long bepi:47;
+#else /* CONFIG_PPC64BRIDGE */
+        unsigned long bepi:15;  /* Effective page index (virtual address) */
+#endif /* CONFIG_PPC64BRIDGE */
+        unsigned long :4;       /* Unused */
+        unsigned long bl:11;    /* Block size mask */
+        unsigned long vs:1;     /* Supervisor valid */
+        unsigned long vp:1;     /* User valid */
+} BATU;
+
+typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
+        unsigned long brpn:15;  /* Real page index (physical address) */
+        unsigned long :10;      /* Unused */
+        unsigned long v:1;      /* Valid bit */
+        unsigned long bl:6;     /* Block size mask */
+} P601_BATL;
+
+typedef struct _BATL {          /* Lower part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+        unsigned long long brpn:47;
+#else /* CONFIG_PPC64BRIDGE */
+        unsigned long brpn:15;  /* Real page index (physical address) */
+#endif /* CONFIG_PPC64BRIDGE */
+        unsigned long :10;      /* Unused */
+        unsigned long w:1;      /* Write-thru cache */
+        unsigned long i:1;      /* Cache inhibit */
+        unsigned long m:1;      /* Memory coherence */
+        unsigned long g:1;      /* Guarded (MBZ in IBAT) */
+        unsigned long :1;       /* Unused */
+        unsigned long pp:2;     /* Page access protections */
+} BATL;
+
+typedef struct _BAT {
+        BATU batu;              /* Upper register */
+        BATL batl;              /* Lower register */
+} BAT;
+
+typedef struct _P601_BAT {
+        P601_BATU batu;         /* Upper register */
+        P601_BATL batl;         /* Lower register */
+} P601_BAT;
+
+#endif /* __ASSEMBLY__ */
+
+/* Block size masks */
+#define BL_128K 0x000
+#define BL_256K 0x001
+#define BL_512K 0x003
+#define BL_1M   0x007
+#define BL_2M   0x00F
+#define BL_4M   0x01F
+#define BL_8M   0x03F
+#define BL_16M  0x07F
+#define BL_32M  0x0FF
+#define BL_64M  0x1FF
+#define BL_128M 0x3FF
+#define BL_256M 0x7FF
+
+/* BAT Access Protection */
+#define BPP_XX  0x00            /* No access */
+#define BPP_RX  0x01            /* Read only */
+#define BPP_RW  0x02            /* Read/write */
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read.  A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define SPRN_MI_CTR     784     /* Instruction TLB control register */
+#define MI_GPM          0x80000000      /* Set domain manager mode */
+#define MI_PPM          0x40000000      /* Set subpage protection */
+#define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
+#define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
+#define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
+#define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
+#define MI_RESETVAL     0x00000000      /* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MI_AP      786
+#define MI_Ks           0x80000000      /* Should not be set */
+#define MI_Kp           0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MI_EPN     787
+#define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
+#define MI_EVALID       0x00000200      /* Entry is valid */
+#define MI_ASIDMASK     0x0000000f      /* ASID match value */
+                                        /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define SPRN_MI_TWC     789
+#define MI_APG          0x000001e0      /* Access protection group (0) */
+#define MI_GUARDED      0x00000010      /* Guarded storage */
+#define MI_PSMASK       0x0000000c      /* Mask of page size bits */
+#define MI_PS8MEG       0x0000000c      /* 8M page size */
+#define MI_PS512K       0x00000004      /* 512K page size */
+#define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
+#define MI_SVALID       0x00000001      /* Segment entry is valid */
+                                        /* Reset value is undefined */
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define SPRN_MI_RPN     790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization.  This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT     0x000001fd
+
+#define SPRN_MD_CTR     792     /* Data TLB control register */
+#define MD_GPM          0x80000000      /* Set domain manager mode */
+#define MD_PPM          0x40000000      /* Set subpage protection */
+#define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
+#define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
+#define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
+#define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
+#define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
+#define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
+#define MD_RESETVAL     0x04000000      /* Value of register at reset */
+
+#define SPRN_M_CASID    793     /* Address space ID (context) to match */
+#define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define SPRN_MD_AP      794
+#define MD_Ks           0x80000000      /* Should not be set */
+#define MD_Kp           0x40000000      /* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define SPRN_MD_EPN     795
+#define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
+#define MD_EVALID       0x00000200      /* Entry is valid */
+#define MD_ASIDMASK     0x0000000f      /* ASID match value */
+                                        /* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define SPRN_M_TWB      796
+#define M_L1TB          0xfffff000      /* Level 1 table base address */
+#define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
+                                        /* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written.  It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define SPRN_MD_TWC     797
+#define MD_L2TB         0xfffff000      /* Level 2 table base address */
+#define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
+#define MD_APG          0x000001e0      /* Access protection group (0) */
+#define MD_GUARDED      0x00000010      /* Guarded storage */
+#define MD_PSMASK       0x0000000c      /* Mask of page size bits */
+#define MD_PS8MEG       0x0000000c      /* 8M page size */
+#define MD_PS512K       0x00000004      /* 512K page size */
+#define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
+#define MD_WT           0x00000002      /* Use writethrough page attribute */
+#define MD_SVALID       0x00000001      /* Segment entry is valid */
+                                        /* Reset value is undefined */
+
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define SPRN_MD_RPN     798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define SPRN_M_TW       799
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully- associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively.
+ */
+
+#define        PPC4XX_TLB_SIZE 64
+
+/*
+ * TLB entries are defined by a "high" tag portion and a "low" data
+ * portion.  On all architectures, the data portion is 32-bits.
+ *
+ * TLB entries are managed entirely under software control by reading,
+ * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
+ * instructions.
+ */
+
+#define TLB_LO          1
+#define TLB_HI          0
+
+#define TLB_DATA        TLB_LO
+#define TLB_TAG         TLB_HI
+
+/* Tag portion */
+
+#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
+#define TLB_PAGESZ_MASK 0x00000380
+#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
+#define   PAGESZ_1K             0
+#define   PAGESZ_4K             1
+#define   PAGESZ_16K            2
+#define   PAGESZ_64K            3
+#define   PAGESZ_256K           4
+#define   PAGESZ_1M             5
+#define   PAGESZ_4M             6
+#define   PAGESZ_16M            7
+#define TLB_VALID       0x00000040      /* Entry is valid */
+
+/* Data portion */
+
+#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
+#define TLB_PERM_MASK   0x00000300
+#define TLB_EX          0x00000200      /* Instruction execution allowed */
+#define TLB_WR          0x00000100      /* Writes permitted */
+#define TLB_ZSEL_MASK   0x000000F0
+#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
+#define TLB_ATTR_MASK   0x0000000F
+#define TLB_W           0x00000008      /* Caching is write-through */
+#define TLB_I           0x00000004      /* Caching is inhibited */
+#define TLB_M           0x00000002      /* Memory is coherent */
+#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
+
+/*
+ * PPC440 support
+ */
+#define PPC44x_MMUCR_TID        0x000000ff
+#define PPC44x_MMUCR_STS        0x00010000
+
+#define PPC44x_TLB_PAGEID       0
+#define PPC44x_TLB_XLAT         1
+#define PPC44x_TLB_ATTRIB       2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
+#define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
+#define PPC44x_TLB_TS           0x00000100      /* Translation address space */
+#define PPC44x_TLB_1K           0x00000000      /* Page sizes */
+#define PPC44x_TLB_4K           0x00000010
+#define PPC44x_TLB_16K          0x00000020
+#define PPC44x_TLB_64K          0x00000030
+#define PPC44x_TLB_256K         0x00000040
+#define PPC44x_TLB_1M           0x00000050
+#define PPC44x_TLB_16M          0x00000070
+#define PPC44x_TLB_256M         0x00000090
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
+#define PPC44x_TLB_ERPN_MASK    0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK    0x0000ff80
+#define PPC44x_TLB_U0           0x00008000      /* User 0 */
+#define PPC44x_TLB_U1           0x00004000      /* User 1 */
+#define PPC44x_TLB_U2           0x00002000      /* User 2 */
+#define PPC44x_TLB_U3           0x00001000      /* User 3 */
+#define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
+#define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
+#define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
+#define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
+#define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK    0x0000003f
+#define PPC44x_TLB_UX           0x00000020      /* User execution */
+#define PPC44x_TLB_UW           0x00000010      /* User write */
+#define PPC44x_TLB_UR           0x00000008      /* User read */
+#define PPC44x_TLB_SX           0x00000004      /* Super execution */
+#define PPC44x_TLB_SW           0x00000002      /* Super write */
+#define PPC44x_TLB_SR           0x00000001      /* Super read */
+
+/* Book-E defined page sizes */
+#define BOOKE_PAGESZ_1K         0
+#define BOOKE_PAGESZ_4K         1
+#define BOOKE_PAGESZ_16K        2
+#define BOOKE_PAGESZ_64K        3
+#define BOOKE_PAGESZ_256K       4
+#define BOOKE_PAGESZ_1M         5
+#define BOOKE_PAGESZ_4M         6
+#define BOOKE_PAGESZ_16M        7
+#define BOOKE_PAGESZ_64M        8
+#define BOOKE_PAGESZ_256M       9
+#define BOOKE_PAGESZ_1GB        10
+#define BOOKE_PAGESZ_4GB        11
+#define BOOKE_PAGESZ_16GB       12
+#define BOOKE_PAGESZ_64GB       13
+#define BOOKE_PAGESZ_256GB      14
+#define BOOKE_PAGESZ_1TB        15
+
+/*
+ * Freescale Book-E MMU support
+ */
+
+#define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
+#define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
+#define MAS0_NV         0x00000FFF
+
+#define MAS1_VALID      0x80000000
+#define MAS1_IPROT      0x40000000
+#define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
+#define MAS1_TS         0x00001000
+#define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
+
+#define MAS2_EPN        0xFFFFF000
+#define MAS2_X0         0x00000040
+#define MAS2_X1         0x00000020
+#define MAS2_W          0x00000010
+#define MAS2_I          0x00000008
+#define MAS2_M          0x00000004
+#define MAS2_G          0x00000002
+#define MAS2_E          0x00000001
+
+#define MAS3_RPN        0xFFFFF000
+#define MAS3_U0         0x00000200
+#define MAS3_U1         0x00000100
+#define MAS3_U2         0x00000080
+#define MAS3_U3         0x00000040
+#define MAS3_UX         0x00000020
+#define MAS3_SX         0x00000010
+#define MAS3_UW         0x00000008
+#define MAS3_SW         0x00000004
+#define MAS3_UR         0x00000002
+#define MAS3_SR         0x00000001
+
+#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
+#define MAS4_TIDDSEL    0x000F0000
+#define MAS4_TSIZED(x)  MAS1_TSIZE(x)
+#define MAS4_X0D        0x00000040
+#define MAS4_X1D        0x00000020
+#define MAS4_WD         0x00000010
+#define MAS4_ID         0x00000008
+#define MAS4_MD         0x00000004
+#define MAS4_GD         0x00000002
+#define MAS4_ED         0x00000001
+
+#define MAS6_SPID0      0x3FFF0000
+#define MAS6_SPID1      0x00007FFE
+#define MAS6_SAS        0x00000001
+#define MAS6_SPID       MAS6_SPID0
+
+#define MAS7_RPN        0xFFFFFFFF
+
+#endif /* _PPC_MMU_H_ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
new file mode 100644
index 000000000000..9222fa6ca172
--- /dev/null
+++ b/include/asm-ppc/mmu_context.h
@@ -0,0 +1,197 @@
+#ifdef __KERNEL__
+#ifndef __PPC_MMU_CONTEXT_H
+#define __PPC_MMU_CONTEXT_H
+
+#include <linux/config.h>
+#include <asm/atomic.h>
+#include <asm/bitops.h>
+#include <asm/mmu.h>
+#include <asm/cputable.h>
+
+/*
+ * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
+ * (virtual segment identifiers) for each context.  Although the
+ * hardware supports 24-bit VSIDs, and thus >1 million contexts,
+ * we only use 32,768 of them.  That is ample, since there can be
+ * at most around 30,000 tasks in the system anyway, and it means
+ * that we can use a bitmap to indicate which contexts are in use.
+ * Using a bitmap means that we entirely avoid all of the problems
+ * that we used to have when the context number overflowed,
+ * particularly on SMP systems.
+ *  -- paulus.
+ */
+
+/*
+ * This function defines the mapping from contexts to VSIDs (virtual
+ * segment IDs).  We use a skew on both the context and the high 4 bits
+ * of the 32-bit virtual address (the "effective segment ID") in order
+ * to spread out the entries in the MMU hash table.  Note, if this
+ * function is changed then arch/ppc/mm/hashtable.S will have to be
+ * changed to correspond.
+ */
+#define CTX_TO_VSID(ctx, va)    (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
+                                 & 0xffffff)
+
+/*
+   The MPC8xx has only 16 contexts.  We rotate through them on each
+   task switch.  A better way would be to keep track of tasks that
+   own contexts, and implement an LRU usage.  That way very active
+   tasks don't always have to pay the TLB reload overhead.  The
+   kernel pages are mapped shared, so the kernel can run on behalf
+   of any task that makes a kernel entry.  Shared does not mean they
+   are not protected, just that the ASID comparison is not performed.
+        -- Dan
+
+   The IBM4xx has 256 contexts, so we can just rotate through these
+   as a way of "switching" contexts.  If the TID of the TLB is zero,
+   the PID/TID comparison is disabled, so we can use a TID of zero
+   to represent all kernel pages as shared among all contexts.
+        -- Dan
+ */
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+#ifdef CONFIG_8xx
+#define NO_CONTEXT              16
+#define LAST_CONTEXT            15
+#define FIRST_CONTEXT           0
+
+#elif defined(CONFIG_4xx)
+#define NO_CONTEXT              256
+#define LAST_CONTEXT            255
+#define FIRST_CONTEXT           1
+
+#elif defined(CONFIG_E500)
+#define NO_CONTEXT              256
+#define LAST_CONTEXT            255
+#define FIRST_CONTEXT           1
+
+#else
+
+/* PPC 6xx, 7xx CPUs */
+#define NO_CONTEXT              ((mm_context_t) -1)
+#define LAST_CONTEXT            32767
+#define FIRST_CONTEXT           1
+#endif
+
+/*
+ * Set the current MMU context.
+ * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
+ * loading up the segment registers for the user part of the address space.
+ *
+ * Since the PGD is immediately available, it is much faster to simply
+ * pass this along as a second parameter, which is required for 8xx and
+ * can be used for debugging on all processors (if you happen to have
+ * an Abatron).
+ */
+extern void set_context(mm_context_t context, pgd_t *pgd);
+
+/*
+ * Bitmap of contexts in use.
+ * The size of this bitmap is LAST_CONTEXT + 1 bits.
+ */
+extern unsigned long context_map[];
+
+/*
+ * This caches the next context number that we expect to be free.
+ * Its use is an optimization only, we can't rely on this context
+ * number to be free, but it usually will be.
+ */
+extern mm_context_t next_mmu_context;
+
+/*
+ * If we don't have sufficient contexts to give one to every task
+ * that could be in the system, we need to be able to steal contexts.
+ * These variables support that.
+ */
+#if LAST_CONTEXT < 30000
+#define FEW_CONTEXTS    1
+extern atomic_t nr_free_contexts;
+extern struct mm_struct *context_mm[LAST_CONTEXT+1];
+extern void steal_context(void);
+#endif
+
+/*
+ * Get a new mmu context for the address space described by `mm'.
+ */
+static inline void get_mmu_context(struct mm_struct *mm)
+{
+        mm_context_t ctx;
+
+        if (mm->context != NO_CONTEXT)
+                return;
+#ifdef FEW_CONTEXTS
+        while (atomic_dec_if_positive(&nr_free_contexts) < 0)
+                steal_context();
+#endif
+        ctx = next_mmu_context;
+        while (test_and_set_bit(ctx, context_map)) {
+                ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
+                if (ctx > LAST_CONTEXT)
+                        ctx = 0;
+        }
+        next_mmu_context = (ctx + 1) & LAST_CONTEXT;
+        mm->context = ctx;
+#ifdef FEW_CONTEXTS
+        context_mm[ctx] = mm;
+#endif
+}
+
+/*
+ * Set up the context for a new address space.
+ */
+#define init_new_context(tsk,mm)        (((mm)->context = NO_CONTEXT), 0)
+
+/*
+ * We're finished using the context for an address space.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+        if (mm->context != NO_CONTEXT) {
+                clear_bit(mm->context, context_map);
+                mm->context = NO_CONTEXT;
+#ifdef FEW_CONTEXTS
+                atomic_inc(&nr_free_contexts);
+#endif
+        }
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+#ifdef CONFIG_ALTIVEC
+        asm volatile (
+ BEGIN_FTR_SECTION
+        "dssall;\n"
+#ifndef CONFIG_POWER4
+         "sync;\n" /* G4 needs a sync here, G5 apparently not */
+#endif
+ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
+         : : );
+#endif /* CONFIG_ALTIVEC */
+
+        tsk->thread.pgdir = next->pgd;
+
+        /* No need to flush userspace segments if the mm doesnt change */
+        if (prev == next)
+                return;
+
+        /* Setup new userspace context */
+        get_mmu_context(next);
+        set_context(next->context, next->pgd);
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+#define activate_mm(active_mm, mm)   switch_mm(active_mm, mm, current)
+
+extern void mmu_context_init(void);
+
+#endif /* __PPC_MMU_CONTEXT_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/module.h b/include/asm-ppc/module.h
new file mode 100644
index 000000000000..fb63492562b0
--- /dev/null
+++ b/include/asm-ppc/module.h
@@ -0,0 +1,44 @@
+#ifndef _ASM_PPC_MODULE_H
+#define _ASM_PPC_MODULE_H
+/* Module stuff for PPC.  (C) 2001 Rusty Russell */
+
+#include <linux/list.h>
+#include <asm/bug.h>
+
+/* Thanks to Paul M for explaining this.
+
+   PPC can only do rel jumps += 32MB, and often the kernel and other
+   modules are furthur away than this.  So, we jump to a table of
+   trampolines attached to the module (the Procedure Linkage Table)
+   whenever that happens.
+*/
+
+struct ppc_plt_entry
+{
+        /* 16 byte jump instruction sequence (4 instructions) */
+        unsigned int jump[4];
+};
+
+struct mod_arch_specific
+{
+        /* Indices of PLT sections within module. */
+        unsigned int core_plt_section, init_plt_section;
+
+        /* List of BUG addresses, source line numbers and filenames */
+        struct list_head bug_list;
+        struct bug_entry *bug_table;
+        unsigned int num_bugs;
+};
+
+extern struct bug_entry *module_find_bug(unsigned long bugaddr);
+
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+
+/* Make empty sections for module_frob_arch_sections to expand. */
+#ifdef MODULE
+asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
+asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
+#endif
+#endif /* _ASM_PPC_MODULE_H */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
new file mode 100644
index 000000000000..d8e7e2d6128e
--- /dev/null
+++ b/include/asm-ppc/mpc10x.h
@@ -0,0 +1,174 @@
+/*
+ * arch/ppc/kernel/mpc10x.h
+ *
+ * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
+ * ctlr/EPIC/etc.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PPC_KERNEL_MPC10X_H
+#define __PPC_KERNEL_MPC10X_H
+
+#include <linux/pci_ids.h>
+#include <asm/pci-bridge.h>
+
+/*
+ * The values here don't completely map everything but should work in most
+ * cases.
+ *
+ * MAP A (PReP Map)
+ *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
+ *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
+ *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
+ *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
+ *
+ * MAP B (CHRP Map)
+ *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
+ *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
+ *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
+ *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
+ */
+
+/*
+ * Define the vendor/device IDs for the various bridges--should be added to
+ * <linux/pci_ids.h>
+ */
+#define MPC10X_BRIDGE_106       ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
+                                  PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_8240      ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_107       ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define MPC10X_BRIDGE_8245      ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
+
+/* Define the type of map to use */
+#define MPC10X_MEM_MAP_A                1
+#define MPC10X_MEM_MAP_B                2
+
+/* Map A (PReP Map) Defines */
+#define MPC10X_MAPA_CNFG_ADDR           0x80000cf8
+#define MPC10X_MAPA_CNFG_DATA           0x80000cfc
+
+#define MPC10X_MAPA_ISA_IO_BASE         0x80000000
+#define MPC10X_MAPA_ISA_MEM_BASE        0xc0000000
+#define MPC10X_MAPA_DRAM_OFFSET         0x80000000
+
+#define MPC10X_MAPA_PCI_INTACK_ADDR     0xbffffff0
+#define MPC10X_MAPA_PCI_IO_START        0x00000000
+#define MPC10X_MAPA_PCI_IO_END         (0x00800000 - 1)
+#define MPC10X_MAPA_PCI_MEM_START       0x00000000
+#define MPC10X_MAPA_PCI_MEM_END        (0x20000000 - 1)
+
+#define MPC10X_MAPA_PCI_MEM_OFFSET      (MPC10X_MAPA_ISA_MEM_BASE -     \
+                                         MPC10X_MAPA_PCI_MEM_START)
+
+/* Map B (CHRP Map) Defines */
+#define MPC10X_MAPB_CNFG_ADDR           0xfec00000
+#define MPC10X_MAPB_CNFG_DATA           0xfee00000
+
+#define MPC10X_MAPB_ISA_IO_BASE         0xfe000000
+#define MPC10X_MAPB_ISA_MEM_BASE        0x80000000
+#define MPC10X_MAPB_DRAM_OFFSET         0x00000000
+
+#define MPC10X_MAPB_PCI_INTACK_ADDR     0xfef00000
+#define MPC10X_MAPB_PCI_IO_START        0x00000000
+#define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
+#define MPC10X_MAPB_PCI_MEM_START       0x80000000
+#define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)
+
+#define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
+                                         MPC10X_MAPB_PCI_MEM_START)
+
+/* Set hose members to values appropriate for the mem map used */
+#define MPC10X_SETUP_HOSE(hose, map) {                                  \
+        (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;      \
+        (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;        \
+        (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;            \
+        (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;      \
+        (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;          \
+        (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;   \
+}
+
+
+/* Miscellaneous Configuration register offsets */
+#define MPC10X_CFG_PIR_REG              0x09
+#define MPC10X_CFG_PIR_HOST_BRIDGE      0x00
+#define MPC10X_CFG_PIR_AGENT            0x01
+
+#define MPC10X_CFG_EUMBBAR              0x78
+
+#define MPC10X_CFG_PICR1_REG            0xa8
+#define MPC10X_CFG_PICR1_ADDR_MAP_MASK  0x00010000
+#define MPC10X_CFG_PICR1_ADDR_MAP_A     0x00010000
+#define MPC10X_CFG_PICR1_ADDR_MAP_B     0x00000000
+#define MPC10X_CFG_PICR1_SPEC_PCI_RD    0x00000004
+#define MPC10X_CFG_PICR1_ST_GATH_EN     0x00000040
+
+#define MPC10X_CFG_PICR2_REG            0xac
+#define MPC10X_CFG_PICR2_COPYBACK_OPT   0x00000001
+
+#define MPC10X_CFG_MAPB_OPTIONS_REG     0xe0
+#define MPC10X_CFG_MAPB_OPTIONS_CFAE    0x80    /* CPU_FD_ALIAS_EN */
+#define MPC10X_CFG_MAPB_OPTIONS_PFAE    0x40    /* PCI_FD_ALIAS_EN */
+#define MPC10X_CFG_MAPB_OPTIONS_DR      0x20    /* DLL_RESET */
+#define MPC10X_CFG_MAPB_OPTIONS_PCICH   0x08    /* PCI_COMPATIBILITY_HOLE */
+#define MPC10X_CFG_MAPB_OPTIONS_PROCCH  0x04    /* PROC_COMPATIBILITY_HOLE */
+
+/* Define offsets for the memory controller registers in the config space */
+#define MPC10X_MCTLR_MEM_START_1        0x80    /* Banks 0-3 */
+#define MPC10X_MCTLR_MEM_START_2        0x84    /* Banks 4-7 */
+#define MPC10X_MCTLR_EXT_MEM_START_1    0x88    /* Banks 0-3 */
+#define MPC10X_MCTLR_EXT_MEM_START_2    0x8c    /* Banks 4-7 */
+
+#define MPC10X_MCTLR_MEM_END_1          0x90    /* Banks 0-3 */
+#define MPC10X_MCTLR_MEM_END_2          0x94    /* Banks 4-7 */
+#define MPC10X_MCTLR_EXT_MEM_END_1      0x98    /* Banks 0-3 */
+#define MPC10X_MCTLR_EXT_MEM_END_2      0x9c    /* Banks 4-7 */
+
+#define MPC10X_MCTLR_MEM_BANK_ENABLES   0xa0
+
+/* Define some offset in the EUMB */
+#define MPC10X_EUMB_SIZE                0x00100000 /* Total EUMB size (1MB) */
+
+#define MPC10X_EUMB_MU_OFFSET           0x00000000 /* Msg Unit reg offset */
+#define MPC10X_EUMB_MU_SIZE             0x00001000 /* Msg Unit reg size */
+#define MPC10X_EUMB_DMA_OFFSET          0x00001000 /* DMA Unit reg offset */
+#define MPC10X_EUMB_DMA_SIZE            0x00001000 /* DMA Unit reg size  */
+#define MPC10X_EUMB_ATU_OFFSET          0x00002000 /* Addr xlate reg offset */
+#define MPC10X_EUMB_ATU_SIZE            0x00001000 /* Addr xlate reg size  */
+#define MPC10X_EUMB_I2C_OFFSET          0x00003000 /* I2C Unit reg offset */
+#define MPC10X_EUMB_I2C_SIZE            0x00001000 /* I2C Unit reg size  */
+#define MPC10X_EUMB_DUART_OFFSET        0x00004000 /* DUART Unit reg offset (8245) */
+#define MPC10X_EUMB_DUART_SIZE          0x00001000 /* DUART Unit reg size (8245) */
+#define MPC10X_EUMB_EPIC_OFFSET         0x00040000 /* EPIC offset in EUMB */
+#define MPC10X_EUMB_EPIC_SIZE           0x00030000 /* EPIC size */
+#define MPC10X_EUMB_PM_OFFSET           0x000fe000 /* Performance Monitor reg offset (8245) */
+#define MPC10X_EUMB_PM_SIZE             0x00001000 /* Performance Monitor reg size (8245) */
+#define MPC10X_EUMB_WP_OFFSET           0x000ff000 /* Data path diagnostic, watchpoint reg offset */
+#define MPC10X_EUMB_WP_SIZE             0x00001000 /* Data path diagnostic, watchpoint reg size */
+
+/*
+ * Define some recommended places to put the EUMB regs.
+ * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
+ */
+extern unsigned long                    ioremap_base;
+#define MPC10X_MAPA_EUMB_BASE           (ioremap_base - MPC10X_EUMB_SIZE)
+#define MPC10X_MAPB_EUMB_BASE           MPC10X_MAPA_EUMB_BASE
+
+
+int mpc10x_bridge_init(struct pci_controller *hose,
+                       uint current_map,
+                       uint new_map,
+                       uint phys_eumb_base);
+unsigned long mpc10x_get_mem_size(uint mem_map);
+int mpc10x_enable_store_gathering(struct pci_controller *hose);
+int mpc10x_disable_store_gathering(struct pci_controller *hose);
+
+/* For MPC107 boards that use the built-in openpic */
+void mpc10x_set_openpic(void);
+
+#endif  /* __PPC_KERNEL_MPC10X_H */
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
new file mode 100644
index 000000000000..e5f80c22fbfc
--- /dev/null
+++ b/include/asm-ppc/mpc52xx.h
@@ -0,0 +1,445 @@
+/*
+ * include/asm-ppc/mpc52xx.h
+ * 
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> 
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_MPC52xx_H__
+#define __ASM_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/ppcboot.h>
+#include <asm/types.h>
+
+struct pt_regs;
+#endif /* __ASSEMBLY__ */
+
+
+/* ======================================================================== */
+/* PPC Sys devices definition                                               */
+/* ======================================================================== */
+
+enum ppc_sys_devices {
+        MPC52xx_MSCAN1,
+        MPC52xx_MSCAN2,
+        MPC52xx_SPI,
+        MPC52xx_USB,
+        MPC52xx_BDLC,
+        MPC52xx_PSC1,
+        MPC52xx_PSC2,
+        MPC52xx_PSC3,
+        MPC52xx_PSC4,
+        MPC52xx_PSC5,
+        MPC52xx_PSC6,
+        MPC52xx_FEC,
+        MPC52xx_ATA,
+        MPC52xx_I2C1,
+        MPC52xx_I2C2,
+};
+
+
+/* ======================================================================== */
+/* Main registers/struct addresses                                          */
+/* ======================================================================== */
+
+/* MBAR position */
+#define MPC52xx_MBAR            0xf0000000      /* Phys address */
+#define MPC52xx_MBAR_VIRT       0xf0000000      /* Virt address */
+#define MPC52xx_MBAR_SIZE       0x00010000
+
+#define MPC52xx_PA(x)           ((phys_addr_t)(MPC52xx_MBAR + (x)))
+#define MPC52xx_VA(x)           ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
+
+/* Registers zone offset/size  */
+#define MPC52xx_MMAP_CTL_OFFSET         0x0000
+#define MPC52xx_MMAP_CTL_SIZE           0x068
+#define MPC52xx_SDRAM_OFFSET            0x0100
+#define MPC52xx_SDRAM_SIZE              0x010
+#define MPC52xx_CDM_OFFSET              0x0200
+#define MPC52xx_CDM_SIZE                0x038
+#define MPC52xx_INTR_OFFSET             0x0500
+#define MPC52xx_INTR_SIZE               0x04c
+#define MPC52xx_GPTx_OFFSET(x)          (0x0600 + ((x)<<4))
+#define MPC52xx_GPT_SIZE                0x010
+#define MPC52xx_RTC_OFFSET              0x0800
+#define MPC52xx_RTC_SIZE                0x024
+#define MPC52xx_GPIO_OFFSET             0x0b00
+#define MPC52xx_GPIO_SIZE               0x040
+#define MPC52xx_GPIO_WKUP_OFFSET        0x0c00
+#define MPC52xx_GPIO_WKUP_SIZE          0x028
+#define MPC52xx_PCI_OFFSET              0x0d00
+#define MPC52xx_PCI_SIZE                0x100
+#define MPC52xx_SDMA_OFFSET             0x1200
+#define MPC52xx_SDMA_SIZE               0x100
+#define MPC52xx_XLB_OFFSET              0x1f00
+#define MPC52xx_XLB_SIZE                0x100
+#define MPC52xx_PSCx_OFFSET(x)          (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
+#define MPC52xx_PSC_SIZE                0x0a0
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM_OFFSET             0x8000
+#define MPC52xx_SRAM_SIZE               0x4000
+
+
+/* ======================================================================== */
+/* IRQ mapping                                                              */
+/* ======================================================================== */
+/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
+ * this
+ */
+
+#define MPC52xx_CRIT_IRQ_NUM    4
+#define MPC52xx_MAIN_IRQ_NUM    17
+#define MPC52xx_SDMA_IRQ_NUM    17
+#define MPC52xx_PERP_IRQ_NUM    23
+
+#define MPC52xx_CRIT_IRQ_BASE   0
+#define MPC52xx_MAIN_IRQ_BASE   (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
+#define MPC52xx_SDMA_IRQ_BASE   (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
+#define MPC52xx_PERP_IRQ_BASE   (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
+
+#define MPC52xx_IRQ0                    (MPC52xx_CRIT_IRQ_BASE + 0)
+#define MPC52xx_SLICE_TIMER_0_IRQ       (MPC52xx_CRIT_IRQ_BASE + 1)
+#define MPC52xx_HI_INT_IRQ              (MPC52xx_CRIT_IRQ_BASE + 2)
+#define MPC52xx_CCS_IRQ                 (MPC52xx_CRIT_IRQ_BASE + 3)
+
+#define MPC52xx_IRQ1                    (MPC52xx_MAIN_IRQ_BASE + 1)
+#define MPC52xx_IRQ2                    (MPC52xx_MAIN_IRQ_BASE + 2)
+#define MPC52xx_IRQ3                    (MPC52xx_MAIN_IRQ_BASE + 3)
+
+#define MPC52xx_SDMA_IRQ                (MPC52xx_PERP_IRQ_BASE + 0)
+#define MPC52xx_PSC1_IRQ                (MPC52xx_PERP_IRQ_BASE + 1)
+#define MPC52xx_PSC2_IRQ                (MPC52xx_PERP_IRQ_BASE + 2)
+#define MPC52xx_PSC3_IRQ                (MPC52xx_PERP_IRQ_BASE + 3)
+#define MPC52xx_PSC6_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
+#define MPC52xx_IRDA_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
+#define MPC52xx_FEC_IRQ                 (MPC52xx_PERP_IRQ_BASE + 5)
+#define MPC52xx_USB_IRQ                 (MPC52xx_PERP_IRQ_BASE + 6)
+#define MPC52xx_ATA_IRQ                 (MPC52xx_PERP_IRQ_BASE + 7)
+#define MPC52xx_PCI_CNTRL_IRQ           (MPC52xx_PERP_IRQ_BASE + 8)
+#define MPC52xx_PCI_SCIRX_IRQ           (MPC52xx_PERP_IRQ_BASE + 9)
+#define MPC52xx_PCI_SCITX_IRQ           (MPC52xx_PERP_IRQ_BASE + 10)
+#define MPC52xx_PSC4_IRQ                (MPC52xx_PERP_IRQ_BASE + 11)
+#define MPC52xx_PSC5_IRQ                (MPC52xx_PERP_IRQ_BASE + 12)
+#define MPC52xx_SPI_MODF_IRQ            (MPC52xx_PERP_IRQ_BASE + 13)
+#define MPC52xx_SPI_SPIF_IRQ            (MPC52xx_PERP_IRQ_BASE + 14)
+#define MPC52xx_I2C1_IRQ                (MPC52xx_PERP_IRQ_BASE + 15)
+#define MPC52xx_I2C2_IRQ                (MPC52xx_PERP_IRQ_BASE + 16)
+#define MPC52xx_MSCAN1_IRQ              (MPC52xx_PERP_IRQ_BASE + 17)
+#define MPC52xx_MSCAN2_IRQ              (MPC52xx_PERP_IRQ_BASE + 18)
+#define MPC52xx_IR_RX_IRQ               (MPC52xx_PERP_IRQ_BASE + 19)
+#define MPC52xx_IR_TX_IRQ               (MPC52xx_PERP_IRQ_BASE + 20)
+#define MPC52xx_XLB_ARB_IRQ             (MPC52xx_PERP_IRQ_BASE + 21)
+#define MPC52xx_BDLC_IRQ                (MPC52xx_PERP_IRQ_BASE + 22)
+
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set                             */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+        u32     mbar;           /* MMAP_CTRL + 0x00 */
+
+        u32     cs0_start;      /* MMAP_CTRL + 0x04 */
+        u32     cs0_stop;       /* MMAP_CTRL + 0x08 */
+        u32     cs1_start;      /* MMAP_CTRL + 0x0c */
+        u32     cs1_stop;       /* MMAP_CTRL + 0x10 */
+        u32     cs2_start;      /* MMAP_CTRL + 0x14 */
+        u32     cs2_stop;       /* MMAP_CTRL + 0x18 */
+        u32     cs3_start;      /* MMAP_CTRL + 0x1c */
+        u32     cs3_stop;       /* MMAP_CTRL + 0x20 */
+        u32     cs4_start;      /* MMAP_CTRL + 0x24 */
+        u32     cs4_stop;       /* MMAP_CTRL + 0x28 */
+        u32     cs5_start;      /* MMAP_CTRL + 0x2c */
+        u32     cs5_stop;       /* MMAP_CTRL + 0x30 */
+
+        u32     sdram0;         /* MMAP_CTRL + 0x34 */
+        u32     sdram1;         /* MMAP_CTRL + 0X38 */
+
+        u32     reserved[4];    /* MMAP_CTRL + 0x3c .. 0x48 */
+
+        u32     boot_start;     /* MMAP_CTRL + 0x4c */
+        u32     boot_stop;      /* MMAP_CTRL + 0x50 */
+
+        u32     ipbi_ws_ctrl;   /* MMAP_CTRL + 0x54 */
+
+        u32     cs6_start;      /* MMAP_CTRL + 0x58 */
+        u32     cs6_stop;       /* MMAP_CTRL + 0x5c */
+        u32     cs7_start;      /* MMAP_CTRL + 0x60 */
+        u32     cs7_stop;       /* MMAP_CTRL + 0x64 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+        u32     mode;           /* SDRAM + 0x00 */
+        u32     ctrl;           /* SDRAM + 0x04 */
+        u32     config1;        /* SDRAM + 0x08 */
+        u32     config2;        /* SDRAM + 0x0c */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+        u32     per_mask;       /* INTR + 0x00 */
+        u32     per_pri1;       /* INTR + 0x04 */
+        u32     per_pri2;       /* INTR + 0x08 */
+        u32     per_pri3;       /* INTR + 0x0c */
+        u32     ctrl;           /* INTR + 0x10 */
+        u32     main_mask;      /* INTR + 0x14 */
+        u32     main_pri1;      /* INTR + 0x18 */
+        u32     main_pri2;      /* INTR + 0x1c */
+        u32     reserved1;      /* INTR + 0x20 */
+        u32     enc_status;     /* INTR + 0x24 */
+        u32     crit_status;    /* INTR + 0x28 */
+        u32     main_status;    /* INTR + 0x2c */
+        u32     per_status;     /* INTR + 0x30 */
+        u32     reserved2;      /* INTR + 0x34 */
+        u32     per_error;      /* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+        u32     taskBar;        /* SDMA + 0x00 */
+        u32     currentPointer; /* SDMA + 0x04 */
+        u32     endPointer;     /* SDMA + 0x08 */
+        u32     variablePointer;/* SDMA + 0x0c */
+
+        u8      IntVect1;       /* SDMA + 0x10 */
+        u8      IntVect2;       /* SDMA + 0x11 */
+        u16     PtdCntrl;       /* SDMA + 0x12 */
+
+        u32     IntPend;        /* SDMA + 0x14 */
+        u32     IntMask;        /* SDMA + 0x18 */
+
+        u16     tcr[16];        /* SDMA + 0x1c .. 0x3a */
+
+        u8      ipr[32];        /* SDMA + 0x3c .. 0x5b */
+
+        u32     cReqSelect;     /* SDMA + 0x5c */
+        u32     task_size0;     /* SDMA + 0x60 */
+        u32     task_size1;     /* SDMA + 0x64 */
+        u32     MDEDebug;       /* SDMA + 0x68 */
+        u32     ADSDebug;       /* SDMA + 0x6c */
+        u32     Value1;         /* SDMA + 0x70 */
+        u32     Value2;         /* SDMA + 0x74 */
+        u32     Control;        /* SDMA + 0x78 */
+        u32     Status;         /* SDMA + 0x7c */
+        u32     PTDDebug;       /* SDMA + 0x80 */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+        u32     mode;           /* GPTx + 0x00 */
+        u32     count;          /* GPTx + 0x04 */
+        u32     pwm;            /* GPTx + 0x08 */
+        u32     status;         /* GPTx + 0X0c */
+};
+
+/* RTC */
+struct mpc52xx_rtc {
+        u32     time_set;       /* RTC + 0x00 */
+        u32     date_set;       /* RTC + 0x04 */
+        u32     stopwatch;      /* RTC + 0x08 */
+        u32     int_enable;     /* RTC + 0x0c */
+        u32     time;           /* RTC + 0x10 */
+        u32     date;           /* RTC + 0x14 */
+        u32     stopwatch_intr; /* RTC + 0x18 */
+        u32     bus_error;      /* RTC + 0x1c */
+        u32     dividers;       /* RTC + 0x20 */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+        u32     port_config;    /* GPIO + 0x00 */
+        u32     simple_gpioe;   /* GPIO + 0x04 */
+        u32     simple_ode;     /* GPIO + 0x08 */
+        u32     simple_ddr;     /* GPIO + 0x0c */
+        u32     simple_dvo;     /* GPIO + 0x10 */
+        u32     simple_ival;    /* GPIO + 0x14 */
+        u8      outo_gpioe;     /* GPIO + 0x18 */
+        u8      reserved1[3];   /* GPIO + 0x19 */
+        u8      outo_dvo;       /* GPIO + 0x1c */
+        u8      reserved2[3];   /* GPIO + 0x1d */
+        u8      sint_gpioe;     /* GPIO + 0x20 */
+        u8      reserved3[3];   /* GPIO + 0x21 */
+        u8      sint_ode;       /* GPIO + 0x24 */
+        u8      reserved4[3];   /* GPIO + 0x25 */
+        u8      sint_ddr;       /* GPIO + 0x28 */
+        u8      reserved5[3];   /* GPIO + 0x29 */
+        u8      sint_dvo;       /* GPIO + 0x2c */
+        u8      reserved6[3];   /* GPIO + 0x2d */
+        u8      sint_inten;     /* GPIO + 0x30 */
+        u8      reserved7[3];   /* GPIO + 0x31 */
+        u16     sint_itype;     /* GPIO + 0x34 */
+        u16     reserved8;      /* GPIO + 0x36 */
+        u8      gpio_control;   /* GPIO + 0x38 */
+        u8      reserved9[3];   /* GPIO + 0x39 */
+        u8      sint_istat;     /* GPIO + 0x3c */
+        u8      sint_ival;      /* GPIO + 0x3d */
+        u8      bus_errs;       /* GPIO + 0x3e */
+        u8      reserved10;     /* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
+#define MPC52xx_GPIO_PCI_DIS                    (1<<15)
+
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+        u8      wkup_gpioe;     /* GPIO_WKUP + 0x00 */
+        u8      reserved1[3];   /* GPIO_WKUP + 0x03 */
+        u8      wkup_ode;       /* GPIO_WKUP + 0x04 */
+        u8      reserved2[3];   /* GPIO_WKUP + 0x05 */
+        u8      wkup_ddr;       /* GPIO_WKUP + 0x08 */
+        u8      reserved3[3];   /* GPIO_WKUP + 0x09 */
+        u8      wkup_dvo;       /* GPIO_WKUP + 0x0C */
+        u8      reserved4[3];   /* GPIO_WKUP + 0x0D */
+        u8      wkup_inten;     /* GPIO_WKUP + 0x10 */
+        u8      reserved5[3];   /* GPIO_WKUP + 0x11 */
+        u8      wkup_iinten;    /* GPIO_WKUP + 0x14 */
+        u8      reserved6[3];   /* GPIO_WKUP + 0x15 */
+        u16     wkup_itype;     /* GPIO_WKUP + 0x18 */
+        u8      reserved7[2];   /* GPIO_WKUP + 0x1A */
+        u8      wkup_maste;     /* GPIO_WKUP + 0x1C */
+        u8      reserved8[3];   /* GPIO_WKUP + 0x1D */
+        u8      wkup_ival;      /* GPIO_WKUP + 0x20 */
+        u8      reserved9[3];   /* GPIO_WKUP + 0x21 */
+        u8      wkup_istat;     /* GPIO_WKUP + 0x24 */
+        u8      reserved10[3];  /* GPIO_WKUP + 0x25 */
+};
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+        u8      reserved[0x40];
+        u32     config;                 /* XLB + 0x40 */
+        u32     version;                /* XLB + 0x44 */
+        u32     status;                 /* XLB + 0x48 */
+        u32     int_enable;             /* XLB + 0x4c */
+        u32     addr_capture;           /* XLB + 0x50 */
+        u32     bus_sig_capture;        /* XLB + 0x54 */
+        u32     addr_timeout;           /* XLB + 0x58 */
+        u32     data_timeout;           /* XLB + 0x5c */
+        u32     bus_act_timeout;        /* XLB + 0x60 */
+        u32     master_pri_enable;      /* XLB + 0x64 */
+        u32     master_priority;        /* XLB + 0x68 */
+        u32     base_address;           /* XLB + 0x6c */
+        u32     snoop_window;           /* XLB + 0x70 */
+};
+
+#define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+        u32     jtag_id;                /* CDM + 0x00  reg0 read only */
+        u32     rstcfg;                 /* CDM + 0x04  reg1 read only */
+        u32     breadcrumb;             /* CDM + 0x08  reg2 */
+
+        u8      mem_clk_sel;            /* CDM + 0x0c  reg3 byte0 */
+        u8      xlb_clk_sel;            /* CDM + 0x0d  reg3 byte1 read only */
+        u8      ipb_clk_sel;            /* CDM + 0x0e  reg3 byte2 */
+        u8      pci_clk_sel;            /* CDM + 0x0f  reg3 byte3 */
+
+        u8      ext_48mhz_en;           /* CDM + 0x10  reg4 byte0 */
+        u8      fd_enable;              /* CDM + 0x11  reg4 byte1 */
+        u16     fd_counters;            /* CDM + 0x12  reg4 byte2,3 */
+
+        u32     clk_enables;            /* CDM + 0x14  reg5 */
+
+        u8      osc_disable;            /* CDM + 0x18  reg6 byte0 */
+        u8      reserved0[3];           /* CDM + 0x19  reg6 byte1,2,3 */
+
+        u8      ccs_sleep_enable;       /* CDM + 0x1c  reg7 byte0 */
+        u8      osc_sleep_enable;       /* CDM + 0x1d  reg7 byte1 */
+        u8      reserved1;              /* CDM + 0x1e  reg7 byte2 */
+        u8      ccs_qreq_test;          /* CDM + 0x1f  reg7 byte3 */
+
+        u8      soft_reset;             /* CDM + 0x20  u8 byte0 */
+        u8      no_ckstp;               /* CDM + 0x21  u8 byte0 */
+        u8      reserved2[2];           /* CDM + 0x22  u8 byte1,2,3 */
+
+        u8      pll_lock;               /* CDM + 0x24  reg9 byte0 */
+        u8      pll_looselock;          /* CDM + 0x25  reg9 byte1 */
+        u8      pll_sm_lockwin;         /* CDM + 0x26  reg9 byte2 */
+        u8      reserved3;              /* CDM + 0x27  reg9 byte3 */
+
+        u16     reserved4;              /* CDM + 0x28  reg10 byte0,1 */
+        u16     mclken_div_psc1;        /* CDM + 0x2a  reg10 byte2,3 */
+
+        u16     reserved5;              /* CDM + 0x2c  reg11 byte0,1 */
+        u16     mclken_div_psc2;        /* CDM + 0x2e  reg11 byte2,3 */
+
+        u16     reserved6;              /* CDM + 0x30  reg12 byte0,1 */
+        u16     mclken_div_psc3;        /* CDM + 0x32  reg12 byte2,3 */
+
+        u16     reserved7;              /* CDM + 0x34  reg13 byte0,1 */
+        u16     mclken_div_psc6;        /* CDM + 0x36  reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx syslib                                             */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern int mpc52xx_get_irq(struct pt_regs *regs);
+
+extern unsigned long mpc52xx_find_end_of_memory(void);
+extern void mpc52xx_set_bat(void);
+extern void mpc52xx_map_io(void);
+extern void mpc52xx_restart(char *cmd);
+extern void mpc52xx_halt(void);
+extern void mpc52xx_power_off(void);
+extern void mpc52xx_progress(char *s, unsigned short hex);
+extern void mpc52xx_calibrate_decr(void);
+
+extern void mpc52xx_find_bridges(void);
+
+
+        /* Matching of PSC function */
+struct mpc52xx_psc_func {
+        int id;
+        char *func;
+};
+
+extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
+extern struct  mpc52xx_psc_func mpc52xx_psc_functions[];
+        /* This array is to be defined in platform file */
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Platform configuration                                                    */
+/* ========================================================================= */
+
+/* The U-Boot platform information struct */
+extern bd_t __res;
+
+/* Platform options */
+#if defined(CONFIG_LITE5200)
+#include <platforms/lite5200.h>
+#endif
+
+
+#endif /* __ASM_MPC52xx_H__ */
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h
new file mode 100644
index 000000000000..9d850b2b20b8
--- /dev/null
+++ b/include/asm-ppc/mpc52xx_psc.h
@@ -0,0 +1,191 @@
+/*
+ * include/asm-ppc/mpc52xx_psc.h
+ * 
+ * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
+ * PSCs. Theses are shared between multiple drivers since a PSC can be
+ * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based/Extracted from some header of the 2.4 originally written by 
+ * Dale Farnsworth <dfarnsworth@mvista.com> 
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_MPC52xx_PSC_H__
+#define __ASM_MPC52xx_PSC_H__
+
+#include <asm/types.h>
+
+/* Max number of PSCs */
+#define MPC52xx_PSC_MAXNUM      6
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR_CDE      0x0080
+#define MPC52xx_PSC_SR_RXRDY    0x0100
+#define MPC52xx_PSC_SR_RXFULL   0x0200
+#define MPC52xx_PSC_SR_TXRDY    0x0400
+#define MPC52xx_PSC_SR_TXEMP    0x0800
+#define MPC52xx_PSC_SR_OE       0x1000
+#define MPC52xx_PSC_SR_PE       0x2000
+#define MPC52xx_PSC_SR_FE       0x4000
+#define MPC52xx_PSC_SR_RB       0x8000
+
+/* PSC Command values */
+#define MPC52xx_PSC_RX_ENABLE           0x0001
+#define MPC52xx_PSC_RX_DISABLE          0x0002
+#define MPC52xx_PSC_TX_ENABLE           0x0004
+#define MPC52xx_PSC_TX_DISABLE          0x0008
+#define MPC52xx_PSC_SEL_MODE_REG_1      0x0010
+#define MPC52xx_PSC_RST_RX              0x0020
+#define MPC52xx_PSC_RST_TX              0x0030
+#define MPC52xx_PSC_RST_ERR_STAT        0x0040
+#define MPC52xx_PSC_RST_BRK_CHG_INT     0x0050
+#define MPC52xx_PSC_START_BRK           0x0060
+#define MPC52xx_PSC_STOP_BRK            0x0070
+
+/* PSC TxRx FIFO status bits */
+#define MPC52xx_PSC_RXTX_FIFO_ERR       0x0040
+#define MPC52xx_PSC_RXTX_FIFO_UF        0x0020
+#define MPC52xx_PSC_RXTX_FIFO_OF        0x0010
+#define MPC52xx_PSC_RXTX_FIFO_FR        0x0008
+#define MPC52xx_PSC_RXTX_FIFO_FULL      0x0004
+#define MPC52xx_PSC_RXTX_FIFO_ALARM     0x0002
+#define MPC52xx_PSC_RXTX_FIFO_EMPTY     0x0001
+
+/* PSC interrupt mask bits */
+#define MPC52xx_PSC_IMR_TXRDY           0x0100
+#define MPC52xx_PSC_IMR_RXRDY           0x0200
+#define MPC52xx_PSC_IMR_DB              0x0400
+#define MPC52xx_PSC_IMR_IPC             0x8000
+
+/* PSC input port change bit */
+#define MPC52xx_PSC_CTS                 0x01
+#define MPC52xx_PSC_DCD                 0x02
+#define MPC52xx_PSC_D_CTS               0x10
+#define MPC52xx_PSC_D_DCD               0x20
+
+/* PSC mode fields */
+#define MPC52xx_PSC_MODE_5_BITS                 0x00
+#define MPC52xx_PSC_MODE_6_BITS                 0x01
+#define MPC52xx_PSC_MODE_7_BITS                 0x02
+#define MPC52xx_PSC_MODE_8_BITS                 0x03
+#define MPC52xx_PSC_MODE_BITS_MASK              0x03
+#define MPC52xx_PSC_MODE_PAREVEN                0x00
+#define MPC52xx_PSC_MODE_PARODD                 0x04
+#define MPC52xx_PSC_MODE_PARFORCE               0x08
+#define MPC52xx_PSC_MODE_PARNONE                0x10
+#define MPC52xx_PSC_MODE_ERR                    0x20
+#define MPC52xx_PSC_MODE_FFULL                  0x40
+#define MPC52xx_PSC_MODE_RXRTS                  0x80
+
+#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS        0x00
+#define MPC52xx_PSC_MODE_ONE_STOP               0x07
+#define MPC52xx_PSC_MODE_TWO_STOP               0x0f
+
+#define MPC52xx_PSC_RFNUM_MASK  0x01ff
+
+
+/* Structure of the hardware registers */
+struct mpc52xx_psc {
+        u8              mode;           /* PSC + 0x00 */
+        u8              reserved0[3];
+        union {                         /* PSC + 0x04 */
+                u16     status;
+                u16     clock_select;
+        } sr_csr;
+#define mpc52xx_psc_status      sr_csr.status
+#define mpc52xx_psc_clock_select sr_csr.clock_select
+        u16             reserved1;
+        u8              command;        /* PSC + 0x08 */
+        u8              reserved2[3];
+        union {                         /* PSC + 0x0c */
+                u8      buffer_8;
+                u16     buffer_16;
+                u32     buffer_32;
+        } buffer;
+#define mpc52xx_psc_buffer_8    buffer.buffer_8
+#define mpc52xx_psc_buffer_16   buffer.buffer_16
+#define mpc52xx_psc_buffer_32   buffer.buffer_32
+        union {                         /* PSC + 0x10 */
+                u8      ipcr;
+                u8      acr;
+        } ipcr_acr;
+#define mpc52xx_psc_ipcr        ipcr_acr.ipcr
+#define mpc52xx_psc_acr         ipcr_acr.acr
+        u8              reserved3[3];
+        union {                         /* PSC + 0x14 */
+                u16     isr;
+                u16     imr;
+        } isr_imr;
+#define mpc52xx_psc_isr         isr_imr.isr
+#define mpc52xx_psc_imr         isr_imr.imr
+        u16             reserved4;
+        u8              ctur;           /* PSC + 0x18 */
+        u8              reserved5[3];
+        u8              ctlr;           /* PSC + 0x1c */
+        u8              reserved6[3];
+        u16             ccr;            /* PSC + 0x20 */
+        u8              reserved7[14];
+        u8              ivr;            /* PSC + 0x30 */
+        u8              reserved8[3];
+        u8              ip;             /* PSC + 0x34 */
+        u8              reserved9[3];
+        u8              op1;            /* PSC + 0x38 */
+        u8              reserved10[3];
+        u8              op0;            /* PSC + 0x3c */
+        u8              reserved11[3];
+        u32             sicr;           /* PSC + 0x40 */
+        u8              ircr1;          /* PSC + 0x44 */
+        u8              reserved13[3];
+        u8              ircr2;          /* PSC + 0x44 */
+        u8              reserved14[3];
+        u8              irsdr;          /* PSC + 0x4c */
+        u8              reserved15[3];
+        u8              irmdr;          /* PSC + 0x50 */
+        u8              reserved16[3];
+        u8              irfdr;          /* PSC + 0x54 */
+        u8              reserved17[3];
+        u16             rfnum;          /* PSC + 0x58 */
+        u16             reserved18;
+        u16             tfnum;          /* PSC + 0x5c */
+        u16             reserved19;
+        u32             rfdata;         /* PSC + 0x60 */
+        u16             rfstat;         /* PSC + 0x64 */
+        u16             reserved20;
+        u8              rfcntl;         /* PSC + 0x68 */
+        u8              reserved21[5];
+        u16             rfalarm;        /* PSC + 0x6e */
+        u16             reserved22;
+        u16             rfrptr;         /* PSC + 0x72 */
+        u16             reserved23;
+        u16             rfwptr;         /* PSC + 0x76 */
+        u16             reserved24;
+        u16             rflrfptr;       /* PSC + 0x7a */
+        u16             reserved25;
+        u16             rflwfptr;       /* PSC + 0x7e */
+        u32             tfdata;         /* PSC + 0x80 */
+        u16             tfstat;         /* PSC + 0x84 */
+        u16             reserved26;
+        u8              tfcntl;         /* PSC + 0x88 */
+        u8              reserved27[5];
+        u16             tfalarm;        /* PSC + 0x8e */
+        u16             reserved28;
+        u16             tfrptr;         /* PSC + 0x92 */
+        u16             reserved29;
+        u16             tfwptr;         /* PSC + 0x96 */
+        u16             reserved30;
+        u16             tflrfptr;       /* PSC + 0x9a */
+        u16             reserved31;
+        u16             tflwfptr;       /* PSC + 0x9e */
+};
+
+
+#endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
new file mode 100644
index 000000000000..d820894e5991
--- /dev/null
+++ b/include/asm-ppc/mpc8260.h
@@ -0,0 +1,79 @@
+/*
+ * Since there are many different boards and no standard configuration,
+ * we have a unique include file for each.  Rather than change every
+ * file that has to include MPC8260 configuration, they all include
+ * this one and the configuration switching is done here.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_MPC8260_H__
+#define __ASM_PPC_MPC8260_H__
+
+#include <linux/config.h>
+
+#ifdef CONFIG_8260
+
+#ifdef CONFIG_EST8260
+#include <platforms/est8260.h>
+#endif
+
+#ifdef CONFIG_SBC82xx
+#include <platforms/sbc82xx.h>
+#endif
+
+#ifdef CONFIG_SBS8260
+#include <platforms/sbs8260.h>
+#endif
+
+#ifdef CONFIG_RPX8260
+#include <platforms/rpx8260.h>
+#endif
+
+#ifdef CONFIG_WILLOW
+#include <platforms/willow.h>
+#endif
+
+#ifdef CONFIG_TQM8260
+#include <platforms/tqm8260.h>
+#endif
+
+#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
+#include <platforms/pq2ads.h>
+#endif
+
+#ifdef CONFIG_PCI_8260
+#include <syslib/m8260_pci.h>
+#endif
+
+/* Make sure the memory translation stuff is there if PCI not used.
+ */
+#ifndef _IO_BASE
+#define _IO_BASE        0
+#endif
+
+#ifndef _ISA_MEM_BASE
+#define _ISA_MEM_BASE   0
+#endif
+
+#ifndef PCI_DRAM_OFFSET
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/* Map 256MB I/O region
+ */
+#ifndef IO_PHYS_ADDR
+#define IO_PHYS_ADDR    0xe0000000
+#endif
+#ifndef IO_VIRT_ADDR
+#define IO_VIRT_ADDR    IO_PHYS_ADDR
+#endif
+
+#ifndef __ASSEMBLY__
+/* The "residual" data board information structure the boot loader
+ * hands to us.
+ */
+extern unsigned char __res[];
+#endif
+
+#endif /* CONFIG_8260 */
+#endif /* !__ASM_PPC_MPC8260_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h
new file mode 100644
index 000000000000..26b3f6e787bc
--- /dev/null
+++ b/include/asm-ppc/mpc8260_pci9.h
@@ -0,0 +1,51 @@
+/* include/asm-ppc/mpc8260_pci9.h
+ *
+ * Undefine the PCI read* and in* macros so we can define them as functions
+ * that implement the workaround for the MPC8260 device erratum PCI 9.
+ *
+ * This header file should only be included at the end of include/asm-ppc/io.h
+ * and never included directly anywhere else.
+ *
+ * Author:  andy_lowe@mvista.com
+ *
+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _PPC_IO_H
+#error "Do not include mpc8260_pci9.h directly."
+#endif
+
+#ifdef __KERNEL__
+#ifndef __CONFIG_8260_PCI9_DEFS
+#define __CONFIG_8260_PCI9_DEFS
+
+#undef readb
+#undef readw
+#undef readl
+#undef insb
+#undef insw
+#undef insl
+#undef inb
+#undef inw
+#undef inl
+#undef insw_ns
+#undef insl_ns
+#undef memcpy_fromio
+
+extern int readb(volatile unsigned char *addr);
+extern int readw(volatile unsigned short *addr);
+extern unsigned readl(volatile unsigned *addr);
+extern void insb(unsigned port, void *buf, int ns);
+extern void insw(unsigned port, void *buf, int ns);
+extern void insl(unsigned port, void *buf, int nl);
+extern int inb(unsigned port);
+extern int inw(unsigned port);
+extern unsigned inl(unsigned port);
+extern void insw_ns(unsigned port, void *buf, int ns);
+extern void insl_ns(unsigned port, void *buf, int nl);
+extern void *memcpy_fromio(void *dest, unsigned long src, size_t count);
+
+#endif /* !__CONFIG_8260_PCI9_DEFS */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
new file mode 100644
index 000000000000..bb1b0576c947
--- /dev/null
+++ b/include/asm-ppc/mpc83xx.h
@@ -0,0 +1,114 @@
+/*
+ * include/asm-ppc/mpc83xx.h
+ *
+ * MPC83xx definitions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_MPC83xx_H__
+#define __ASM_MPC83xx_H__
+
+#include <linux/config.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_83xx
+
+#ifdef CONFIG_MPC834x_SYS
+#include <platforms/83xx/mpc834x_sys.h>
+#endif
+
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Internal IRQs on MPC83xx OpenPIC */
+/* Not all of these exist on all MPC83xx implementations */
+
+#ifndef MPC83xx_IPIC_IRQ_OFFSET
+#define MPC83xx_IPIC_IRQ_OFFSET 0
+#endif
+
+#define NR_IPIC_INTS 128
+
+#define MPC83xx_IRQ_UART1       ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_UART2       (10 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SEC2        (11 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC1        (14 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_IIC2        (15 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SPI         (16 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT1        (17 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT2        (18 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT3        (19 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT4        (20 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT5        (21 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT6        (22 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT7        (23 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_TX    (32 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_RX    (33 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_TX    (35 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_RX    (36 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_DR     (38 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_USB2_MPH    (39 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_EXT0        (48 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_SEC     (64 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PIT         (65 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI1        (66 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PCI2        (67 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_RTC_ALR     (68 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_MU          (69 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_SBA         (70 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DMA         (71 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM4        (72 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM8        (73 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO1       (74 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GPIO2       (75 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_DDR         (76 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_LBC         (77 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM2        (78 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM6        (79 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_PMC         (80 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM3        (84 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM7        (85 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM1        (90 + MPC83xx_IPIC_IRQ_OFFSET)
+#define MPC83xx_IRQ_GTM5        (91 + MPC83xx_IPIC_IRQ_OFFSET)
+
+#define MPC83xx_CCSRBAR_SIZE    (1024*1024)
+
+/* Let modules/drivers get at immrbar (physical) */
+extern phys_addr_t immrbar;
+
+enum ppc_sys_devices {
+        MPC83xx_TSEC1,
+        MPC83xx_TSEC2,
+        MPC83xx_IIC1,
+        MPC83xx_IIC2,
+        MPC83xx_DUART,
+        MPC83xx_SEC2,
+        MPC83xx_USB2_DR,
+        MPC83xx_USB2_MPH,
+};
+
+#endif /* CONFIG_83xx */
+#endif /* __ASM_MPC83xx_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
new file mode 100644
index 000000000000..22713e331585
--- /dev/null
+++ b/include/asm-ppc/mpc85xx.h
@@ -0,0 +1,134 @@
+/*
+ * include/asm-ppc/mpc85xx.h
+ *
+ * MPC85xx definitions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_MPC85xx_H__
+#define __ASM_MPC85xx_H__
+
+#include <linux/config.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_85xx
+
+#ifdef CONFIG_MPC8540_ADS
+#include <platforms/85xx/mpc8540_ads.h>
+#endif
+#ifdef CONFIG_MPC8555_CDS
+#include <platforms/85xx/mpc8555_cds.h>
+#endif
+#ifdef CONFIG_MPC8560_ADS
+#include <platforms/85xx/mpc8560_ads.h>
+#endif
+#ifdef CONFIG_SBC8560
+#include <platforms/85xx/sbc8560.h>
+#endif
+#ifdef CONFIG_STX_GP3
+#include <platforms/85xx/stx_gp3.h>
+#endif
+
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern unsigned char __res[];
+
+/* Offset from CCSRBAR */
+#define MPC85xx_CPM_OFFSET      (0x80000)
+#define MPC85xx_CPM_SIZE        (0x40000)
+#define MPC85xx_DMA_OFFSET      (0x21000)
+#define MPC85xx_DMA_SIZE        (0x01000)
+#define MPC85xx_DMA0_OFFSET     (0x21100)
+#define MPC85xx_DMA0_SIZE       (0x00080)
+#define MPC85xx_DMA1_OFFSET     (0x21180)
+#define MPC85xx_DMA1_SIZE       (0x00080)
+#define MPC85xx_DMA2_OFFSET     (0x21200)
+#define MPC85xx_DMA2_SIZE       (0x00080)
+#define MPC85xx_DMA3_OFFSET     (0x21280)
+#define MPC85xx_DMA3_SIZE       (0x00080)
+#define MPC85xx_ENET1_OFFSET    (0x24000)
+#define MPC85xx_ENET1_SIZE      (0x01000)
+#define MPC85xx_ENET2_OFFSET    (0x25000)
+#define MPC85xx_ENET2_SIZE      (0x01000)
+#define MPC85xx_ENET3_OFFSET    (0x26000)
+#define MPC85xx_ENET3_SIZE      (0x01000)
+#define MPC85xx_GUTS_OFFSET     (0xe0000)
+#define MPC85xx_GUTS_SIZE       (0x01000)
+#define MPC85xx_IIC1_OFFSET     (0x03000)
+#define MPC85xx_IIC1_SIZE       (0x01000)
+#define MPC85xx_OPENPIC_OFFSET  (0x40000)
+#define MPC85xx_OPENPIC_SIZE    (0x40000)
+#define MPC85xx_PCI1_OFFSET     (0x08000)
+#define MPC85xx_PCI1_SIZE       (0x01000)
+#define MPC85xx_PCI2_OFFSET     (0x09000)
+#define MPC85xx_PCI2_SIZE       (0x01000)
+#define MPC85xx_PERFMON_OFFSET  (0xe1000)
+#define MPC85xx_PERFMON_SIZE    (0x01000)
+#define MPC85xx_SEC2_OFFSET     (0x30000)
+#define MPC85xx_SEC2_SIZE       (0x10000)
+#define MPC85xx_UART0_OFFSET    (0x04500)
+#define MPC85xx_UART0_SIZE      (0x00100)
+#define MPC85xx_UART1_OFFSET    (0x04600)
+#define MPC85xx_UART1_SIZE      (0x00100)
+
+#define MPC85xx_CCSRBAR_SIZE    (1024*1024)
+
+/* Let modules/drivers get at CCSRBAR */
+extern phys_addr_t get_ccsrbar(void);
+
+#ifdef MODULE
+#define CCSRBAR get_ccsrbar()
+#else
+#define CCSRBAR BOARD_CCSRBAR
+#endif
+
+enum ppc_sys_devices {
+        MPC85xx_TSEC1,
+        MPC85xx_TSEC2,
+        MPC85xx_FEC,
+        MPC85xx_IIC1,
+        MPC85xx_DMA0,
+        MPC85xx_DMA1,
+        MPC85xx_DMA2,
+        MPC85xx_DMA3,
+        MPC85xx_DUART,
+        MPC85xx_PERFMON,
+        MPC85xx_SEC2,
+        MPC85xx_CPM_SPI,
+        MPC85xx_CPM_I2C,
+        MPC85xx_CPM_USB,
+        MPC85xx_CPM_SCC1,
+        MPC85xx_CPM_SCC2,
+        MPC85xx_CPM_SCC3,
+        MPC85xx_CPM_SCC4,
+        MPC85xx_CPM_FCC1,
+        MPC85xx_CPM_FCC2,
+        MPC85xx_CPM_FCC3,
+        MPC85xx_CPM_MCC1,
+        MPC85xx_CPM_MCC2,
+        MPC85xx_CPM_SMC1,
+        MPC85xx_CPM_SMC2,
+};
+
+#endif /* CONFIG_85xx */
+#endif /* __ASM_MPC85xx_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
new file mode 100644
index 000000000000..714d69c819d3
--- /dev/null
+++ b/include/asm-ppc/mpc8xx.h
@@ -0,0 +1,103 @@
+/* This is the single file included by all MPC8xx build options.
+ * Since there are many different boards and no standard configuration,
+ * we have a unique include file for each.  Rather than change every
+ * file that has to include MPC8xx configuration, they all include
+ * this one and the configuration switching is done here.
+ */
+#ifdef __KERNEL__
+#ifndef __CONFIG_8xx_DEFS
+#define __CONFIG_8xx_DEFS
+
+#include <linux/config.h>
+
+#ifdef CONFIG_8xx
+
+#ifdef CONFIG_MBX
+#include <platforms/mbx.h>
+#endif
+
+#ifdef CONFIG_FADS
+#include <platforms/fads.h>
+#endif
+
+#ifdef CONFIG_RPXLITE
+#include <platforms/rpxlite.h>
+#endif
+
+#ifdef CONFIG_BSEIP
+#include <platforms/bseip.h>
+#endif
+
+#ifdef CONFIG_RPXCLASSIC
+#include <platforms/rpxclassic.h>
+#endif
+
+#if defined(CONFIG_TQM8xxL)
+#include <platforms/tqm8xx.h>
+#endif
+
+#if defined(CONFIG_SPD823TS)
+#include <platforms/spd8xx.h>
+#endif
+
+#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
+#include <platforms/ivms8.h>
+#endif
+
+#if defined(CONFIG_HERMES_PRO)
+#include <platforms/hermes.h>
+#endif
+
+#if defined(CONFIG_IP860)
+#include <platforms/ip860.h>
+#endif
+
+#if defined(CONFIG_LWMON)
+#include <platforms/lwmon.h>
+#endif
+
+#if defined(CONFIG_PCU_E)
+#include <platforms/pcu_e.h>
+#endif
+
+#if defined(CONFIG_CCM)
+#include <platforms/ccm.h>
+#endif
+
+#if defined(CONFIG_LANTEC)
+#include <platforms/lantec.h>
+#endif
+
+/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
+ * use the same memory map.
+ */
+#if 0
+#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
+#define _IO_BASE PCI_ISA_IO_ADDR
+#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR
+#define PCI_DRAM_OFFSET 0x80000000
+#else
+#define _IO_BASE        0
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#endif
+#else
+#if !defined(_IO_BASE)  /* defined in board specific header */
+#define _IO_BASE        0
+#endif
+#define _ISA_MEM_BASE   0
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#ifndef __ASSEMBLY__
+/* The "residual" data board information structure the boot loader
+ * hands to us.
+ */
+extern unsigned char __res[];
+
+struct pt_regs;
+
+#endif /* !__ASSEMBLY__ */
+#endif /* CONFIG_8xx */
+#endif /* __CONFIG_8xx_DEFS */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/msgbuf.h b/include/asm-ppc/msgbuf.h
new file mode 100644
index 000000000000..1053452a9376
--- /dev/null
+++ b/include/asm-ppc/msgbuf.h
@@ -0,0 +1,25 @@
+#ifndef _PPC_MSGBUF_H
+#define _PPC_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for the PPC architecture.
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        unsigned int    __unused1;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned int    __unused2;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned int    __unused3;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _PPC_MSGBUF_H */
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
new file mode 100644
index 000000000000..cc25b921ad4f
--- /dev/null
+++ b/include/asm-ppc/mv64x60.h
@@ -0,0 +1,345 @@
+/*
+ * include/asm-ppc/mv64x60.h
+ *
+ * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASMPPC_MV64x60_H
+#define __ASMPPC_MV64x60_H
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/config.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/mv64x60_defs.h>
+
+extern u8       mv64x60_pci_exclude_bridge;
+
+extern spinlock_t mv64x60_lock;
+
+/* 32-bit Window table entry defines */
+#define MV64x60_CPU2MEM_0_WIN                   0
+#define MV64x60_CPU2MEM_1_WIN                   1
+#define MV64x60_CPU2MEM_2_WIN                   2
+#define MV64x60_CPU2MEM_3_WIN                   3
+#define MV64x60_CPU2DEV_0_WIN                   4
+#define MV64x60_CPU2DEV_1_WIN                   5
+#define MV64x60_CPU2DEV_2_WIN                   6
+#define MV64x60_CPU2DEV_3_WIN                   7
+#define MV64x60_CPU2BOOT_WIN                    8
+#define MV64x60_CPU2PCI0_IO_WIN                 9
+#define MV64x60_CPU2PCI0_MEM_0_WIN              10
+#define MV64x60_CPU2PCI0_MEM_1_WIN              11
+#define MV64x60_CPU2PCI0_MEM_2_WIN              12
+#define MV64x60_CPU2PCI0_MEM_3_WIN              13
+#define MV64x60_CPU2PCI1_IO_WIN                 14
+#define MV64x60_CPU2PCI1_MEM_0_WIN              15
+#define MV64x60_CPU2PCI1_MEM_1_WIN              16
+#define MV64x60_CPU2PCI1_MEM_2_WIN              17
+#define MV64x60_CPU2PCI1_MEM_3_WIN              18
+#define MV64x60_CPU2SRAM_WIN                    19
+#define MV64x60_CPU2PCI0_IO_REMAP_WIN           20
+#define MV64x60_CPU2PCI1_IO_REMAP_WIN           21
+#define MV64x60_CPU_PROT_0_WIN                  22
+#define MV64x60_CPU_PROT_1_WIN                  23
+#define MV64x60_CPU_PROT_2_WIN                  24
+#define MV64x60_CPU_PROT_3_WIN                  25
+#define MV64x60_CPU_SNOOP_0_WIN                 26
+#define MV64x60_CPU_SNOOP_1_WIN                 27
+#define MV64x60_CPU_SNOOP_2_WIN                 28
+#define MV64x60_CPU_SNOOP_3_WIN                 29
+#define MV64x60_PCI02MEM_REMAP_0_WIN            30
+#define MV64x60_PCI02MEM_REMAP_1_WIN            31
+#define MV64x60_PCI02MEM_REMAP_2_WIN            32
+#define MV64x60_PCI02MEM_REMAP_3_WIN            33
+#define MV64x60_PCI12MEM_REMAP_0_WIN            34
+#define MV64x60_PCI12MEM_REMAP_1_WIN            35
+#define MV64x60_PCI12MEM_REMAP_2_WIN            36
+#define MV64x60_PCI12MEM_REMAP_3_WIN            37
+#define MV64x60_ENET2MEM_0_WIN                  38
+#define MV64x60_ENET2MEM_1_WIN                  39
+#define MV64x60_ENET2MEM_2_WIN                  40
+#define MV64x60_ENET2MEM_3_WIN                  41
+#define MV64x60_ENET2MEM_4_WIN                  42
+#define MV64x60_ENET2MEM_5_WIN                  43
+#define MV64x60_MPSC2MEM_0_WIN                  44
+#define MV64x60_MPSC2MEM_1_WIN                  45
+#define MV64x60_MPSC2MEM_2_WIN                  46
+#define MV64x60_MPSC2MEM_3_WIN                  47
+#define MV64x60_IDMA2MEM_0_WIN                  48
+#define MV64x60_IDMA2MEM_1_WIN                  49
+#define MV64x60_IDMA2MEM_2_WIN                  50
+#define MV64x60_IDMA2MEM_3_WIN                  51
+#define MV64x60_IDMA2MEM_4_WIN                  52
+#define MV64x60_IDMA2MEM_5_WIN                  53
+#define MV64x60_IDMA2MEM_6_WIN                  54
+#define MV64x60_IDMA2MEM_7_WIN                  55
+
+#define MV64x60_32BIT_WIN_COUNT                 56
+
+/* 64-bit Window table entry defines */
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN        0
+#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN        1
+#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN        2
+#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN        3
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN        4
+#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN        5
+#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN        6
+#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN        7
+#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN         8
+#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN         9
+#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN         10
+#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN         11
+#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN         12
+#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN         13
+#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN         14
+#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN         15
+#define MV64x60_PCI02MEM_SNOOP_0_WIN            16
+#define MV64x60_PCI02MEM_SNOOP_1_WIN            17
+#define MV64x60_PCI02MEM_SNOOP_2_WIN            18
+#define MV64x60_PCI02MEM_SNOOP_3_WIN            19
+#define MV64x60_PCI12MEM_SNOOP_0_WIN            20
+#define MV64x60_PCI12MEM_SNOOP_1_WIN            21
+#define MV64x60_PCI12MEM_SNOOP_2_WIN            22
+#define MV64x60_PCI12MEM_SNOOP_3_WIN            23
+
+#define MV64x60_64BIT_WIN_COUNT                 24
+
+/*
+ * Define a structure that's used to pass in config information to the
+ * core routines.
+ */
+struct mv64x60_pci_window {
+        u32     cpu_base;
+        u32     pci_base_hi;
+        u32     pci_base_lo;
+        u32     size;
+        u32     swap;
+};
+
+struct mv64x60_pci_info {
+        u8      enable_bus;     /* allow access to this PCI bus? */
+
+        struct mv64x60_pci_window       pci_io;
+        struct mv64x60_pci_window       pci_mem[3];
+
+        u32     acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
+        u32     snoop_options[MV64x60_CPU2MEM_WINDOWS];
+        u16     pci_cmd_bits;
+        u16     latency_timer;
+};
+
+struct mv64x60_setup_info {
+        u32     phys_reg_base;
+        u32     window_preserve_mask_32_hi;
+        u32     window_preserve_mask_32_lo;
+        u32     window_preserve_mask_64;
+
+        u32     cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
+        u32     cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
+        u32     enet_options[MV64x60_CPU2MEM_WINDOWS];
+        u32     mpsc_options[MV64x60_CPU2MEM_WINDOWS];
+        u32     idma_options[MV64x60_CPU2MEM_WINDOWS];
+
+        struct mv64x60_pci_info pci_0;
+        struct mv64x60_pci_info pci_1;
+};
+
+/* Define what the top bits in the extra member of a window entry means. */
+#define MV64x60_EXTRA_INVALID           0x00000000
+#define MV64x60_EXTRA_CPUWIN_ENAB       0x10000000
+#define MV64x60_EXTRA_CPUPROT_ENAB      0x20000000
+#define MV64x60_EXTRA_ENET_ENAB         0x30000000
+#define MV64x60_EXTRA_MPSC_ENAB         0x40000000
+#define MV64x60_EXTRA_IDMA_ENAB         0x50000000
+#define MV64x60_EXTRA_PCIACC_ENAB       0x60000000
+
+#define MV64x60_EXTRA_MASK              0xf0000000
+
+/*
+ * Define the 'handle' struct that will be passed between the 64x60 core
+ * code and the platform-specific code that will use it.  The handle
+ * will contain pointers to chip-specific routines & information.
+ */
+struct mv64x60_32bit_window {
+        u32     base_reg;
+        u32     size_reg;
+        u8      base_bits;
+        u8      size_bits;
+        u32     (*get_from_field)(u32 val, u32 num_bits);
+        u32     (*map_to_field)(u32 val, u32 num_bits);
+        u32     extra;
+};
+
+struct mv64x60_64bit_window {
+        u32     base_hi_reg;
+        u32     base_lo_reg;
+        u32     size_reg;
+        u8      base_lo_bits;
+        u8      size_bits;
+        u32     (*get_from_field)(u32 val, u32 num_bits);
+        u32     (*map_to_field)(u32 val, u32 num_bits);
+        u32     extra;
+};
+
+typedef struct mv64x60_handle   mv64x60_handle_t;
+struct mv64x60_chip_info {
+        u32     (*translate_size)(u32 base, u32 size, u32 num_bits);
+        u32     (*untranslate_size)(u32 base, u32 size, u32 num_bits);
+        void    (*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
+                        u32 window, u32 base);
+        void    (*set_pci2regs_window)(struct mv64x60_handle *bh,
+                        struct pci_controller *hose, u32 bus, u32 base);
+        u32     (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
+        void    (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
+        void    (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
+        void    (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
+        void    (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
+        void    (*disable_all_windows)(mv64x60_handle_t *bh,
+                        struct mv64x60_setup_info *si);
+        void    (*config_io2mem_windows)(mv64x60_handle_t *bh,
+                        struct mv64x60_setup_info *si,
+                        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
+        void    (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
+        void    (*chip_specific_init)(mv64x60_handle_t *bh,
+                        struct mv64x60_setup_info *si);
+
+        struct mv64x60_32bit_window     *window_tab_32bit;
+        struct mv64x60_64bit_window     *window_tab_64bit;
+};
+
+struct mv64x60_handle {
+        u32             type;           /* type of bridge */
+        u32             rev;            /* revision of bridge */
+        void            *v_base;        /* virtual base addr of bridge regs */
+        phys_addr_t     p_base;         /* physical base addr of bridge regs */
+
+        u32             pci_mode_a;     /* pci 0 mode: conventional pci, pci-x*/
+        u32             pci_mode_b;     /* pci 1 mode: conventional pci, pci-x*/
+
+        u32             io_base_a;      /* vaddr of pci 0's I/O space */
+        u32             io_base_b;      /* vaddr of pci 1's I/O space */
+
+        struct pci_controller   *hose_a;
+        struct pci_controller   *hose_b;
+
+        struct mv64x60_chip_info *ci;   /* chip/bridge-specific info */
+};
+
+
+/* Define I/O routines for accessing registers on the 64x60 bridge. */
+extern inline void
+mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
+        ulong   flags;
+
+        spin_lock_irqsave(&mv64x60_lock, flags);
+        out_le32(bh->v_base + offset, val);
+        spin_unlock_irqrestore(&mv64x60_lock, flags);
+}
+
+extern inline u32
+mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
+        ulong   flags;
+        u32     reg;
+
+        spin_lock_irqsave(&mv64x60_lock, flags);
+        reg = in_le32(bh->v_base + offset);
+        spin_unlock_irqrestore(&mv64x60_lock, flags);
+        return reg;
+}
+
+extern inline void
+mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
+{
+        u32     reg;
+        ulong   flags;
+
+        spin_lock_irqsave(&mv64x60_lock, flags);
+        reg = in_le32(bh->v_base + offs) & (~mask);
+        reg |= data & mask;
+        out_le32(bh->v_base + offs, reg);
+        spin_unlock_irqrestore(&mv64x60_lock, flags);
+}
+
+#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
+#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
+
+
+/* Externally visible function prototypes */
+int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
+u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
+void mv64x60_early_init(struct mv64x60_handle *bh,
+        struct mv64x60_setup_info *si);
+void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
+        u32 cfg_data, struct pci_controller **hose);
+int mv64x60_get_type(struct mv64x60_handle *bh);
+int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
+void *mv64x60_get_bridge_vbase(void);
+u32 mv64x60_get_bridge_type(void);
+u32 mv64x60_get_bridge_rev(void);
+void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
+        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
+void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
+        struct mv64x60_setup_info *si,
+        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
+void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
+        struct mv64x60_pci_info *pi, u32 bus);
+void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
+        struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
+        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
+void mv64x60_config_resources(struct pci_controller *hose,
+        struct mv64x60_pci_info *pi, u32 io_base);
+void mv64x60_config_pci_params(struct pci_controller *hose,
+        struct mv64x60_pci_info *pi);
+void mv64x60_pd_fixup(struct mv64x60_handle *bh,
+        struct platform_device *pd_devs[], u32 entries);
+void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
+        u32 *base, u32 *size);
+void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
+        u32 size, u32 other_bits);
+void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
+        u32 *base_hi, u32 *base_lo, u32 *size);
+void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
+        u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
+void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
+int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
+
+
+void gt64260_init_irq(void);
+int gt64260_get_irq(struct pt_regs *regs);
+void mv64360_init_irq(void);
+int mv64360_get_irq(struct pt_regs *regs);
+
+u32 mv64x60_mask(u32 val, u32 num_bits);
+u32 mv64x60_shift_left(u32 val, u32 num_bits);
+u32 mv64x60_shift_right(u32 val, u32 num_bits);
+u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
+        u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
+
+void mv64x60_progress_init(u32 base);
+void mv64x60_mpsc_progress(char *s, unsigned short hex);
+
+extern struct mv64x60_32bit_window
+        gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
+extern struct mv64x60_64bit_window
+        gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
+extern struct mv64x60_32bit_window
+        mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
+extern struct mv64x60_64bit_window
+        mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
+
+#endif /* __ASMPPC_MV64x60_H */
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
new file mode 100644
index 000000000000..2f428746c02b
--- /dev/null
+++ b/include/asm-ppc/mv64x60_defs.h
@@ -0,0 +1,973 @@
+/*
+ * include/asm-ppc/gt64260_defs.h
+ *
+ * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
+ * host bridges.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASMPPC_MV64x60_DEFS_H
+#define __ASMPPC_MV64x60_DEFS_H
+
+/*
+ * Define the Marvell bridges that are supported
+ */
+#define MV64x60_TYPE_INVALID                    0
+#define MV64x60_TYPE_GT64260A                   1
+#define MV64x60_TYPE_GT64260B                   2
+#define MV64x60_TYPE_MV64360                    3
+#define MV64x60_TYPE_MV64361                    4
+#define MV64x60_TYPE_MV64362                    5
+#define MV64x60_TYPE_MV64460                    6
+
+
+/* Revisions of each supported chip */
+#define GT64260_REV_A                           0x10
+#define GT64260_REV_B                           0x20
+#define MV64360                                 0x01
+#define MV64460                                 0x01
+
+/* Minimum window size supported by 64260 is 1MB */
+#define GT64260_WINDOW_SIZE_MIN                 0x00100000
+#define MV64360_WINDOW_SIZE_MIN                 0x00010000
+
+#define MV64x60_TCLK_FREQ_MAX                   133333333U
+
+/* IRQ's for embedded controllers */
+#define MV64x60_IRQ_DEV                         1
+#define MV64x60_IRQ_CPU_ERR                     3
+#define MV64x60_IRQ_TIMER_0_1                   8
+#define MV64x60_IRQ_TIMER_2_3                   9
+#define MV64x60_IRQ_TIMER_4_5                   10
+#define MV64x60_IRQ_TIMER_6_7                   11
+#define MV64x60_IRQ_P1_GPP_0_7                  24
+#define MV64x60_IRQ_P1_GPP_8_15                 25
+#define MV64x60_IRQ_P1_GPP_16_23                26
+#define MV64x60_IRQ_P1_GPP_24_31                27
+#define MV64x60_IRQ_DOORBELL                    28
+#define MV64x60_IRQ_ETH_0                       32
+#define MV64x60_IRQ_ETH_1                       33
+#define MV64x60_IRQ_ETH_2                       34
+#define MV64x60_IRQ_SDMA_0                      36
+#define MV64x60_IRQ_I2C                         37
+#define MV64x60_IRQ_BRG                         39
+#define MV64x60_IRQ_MPSC_0                      40
+#define MV64x60_IRQ_MPSC_1                      42
+#define MV64x60_IRQ_COMM                        43
+#define MV64x60_IRQ_P0_GPP_0_7                  56
+#define MV64x60_IRQ_P0_GPP_8_15                 57
+#define MV64x60_IRQ_P0_GPP_16_23                58
+#define MV64x60_IRQ_P0_GPP_24_31                59
+
+#define MV64360_IRQ_PCI0                        12
+#define MV64360_IRQ_SRAM_PAR_ERR                13
+#define MV64360_IRQ_PCI1                        16
+#define MV64360_IRQ_SDMA_1                      38
+
+#define MV64x60_IRQ_GPP0                        64
+#define MV64x60_IRQ_GPP1                        65
+#define MV64x60_IRQ_GPP2                        66
+#define MV64x60_IRQ_GPP3                        67
+#define MV64x60_IRQ_GPP4                        68
+#define MV64x60_IRQ_GPP5                        69
+#define MV64x60_IRQ_GPP6                        70
+#define MV64x60_IRQ_GPP7                        71
+#define MV64x60_IRQ_GPP8                        72
+#define MV64x60_IRQ_GPP9                        73
+#define MV64x60_IRQ_GPP10                       74
+#define MV64x60_IRQ_GPP11                       75
+#define MV64x60_IRQ_GPP12                       76
+#define MV64x60_IRQ_GPP13                       77
+#define MV64x60_IRQ_GPP14                       78
+#define MV64x60_IRQ_GPP15                       79
+#define MV64x60_IRQ_GPP16                       80
+#define MV64x60_IRQ_GPP17                       81
+#define MV64x60_IRQ_GPP18                       82
+#define MV64x60_IRQ_GPP19                       83
+#define MV64x60_IRQ_GPP20                       84
+#define MV64x60_IRQ_GPP21                       85
+#define MV64x60_IRQ_GPP22                       86
+#define MV64x60_IRQ_GPP23                       87
+#define MV64x60_IRQ_GPP24                       88
+#define MV64x60_IRQ_GPP25                       89
+#define MV64x60_IRQ_GPP26                       90
+#define MV64x60_IRQ_GPP27                       91
+#define MV64x60_IRQ_GPP28                       92
+#define MV64x60_IRQ_GPP29                       93
+#define MV64x60_IRQ_GPP30                       94
+#define MV64x60_IRQ_GPP31                       95
+
+/* Offsets for register blocks */
+#define GT64260_ENET_PHY_ADDR                   0x2000
+#define GT64260_ENET_ESMIR                      0x2010
+#define GT64260_ENET_0_OFFSET                   0x2400
+#define GT64260_ENET_1_OFFSET                   0x2800
+#define GT64260_ENET_2_OFFSET                   0x2c00
+#define MV64x60_SDMA_0_OFFSET                   0x4000
+#define MV64x60_SDMA_1_OFFSET                   0x6000
+#define MV64x60_MPSC_0_OFFSET                   0x8000
+#define MV64x60_MPSC_1_OFFSET                   0x9000
+#define MV64x60_MPSC_ROUTING_OFFSET             0xb400
+#define MV64x60_SDMA_INTR_OFFSET                0xb800
+#define MV64x60_BRG_0_OFFSET                    0xb200
+#define MV64x60_BRG_1_OFFSET                    0xb208
+
+/*
+ *****************************************************************************
+ *
+ *      CPU Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* CPU physical address of bridge's registers */
+#define MV64x60_INTERNAL_SPACE_DECODE           0x0068
+#define MV64x60_INTERNAL_SPACE_SIZE             0x10000
+#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR     0x14000000
+
+#define MV64360_CPU_BAR_ENABLE                  0x0278
+
+/* CPU Memory Controller Window Registers (4 windows) */
+#define MV64x60_CPU2MEM_WINDOWS                 4
+
+#define MV64x60_CPU2MEM_0_BASE                  0x0008
+#define MV64x60_CPU2MEM_0_SIZE                  0x0010
+#define MV64x60_CPU2MEM_1_BASE                  0x0208
+#define MV64x60_CPU2MEM_1_SIZE                  0x0210
+#define MV64x60_CPU2MEM_2_BASE                  0x0018
+#define MV64x60_CPU2MEM_2_SIZE                  0x0020
+#define MV64x60_CPU2MEM_3_BASE                  0x0218
+#define MV64x60_CPU2MEM_3_SIZE                  0x0220
+
+/* CPU Device Controller Window Registers (4 windows) */
+#define MV64x60_CPU2DEV_WINDOWS                 4
+
+#define MV64x60_CPU2DEV_0_BASE                  0x0028
+#define MV64x60_CPU2DEV_0_SIZE                  0x0030
+#define MV64x60_CPU2DEV_1_BASE                  0x0228
+#define MV64x60_CPU2DEV_1_SIZE                  0x0230
+#define MV64x60_CPU2DEV_2_BASE                  0x0248
+#define MV64x60_CPU2DEV_2_SIZE                  0x0250
+#define MV64x60_CPU2DEV_3_BASE                  0x0038
+#define MV64x60_CPU2DEV_3_SIZE                  0x0040
+
+#define MV64x60_CPU2BOOT_0_BASE                 0x0238
+#define MV64x60_CPU2BOOT_0_SIZE                 0x0240
+
+#define MV64360_CPU2SRAM_BASE                   0x0268
+
+/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
+#define MV64x60_PCI_BUSES                       2
+#define MV64x60_PCI_IO_WINDOWS_PER_BUS          1
+#define MV64x60_PCI_MEM_WINDOWS_PER_BUS         4
+
+#define MV64x60_CPU2PCI_SWAP_BYTE               0x00000000
+#define MV64x60_CPU2PCI_SWAP_NONE               0x01000000
+#define MV64x60_CPU2PCI_SWAP_BYTE_WORD          0x02000000
+#define MV64x60_CPU2PCI_SWAP_WORD               0x03000000
+
+#define MV64x60_CPU2PCI_MEM_REQ64               (1<<27)
+
+#define MV64x60_CPU2PCI0_IO_BASE                0x0048
+#define MV64x60_CPU2PCI0_IO_SIZE                0x0050
+#define MV64x60_CPU2PCI0_MEM_0_BASE             0x0058
+#define MV64x60_CPU2PCI0_MEM_0_SIZE             0x0060
+#define MV64x60_CPU2PCI0_MEM_1_BASE             0x0080
+#define MV64x60_CPU2PCI0_MEM_1_SIZE             0x0088
+#define MV64x60_CPU2PCI0_MEM_2_BASE             0x0258
+#define MV64x60_CPU2PCI0_MEM_2_SIZE             0x0260
+#define MV64x60_CPU2PCI0_MEM_3_BASE             0x0280
+#define MV64x60_CPU2PCI0_MEM_3_SIZE             0x0288
+
+#define MV64x60_CPU2PCI0_IO_REMAP               0x00f0
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO         0x00f8
+#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI         0x0320
+#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO         0x0100
+#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI         0x0328
+#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO         0x02f8
+#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI         0x0330
+#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO         0x0300
+#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI         0x0338
+
+#define MV64x60_CPU2PCI1_IO_BASE                0x0090
+#define MV64x60_CPU2PCI1_IO_SIZE                0x0098
+#define MV64x60_CPU2PCI1_MEM_0_BASE             0x00a0
+#define MV64x60_CPU2PCI1_MEM_0_SIZE             0x00a8
+#define MV64x60_CPU2PCI1_MEM_1_BASE             0x00b0
+#define MV64x60_CPU2PCI1_MEM_1_SIZE             0x00b8
+#define MV64x60_CPU2PCI1_MEM_2_BASE             0x02a0
+#define MV64x60_CPU2PCI1_MEM_2_SIZE             0x02a8
+#define MV64x60_CPU2PCI1_MEM_3_BASE             0x02b0
+#define MV64x60_CPU2PCI1_MEM_3_SIZE             0x02b8
+
+#define MV64x60_CPU2PCI1_IO_REMAP               0x0108
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO         0x0110
+#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI         0x0340
+#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO         0x0118
+#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI         0x0348
+#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO         0x0310
+#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI         0x0350
+#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO         0x0318
+#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI         0x0358
+
+/* CPU Control Registers */
+#define MV64x60_CPU_CONFIG                      0x0000
+#define MV64x60_CPU_MODE                        0x0120
+#define MV64x60_CPU_MASTER_CNTL                 0x0160
+#define MV64x60_CPU_XBAR_CNTL_LO                0x0150
+#define MV64x60_CPU_XBAR_CNTL_HI                0x0158
+#define MV64x60_CPU_XBAR_TO                     0x0168
+
+#define GT64260_CPU_RR_XBAR_CNTL_LO             0x0170
+#define GT64260_CPU_RR_XBAR_CNTL_HI             0x0178
+
+#define MV64360_CPU_PADS_CALIBRATION            0x03b4
+#define MV64360_CPU_RESET_SAMPLE_LO             0x03c4
+#define MV64360_CPU_RESET_SAMPLE_HI             0x03d4
+
+/* SMP Register Map */
+#define MV64360_WHO_AM_I                        0x0200
+#define MV64360_CPU0_DOORBELL                   0x0214
+#define MV64360_CPU0_DOORBELL_CLR               0x021c
+#define MV64360_CPU0_DOORBELL_MASK              0x0234
+#define MV64360_CPU1_DOORBELL                   0x0224
+#define MV64360_CPU1_DOORBELL_CLR               0x022c
+#define MV64360_CPU1_DOORBELL_MASK              0x023c
+#define MV64360_CPUx_DOORBELL(x)                (0x0214 + ((x)*0x10))
+#define MV64360_CPUx_DOORBELL_CLR(x)            (0x021c + ((x)*0x10))
+#define MV64360_CPUx_DOORBELL_MASK(x)           (0x0234 + ((x)*0x08))
+#define MV64360_SEMAPHORE_0                     0x0244
+#define MV64360_SEMAPHORE_1                     0x024c
+#define MV64360_SEMAPHORE_2                     0x0254
+#define MV64360_SEMAPHORE_3                     0x025c
+#define MV64360_SEMAPHORE_4                     0x0264
+#define MV64360_SEMAPHORE_5                     0x026c
+#define MV64360_SEMAPHORE_6                     0x0274
+#define MV64360_SEMAPHORE_7                     0x027c
+
+/* CPU Sync Barrier Registers */
+#define GT64260_CPU_SYNC_BARRIER_PCI0           0x00c0
+#define GT64260_CPU_SYNC_BARRIER_PCI1           0x00c8
+
+#define MV64360_CPU0_SYNC_BARRIER_TRIG          0x00c0
+#define MV64360_CPU0_SYNC_BARRIER_VIRT          0x00c8
+#define MV64360_CPU1_SYNC_BARRIER_TRIG          0x00d0
+#define MV64360_CPU1_SYNC_BARRIER_VIRT          0x00d8
+
+/* CPU Deadlock and Ordering registers (Rev B part only) */
+#define GT64260_CPU_DEADLOCK_ORDERING                   0x02d0
+#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH            0x02d8
+#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE     0x02e0
+
+/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
+#define MV64x260_CPU_PROT_WINDOWS               4
+
+#define GT64260_CPU_PROT_ACCPROTECT             (1<<16)
+#define GT64260_CPU_PROT_WRPROTECT              (1<<17)
+#define GT64260_CPU_PROT_CACHEPROTECT           (1<<18)
+
+#define MV64360_CPU_PROT_ACCPROTECT             (1<<20)
+#define MV64360_CPU_PROT_WRPROTECT              (1<<21)
+#define MV64360_CPU_PROT_CACHEPROTECT           (1<<22)
+#define MV64360_CPU_PROT_WIN_ENABLE             (1<<31)
+
+#define MV64x60_CPU_PROT_BASE_0                 0x0180
+#define MV64x60_CPU_PROT_SIZE_0                 0x0188
+#define MV64x60_CPU_PROT_BASE_1                 0x0190
+#define MV64x60_CPU_PROT_SIZE_1                 0x0198
+#define MV64x60_CPU_PROT_BASE_2                 0x01a0
+#define MV64x60_CPU_PROT_SIZE_2                 0x01a8
+#define MV64x60_CPU_PROT_BASE_3                 0x01b0
+#define MV64x60_CPU_PROT_SIZE_3                 0x01b8
+
+#define GT64260_CPU_PROT_BASE_4                 0x01c0
+#define GT64260_CPU_PROT_SIZE_4                 0x01c8
+#define GT64260_CPU_PROT_BASE_5                 0x01d0
+#define GT64260_CPU_PROT_SIZE_5                 0x01d8
+#define GT64260_CPU_PROT_BASE_6                 0x01e0
+#define GT64260_CPU_PROT_SIZE_6                 0x01e8
+#define GT64260_CPU_PROT_BASE_7                 0x01f0
+#define GT64260_CPU_PROT_SIZE_7                 0x01f8
+
+/* CPU Snoop Control Registers (64260 only) */
+#define GT64260_CPU_SNOOP_WINDOWS               4
+
+#define GT64260_CPU_SNOOP_NONE                  0x00000000
+#define GT64260_CPU_SNOOP_WT                    0x00010000
+#define GT64260_CPU_SNOOP_WB                    0x00020000
+#define GT64260_CPU_SNOOP_MASK                  0x00030000
+#define GT64260_CPU_SNOOP_ALL_BITS              GT64260_CPU_SNOOP_MASK
+
+#define GT64260_CPU_SNOOP_BASE_0                0x0380
+#define GT64260_CPU_SNOOP_SIZE_0                0x0388
+#define GT64260_CPU_SNOOP_BASE_1                0x0390
+#define GT64260_CPU_SNOOP_SIZE_1                0x0398
+#define GT64260_CPU_SNOOP_BASE_2                0x03a0
+#define GT64260_CPU_SNOOP_SIZE_2                0x03a8
+#define GT64260_CPU_SNOOP_BASE_3                0x03b0
+#define GT64260_CPU_SNOOP_SIZE_3                0x03b8
+
+/* CPU Snoop Control Registers (64360 only) */
+#define MV64360_CPU_SNOOP_WINDOWS               4
+#define MV64360_CPU_SNOOP_NONE                  0x00000000
+#define MV64360_CPU_SNOOP_WT                    0x00010000
+#define MV64360_CPU_SNOOP_WB                    0x00020000
+#define MV64360_CPU_SNOOP_MASK                  0x00030000
+#define MV64360_CPU_SNOOP_ALL_BITS              MV64360_CPU_SNOOP_MASK
+
+
+/* CPU Error Report Registers */
+#define MV64x60_CPU_ERR_ADDR_LO                 0x0070
+#define MV64x60_CPU_ERR_ADDR_HI                 0x0078
+#define MV64x60_CPU_ERR_DATA_LO                 0x0128
+#define MV64x60_CPU_ERR_DATA_HI                 0x0130
+#define MV64x60_CPU_ERR_PARITY                  0x0138
+#define MV64x60_CPU_ERR_CAUSE                   0x0140
+#define MV64x60_CPU_ERR_MASK                    0x0148
+
+/*
+ *****************************************************************************
+ *
+ *      SRAM Cotnroller Registers
+ *
+ *****************************************************************************
+ */
+
+#define MV64360_SRAM_CONFIG                     0x0380
+#define MV64360_SRAM_TEST_MODE                  0x03f4
+#define MV64360_SRAM_ERR_CAUSE                  0x0388
+#define MV64360_SRAM_ERR_ADDR_LO                0x0390
+#define MV64360_SRAM_ERR_ADDR_HI                0x03f8
+#define MV64360_SRAM_ERR_DATA_LO                0x0398
+#define MV64360_SRAM_ERR_DATA_HI                0x03a0
+#define MV64360_SRAM_ERR_PARITY                 0x03a8
+
+#define MV64360_SRAM_SIZE                       0x00040000 /* 2Mb/256KB SRAM */
+
+/*
+ *****************************************************************************
+ *
+ *      SDRAM/MEM Cotnroller Registers
+ *
+ *****************************************************************************
+ */
+
+/* SDRAM Config Registers (64260) */
+#define GT64260_SDRAM_CONFIG                    0x0448
+
+/* SDRAM Error Report Registers (64260) */
+#define GT64260_SDRAM_ERR_DATA_LO               0x0484
+#define GT64260_SDRAM_ERR_DATA_HI               0x0480
+#define GT64260_SDRAM_ERR_ADDR                  0x0490
+#define GT64260_SDRAM_ERR_ECC_RCVD              0x0488
+#define GT64260_SDRAM_ERR_ECC_CALC              0x048c
+#define GT64260_SDRAM_ERR_ECC_CNTL              0x0494
+#define GT64260_SDRAM_ERR_ECC_ERR_CNT           0x0498
+
+/* SDRAM Config Registers (64360) */
+#define MV64360_SDRAM_CONFIG                    0x1400
+
+/* SDRAM Control Registers */
+#define MV64360_D_UNIT_CONTROL_LOW              0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH             0x1424
+
+/* SDRAM Error Report Registers (64360) */
+#define MV64360_SDRAM_ERR_DATA_LO               0x1444
+#define MV64360_SDRAM_ERR_DATA_HI               0x1440
+#define MV64360_SDRAM_ERR_ADDR                  0x1450
+#define MV64360_SDRAM_ERR_ECC_RCVD              0x1448
+#define MV64360_SDRAM_ERR_ECC_CALC              0x144c
+#define MV64360_SDRAM_ERR_ECC_CNTL              0x1454
+#define MV64360_SDRAM_ERR_ECC_ERR_CNT           0x1458
+
+/*
+ *****************************************************************************
+ *
+ *      Device/BOOT Cotnroller Registers
+ *
+ *****************************************************************************
+ */
+
+/* Device Control Registers */
+#define MV64x60_DEV_BANK_PARAMS_0               0x045c
+#define MV64x60_DEV_BANK_PARAMS_1               0x0460
+#define MV64x60_DEV_BANK_PARAMS_2               0x0464
+#define MV64x60_DEV_BANK_PARAMS_3               0x0468
+#define MV64x60_DEV_BOOT_PARAMS                 0x046c
+#define MV64x60_DEV_IF_CNTL                     0x04c0
+#define MV64x60_DEV_IF_XBAR_CNTL_LO             0x04c8
+#define MV64x60_DEV_IF_XBAR_CNTL_HI             0x04cc
+#define MV64x60_DEV_IF_XBAR_CNTL_TO             0x04c4
+
+/* Device Interrupt Registers */
+#define MV64x60_DEV_INTR_CAUSE                  0x04d0
+#define MV64x60_DEV_INTR_MASK                   0x04d4
+#define MV64x60_DEV_INTR_ERR_ADDR               0x04d8
+
+#define MV64360_DEV_INTR_ERR_DATA               0x04dc
+#define MV64360_DEV_INTR_ERR_PAR                0x04e0
+
+/*
+ *****************************************************************************
+ *
+ *      PCI Bridge Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* PCI Configuration Access Registers */
+#define MV64x60_PCI0_CONFIG_ADDR                0x0cf8
+#define MV64x60_PCI0_CONFIG_DATA                0x0cfc
+#define MV64x60_PCI0_IACK                       0x0c34
+
+#define MV64x60_PCI1_CONFIG_ADDR                0x0c78
+#define MV64x60_PCI1_CONFIG_DATA                0x0c7c
+#define MV64x60_PCI1_IACK                       0x0cb4
+
+/* PCI Control Registers */
+#define MV64x60_PCI0_CMD                        0x0c00
+#define MV64x60_PCI0_MODE                       0x0d00
+#define MV64x60_PCI0_TO_RETRY                   0x0c04
+#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER       0x0d04
+#define MV64x60_PCI0_MSI_TRIGGER_TIMER          0x0c38
+#define MV64x60_PCI0_ARBITER_CNTL               0x1d00
+#define MV64x60_PCI0_XBAR_CNTL_LO               0x1d08
+#define MV64x60_PCI0_XBAR_CNTL_HI               0x1d0c
+#define MV64x60_PCI0_XBAR_CNTL_TO               0x1d04
+#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO       0x1d18
+#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI       0x1d1c
+#define MV64x60_PCI0_SYNC_BARRIER               0x1d10
+#define MV64x60_PCI0_P2P_CONFIG                 0x1d14
+#define MV64x60_PCI0_INTR_MASK
+
+#define GT64260_PCI0_P2P_SWAP_CNTL              0x1d54
+
+#define MV64x60_PCI1_CMD                        0x0c80
+#define MV64x60_PCI1_MODE                       0x0d80
+#define MV64x60_PCI1_TO_RETRY                   0x0c84
+#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER       0x0d84
+#define MV64x60_PCI1_MSI_TRIGGER_TIMER          0x0cb8
+#define MV64x60_PCI1_ARBITER_CNTL               0x1d80
+#define MV64x60_PCI1_XBAR_CNTL_LO               0x1d88
+#define MV64x60_PCI1_XBAR_CNTL_HI               0x1d8c
+#define MV64x60_PCI1_XBAR_CNTL_TO               0x1d84
+#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO       0x1d98
+#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI       0x1d9c
+#define MV64x60_PCI1_SYNC_BARRIER               0x1d90
+#define MV64x60_PCI1_P2P_CONFIG                 0x1d94
+
+#define GT64260_PCI1_P2P_SWAP_CNTL              0x1dd4
+
+/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
+#define MV64x60_PCIMODE_CONVENTIONAL            0
+#define MV64x60_PCIMODE_PCIX_66                 (1 << 4)
+#define MV64x60_PCIMODE_PCIX_100                (2 << 4)
+#define MV64x60_PCIMODE_PCIX_133                (3 << 4)
+#define MV64x60_PCIMODE_MASK                    (0x3 << 4)
+
+/* PCI Access Control Regions Registers */
+#define GT64260_PCI_ACC_CNTL_PREFETCHEN         (1<<12)
+#define GT64260_PCI_ACC_CNTL_DREADEN            (1<<13)
+#define GT64260_PCI_ACC_CNTL_RDPREFETCH         (1<<16)
+#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH     (1<<17)
+#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH      (1<<18)
+#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES    0x00000000
+#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES    0x00100000
+#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES   0x00200000
+#define GT64260_PCI_ACC_CNTL_MBURST_MASK        0x00300000
+#define GT64260_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
+#define GT64260_PCI_ACC_CNTL_SWAP_NONE          0x01000000
+#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x02000000
+#define GT64260_PCI_ACC_CNTL_SWAP_WORD          0x03000000
+#define GT64260_PCI_ACC_CNTL_SWAP_MASK          0x03000000
+#define GT64260_PCI_ACC_CNTL_ACCPROT            (1<<28)
+#define GT64260_PCI_ACC_CNTL_WRPROT             (1<<29)
+
+#define GT64260_PCI_ACC_CNTL_ALL_BITS   (GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
+                                         GT64260_PCI_ACC_CNTL_DREADEN |       \
+                                         GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
+                                         GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
+                                         GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
+                                         GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
+                                         GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
+                                         GT64260_PCI_ACC_CNTL_ACCPROT|        \
+                                         GT64260_PCI_ACC_CNTL_WRPROT)
+
+#define MV64360_PCI_ACC_CNTL_ENABLE             (1<<0)
+#define MV64360_PCI_ACC_CNTL_REQ64              (1<<1)
+#define MV64360_PCI_ACC_CNTL_SNOOP_NONE         0x00000000
+#define MV64360_PCI_ACC_CNTL_SNOOP_WT           0x00000004
+#define MV64360_PCI_ACC_CNTL_SNOOP_WB           0x00000008
+#define MV64360_PCI_ACC_CNTL_SNOOP_MASK         0x0000000c
+#define MV64360_PCI_ACC_CNTL_ACCPROT            (1<<4)
+#define MV64360_PCI_ACC_CNTL_WRPROT             (1<<5)
+#define MV64360_PCI_ACC_CNTL_SWAP_BYTE          0x00000000
+#define MV64360_PCI_ACC_CNTL_SWAP_NONE          0x00000040
+#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD     0x00000080
+#define MV64360_PCI_ACC_CNTL_SWAP_WORD          0x000000c0
+#define MV64360_PCI_ACC_CNTL_SWAP_MASK          0x000000c0
+#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES    0x00000000
+#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES    0x00000100
+#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES   0x00000200
+#define MV64360_PCI_ACC_CNTL_MBURST_MASK        0x00000300
+#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES    0x00000000
+#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES    0x00000400
+#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES   0x00000800
+#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES   0x00000c00
+#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK        0x00000c00
+
+#define MV64360_PCI_ACC_CNTL_ALL_BITS   (MV64360_PCI_ACC_CNTL_ENABLE |      \
+                                         MV64360_PCI_ACC_CNTL_REQ64 |       \
+                                         MV64360_PCI_ACC_CNTL_SNOOP_MASK |  \
+                                         MV64360_PCI_ACC_CNTL_ACCPROT |     \
+                                         MV64360_PCI_ACC_CNTL_WRPROT |      \
+                                         MV64360_PCI_ACC_CNTL_SWAP_MASK |   \
+                                         MV64360_PCI_ACC_CNTL_MBURST_MASK | \
+                                         MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
+
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO         0x1e00
+#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI         0x1e04
+#define MV64x60_PCI0_ACC_CNTL_0_SIZE            0x1e08
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO         0x1e10
+#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI         0x1e14
+#define MV64x60_PCI0_ACC_CNTL_1_SIZE            0x1e18
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO         0x1e20
+#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI         0x1e24
+#define MV64x60_PCI0_ACC_CNTL_2_SIZE            0x1e28
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO         0x1e30
+#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI         0x1e34
+#define MV64x60_PCI0_ACC_CNTL_3_SIZE            0x1e38
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO         0x1e40
+#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI         0x1e44
+#define MV64x60_PCI0_ACC_CNTL_4_SIZE            0x1e48
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO         0x1e50
+#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI         0x1e54
+#define MV64x60_PCI0_ACC_CNTL_5_SIZE            0x1e58
+
+#define GT64260_PCI0_ACC_CNTL_6_BASE_LO         0x1e60
+#define GT64260_PCI0_ACC_CNTL_6_BASE_HI         0x1e64
+#define GT64260_PCI0_ACC_CNTL_6_SIZE            0x1e68
+#define GT64260_PCI0_ACC_CNTL_7_BASE_LO         0x1e70
+#define GT64260_PCI0_ACC_CNTL_7_BASE_HI         0x1e74
+#define GT64260_PCI0_ACC_CNTL_7_SIZE            0x1e78
+
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO         0x1e80
+#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI         0x1e84
+#define MV64x60_PCI1_ACC_CNTL_0_SIZE            0x1e88
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO         0x1e90
+#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI         0x1e94
+#define MV64x60_PCI1_ACC_CNTL_1_SIZE            0x1e98
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO         0x1ea0
+#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI         0x1ea4
+#define MV64x60_PCI1_ACC_CNTL_2_SIZE            0x1ea8
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO         0x1eb0
+#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI         0x1eb4
+#define MV64x60_PCI1_ACC_CNTL_3_SIZE            0x1eb8
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO         0x1ec0
+#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI         0x1ec4
+#define MV64x60_PCI1_ACC_CNTL_4_SIZE            0x1ec8
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO         0x1ed0
+#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI         0x1ed4
+#define MV64x60_PCI1_ACC_CNTL_5_SIZE            0x1ed8
+
+#define GT64260_PCI1_ACC_CNTL_6_BASE_LO         0x1ee0
+#define GT64260_PCI1_ACC_CNTL_6_BASE_HI         0x1ee4
+#define GT64260_PCI1_ACC_CNTL_6_SIZE            0x1ee8
+#define GT64260_PCI1_ACC_CNTL_7_BASE_LO         0x1ef0
+#define GT64260_PCI1_ACC_CNTL_7_BASE_HI         0x1ef4
+#define GT64260_PCI1_ACC_CNTL_7_SIZE            0x1ef8
+
+/* PCI Snoop Control Registers (64260 only) */
+#define GT64260_PCI_SNOOP_NONE                  0x00000000
+#define GT64260_PCI_SNOOP_WT                    0x00001000
+#define GT64260_PCI_SNOOP_WB                    0x00002000
+
+#define GT64260_PCI0_SNOOP_0_BASE_LO            0x1f00
+#define GT64260_PCI0_SNOOP_0_BASE_HI            0x1f04
+#define GT64260_PCI0_SNOOP_0_SIZE               0x1f08
+#define GT64260_PCI0_SNOOP_1_BASE_LO            0x1f10
+#define GT64260_PCI0_SNOOP_1_BASE_HI            0x1f14
+#define GT64260_PCI0_SNOOP_1_SIZE               0x1f18
+#define GT64260_PCI0_SNOOP_2_BASE_LO            0x1f20
+#define GT64260_PCI0_SNOOP_2_BASE_HI            0x1f24
+#define GT64260_PCI0_SNOOP_2_SIZE               0x1f28
+#define GT64260_PCI0_SNOOP_3_BASE_LO            0x1f30
+#define GT64260_PCI0_SNOOP_3_BASE_HI            0x1f34
+#define GT64260_PCI0_SNOOP_3_SIZE               0x1f38
+
+#define GT64260_PCI1_SNOOP_0_BASE_LO            0x1f80
+#define GT64260_PCI1_SNOOP_0_BASE_HI            0x1f84
+#define GT64260_PCI1_SNOOP_0_SIZE               0x1f88
+#define GT64260_PCI1_SNOOP_1_BASE_LO            0x1f90
+#define GT64260_PCI1_SNOOP_1_BASE_HI            0x1f94
+#define GT64260_PCI1_SNOOP_1_SIZE               0x1f98
+#define GT64260_PCI1_SNOOP_2_BASE_LO            0x1fa0
+#define GT64260_PCI1_SNOOP_2_BASE_HI            0x1fa4
+#define GT64260_PCI1_SNOOP_2_SIZE               0x1fa8
+#define GT64260_PCI1_SNOOP_3_BASE_LO            0x1fb0
+#define GT64260_PCI1_SNOOP_3_BASE_HI            0x1fb4
+#define GT64260_PCI1_SNOOP_3_SIZE               0x1fb8
+
+/* PCI Error Report Registers */
+#define MV64x60_PCI0_ERR_SERR_MASK              0x0c28
+#define MV64x60_PCI0_ERR_ADDR_LO                0x1d40
+#define MV64x60_PCI0_ERR_ADDR_HI                0x1d44
+#define MV64x60_PCI0_ERR_DATA_LO                0x1d48
+#define MV64x60_PCI0_ERR_DATA_HI                0x1d4c
+#define MV64x60_PCI0_ERR_CMD                    0x1d50
+#define MV64x60_PCI0_ERR_CAUSE                  0x1d58
+#define MV64x60_PCI0_ERR_MASK                   0x1d5c
+
+#define MV64x60_PCI1_ERR_SERR_MASK              0x0ca8
+#define MV64x60_PCI1_ERR_ADDR_LO                0x1dc0
+#define MV64x60_PCI1_ERR_ADDR_HI                0x1dc4
+#define MV64x60_PCI1_ERR_DATA_LO                0x1dc8
+#define MV64x60_PCI1_ERR_DATA_HI                0x1dcc
+#define MV64x60_PCI1_ERR_CMD                    0x1dd0
+#define MV64x60_PCI1_ERR_CAUSE                  0x1dd8
+#define MV64x60_PCI1_ERR_MASK                   0x1ddc
+
+/* PCI Slave Address Decoding Registers */
+#define MV64x60_PCI0_MEM_0_SIZE                 0x0c08
+#define MV64x60_PCI0_MEM_1_SIZE                 0x0d08
+#define MV64x60_PCI0_MEM_2_SIZE                 0x0c0c
+#define MV64x60_PCI0_MEM_3_SIZE                 0x0d0c
+#define MV64x60_PCI1_MEM_0_SIZE                 0x0c88
+#define MV64x60_PCI1_MEM_1_SIZE                 0x0d88
+#define MV64x60_PCI1_MEM_2_SIZE                 0x0c8c
+#define MV64x60_PCI1_MEM_3_SIZE                 0x0d8c
+
+#define MV64x60_PCI0_BAR_ENABLE                 0x0c3c
+#define MV64x60_PCI1_BAR_ENABLE                 0x0cbc
+
+#define MV64x60_PCI0_PCI_DECODE_CNTL            0x0d3c
+#define MV64x60_PCI1_PCI_DECODE_CNTL            0x0dbc
+
+#define MV64x60_PCI0_SLAVE_MEM_0_REMAP          0x0c48
+#define MV64x60_PCI0_SLAVE_MEM_1_REMAP          0x0d48
+#define MV64x60_PCI0_SLAVE_MEM_2_REMAP          0x0c4c
+#define MV64x60_PCI0_SLAVE_MEM_3_REMAP          0x0d4c
+#define MV64x60_PCI0_SLAVE_DEV_0_REMAP          0x0c50
+#define MV64x60_PCI0_SLAVE_DEV_1_REMAP          0x0d50
+#define MV64x60_PCI0_SLAVE_DEV_2_REMAP          0x0d58
+#define MV64x60_PCI0_SLAVE_DEV_3_REMAP          0x0c54
+#define MV64x60_PCI0_SLAVE_BOOT_REMAP           0x0d54
+#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO   0x0d5c
+#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI   0x0d60
+#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO   0x0d64
+#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI   0x0d68
+#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP         0x0d6c
+#define MV64x60_PCI0_SLAVE_CPU_REMAP            0x0d70
+
+#define MV64x60_PCI1_SLAVE_MEM_0_REMAP          0x0cc8
+#define MV64x60_PCI1_SLAVE_MEM_1_REMAP          0x0dc8
+#define MV64x60_PCI1_SLAVE_MEM_2_REMAP          0x0ccc
+#define MV64x60_PCI1_SLAVE_MEM_3_REMAP          0x0dcc
+#define MV64x60_PCI1_SLAVE_DEV_0_REMAP          0x0cd0
+#define MV64x60_PCI1_SLAVE_DEV_1_REMAP          0x0dd0
+#define MV64x60_PCI1_SLAVE_DEV_2_REMAP          0x0dd8
+#define MV64x60_PCI1_SLAVE_DEV_3_REMAP          0x0cd4
+#define MV64x60_PCI1_SLAVE_BOOT_REMAP           0x0dd4
+#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO   0x0ddc
+#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI   0x0de0
+#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO   0x0de4
+#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI   0x0de8
+#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP         0x0dec
+#define MV64x60_PCI1_SLAVE_CPU_REMAP            0x0df0
+
+/*
+ *****************************************************************************
+ *
+ *      ENET Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* ENET Controller Window Registers (6 windows) */
+#define MV64360_ENET2MEM_WINDOWS                6
+
+#define MV64360_ENET2MEM_0_BASE                 0x2200
+#define MV64360_ENET2MEM_0_SIZE                 0x2204
+#define MV64360_ENET2MEM_1_BASE                 0x2208
+#define MV64360_ENET2MEM_1_SIZE                 0x220c
+#define MV64360_ENET2MEM_2_BASE                 0x2210
+#define MV64360_ENET2MEM_2_SIZE                 0x2214
+#define MV64360_ENET2MEM_3_BASE                 0x2218
+#define MV64360_ENET2MEM_3_SIZE                 0x221c
+#define MV64360_ENET2MEM_4_BASE                 0x2220
+#define MV64360_ENET2MEM_4_SIZE                 0x2224
+#define MV64360_ENET2MEM_5_BASE                 0x2228
+#define MV64360_ENET2MEM_5_SIZE                 0x222c
+
+#define MV64360_ENET2MEM_SNOOP_NONE             0x00000000
+#define MV64360_ENET2MEM_SNOOP_WT               0x00001000
+#define MV64360_ENET2MEM_SNOOP_WB               0x00002000
+
+#define MV64360_ENET2MEM_BAR_ENABLE             0x2290
+
+#define MV64360_ENET2MEM_ACC_PROT_0             0x2294
+#define MV64360_ENET2MEM_ACC_PROT_1             0x2298
+#define MV64360_ENET2MEM_ACC_PROT_2             0x229c
+
+/*
+ *****************************************************************************
+ *
+ *      MPSC Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* MPSC Controller Window Registers (4 windows) */
+#define MV64360_MPSC2MEM_WINDOWS                4
+
+#define MV64360_MPSC2MEM_0_BASE                 0xf200
+#define MV64360_MPSC2MEM_0_SIZE                 0xf204
+#define MV64360_MPSC2MEM_1_BASE                 0xf208
+#define MV64360_MPSC2MEM_1_SIZE                 0xf20c
+#define MV64360_MPSC2MEM_2_BASE                 0xf210
+#define MV64360_MPSC2MEM_2_SIZE                 0xf214
+#define MV64360_MPSC2MEM_3_BASE                 0xf218
+#define MV64360_MPSC2MEM_3_SIZE                 0xf21c
+
+#define MV64360_MPSC_0_REMAP                    0xf240
+#define MV64360_MPSC_1_REMAP                    0xf244
+
+#define MV64360_MPSC2MEM_SNOOP_NONE             0x00000000
+#define MV64360_MPSC2MEM_SNOOP_WT               0x00001000
+#define MV64360_MPSC2MEM_SNOOP_WB               0x00002000
+
+#define MV64360_MPSC2MEM_BAR_ENABLE             0xf250
+
+#define MV64360_MPSC2MEM_ACC_PROT_0             0xf254
+#define MV64360_MPSC2MEM_ACC_PROT_1             0xf258
+
+#define MV64360_MPSC2REGS_BASE                  0xf25c
+
+/*
+ *****************************************************************************
+ *
+ *      Timer/Counter Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define MV64x60_TIMR_CNTR_0                     0x0850
+#define MV64x60_TIMR_CNTR_1                     0x0854
+#define MV64x60_TIMR_CNTR_2                     0x0858
+#define MV64x60_TIMR_CNTR_3                     0x085c
+#define MV64x60_TIMR_CNTR_0_3_CNTL              0x0864
+#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE        0x0868
+#define MV64x60_TIMR_CNTR_0_3_INTR_MASK         0x086c
+
+#define GT64260_TIMR_CNTR_4                     0x0950
+#define GT64260_TIMR_CNTR_5                     0x0954
+#define GT64260_TIMR_CNTR_6                     0x0958
+#define GT64260_TIMR_CNTR_7                     0x095c
+#define GT64260_TIMR_CNTR_4_7_CNTL              0x0964
+#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE        0x0968
+#define GT64260_TIMR_CNTR_4_7_INTR_MASK         0x096c
+
+/*
+ *****************************************************************************
+ *
+ *      Communications Controller
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_SER_INIT_PCI_ADDR_HI            0xf320
+#define GT64260_SER_INIT_LAST_DATA              0xf324
+#define GT64260_SER_INIT_CONTROL                0xf328
+#define GT64260_SER_INIT_STATUS                 0xf32c
+
+#define MV64x60_COMM_ARBITER_CNTL               0xf300
+#define MV64x60_COMM_CONFIG                     0xb40c
+#define MV64x60_COMM_XBAR_TO                    0xf304
+#define MV64x60_COMM_INTR_CAUSE                 0xf310
+#define MV64x60_COMM_INTR_MASK                  0xf314
+#define MV64x60_COMM_ERR_ADDR                   0xf318
+
+#define MV64360_COMM_ARBITER_CNTL               0xf300
+
+/*
+ *****************************************************************************
+ *
+ *      IDMA Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* IDMA Controller Window Registers (8 windows) */
+#define MV64360_IDMA2MEM_WINDOWS                8
+
+#define MV64360_IDMA2MEM_0_BASE                 0x0a00
+#define MV64360_IDMA2MEM_0_SIZE                 0x0a04
+#define MV64360_IDMA2MEM_1_BASE                 0x0a08
+#define MV64360_IDMA2MEM_1_SIZE                 0x0a0c
+#define MV64360_IDMA2MEM_2_BASE                 0x0a10
+#define MV64360_IDMA2MEM_2_SIZE                 0x0a14
+#define MV64360_IDMA2MEM_3_BASE                 0x0a18
+#define MV64360_IDMA2MEM_3_SIZE                 0x0a1c
+#define MV64360_IDMA2MEM_4_BASE                 0x0a20
+#define MV64360_IDMA2MEM_4_SIZE                 0x0a24
+#define MV64360_IDMA2MEM_5_BASE                 0x0a28
+#define MV64360_IDMA2MEM_5_SIZE                 0x0a2c
+#define MV64360_IDMA2MEM_6_BASE                 0x0a30
+#define MV64360_IDMA2MEM_6_SIZE                 0x0a34
+#define MV64360_IDMA2MEM_7_BASE                 0x0a38
+#define MV64360_IDMA2MEM_7_SIZE                 0x0a3c
+
+#define MV64360_IDMA2MEM_SNOOP_NONE             0x00000000
+#define MV64360_IDMA2MEM_SNOOP_WT               0x00001000
+#define MV64360_IDMA2MEM_SNOOP_WB               0x00002000
+
+#define MV64360_IDMA2MEM_BAR_ENABLE             0x0a80
+
+#define MV64360_IDMA2MEM_ACC_PROT_0             0x0a70
+#define MV64360_IDMA2MEM_ACC_PROT_1             0x0a74
+#define MV64360_IDMA2MEM_ACC_PROT_2             0x0a78
+#define MV64360_IDMA2MEM_ACC_PROT_3             0x0a7c
+
+#define MV64x60_IDMA_0_OFFSET                   0x0800
+#define MV64x60_IDMA_1_OFFSET                   0x0804
+#define MV64x60_IDMA_2_OFFSET                   0x0808
+#define MV64x60_IDMA_3_OFFSET                   0x080c
+#define MV64x60_IDMA_4_OFFSET                   0x0900
+#define MV64x60_IDMA_5_OFFSET                   0x0904
+#define MV64x60_IDMA_6_OFFSET                   0x0908
+#define MV64x60_IDMA_7_OFFSET                   0x090c
+
+#define MV64x60_IDMA_BYTE_COUNT                 (0x0800 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_SRC_ADDR                   (0x0810 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_DST_ADDR                   (0x0820 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_NEXT_DESC                  (0x0830 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_CUR_DESC                   (0x0870 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_SRC_PCI_ADDR_HI            (0x0890 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_DST_PCI_ADDR_HI            (0x08a0 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI      (0x08b0 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_CONTROL_LO                 (0x0840 - MV64x60_IDMA_0_OFFSET)
+#define MV64x60_IDMA_CONTROL_HI                 (0x0880 - MV64x60_IDMA_0_OFFSET)
+
+#define MV64x60_IDMA_0_3_ARBITER_CNTL           0x0860
+#define MV64x60_IDMA_4_7_ARBITER_CNTL           0x0960
+
+#define MV64x60_IDMA_0_3_XBAR_TO                0x08d0
+#define MV64x60_IDMA_4_7_XBAR_TO                0x09d0
+
+#define MV64x60_IDMA_0_3_INTR_CAUSE             0x08c0
+#define MV64x60_IDMA_0_3_INTR_MASK              0x08c4
+#define MV64x60_IDMA_0_3_ERROR_ADDR             0x08c8
+#define MV64x60_IDMA_0_3_ERROR_SELECT           0x08cc
+#define MV64x60_IDMA_4_7_INTR_CAUSE             0x09c0
+#define MV64x60_IDMA_4_7_INTR_MASK              0x09c4
+#define MV64x60_IDMA_4_7_ERROR_ADDR             0x09c8
+#define MV64x60_IDMA_4_7_ERROR_SELECT           0x09cc
+
+/*
+ *****************************************************************************
+ *
+ *      Watchdog Timer Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define MV64x60_WDT_WDC                         0xb410
+#define MV64x60_WDT_WDV                         0xb414
+
+
+/*
+ *****************************************************************************
+ *
+ *       General Purpose Pins Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define MV64x60_GPP_IO_CNTL                     0xf100
+#define MV64x60_GPP_LEVEL_CNTL                  0xf110
+#define MV64x60_GPP_VALUE                       0xf104
+#define MV64x60_GPP_INTR_CAUSE                  0xf108
+#define MV64x60_GPP_INTR_MASK                   0xf10c
+#define MV64x60_GPP_VALUE_SET                   0xf118
+#define MV64x60_GPP_VALUE_CLR                   0xf11c
+
+
+/*
+ *****************************************************************************
+ *
+ *      Multi-Purpose Pins Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define MV64x60_MPP_CNTL_0                      0xf000
+#define MV64x60_MPP_CNTL_1                      0xf004
+#define MV64x60_MPP_CNTL_2                      0xf008
+#define MV64x60_MPP_CNTL_3                      0xf00c
+#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX      0xf010
+
+#define MV64x60_ETH_BAR_GAP                     0x8
+#define MV64x60_ETH_SIZE_REG_GAP                0x8
+#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP     0x4
+#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP        0x4
+
+#define MV64x60_EBAR_ATTR_DRAM_CS0              0x00000E00
+#define MV64x60_EBAR_ATTR_DRAM_CS1              0x00000D00
+#define MV64x60_EBAR_ATTR_DRAM_CS2              0x00000B00
+#define MV64x60_EBAR_ATTR_DRAM_CS3              0x00000700
+
+#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0       0x00000000
+#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1       0x00000100
+#define MV64x60_EBAR_ATTR_CBS_SRAM              0x00000000
+#define MV64x60_EBAR_ATTR_CBS_CPU_BUS           0x00000800
+
+
+/*
+ *****************************************************************************
+ *
+ *      Interrupt Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define GT64260_IC_OFFSET                       0x0c18
+
+#define GT64260_IC_MAIN_CAUSE_LO                0x0c18
+#define GT64260_IC_MAIN_CAUSE_HI                0x0c68
+#define GT64260_IC_CPU_INTR_MASK_LO             0x0c1c
+#define GT64260_IC_CPU_INTR_MASK_HI             0x0c6c
+#define GT64260_IC_CPU_SELECT_CAUSE             0x0c70
+#define GT64260_IC_PCI0_INTR_MASK_LO            0x0c24
+#define GT64260_IC_PCI0_INTR_MASK_HI            0x0c64
+#define GT64260_IC_PCI0_SELECT_CAUSE            0x0c74
+#define GT64260_IC_PCI1_INTR_MASK_LO            0x0ca4
+#define GT64260_IC_PCI1_INTR_MASK_HI            0x0ce4
+#define GT64260_IC_PCI1_SELECT_CAUSE            0x0cf4
+#define GT64260_IC_CPU_INT_0_MASK               0x0e60
+#define GT64260_IC_CPU_INT_1_MASK               0x0e64
+#define GT64260_IC_CPU_INT_2_MASK               0x0e68
+#define GT64260_IC_CPU_INT_3_MASK               0x0e6c
+
+#define MV64360_IC_OFFSET                       0x0000
+
+#define MV64360_IC_MAIN_CAUSE_LO                0x0004
+#define MV64360_IC_MAIN_CAUSE_HI                0x000c
+#define MV64360_IC_CPU0_INTR_MASK_LO            0x0014
+#define MV64360_IC_CPU0_INTR_MASK_HI            0x001c
+#define MV64360_IC_CPU0_SELECT_CAUSE            0x0024
+#define MV64360_IC_CPU1_INTR_MASK_LO            0x0034
+#define MV64360_IC_CPU1_INTR_MASK_HI            0x003c
+#define MV64360_IC_CPU1_SELECT_CAUSE            0x0044
+#define MV64360_IC_INT0_MASK_LO                 0x0054
+#define MV64360_IC_INT0_MASK_HI                 0x005c
+#define MV64360_IC_INT0_SELECT_CAUSE            0x0064
+#define MV64360_IC_INT1_MASK_LO                 0x0074
+#define MV64360_IC_INT1_MASK_HI                 0x007c
+#define MV64360_IC_INT1_SELECT_CAUSE            0x0084
+
+#endif /* __ASMPPC_MV64x60_DEFS_H */
diff --git a/include/asm-ppc/namei.h b/include/asm-ppc/namei.h
new file mode 100644
index 000000000000..29c9ec832133
--- /dev/null
+++ b/include/asm-ppc/namei.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-ppc/namei.h
+ * Adapted from include/asm-alpha/namei.h
+ *
+ * Included from fs/namei.c
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_NAMEI_H
+#define __PPC_NAMEI_H
+
+/* This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ * Look at asm-sparc/namei.h for details.
+ */
+
+#define __emul_prefix() NULL
+
+#endif /* __PPC_NAMEI_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/nvram.h b/include/asm-ppc/nvram.h
new file mode 100644
index 000000000000..31ef16e3fc4f
--- /dev/null
+++ b/include/asm-ppc/nvram.h
@@ -0,0 +1,73 @@
+/*
+ * PreP compliant NVRAM access
+ */
+
+#ifdef __KERNEL__
+#ifndef _PPC_NVRAM_H
+#define _PPC_NVRAM_H
+
+#define NVRAM_AS0  0x74
+#define NVRAM_AS1  0x75
+#define NVRAM_DATA 0x77
+
+
+/* RTC Offsets */
+
+#define MOTO_RTC_SECONDS                0x1FF9
+#define MOTO_RTC_MINUTES                0x1FFA
+#define MOTO_RTC_HOURS          0x1FFB
+#define MOTO_RTC_DAY_OF_WEEK            0x1FFC
+#define MOTO_RTC_DAY_OF_MONTH   0x1FFD
+#define MOTO_RTC_MONTH          0x1FFE
+#define MOTO_RTC_YEAR           0x1FFF
+#define MOTO_RTC_CONTROLA            0x1FF8
+#define MOTO_RTC_CONTROLB            0x1FF9
+
+/* PowerMac specific nvram stuffs */
+
+enum {
+        pmac_nvram_OF,          /* Open Firmware partition */
+        pmac_nvram_XPRAM,       /* MacOS XPRAM partition */
+        pmac_nvram_NR           /* MacOS Name Registry partition */
+};
+
+/* Return partition offset in nvram */
+extern int      pmac_get_partition(int partition);
+
+/* Direct access to XPRAM on PowerMacs */
+extern u8       pmac_xpram_read(int xpaddr);
+extern void     pmac_xpram_write(int xpaddr, u8 data);
+
+/* Synchronize NVRAM */
+extern void     nvram_sync(void);
+
+/* Normal access to NVRAM */
+extern unsigned char nvram_read_byte(int i);
+extern void nvram_write_byte(unsigned char c, int i);
+
+/* Some offsets in XPRAM */
+#define PMAC_XPRAM_MACHINE_LOC  0xe4
+#define PMAC_XPRAM_SOUND_VOLUME 0x08
+
+/* Machine location structure in PowerMac XPRAM */
+struct pmac_machine_location {
+        unsigned int    latitude;       /* 2+30 bit Fractional number */
+        unsigned int    longitude;      /* 2+30 bit Fractional number */
+        unsigned int    delta;          /* mix of GMT delta and DLS */
+};
+
+/*
+ * /dev/nvram ioctls
+ *
+ * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
+ * definitely obsolete. Do not use it if you can avoid it
+ */
+
+#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
+                                _IOWR('p', 0x40, int)
+
+#define IOC_NVRAM_GET_OFFSET    _IOWR('p', 0x42, int)   /* Get NVRAM partition offset */
+#define IOC_NVRAM_SYNC          _IO('p', 0x43)          /* Sync NVRAM image */
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
new file mode 100644
index 000000000000..5ea44cabfaa4
--- /dev/null
+++ b/include/asm-ppc/ocp.h
@@ -0,0 +1,211 @@
+/*
+ * ocp.h
+ *
+ *      (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *          Mipsys - France
+ *
+ *          Derived from work (c) Armin Kuster akuster@pacbell.net
+ *
+ *          Additional support and port to 2.6 LDM/sysfs by
+ *          Matt Porter <mporter@kernel.crashing.org>
+ *          Copyright 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *  TODO: - Add get/put interface & fixup locking to provide same API for
+ *          2.4 and 2.5
+ *        - Rework PM callbacks
+ */
+
+#ifdef __KERNEL__
+#ifndef __OCP_H__
+#define __OCP_H__
+
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/config.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/device.h>
+
+#include <asm/mmu.h>
+#include <asm/ocp_ids.h>
+#include <asm/rwsem.h>
+#include <asm/semaphore.h>
+
+#ifdef CONFIG_PPC_OCP
+
+#define OCP_MAX_IRQS    7
+#define MAX_EMACS       4
+#define OCP_IRQ_NA      -1      /* used when ocp device does not have an irq */
+#define OCP_IRQ_MUL     -2      /* used for ocp devices with multiply irqs */
+#define OCP_NULL_TYPE   -1      /* used to mark end of list */
+#define OCP_CPM_NA      0       /* No Clock or Power Management avaliable */
+#define OCP_PADDR_NA    0       /* No MMIO registers */
+
+#define OCP_ANY_ID      (~0)
+#define OCP_ANY_INDEX   -1
+
+extern struct list_head         ocp_devices;
+extern struct rw_semaphore      ocp_devices_sem;
+
+struct ocp_device_id {
+        unsigned int    vendor, function;       /* Vendor and function ID or OCP_ANY_ID */
+        unsigned long   driver_data;            /* Data private to the driver */
+};
+
+
+/*
+ * Static definition of an OCP device.
+ *
+ * @vendor:    Vendor code. It is _STRONGLY_ discouraged to use
+ *             the vendor code as a way to match a unique device,
+ *             though I kept that possibility open, you should
+ *             really define different function codes for different
+ *             device types
+ * @function:  This is the function code for this device.
+ * @index:     This index is used for mapping the Nth function of a
+ *             given core. This is typically used for cross-driver
+ *             matching, like looking for a given MAL or ZMII from
+ *             an EMAC or for getting to the proper set of DCRs.
+ *             Indices are no longer magically calculated based on
+ *             structure ordering, they have to be actually coded
+ *             into the ocp_def to avoid any possible confusion
+ *             I _STRONGLY_ (again ? wow !) encourage anybody relying
+ *             on index mapping to encode the "target" index in an
+ *             associated structure pointed to by "additions", see
+ *             how it's done for the EMAC driver.
+ * @paddr:     Device physical address (may not mean anything...)
+ * @irq:       Interrupt line for this device (TODO: think about making
+ *             an array with this)
+ * @pm:        Currently, contains the bitmask in CPMFR DCR for the device
+ * @additions: Optionally points to a function specific structure
+ *             providing additional informations for a given device
+ *             instance. It's currently used by the EMAC driver for MAL
+ *             channel & ZMII port mapping among others.
+ * @show:      Optionally points to a function specific structure
+ *             providing a sysfs show routine for additions fields.
+ */
+struct ocp_def {
+        unsigned int    vendor;
+        unsigned int    function;
+        int             index;
+        phys_addr_t     paddr;
+        int             irq;
+        unsigned long   pm;
+        void            *additions;
+        void            (*show)(struct device *);
+};
+
+
+/* Struct for a given device instance */
+struct ocp_device {
+        struct list_head        link;
+        char                    name[80];       /* device name */
+        struct ocp_def          *def;           /* device definition */
+        void                    *drvdata;       /* driver data for this device */
+        struct ocp_driver       *driver;
+        u32                     current_state;  /* Current operating state. In ACPI-speak,
+                                                   this is D0-D3, D0 being fully functional,
+                                                   and D3 being off. */
+        struct                  device dev;
+};
+
+struct ocp_driver {
+        struct list_head node;
+        char *name;
+        const struct ocp_device_id *id_table;   /* NULL if wants all devices */
+        int  (*probe)  (struct ocp_device *dev);        /* New device inserted */
+        void (*remove) (struct ocp_device *dev);        /* Device removed (NULL if not a hot-plug capable driver) */
+        int  (*suspend) (struct ocp_device *dev, u32 state);    /* Device suspended */
+        int  (*resume) (struct ocp_device *dev);                        /* Device woken up */
+        struct device_driver driver;
+};
+
+#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
+#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
+
+/* Similar to the helpers above, these manipulate per-ocp_dev
+ * driver-specific data.  Currently stored as ocp_dev::ocpdev,
+ * a void pointer, but it is not present on older kernels.
+ */
+static inline void *
+ocp_get_drvdata(struct ocp_device *pdev)
+{
+        return pdev->drvdata;
+}
+
+static inline void
+ocp_set_drvdata(struct ocp_device *pdev, void *data)
+{
+        pdev->drvdata = data;
+}
+
+#if defined (CONFIG_PM)
+/*
+ * This is right for the IBM 405 and 440 but will need to be
+ * generalized if the OCP stuff gets used on other processors.
+ */
+static inline void
+ocp_force_power_off(struct ocp_device *odev)
+{
+        mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
+}
+
+static inline void
+ocp_force_power_on(struct ocp_device *odev)
+{
+        mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
+}
+#else
+#define ocp_force_power_off(x)  (void)(x)
+#define ocp_force_power_on(x)   (void)(x)
+#endif
+
+/* Register/Unregister an OCP driver */
+extern int ocp_register_driver(struct ocp_driver *drv);
+extern void ocp_unregister_driver(struct ocp_driver *drv);
+
+/* Build list of devices */
+extern int ocp_early_init(void) __init;
+
+/* Find a device by index */
+extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
+
+/* Get a def by index */
+extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Add a device by index */
+extern int ocp_add_one_device(struct ocp_def *def);
+
+/* Remove a device by index */
+extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
+
+/* Iterate over devices and execute a routine */
+extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
+
+/* Sysfs support */
+#define OCP_SYSFS_ADDTL(type, format, name, field)                      \
+static ssize_t                                                          \
+show_##name##_##field(struct device *dev, char *buf)                    \
+{                                                                       \
+        struct ocp_device *odev = to_ocp_dev(dev);                      \
+        type *add = odev->def->additions;                               \
+                                                                        \
+        return sprintf(buf, format, add->field);                        \
+}                                                                       \
+static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
+
+#ifdef CONFIG_IBM_OCP
+#include <asm/ibm_ocp.h>
+#endif
+
+#ifdef CONFIG_FSL_OCP
+#include <asm/fsl_ocp.h>
+#endif
+
+#endif                          /* CONFIG_PPC_OCP */
+#endif                          /* __OCP_H__ */
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
new file mode 100644
index 000000000000..8ae4b311a37c
--- /dev/null
+++ b/include/asm-ppc/ocp_ids.h
@@ -0,0 +1,73 @@
+/*
+ * ocp_ids.h
+ *
+ * OCP device ids based on the ideas from PCI
+ *
+ * The numbers below are almost completely arbitrary, and in fact
+ * strings might work better.  -- paulus
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * Vender  device
+ * [xxxx]  [xxxx]
+ *
+ *  Keep in order, please
+ */
+
+/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
+
+#define OCP_VENDOR_INVALID      0x0000
+#define OCP_VENDOR_ARM          0x0004
+#define OCP_VENDOR_FREESCALE    0x1057
+#define OCP_VENDOR_IBM          0x1014
+#define OCP_VENDOR_MOTOROLA     OCP_VENDOR_FREESCALE
+#define OCP_VENDOR_XILINX       0x10ee
+#define OCP_VENDOR_UNKNOWN      0xFFFF
+
+/* device identification */
+
+/* define type */
+#define OCP_FUNC_INVALID        0x0000
+
+/* system 0x0001 - 0x001F */
+
+/* Timers 0x0020 - 0x002F */
+
+/* Serial 0x0030 - 0x006F*/
+#define OCP_FUNC_16550          0x0031
+#define OCP_FUNC_IIC            0x0032
+#define OCP_FUNC_USB            0x0033
+#define OCP_FUNC_PSC_UART       0x0034
+
+/* Memory devices 0x0090 - 0x009F */
+#define OCP_FUNC_MAL            0x0090
+#define OCP_FUNC_DMA            0x0091
+
+/* Display 0x00A0 - 0x00AF */
+
+/* Sound 0x00B0 - 0x00BF */
+
+/* Mass Storage 0x00C0 - 0xxCF */
+#define OCP_FUNC_IDE            0x00C0
+
+/* Misc 0x00D0 - 0x00DF*/
+#define OCP_FUNC_GPIO           0x00D0
+#define OCP_FUNC_ZMII           0x00D1
+#define OCP_FUNC_PERFMON        0x00D2  /* Performance Monitor */
+#define OCP_FUNC_RGMII          0x00D3
+#define OCP_FUNC_TAH            0x00D4
+#define OCP_FUNC_SEC2           0x00D5  /* Crypto/Security 2.0 */
+
+/* Network 0x0200 - 0x02FF */
+#define OCP_FUNC_EMAC           0x0200
+#define OCP_FUNC_GFAR           0x0201  /* TSEC & FEC */
+
+/* Bridge devices 0xE00 - 0xEFF */
+#define OCP_FUNC_OPB            0x0E00
+
+#define OCP_FUNC_UNKNOWN        0xFFFF
diff --git a/include/asm-ppc/of_device.h b/include/asm-ppc/of_device.h
new file mode 100644
index 000000000000..14441c629010
--- /dev/null
+++ b/include/asm-ppc/of_device.h
@@ -0,0 +1,74 @@
+#ifndef __OF_DEVICE_H__
+#define __OF_DEVICE_H__
+
+#include <linux/device.h>
+#include <asm/prom.h>
+
+/*
+ * The of_platform_bus_type is a bus type used by drivers that do not
+ * attach to a macio or similar bus but still use OF probing
+ * mecanism
+ */
+extern struct bus_type of_platform_bus_type;
+
+/*
+ * The of_device is a kind of "base class" that is a superset of
+ * struct device for use by devices attached to an OF node and
+ * probed using OF properties
+ */
+struct of_device
+{
+        struct device_node      *node;          /* OF device node */
+        u64                     dma_mask;       /* DMA mask */
+        struct device           dev;            /* Generic device interface */
+};
+#define to_of_device(d) container_of(d, struct of_device, dev)
+
+/*
+ * Struct used for matching a device
+ */
+struct of_match
+{
+        char    *name;
+        char    *type;
+        char    *compatible;
+        void    *data;
+};
+#define OF_ANY_MATCH            ((char *)-1L)
+
+extern const struct of_match *of_match_device(
+        const struct of_match *matches, const struct of_device *dev);
+
+extern struct of_device *of_dev_get(struct of_device *dev);
+extern void of_dev_put(struct of_device *dev);
+
+/*
+ * An of_platform_driver driver is attached to a basic of_device on
+ * the "platform bus" (of_platform_bus_type)
+ */
+struct of_platform_driver
+{
+        char                    *name;
+        struct of_match         *match_table;
+        struct module           *owner;
+
+        int     (*probe)(struct of_device* dev, const struct of_match *match);
+        int     (*remove)(struct of_device* dev);
+
+        int     (*suspend)(struct of_device* dev, u32 state);
+        int     (*resume)(struct of_device* dev);
+        int     (*shutdown)(struct of_device* dev);
+
+        struct device_driver    driver;
+};
+#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
+
+extern int of_register_driver(struct of_platform_driver *drv);
+extern void of_unregister_driver(struct of_platform_driver *drv);
+extern int of_device_register(struct of_device *ofdev);
+extern void of_device_unregister(struct of_device *ofdev);
+extern struct of_device *of_platform_device_create(struct device_node *np, const char *bus_id);
+extern void of_release_dev(struct device *dev);
+
+#endif /* __OF_DEVICE_H__ */
+
diff --git a/include/asm-ppc/ohare.h b/include/asm-ppc/ohare.h
new file mode 100644
index 000000000000..023b59772231
--- /dev/null
+++ b/include/asm-ppc/ohare.h
@@ -0,0 +1,48 @@
+/*
+ * ohare.h: definitions for using the "O'Hare" I/O controller chip.
+ *
+ * Copyright (C) 1997 Paul Mackerras.
+ *
+ * BenH: Changed to match those of heathrow (but not all of them). Please
+ *       check if I didn't break anything (especially the media bay).
+ */
+
+/* offset from ohare base for feature control register */
+#define OHARE_MBCR      0x34
+#define OHARE_FCR       0x38
+
+/*
+ * Bits in feature control register.
+ * These were mostly derived by experiment on a powerbook 3400
+ * and may differ for other machines.
+ */
+#define OH_SCC_RESET            1
+#define OH_BAY_POWER_N          2       /* a guess */
+#define OH_BAY_PCI_ENABLE       4       /* a guess */
+#define OH_BAY_IDE_ENABLE       8
+#define OH_BAY_FLOPPY_ENABLE    0x10
+#define OH_IDE0_ENABLE          0x20
+#define OH_IDE0_RESET_N         0x40    /* a guess */
+#define OH_BAY_DEV_MASK         0x1c
+#define OH_BAY_RESET_N          0x80
+#define OH_IOBUS_ENABLE         0x100   /* IOBUS seems to be IDE */
+#define OH_SCC_ENABLE           0x200
+#define OH_MESH_ENABLE          0x400
+#define OH_FLOPPY_ENABLE        0x800
+#define OH_SCCA_IO              0x4000
+#define OH_SCCB_IO              0x8000
+#define OH_VIA_ENABLE           0x10000 /* Is apparently wrong, to be verified */
+#define OH_IDE1_RESET_N         0x800000
+
+/*
+ * Bits to set in the feature control register on PowerBooks.
+ */
+#define PBOOK_FEATURES          (OH_IDE_ENABLE | OH_SCC_ENABLE | \
+                                 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
+
+/*
+ * A magic value to put into the feature control register of the
+ * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
+ * Contributed by Harry Eaton.
+ */
+#define STARMAX_FEATURES        0xbeff7a
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
new file mode 100644
index 000000000000..58545e4cdbc0
--- /dev/null
+++ b/include/asm-ppc/open_pic.h
@@ -0,0 +1,93 @@
+/*
+ *  include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
+ *
+ *  Copyright (C) 1997 Geert Uytterhoeven
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License.  See the file COPYING in the main directory of this archive
+ *  for more details.
+ *
+ */
+
+#ifndef _PPC_KERNEL_OPEN_PIC_H
+#define _PPC_KERNEL_OPEN_PIC_H
+
+#include <linux/config.h>
+#include <linux/irq.h>
+
+#define OPENPIC_SIZE    0x40000
+
+/*
+ *  Non-offset'ed vector numbers
+ */
+
+#define OPENPIC_VEC_TIMER       110     /* and up */
+#define OPENPIC_VEC_IPI         118     /* and up */
+#define OPENPIC_VEC_SPURIOUS    255
+
+/* OpenPIC IRQ controller structure */
+extern struct hw_interrupt_type open_pic;
+
+/* OpenPIC IPI controller structure */
+#ifdef CONFIG_SMP
+extern struct hw_interrupt_type open_pic_ipi;
+#endif /* CONFIG_SMP */
+
+extern u_int OpenPIC_NumInitSenses;
+extern u_char *OpenPIC_InitSenses;
+extern void __iomem * OpenPIC_Addr;
+extern int epic_serial_mode;
+
+/* Exported functions */
+extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr);
+extern void openpic_init(int linux_irq_offset);
+extern void openpic_init_nmi_irq(u_int irq);
+extern void openpic_hookup_cascade(u_int irq, char *name,
+                                   int (*cascade_fn)(struct pt_regs *));
+extern u_int openpic_irq(void);
+extern void openpic_eoi(void);
+extern void openpic_request_IPIs(void);
+extern void do_openpic_setup_cpu(void);
+extern int openpic_get_irq(struct pt_regs *regs);
+extern void openpic_reset_processor_phys(u_int cpumask);
+extern void openpic_setup_ISU(int isu_num, unsigned long addr);
+extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
+extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
+                                     int wait);
+extern void openpic_set_k2_cascade(int irq);
+extern void openpic_set_priority(u_int pri);
+
+extern inline int openpic_to_irq(int irq)
+{
+        /* IRQ 0 usually means 'disabled'.. don't mess with it
+         * exceptions to this (sandpoint maybe?)
+         * shouldn't use openpic_to_irq
+         */
+        if (irq != 0){
+                return irq += NUM_8259_INTERRUPTS;
+        } else {
+                return 0;
+        }
+}
+/* Support for second openpic on G5 macs */
+
+// FIXME: To be replaced by sane cascaded controller management */
+
+#define PMAC_OPENPIC2_OFFSET    128
+
+#define OPENPIC2_VEC_TIMER      110     /* and up */
+#define OPENPIC2_VEC_IPI        118     /* and up */
+#define OPENPIC2_VEC_SPURIOUS   127
+
+
+extern void* OpenPIC2_Addr;
+
+/* Exported functions */
+extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
+extern void openpic2_init(int linux_irq_offset);
+extern void openpic2_init_nmi_irq(u_int irq);
+extern u_int openpic2_irq(void);
+extern void openpic2_eoi(void);
+extern int openpic2_get_irq(struct pt_regs *regs);
+extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
+#endif /* _PPC_KERNEL_OPEN_PIC_H */
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
new file mode 100644
index 000000000000..4789dc024240
--- /dev/null
+++ b/include/asm-ppc/page.h
@@ -0,0 +1,169 @@
+#ifndef _PPC_PAGE_H
+#define _PPC_PAGE_H
+
+/* PAGE_SHIFT determines the page size */
+#define PAGE_SHIFT      12
+#define PAGE_SIZE       (1UL << PAGE_SHIFT)
+
+/*
+ * Subtle: this is an int (not an unsigned long) and so it
+ * gets extended to 64 bits the way want (i.e. with 1s).  -- paulus
+ */
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+
+/* This must match what is in arch/ppc/Makefile */
+#define PAGE_OFFSET     CONFIG_KERNEL_START
+#define KERNELBASE      PAGE_OFFSET
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
+ * physical addressing.  For now this just the IBM PPC440.
+ */
+#ifdef CONFIG_PTE_64BIT
+typedef unsigned long long pte_basic_t;
+#define PTE_SHIFT       (PAGE_SHIFT - 3)        /* 512 ptes per page */
+#define PTE_FMT         "%16Lx"
+#else
+typedef unsigned long pte_basic_t;
+#define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
+#define PTE_FMT         "%.8lx"
+#endif
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pte_basic_t pte; } pte_t;
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else
+/*
+ * .. while these make it easier on the compiler
+ */
+typedef pte_basic_t pte_t;
+typedef unsigned long pmd_t;
+typedef unsigned long pgd_t;
+typedef unsigned long pgprot_t;
+
+#define pte_val(x)      (x)
+#define pmd_val(x)      (x)
+#define pgd_val(x)      (x)
+#define pgprot_val(x)   (x)
+
+#define __pte(x)        (x)
+#define __pmd(x)        (x)
+#define __pgd(x)        (x)
+#define __pgprot(x)     (x)
+
+#endif
+
+
+/* align addr on a size boundary - adjust address up if needed -- Cort */
+#define _ALIGN(addr,size)       (((addr)+(size)-1)&(~((size)-1)))
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+struct page;
+extern void clear_pages(void *page, int order);
+static inline void clear_page(void *page) { clear_pages(page, 0); }
+extern void copy_page(void *to, void *from);
+extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
+extern void copy_user_page(void *to, void *from, unsigned long vaddr,
+                           struct page *pg);
+
+#ifndef CONFIG_APUS
+#define PPC_MEMSTART    0
+#define PPC_PGSTART     0
+#define PPC_MEMOFFSET   PAGE_OFFSET
+#else
+extern unsigned long ppc_memstart;
+extern unsigned long ppc_pgstart;
+extern unsigned long ppc_memoffset;
+#define PPC_MEMSTART    ppc_memstart
+#define PPC_PGSTART     ppc_pgstart
+#define PPC_MEMOFFSET   ppc_memoffset
+#endif
+
+#if defined(CONFIG_APUS) && !defined(MODULE)
+/* map phys->virtual and virtual->phys for RAM pages */
+static inline unsigned long ___pa(unsigned long v)
+{
+        unsigned long p;
+        asm volatile ("1: addis %0, %1, %2;"
+                      ".section \".vtop_fixup\",\"aw\";"
+                      ".align  1;"
+                      ".long   1b;"
+                      ".previous;"
+                      : "=r" (p)
+                      : "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff));
+
+        return p;
+}
+static inline void* ___va(unsigned long p)
+{
+        unsigned long v;
+        asm volatile ("1: addis %0, %1, %2;"
+                      ".section \".ptov_fixup\",\"aw\";"
+                      ".align  1;"
+                      ".long   1b;"
+                      ".previous;"
+                      : "=r" (v)
+                      : "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff));
+
+        return (void*) v;
+}
+#else
+#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET)
+#define ___va(paddr) ((paddr)+PPC_MEMOFFSET)
+#endif
+
+extern int page_is_ram(unsigned long pfn);
+
+#define __pa(x) ___pa((unsigned long)(x))
+#define __va(x) ((void *)(___va((unsigned long)(x))))
+
+#define pfn_to_page(pfn)        (mem_map + ((pfn) - PPC_PGSTART))
+#define page_to_pfn(page)       ((unsigned long)((page) - mem_map) + PPC_PGSTART)
+#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_virt(page)      __va(page_to_pfn(page) << PAGE_SHIFT)
+
+#define pfn_valid(pfn)          (((pfn) - PPC_PGSTART) < max_mapnr)
+#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+
+/* Pure 2^n version of get_order */
+extern __inline__ int get_order(unsigned long size)
+{
+        int lz;
+
+        size = (size-1) >> PAGE_SHIFT;
+        asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
+        return 32 - lz;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+#endif /* _PPC_PAGE_H */
diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h
new file mode 100644
index 000000000000..b24a4e37196a
--- /dev/null
+++ b/include/asm-ppc/param.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_PPC_PARAM_H
+#define _ASM_PPC_PARAM_H
+
+#ifdef __KERNEL__
+#define HZ              1000            /* internal timer frequency */
+#define USER_HZ         100             /* for user interfaces in "ticks" */
+#define CLOCKS_PER_SEC  (USER_HZ)       /* frequency at which times() counts */
+#endif /* __KERNEL__ */
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif
diff --git a/include/asm-ppc/parport.h b/include/asm-ppc/parport.h
new file mode 100644
index 000000000000..11f96d3de5b6
--- /dev/null
+++ b/include/asm-ppc/parport.h
@@ -0,0 +1,18 @@
+/*
+ * parport.h: platform-specific PC-style parport initialisation
+ *
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+
+#ifndef _ASM_PPC_PARPORT_H
+#define _ASM_PPC_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
+static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports (autoirq, autodma);
+}
+
+#endif /* !(_ASM_PPC_PARPORT_H) */
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
new file mode 100644
index 000000000000..fa9cbb67ce3e
--- /dev/null
+++ b/include/asm-ppc/pc_serial.h
@@ -0,0 +1,127 @@
+/*
+ * include/asm-ppc/pc_serial.h
+ *
+ * This is basically a copy of include/asm-i386/serial.h.
+ * It is used on platforms which have an ISA bus and thus are likely
+ * to have PC-style serial ports at the legacy I/O port addresses.
+ * It also includes the definitions for the fourport, accent, boca
+ * and hub6 multiport serial cards, although I have never heard of
+ * anyone using any of those on a PPC platform.  -- paulus
+ */
+
+#include <linux/config.h>
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define RS_TABLE_SIZE  64
+#else
+#define RS_TABLE_SIZE  4
+#endif
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define FOURPORT_FLAGS ASYNC_FOURPORT
+#define ACCENT_FLAGS 0
+#define BOCA_FLAGS 0
+#define HUB6_FLAGS 0
+#endif
+        
+/*
+ * The following define the access methods for the HUB6 card. All
+ * access is through two ports for all 24 possible chips. The card is
+ * selected through the high 2 bits, the port on that card with the
+ * "middle" 3 bits, and the register on that port with the bottom
+ * 3 bits.
+ *
+ * While the access port and interrupt is configurable, the default
+ * port locations are 0x302 for the port control register, and 0x303
+ * for the data read/write register. Normally, the interrupt is at irq3
+ * but can be anything from 3 to 7 inclusive. Note that using 3 will
+ * require disabling com2.
+ */
+
+#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
+
+#define STD_SERIAL_PORT_DEFNS                   \
+        /* UART CLK   PORT IRQ     FLAGS        */                      \
+        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
+        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
+        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
+        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
+
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define EXTRA_SERIAL_PORT_DEFNS                 \
+        { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS },     /* ttyS4 */     \
+        { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS },     /* ttyS5 */     \
+        { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS },     /* ttyS6 */     \
+        { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS },     /* ttyS7 */     \
+        { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS },     /* ttyS8 */     \
+        { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS },     /* ttyS9 */     \
+        { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS },     /* ttyS10 */    \
+        { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS },     /* ttyS11 */    \
+        { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS },       /* ttyS12 */    \
+        { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS },       /* ttyS13 */    \
+        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS14 (spare) */            \
+        { 0, BASE_BAUD, 0x000, 0, 0 },  /* ttyS15 (spare) */            \
+        { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS },        /* ttyS16 */    \
+        { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS },        /* ttyS17 */    \
+        { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS },        /* ttyS18 */    \
+        { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS },        /* ttyS19 */    \
+        { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS },        /* ttyS20 */    \
+        { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS },        /* ttyS21 */    \
+        { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS },        /* ttyS22 */    \
+        { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS },        /* ttyS23 */    \
+        { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS },        /* ttyS24 */    \
+        { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS },        /* ttyS25 */    \
+        { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS },        /* ttyS26 */    \
+        { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS },        /* ttyS27 */    \
+        { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS },        /* ttyS28 */    \
+        { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS },        /* ttyS29 */    \
+        { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS },        /* ttyS30 */    \
+        { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS },        /* ttyS31 */
+#else
+#define EXTRA_SERIAL_PORT_DEFNS
+#endif
+
+/* You can have up to four HUB6's in the system, but I've only
+ * included two cards here for a total of twelve ports.
+ */
+#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
+#define HUB6_SERIAL_PORT_DFNS           \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) },  /* ttyS32 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) },  /* ttyS33 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) },  /* ttyS34 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) },  /* ttyS35 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) },  /* ttyS36 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) },  /* ttyS37 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) },  /* ttyS38 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) },  /* ttyS39 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) },  /* ttyS40 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) },  /* ttyS41 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) },  /* ttyS42 */ \
+        { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) },  /* ttyS43 */
+#else
+#define HUB6_SERIAL_PORT_DFNS
+#endif
+
+#define SERIAL_PORT_DFNS                \
+        STD_SERIAL_PORT_DEFNS           \
+        EXTRA_SERIAL_PORT_DEFNS         \
+        HUB6_SERIAL_PORT_DFNS
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
new file mode 100644
index 000000000000..78e9be619f14
--- /dev/null
+++ b/include/asm-ppc/pci-bridge.h
@@ -0,0 +1,136 @@
+#ifdef __KERNEL__
+#ifndef _ASM_PCI_BRIDGE_H
+#define _ASM_PCI_BRIDGE_H
+
+#include <linux/ioport.h>
+#include <linux/pci.h>
+
+struct device_node;
+struct pci_controller;
+
+/*
+ * pci_io_base returns the memory address at which you can access
+ * the I/O space for PCI bus number `bus' (or NULL on error).
+ */
+extern void *pci_bus_io_base(unsigned int bus);
+extern unsigned long pci_bus_io_base_phys(unsigned int bus);
+extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
+
+/* Allocate a new PCI host bridge structure */
+extern struct pci_controller* pcibios_alloc_controller(void);
+
+/* Helper function for setting up resources */
+extern void pci_init_resource(struct resource *res, unsigned long start,
+                              unsigned long end, int flags, char *name);
+
+/* Get the PCI host controller for a bus */
+extern struct pci_controller* pci_bus_to_hose(int bus);
+
+/* Get the PCI host controller for an OF device */
+extern struct pci_controller*
+pci_find_hose_for_OF_device(struct device_node* node);
+
+/* Fill up host controller resources from the OF node */
+extern void
+pci_process_bridge_OF_ranges(struct pci_controller *hose,
+                           struct device_node *dev, int primary);
+
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct pci_controller {
+        int index;                      /* PCI domain number */
+        struct pci_controller *next;
+        struct pci_bus *bus;
+        void *arch_data;
+
+        int first_busno;
+        int last_busno;
+        int bus_offset;
+
+        void *io_base_virt;
+        unsigned long io_base_phys;
+
+        /* Some machines (PReP) have a non 1:1 mapping of
+         * the PCI memory space in the CPU bus space
+         */
+        unsigned long pci_mem_offset;
+
+        struct pci_ops *ops;
+        volatile unsigned int __iomem *cfg_addr;
+        volatile void __iomem *cfg_data;
+        /*
+         * If set, indirect method will set the cfg_type bit as
+         * needed to generate type 1 configuration transactions.
+         */
+        int set_cfg_type;
+
+        /* Currently, we limit ourselves to 1 IO range and 3 mem
+         * ranges since the common pci_bus structure can't handle more
+         */
+        struct resource io_resource;
+        struct resource mem_resources[3];
+        int mem_resource_count;
+
+        /* Host bridge I/O and Memory space
+         * Used for BAR placement algorithms
+         */
+        struct resource io_space;
+        struct resource mem_space;
+};
+
+/* These are used for config access before all the PCI probing
+   has been done. */
+int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
+                           int where, u8 *val);
+int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
+                           int where, u16 *val);
+int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
+                            int where, u32 *val);
+int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
+                            int where, u8 val);
+int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
+                            int where, u16 val);
+int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
+                             int where, u32 val);
+
+extern void setup_indirect_pci_nomap(struct pci_controller* hose,
+                               void __iomem *cfg_addr, void __iomem *cfg_data);
+extern void setup_indirect_pci(struct pci_controller* hose,
+                               u32 cfg_addr, u32 cfg_data);
+extern void setup_grackle(struct pci_controller *hose);
+
+extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
+
+/*
+ *   The following code swizzles for exactly one bridge.  The routine
+ *   common_swizzle below handles multiple bridges.  But there are a
+ *   some boards that don't follow the PCI spec's suggestion so we
+ *   break this piece out separately.
+ */
+static inline unsigned char bridge_swizzle(unsigned char pin,
+                unsigned char idsel)
+{
+        return (((pin-1) + idsel) % 4) + 1;
+}
+
+/*
+ * The following macro is used to lookup irqs in a standard table
+ * format for those PPC systems that do not already have PCI
+ * interrupts properly routed.
+ */
+/* FIXME - double check this */
+#define PCI_IRQ_TABLE_LOOKUP                                                \
+({ long _ctl_ = -1;                                                         \
+   if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot)    \
+     _ctl_ = pci_irq_table[idsel - min_idsel][pin-1];                       \
+   _ctl_; })
+
+/*
+ * Scan the buses below a given PCI host bridge and assign suitable
+ * resources to all devices found.
+ */
+extern int pciauto_bus_scan(struct pci_controller *, int);
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
new file mode 100644
index 000000000000..ce5ae6d048f5
--- /dev/null
+++ b/include/asm-ppc/pci.h
@@ -0,0 +1,108 @@
+#ifndef __PPC_PCI_H
+#define __PPC_PCI_H
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <asm/scatterlist.h>
+#include <asm/io.h>
+#include <asm/pci-bridge.h>
+#include <asm-generic/pci-dma-compat.h>
+
+struct pci_dev;
+
+/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
+#define IOBASE_BRIDGE_NUMBER    0
+#define IOBASE_MEMORY           1
+#define IOBASE_IO               2
+#define IOBASE_ISA_IO           3
+#define IOBASE_ISA_MEM          4
+
+/*
+ * Set this to 1 if you want the kernel to re-assign all PCI
+ * bus numbers
+ */
+extern int pci_assign_all_busses;
+
+#define pcibios_assign_all_busses()     (pci_assign_all_busses)
+#define pcibios_scan_all_fns(a, b)      0
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x10000000
+
+extern inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+extern inline void pcibios_penalize_isa_irq(int irq)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res);
+
+/*
+ * The PCI bus bridge can translate addresses issued by the processor(s)
+ * into a different address on the PCI bus.  On 32-bit cpus, we assume
+ * this mapping is 1-1, but on 64-bit systems it often isn't.
+ *
+ * Obsolete ! Drivers should now use pci_resource_to_bus
+ */
+extern unsigned long phys_to_bus(unsigned long pa);
+extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
+extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
+
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (1)
+
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+/*
+ * At present there are very few 32-bit PPC machines that can have
+ * memory above the 4GB point, and we don't support that.
+ */
+#define pci_dac_dma_supported(pci_dev, mask)    (0)
+
+/* Return the index of the PCI controller for device PDEV. */
+#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+
+/* Set the name of the bus as it appears in /proc/bus/pci */
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        return 0;
+}
+
+/* Map a range of PCI memory or I/O space for a device into user space */
+int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
+                        enum pci_mmap_state mmap_state, int write_combine);
+
+/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
+#define HAVE_PCI_MMAP   1
+
+extern void
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+                        struct resource *res);
+
+extern void pcibios_add_platform_entries(struct pci_dev *dev);
+
+struct file;
+extern pgprot_t pci_phys_mem_access_prot(struct file *file,
+                                         unsigned long offset,
+                                         unsigned long size,
+                                         pgprot_t prot);
+
+#endif  /* __KERNEL__ */
+
+#endif /* __PPC_PCI_H */
diff --git a/include/asm-ppc/percpu.h b/include/asm-ppc/percpu.h
new file mode 100644
index 000000000000..d66667cd5878
--- /dev/null
+++ b/include/asm-ppc/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_PPC_PERCPU__
+#define __ARCH_PPC_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ARCH_PPC_PERCPU__ */
diff --git a/include/asm-ppc/perfmon.h b/include/asm-ppc/perfmon.h
new file mode 100644
index 000000000000..5e7a89c47b5b
--- /dev/null
+++ b/include/asm-ppc/perfmon.h
@@ -0,0 +1,22 @@
+#ifndef __PERFMON_H
+#define __PERFMON_H
+
+extern void (*perf_irq)(struct pt_regs *);
+
+int request_perfmon_irq(void (*handler)(struct pt_regs *));
+void free_perfmon_irq(void);
+
+#ifdef CONFIG_FSL_BOOKE
+void init_pmc_stop(int ctr);
+void set_pmc_event(int ctr, int event);
+void set_pmc_user_kernel(int ctr, int user, int kernel);
+void set_pmc_marked(int ctr, int mark0, int mark1);
+void pmc_start_ctr(int ctr, int enable);
+void pmc_start_ctrs(int enable);
+void pmc_stop_ctrs(void);
+void dump_pmcs(void);
+
+extern struct op_ppc32_model op_model_fsl_booke;
+#endif
+
+#endif /* __PERFMON_H */
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h
new file mode 100644
index 000000000000..931b6de7ef53
--- /dev/null
+++ b/include/asm-ppc/pgalloc.h
@@ -0,0 +1,44 @@
+#ifdef __KERNEL__
+#ifndef _PPC_PGALLOC_H
+#define _PPC_PGALLOC_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+
+extern void __bad_pte(pmd_t *pmd);
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(pgd_t *pgd);
+
+/*
+ * We don't have any real pmd's, and this code never triggers because
+ * the pgd will always be present..
+ */
+#define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(x)                     do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+#define pgd_populate(mm, pmd, pte)      BUG()
+
+#ifndef CONFIG_BOOKE
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#else
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (unsigned long)page_to_virt(pte) | _PMD_PRESENT)
+#endif
+
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
+extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern void pte_free_kernel(pte_t *pte);
+extern void pte_free(struct page *pte);
+
+#define __pte_free_tlb(tlb, pte)        pte_free((pte))
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _PPC_PGALLOC_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
new file mode 100644
index 000000000000..19dfb7abaa21
--- /dev/null
+++ b/include/asm-ppc/pgtable.h
@@ -0,0 +1,776 @@
+#ifdef __KERNEL__
+#ifndef _PPC_PGTABLE_H
+#define _PPC_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <asm/processor.h>              /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+
+extern unsigned long va_to_phys(unsigned long address);
+extern pte_t *va_to_pte(unsigned long address);
+extern unsigned long ioremap_bot, ioremap_base;
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The PowerPC MMU uses a hash table containing PTEs, together with
+ * a set of 16 segment registers (on 32-bit implementations), to define
+ * the virtual to physical address mapping.
+ *
+ * We use the hash table as an extended TLB, i.e. a cache of currently
+ * active mappings.  We maintain a two-level page table tree, much
+ * like that used by the i386, for the sake of the Linux memory
+ * management code.  Low-level assembler code in hashtable.S
+ * (procedure hash_page) is responsible for extracting ptes from the
+ * tree and putting them into the hash table when necessary, and
+ * updating the accessed and modified bits in the page table tree.
+ */
+
+/*
+ * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
+ * We also use the two level tables, but we can put the real bits in them
+ * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
+ * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
+ * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
+ * based upon user/super access.  The TLB does not have accessed nor write
+ * protect.  We assume that if the TLB get loaded with an entry it is
+ * accessed, and overload the changed bit for write protect.  We use
+ * two bits in the software pte that are supposed to be set to zero in
+ * the TLB entry (24 and 25) for these indicators.  Although the level 1
+ * descriptor contains the guarded and writethrough/copyback bits, we can
+ * set these at the page level since they get copied from the Mx_TWC
+ * register when the TLB entry is loaded.  We will use bit 27 for guard, since
+ * that is where it exists in the MD_TWC, and bit 26 for writethrough.
+ * These will get masked from the level 2 descriptor at TLB load time, and
+ * copied to the MD_TWC before it gets loaded.
+ * Large page sizes added.  We currently support two sizes, 4K and 8M.
+ * This also allows a TLB hander optimization because we can directly
+ * load the PMD into MD_TWC.  The 8M pages are only used for kernel
+ * mapping of well known areas.  The PMD (PGD) entries contain control
+ * flags in addition to the address, so care must be taken that the
+ * software no longer assumes these are only pointers.
+ */
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully-associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively (see "mmu.h" for definitions).
+ */
+
+/*
+ * The normal case is that PTEs are 32-bits and we have a 1-page
+ * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
+ *
+ * For any >32-bit physical address platform, we can use the following
+ * two level page table layout where the pgdir is 8KB and the MS 13 bits
+ * are an index to the second level table.  The combined pgdir/pmd first
+ * level has 2048 entries and the second level has 512 64-bit PTE entries.
+ * -Matt
+ */
+/* PMD_SHIFT determines the size of the area mapped by the PTE pages */
+#define PMD_SHIFT       (PAGE_SHIFT + PTE_SHIFT)
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#define PGDIR_SHIFT     PMD_SHIFT
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: our page-table tree is two-level, so
+ * we don't really have any PMD directory.
+ */
+#define PTRS_PER_PTE    (1 << PTE_SHIFT)
+#define PTRS_PER_PMD    1
+#define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_PGD_NR       0
+
+#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
+#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 64MB value just means that there will be a 64MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ *
+ * We no longer map larger than phys RAM with the BATs so we don't have
+ * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
+ * about clashes between our early calls to ioremap() that start growing down
+ * from ioremap_base being run into the VM area allocations (growing upwards
+ * from VMALLOC_START).  For this reason we have ioremap_bot to check when
+ * we actually run into our mappings setup in the early boot with the VM
+ * system.  This really does become a problem for machines with good amounts
+ * of RAM.  -- Cort
+ */
+#define VMALLOC_OFFSET (0x1000000) /* 16M */
+#ifdef CONFIG_44x
+#include <asm/ibm44x.h>
+#define VMALLOC_START (((_ALIGN((long)high_memory, PPC44x_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#else
+#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#endif
+#define VMALLOC_END     ioremap_bot
+
+/*
+ * Bits in a linux-style PTE.  These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible.
+ */
+
+#if defined(CONFIG_40x)
+
+/* There are several potential gotchas here.  The 40x hardware TLBLO
+   field looks like this:
+
+   0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+   RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
+
+   Where possible we make the Linux PTE bits match up with this
+
+   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
+     support down to 1k pages), this is done in the TLBMiss exception
+     handler.
+   - We use only zones 0 (for kernel pages) and 1 (for user pages)
+     of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
+     miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
+     zone.
+   - PRESENT *must* be in the bottom two bits because swap cache
+     entries use the top 30 bits.  Because 40x doesn't support SMP
+     anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
+     is cleared in the TLB miss handler before the TLB entry is loaded.
+   - All other bits of the PTE are loaded into TLBLO without
+     modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
+     software PTE bits.  We actually use use bits 21, 24, 25, and
+     30 respectively for the software bits: ACCESSED, DIRTY, RW, and
+     PRESENT.
+*/
+
+/* Definitions for 40x embedded chips. */
+#define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
+#define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
+#define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
+#define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
+#define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
+#define _PAGE_USER      0x010   /* matches one of the zone permission bits */
+#define _PAGE_RW        0x040   /* software: Writes permitted */
+#define _PAGE_DIRTY     0x080   /* software: dirty page */
+#define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
+#define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
+#define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
+
+#define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
+#define _PMD_BAD        0x802
+#define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
+#define _PMD_SIZE_4M    0x0c0
+#define _PMD_SIZE_16M   0x0e0
+#define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+
+#elif defined(CONFIG_44x)
+/*
+ * Definitions for PPC440
+ *
+ * Because of the 3 word TLB entries to support 36-bit addressing,
+ * the attribute are difficult to map in such a fashion that they
+ * are easily loaded during exception processing.  I decided to
+ * organize the entry so the ERPN is the only portion in the
+ * upper word of the PTE and the attribute bits below are packed
+ * in as sensibly as they can be in the area below a 4KB page size
+ * oriented RPN.  This at least makes it easy to load the RPN and
+ * ERPN fields in the TLB. -Matt
+ *
+ * Note that these bits preclude future use of a page size
+ * less than 4KB.
+ */
+#define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
+#define _PAGE_RW        0x00000002              /* S: Write permission */
+#define _PAGE_DIRTY     0x00000004              /* S: Page dirty */
+#define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
+#define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
+#define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
+#define _PAGE_USER      0x00000040              /* S: User page */
+#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
+#define _PAGE_GUARDED   0x00000100              /* H: G bit */
+#define _PAGE_COHERENT  0x00000200              /* H: M bit */
+#define _PAGE_FILE      0x00000400              /* S: nonlinear file mapping */
+#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
+
+/* TODO: Add large page lowmem mapping support */
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK  0xffffffff00000000ULL
+
+#elif defined(CONFIG_E500)
+
+/*
+   MMU Assist Register 3:
+
+   32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
+   RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
+
+   - PRESENT *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+
+   - FILE *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+*/
+
+/* Definitions for e500 core */
+#define _PAGE_PRESENT   0x001   /* S: PTE contains a translation */
+#define _PAGE_USER      0x002   /* S: User page (maps to UR) */
+#define _PAGE_FILE      0x002   /* S: when !present: nonlinear file mapping */
+#define _PAGE_ACCESSED  0x004   /* S: Page referenced */
+#define _PAGE_HWWRITE   0x008   /* H: Dirty & RW, set in exception */
+#define _PAGE_RW        0x010   /* S: Write permission */
+#define _PAGE_HWEXEC    0x020   /* H: UX permission */
+
+#define _PAGE_ENDIAN    0x040   /* H: E bit */
+#define _PAGE_GUARDED   0x080   /* H: G bit */
+#define _PAGE_COHERENT  0x100   /* H: M bit */
+#define _PAGE_NO_CACHE  0x200   /* H: I bit */
+#define _PAGE_WRITETHRU 0x400   /* H: W bit */
+#define _PAGE_DIRTY     0x800   /* S: Page dirty */
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+#define NUM_TLBCAMS     (16)
+
+#elif defined(CONFIG_8xx)
+/* Definitions for 8xx embedded chips. */
+#define _PAGE_PRESENT   0x0001  /* Page is valid */
+#define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
+#define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
+#define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
+
+/* These five software bits must be masked out when the entry is loaded
+ * into the TLB.
+ */
+#define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
+#define _PAGE_GUARDED   0x0010  /* software: guarded access */
+#define _PAGE_DIRTY     0x0020  /* software: page changed */
+#define _PAGE_RW        0x0040  /* software: user write access allowed */
+#define _PAGE_ACCESSED  0x0080  /* software: page referenced */
+
+/* Setting any bits in the nibble with the follow two controls will
+ * require a TLB exception handler change.  It is assumed unused bits
+ * are always zero.
+ */
+#define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
+#define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
+
+#define _PMD_PRESENT    0x0001
+#define _PMD_BAD        0x0ff0
+#define _PMD_PAGE_MASK  0x000c
+#define _PMD_PAGE_8M    0x000c
+
+/*
+ * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
+ * for an address even if _PAGE_PRESENT is not set, as a performance
+ * optimization.  This is a bug if you ever want to use swap unless
+ * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
+ * definitions for __swp_entry etc. below, which would be gross.
+ *  -- paulus
+ */
+#define _PTE_NONE_MASK _PAGE_ACCESSED
+
+#else /* CONFIG_6xx */
+/* Definitions for 60x, 740/750, etc. */
+#define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
+#define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
+#define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
+#define _PAGE_USER      0x004   /* usermode access allowed */
+#define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
+#define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
+#define _PAGE_DIRTY     0x080   /* C: page changed */
+#define _PAGE_ACCESSED  0x100   /* R: page referenced */
+#define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
+#define _PAGE_RW        0x400   /* software: user write access allowed */
+
+#define _PTE_NONE_MASK  _PAGE_HASHPTE
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+#endif
+
+/*
+ * Some bits are only used on some cpu families...
+ */
+#ifndef _PAGE_HASHPTE
+#define _PAGE_HASHPTE   0
+#endif
+#ifndef _PTE_NONE_MASK
+#define _PTE_NONE_MASK 0
+#endif
+#ifndef _PAGE_SHARED
+#define _PAGE_SHARED    0
+#endif
+#ifndef _PAGE_HWWRITE
+#define _PAGE_HWWRITE   0
+#endif
+#ifndef _PAGE_HWEXEC
+#define _PAGE_HWEXEC    0
+#endif
+#ifndef _PAGE_EXEC
+#define _PAGE_EXEC      0
+#endif
+#ifndef _PMD_PRESENT_MASK
+#define _PMD_PRESENT_MASK       _PMD_PRESENT
+#endif
+#ifndef _PMD_SIZE
+#define _PMD_SIZE       0
+#define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
+#endif
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+/*
+ * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
+ * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
+ * to have it in the Linux PTE, and in fact the bit could be reused for
+ * another purpose.  -- paulus.
+ */
+
+#ifdef CONFIG_44x
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#else
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
+#endif
+#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
+#define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
+
+#ifdef CONFIG_PPC_STD_MMU
+/* On standard PPC MMU, no user access implies kernel read/write access,
+ * so to write-protect kernel memory we must turn on user access */
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
+#else
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
+#endif
+
+#define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
+/* We want the debuggers to be able to set breakpoints anywhere, so
+ * don't write protect the kernel text */
+#define _PAGE_RAM_TEXT  _PAGE_RAM
+#else
+#define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
+#endif
+
+#define PAGE_NONE       __pgprot(_PAGE_BASE)
+#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
+#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
+#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+
+#define PAGE_KERNEL             __pgprot(_PAGE_RAM)
+#define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
+
+/*
+ * The PowerPC can only do execute protection on a segment (256MB) basis,
+ * not on a page basis.  So we consider execute permission the same as read.
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY_X
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY_X
+#define __P100  PAGE_READONLY
+#define __P101  PAGE_READONLY_X
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY_X
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY_X
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED_X
+#define __S100  PAGE_READONLY
+#define __S101  PAGE_READONLY_X
+#define __S110  PAGE_SHARED
+#define __S111  PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
+ * kernel without large page PMD support */
+extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
+
+/*
+ * Conversions between PTE values and page frame numbers.
+ */
+
+#define pte_pfn(x)              (pte_val(x) >> PAGE_SHIFT)
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#define pfn_pte(pfn, prot)      __pte(((pte_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[1024];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* __ASSEMBLY__ */
+
+#define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
+
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
+#define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
+#define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
+
+#ifndef __ASSEMBLY__
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+static inline int pgd_none(pgd_t pgd)           { return 0; }
+static inline int pgd_bad(pgd_t pgd)            { return 0; }
+static inline int pgd_present(pgd_t pgd)        { return 1; }
+#define pgd_clear(xp)                           do { } while (0)
+
+#define pgd_page(pgd) \
+        ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
+static inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_EXEC; }
+static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
+
+static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_rdprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_exprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_EXEC; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_mkread(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+        pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+        pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+        return pte;
+}
+
+/*
+ * When flushing the tlb entry for a page, we also need to flush the hash
+ * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
+ */
+extern int flush_hash_pages(unsigned context, unsigned long va,
+                            unsigned long pmdval, int count);
+
+/* Add an HPTE to the hash table */
+extern void add_hash_page(unsigned context, unsigned long va,
+                          unsigned long pmdval);
+
+/*
+ * Atomic PTE updates.
+ *
+ * pte_update clears and sets bit atomically, and returns
+ * the old pte value.
+ * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
+ * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
+ */
+static inline unsigned long pte_update(pte_t *p, unsigned long clr,
+                                       unsigned long set)
+{
+        unsigned long old, tmp;
+
+        __asm__ __volatile__("\
+1:      lwarx   %0,0,%3\n\
+        andc    %1,%0,%4\n\
+        or      %1,%1,%5\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %1,0,%3\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p)
+        : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+        return old;
+}
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ * On machines which use an MMU hash table we avoid changing the
+ * _PAGE_HASHPTE bit.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pte)
+{
+#if _PAGE_HASHPTE != 0
+        pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
+#else
+        *ptep = pte;
+#endif
+}
+
+/*
+ * 2.6 calles this without flushing the TLB entry, this is wrong
+ * for our hash-based implementation, we fix that up here
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+        old = pte_update(ptep, _PAGE_ACCESSED, 0);
+#if _PAGE_HASHPTE != 0
+        if (old & _PAGE_HASHPTE) {
+                unsigned long ptephys = __pa(ptep) & PAGE_MASK;
+                flush_hash_pages(context, addr, ptephys, 1);
+        }
+#endif
+        return (old & _PAGE_ACCESSED) != 0;
+}
+#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
+        __ptep_test_and_clear_young((__vma)->vm_mm->context, __addr, __ptep)
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
+}
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                                       pte_t *ptep)
+{
+        return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pte_t *ptep)
+{
+        pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
+}
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+        unsigned long bits = pte_val(entry) &
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
+        pte_update(ptep, 0, bits);
+}
+
+#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+        do {                                                               \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        } while(0)
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
+
+/*
+ * Note that on Book E processors, the pmd contains the kernel virtual
+ * (lowmem) address of the pte page.  The physical address is less useful
+ * because everything runs with translation enabled (even the TLB miss
+ * handler).  On everything else the pmd contains the physical address
+ * of the pte page.  -- paulus
+ */
+#ifndef CONFIG_BOOKE
+#define pmd_page_kernel(pmd)    \
+        ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
+#else
+#define pmd_page_kernel(pmd)    \
+        ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+#endif
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address)       ((address) >> PGDIR_SHIFT)
+#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
+{
+        return (pmd_t *) dir;
+}
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)              \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, addr)    \
+        ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir, addr)               \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
+#define pte_offset_map_nested(dir, addr)        \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
+
+#define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
+#define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+extern void paging_init(void);
+
+/*
+ * Encode and decode a swap entry.
+ * Note that the bits we use in a PTE for representing a swap entry
+ * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
+ *_PAGE_HASHPTE bit (if used).  -- paulus
+ */
+#define __swp_type(entry)               ((entry).val & 0x1f)
+#define __swp_offset(entry)             ((entry).val >> 5)
+#define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
+
+/* CONFIG_APUS */
+/* For virtual address to physical address conversion */
+extern void cache_clear(__u32 addr, int length);
+extern void cache_push(__u32 addr, int length);
+extern int mm_end_of_chunk (unsigned long addr, int len);
+extern unsigned long iopa(unsigned long addr);
+extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
+
+/* Values for nocacheflag and cmode */
+/* These are not used by the APUS kernel_map, but prevents
+   compilation errors. */
+#define KERNELMAP_FULL_CACHING          0
+#define KERNELMAP_NOCACHE_SER           1
+#define KERNELMAP_NOCACHE_NONSER        2
+#define KERNELMAP_NO_COPYBACK           3
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
+                                int nocacheflag, unsigned long *memavailp );
+
+/*
+ * Set cache mode of (kernel space) address range.
+ */
+extern void kernel_set_cachemode (unsigned long address, unsigned long size,
+                                 unsigned int cmode);
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr)   (1)
+
+#ifdef CONFIG_PHYS_64BIT
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
+                        unsigned long paddr, unsigned long size, pgprot_t prot);
+static inline int io_remap_page_range(struct vm_area_struct *vma,
+                                        unsigned long vaddr,
+                                        unsigned long paddr,
+                                        unsigned long size,
+                                        pgprot_t prot)
+{
+        phys_addr_t paddr64 = fixup_bigphys_addr(paddr, size);
+        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
+}
+
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+                                        unsigned long vaddr,
+                                        unsigned long pfn,
+                                        unsigned long size,
+                                        pgprot_t prot)
+{
+        phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
+}
+#else
+#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
+                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#endif
+
+#define MK_IOSPACE_PFN(space, pfn)      (pfn)
+#define GET_IOSPACE(pfn)                0
+#define GET_PFN(pfn)                    (pfn)
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
+
+#include <asm-generic/pgtable.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _PPC_PGTABLE_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h
new file mode 100644
index 000000000000..98c206d8c024
--- /dev/null
+++ b/include/asm-ppc/pmac_feature.h
@@ -0,0 +1,365 @@
+/*
+ * Definition of platform feature hooks for PowerMacs
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Paul Mackerras &
+ *                    Ben. Herrenschmidt.
+ *
+ *
+ * Note: I removed media-bay details from the feature stuff, I believe it's
+ *       not worth it, the media-bay driver can directly use the mac-io
+ *       ASIC registers.
+ *
+ * Implementation note: Currently, none of these functions will block.
+ * However, they may internally protect themselves with a spinlock
+ * for way too long. Be prepared for at least some of these to block
+ * in the future.
+ *
+ * Unless specifically defined, the result code is assumed to be an
+ * error when negative, 0 is the default success result. Some functions
+ * may return additional positive result values.
+ *
+ * To keep implementation simple, all feature calls are assumed to have
+ * the prototype parameters (struct device_node* node, int value).
+ * When either is not used, pass 0.
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_ASM_PMAC_FEATURE_H
+#define __PPC_ASM_PMAC_FEATURE_H
+
+#include <asm/macio.h>
+
+/*
+ * Known Mac motherboard models
+ *
+ * Please, report any error here to benh@kernel.crashing.org, thanks !
+ *
+ * Note that I don't fully maintain this list for Core99 & MacRISC2
+ * and I'm considering removing all NewWorld entries from it and
+ * entirely rely on the model string.
+ */
+
+/* PowerSurge are the first generation of PCI Pmacs. This include
+ * all of the Grand-Central based machines. We currently don't
+ * differenciate most of them.
+ */
+#define PMAC_TYPE_PSURGE                0x10    /* PowerSurge */
+#define PMAC_TYPE_ANS                   0x11    /* Apple Network Server */
+
+/* Here is the infamous serie of OHare based machines
+ */
+#define PMAC_TYPE_COMET                 0x20    /* Beleived to be PowerBook 2400 */
+#define PMAC_TYPE_HOOPER                0x21    /* Beleived to be PowerBook 3400 */
+#define PMAC_TYPE_KANGA                 0x22    /* PowerBook 3500 (first G3) */
+#define PMAC_TYPE_ALCHEMY               0x23    /* Alchemy motherboard base */
+#define PMAC_TYPE_GAZELLE               0x24    /* Spartacus, some 5xxx/6xxx */
+#define PMAC_TYPE_UNKNOWN_OHARE         0x2f    /* Unknown, but OHare based */
+
+/* Here are the Heathrow based machines
+ * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
+ */
+#define PMAC_TYPE_GOSSAMER              0x30    /* Gossamer motherboard */
+#define PMAC_TYPE_SILK                  0x31    /* Desktop PowerMac G3 */
+#define PMAC_TYPE_WALLSTREET            0x32    /* Wallstreet/Mainstreet PowerBook*/
+#define PMAC_TYPE_UNKNOWN_HEATHROW      0x3f    /* Unknown but heathrow based */
+
+/* Here are newworld machines based on Paddington (heathrow derivative)
+ */
+#define PMAC_TYPE_101_PBOOK             0x40    /* 101 PowerBook (aka Lombard) */
+#define PMAC_TYPE_ORIG_IMAC             0x41    /* First generation iMac */
+#define PMAC_TYPE_YOSEMITE              0x42    /* B&W G3 */
+#define PMAC_TYPE_YIKES                 0x43    /* Yikes G4 (PCI graphics) */
+#define PMAC_TYPE_UNKNOWN_PADDINGTON    0x4f    /* Unknown but paddington based */
+
+/* Core99 machines based on UniNorth 1.0 and 1.5
+ *
+ * Note: A single entry here may cover several actual models according
+ * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
+ * FireWire based iMacs, etc...). Those machines are too similar to be
+ * distinguished here, when they need to be differencied, use the
+ * device-tree "model" or "compatible" property.
+ */
+#define PMAC_TYPE_ORIG_IBOOK            0x40    /* First iBook model (no firewire) */
+#define PMAC_TYPE_SAWTOOTH              0x41    /* Desktop G4s */
+#define PMAC_TYPE_FW_IMAC               0x42    /* FireWire iMacs (except Pangea based) */
+#define PMAC_TYPE_FW_IBOOK              0x43    /* FireWire iBooks (except iBook2) */
+#define PMAC_TYPE_CUBE                  0x44    /* Cube PowerMac */
+#define PMAC_TYPE_QUICKSILVER           0x45    /* QuickSilver G4s */
+#define PMAC_TYPE_PISMO                 0x46    /* Pismo PowerBook */
+#define PMAC_TYPE_TITANIUM              0x47    /* Titanium PowerBook */
+#define PMAC_TYPE_TITANIUM2             0x48    /* Titanium II PowerBook (no L3, M6) */
+#define PMAC_TYPE_TITANIUM3             0x49    /* Titanium III PowerBook (with L3 & M7) */
+#define PMAC_TYPE_TITANIUM4             0x50    /* Titanium IV PowerBook (with L3 & M9) */
+#define PMAC_TYPE_EMAC                  0x50    /* eMac */
+#define PMAC_TYPE_UNKNOWN_CORE99        0x5f
+
+/* MacRisc2 with UniNorth 2.0 */
+#define PMAC_TYPE_RACKMAC               0x80    /* XServe */
+#define PMAC_TYPE_WINDTUNNEL            0x81
+
+/* MacRISC2 machines based on the Pangea chipset
+ */
+#define PMAC_TYPE_PANGEA_IMAC           0x100   /* Flower Power iMac */
+#define PMAC_TYPE_IBOOK2                0x101   /* iBook2 (polycarbonate) */
+#define PMAC_TYPE_FLAT_PANEL_IMAC       0x102   /* Flat panel iMac */
+#define PMAC_TYPE_UNKNOWN_PANGEA        0x10f
+
+/* MacRISC2 machines based on the Intrepid chipset
+ */
+#define PMAC_TYPE_UNKNOWN_INTREPID      0x11f   /* Generic */
+
+/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
+ * but rather machine families
+ */
+#define PMAC_TYPE_POWERMAC_G5           0x150   /* U3 & U3H based */
+#define PMAC_TYPE_POWERMAC_G5_U3L       0x151   /* U3L based desktop */
+#define PMAC_TYPE_IMAC_G5               0x152   /* iMac G5 */
+#define PMAC_TYPE_XSERVE_G5             0x153   /* Xserve G5 */
+#define PMAC_TYPE_UNKNOWN_K2            0x19f   /* Any other K2 based */
+
+/*
+ * Motherboard flags
+ */
+
+#define PMAC_MB_CAN_SLEEP               0x00000001
+#define PMAC_MB_HAS_FW_POWER            0x00000002
+#define PMAC_MB_OLD_CORE99              0x00000004
+#define PMAC_MB_MOBILE                  0x00000008
+#define PMAC_MB_MAY_SLEEP               0x00000010
+
+/*
+ * Feature calls supported on pmac
+ *
+ */
+
+/*
+ * Use this inline wrapper
+ */
+struct device_node;
+
+static inline long pmac_call_feature(int selector, struct device_node* node,
+                                        long param, long value)
+{
+        if (!ppc_md.feature_call)
+                return -ENODEV;
+        return ppc_md.feature_call(selector, node, param, value);
+}
+
+/* PMAC_FTR_SERIAL_ENABLE       (struct device_node* node, int param, int value)
+ * enable/disable an SCC side. Pass the node corresponding to the
+ * channel side as a parameter.
+ * param is the type of port
+ * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
+ * for use by xmon.
+ */
+#define PMAC_FTR_SCC_ENABLE             PMAC_FTR_DEF(0)
+        #define PMAC_SCC_ASYNC          0
+        #define PMAC_SCC_IRDA           1
+        #define PMAC_SCC_I2S1           2
+        #define PMAC_SCC_FLAG_XMON      0x00001000
+
+/* PMAC_FTR_MODEM_ENABLE        (struct device_node* node, 0, int value)
+ * enable/disable the internal modem.
+ */
+#define PMAC_FTR_MODEM_ENABLE           PMAC_FTR_DEF(1)
+
+/* PMAC_FTR_SWIM3_ENABLE        (struct device_node* node, 0,int value)
+ * enable/disable the swim3 (floppy) cell of a mac-io ASIC
+ */
+#define PMAC_FTR_SWIM3_ENABLE           PMAC_FTR_DEF(2)
+
+/* PMAC_FTR_MESH_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the mesh (scsi) cell of a mac-io ASIC
+ */
+#define PMAC_FTR_MESH_ENABLE            PMAC_FTR_DEF(3)
+
+/* PMAC_FTR_IDE_ENABLE          (struct device_node* node, int busID, int value)
+ * enable/disable an IDE port of a mac-io ASIC
+ * pass the busID parameter
+ */
+#define PMAC_FTR_IDE_ENABLE             PMAC_FTR_DEF(4)
+
+/* PMAC_FTR_IDE_RESET           (struct device_node* node, int busID, int value)
+ * assert(1)/release(0) an IDE reset line (mac-io IDE only)
+ */
+#define PMAC_FTR_IDE_RESET              PMAC_FTR_DEF(5)
+
+/* PMAC_FTR_BMAC_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
+ * it's reset line
+ */
+#define PMAC_FTR_BMAC_ENABLE            PMAC_FTR_DEF(6)
+
+/* PMAC_FTR_GMAC_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
+ * control the cell's clock.
+ */
+#define PMAC_FTR_GMAC_ENABLE            PMAC_FTR_DEF(7)
+
+/* PMAC_FTR_GMAC_PHY_RESET      (struct device_node* node, 0, 0)
+ * Perform a HW reset of the PHY connected to a gmac controller.
+ * Pass the gmac device node, not the PHY node.
+ */
+#define PMAC_FTR_GMAC_PHY_RESET         PMAC_FTR_DEF(8)
+
+/* PMAC_FTR_SOUND_CHIP_ENABLE   (struct device_node* node, 0, int value)
+ * enable/disable the sound chip, whatever it is and provided it can
+ * acually be controlled
+ */
+#define PMAC_FTR_SOUND_CHIP_ENABLE      PMAC_FTR_DEF(9)
+
+/* -- add various tweaks related to sound routing -- */
+
+/* PMAC_FTR_AIRPORT_ENABLE      (struct device_node* node, 0, int value)
+ * enable/disable the airport card
+ */
+#define PMAC_FTR_AIRPORT_ENABLE         PMAC_FTR_DEF(10)
+
+/* PMAC_FTR_RESET_CPU           (NULL, int cpu_nr, 0)
+ * toggle the reset line of a CPU on an uninorth-based SMP machine
+ */
+#define PMAC_FTR_RESET_CPU              PMAC_FTR_DEF(11)
+
+/* PMAC_FTR_USB_ENABLE          (struct device_node* node, 0, int value)
+ * enable/disable an USB cell, along with the power of the USB "pad"
+ * on keylargo based machines
+ */
+#define PMAC_FTR_USB_ENABLE             PMAC_FTR_DEF(12)
+
+/* PMAC_FTR_1394_ENABLE         (struct device_node* node, 0, int value)
+ * enable/disable the firewire cell of an uninorth ASIC.
+ */
+#define PMAC_FTR_1394_ENABLE            PMAC_FTR_DEF(13)
+
+/* PMAC_FTR_1394_CABLE_POWER    (struct device_node* node, 0, int value)
+ * enable/disable the firewire cable power supply of the uninorth
+ * firewire cell
+ */
+#define PMAC_FTR_1394_CABLE_POWER       PMAC_FTR_DEF(14)
+
+/* PMAC_FTR_SLEEP_STATE         (struct device_node* node, 0, int value)
+ * set the sleep state of the motherboard.
+ *
+ * Pass -1 as value to query for sleep capability
+ * Pass 1 to set IOs to sleep
+ * Pass 0 to set IOs to wake
+ */
+#define PMAC_FTR_SLEEP_STATE            PMAC_FTR_DEF(15)
+
+/* PMAC_FTR_GET_MB_INFO         (NULL, selector, 0)
+ *
+ * returns some motherboard infos.
+ * selector: 0  - model id
+ *           1  - model flags (capabilities)
+ *           2  - model name (cast to const char *)
+ */
+#define PMAC_FTR_GET_MB_INFO            PMAC_FTR_DEF(16)
+#define   PMAC_MB_INFO_MODEL    0
+#define   PMAC_MB_INFO_FLAGS    1
+#define   PMAC_MB_INFO_NAME     2
+
+/* PMAC_FTR_READ_GPIO           (NULL, int index, 0)
+ *
+ * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
+ * the value returned is a byte (positive), or a negative error code
+ */
+#define PMAC_FTR_READ_GPIO              PMAC_FTR_DEF(17)
+
+/* PMAC_FTR_WRITE_GPIO          (NULL, int index, int value)
+ *
+ * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
+ */
+#define PMAC_FTR_WRITE_GPIO             PMAC_FTR_DEF(18)
+
+/* PMAC_FTR_ENABLE_MPIC
+ *
+ * Enable the MPIC cell
+ */
+#define PMAC_FTR_ENABLE_MPIC            PMAC_FTR_DEF(19)
+
+/* PMAC_FTR_AACK_DELAY_ENABLE   (NULL, int enable, 0)
+ *
+ * Enable/disable the AACK delay on the northbridge for systems using DFS
+ */
+#define PMAC_FTR_AACK_DELAY_ENABLE      PMAC_FTR_DEF(20)
+
+/* PMAC_FTR_DEVICE_CAN_WAKE
+ *
+ * Used by video drivers to inform system that they can actually perform
+ * wakeup from sleep
+ */
+#define PMAC_FTR_DEVICE_CAN_WAKE        PMAC_FTR_DEF(22)
+
+
+/* Don't use those directly, they are for the sake of pmac_setup.c */
+extern long pmac_do_feature_call(unsigned int selector, ...);
+extern void pmac_feature_init(void);
+
+/* Video suspend tweak */
+extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
+extern void pmac_call_early_video_resume(void);
+
+#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x))
+
+
+/*
+ * The part below is for use by macio_asic.c only, do not rely
+ * on the data structures or constants below in a normal driver
+ *
+ */
+
+#define MAX_MACIO_CHIPS         2
+
+enum {
+        macio_unknown = 0,
+        macio_grand_central,
+        macio_ohare,
+        macio_ohareII,
+        macio_heathrow,
+        macio_gatwick,
+        macio_paddington,
+        macio_keylargo,
+        macio_pangea,
+        macio_intrepid,
+        macio_keylargo2,
+};
+
+struct macio_chip
+{
+        struct device_node      *of_node;
+        int                     type;
+        const char              *name;
+        int                     rev;
+        volatile u32            __iomem *base;
+        unsigned long           flags;
+
+        /* For use by macio_asic PCI driver */
+        struct macio_bus        lbus;
+};
+
+extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
+
+#define MACIO_FLAG_SCCA_ON      0x00000001
+#define MACIO_FLAG_SCCB_ON      0x00000002
+#define MACIO_FLAG_SCC_LOCKED   0x00000004
+#define MACIO_FLAG_AIRPORT_ON   0x00000010
+#define MACIO_FLAG_FW_SUPPORTED 0x00000020
+
+extern struct macio_chip* macio_find(struct device_node* child, int type);
+
+#define MACIO_FCR32(macio, r)   ((macio)->base + ((r) >> 2))
+#define MACIO_FCR8(macio, r)    (((volatile u8 __iomem *)((macio)->base)) + (r))
+
+#define MACIO_IN32(r)           (in_le32(MACIO_FCR32(macio,r)))
+#define MACIO_OUT32(r,v)        (out_le32(MACIO_FCR32(macio,r), (v)))
+#define MACIO_BIS(r,v)          (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
+#define MACIO_BIC(r,v)          (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
+#define MACIO_IN8(r)            (in_8(MACIO_FCR8(macio,r)))
+#define MACIO_OUT8(r,v)         (out_8(MACIO_FCR8(macio,r), (v)))
+
+#endif /* __PPC_ASM_PMAC_FEATURE_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pmac_low_i2c.h b/include/asm-ppc/pmac_low_i2c.h
new file mode 100644
index 000000000000..809a5963d5e7
--- /dev/null
+++ b/include/asm-ppc/pmac_low_i2c.h
@@ -0,0 +1,43 @@
+/* 
+ *  include/asm-ppc/pmac_low_i2c.h
+ *
+ *  Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ *
+ */
+#ifndef __PMAC_LOW_I2C_H__
+#define __PMAC_LOW_I2C_H__
+
+/* i2c mode (based on the platform functions format) */
+enum {
+        pmac_low_i2c_mode_dumb          = 1,
+        pmac_low_i2c_mode_std           = 2,
+        pmac_low_i2c_mode_stdsub        = 3,
+        pmac_low_i2c_mode_combined      = 4,
+};
+
+/* RW bit in address */
+enum {
+        pmac_low_i2c_read               = 0x01,
+        pmac_low_i2c_write              = 0x00
+};
+
+/* Init, called early during boot */
+extern void pmac_init_low_i2c(void);
+
+/* Locking functions exposed to i2c-keywest */
+int pmac_low_i2c_lock(struct device_node *np);
+int pmac_low_i2c_unlock(struct device_node *np);
+
+/* Access functions for platform code */
+int pmac_low_i2c_open(struct device_node *np, int channel);
+int pmac_low_i2c_close(struct device_node *np);
+int pmac_low_i2c_setmode(struct device_node *np, int mode);
+int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len);
+
+
+#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h
new file mode 100644
index 000000000000..6f6760b30dd8
--- /dev/null
+++ b/include/asm-ppc/pnp.h
@@ -0,0 +1,645 @@
+#ifdef __KERNEL__
+/* 11/02/95                                                                   */
+/*----------------------------------------------------------------------------*/
+/*      Plug and Play header definitions                                      */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for PnP on PowerPC Reference Platform                        */
+/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
+/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
+/* This code has extensions to that specification, namely new short and       */
+/* long tag types for platform dependent information                          */
+
+/* Warning: LE notation used throughout this file                             */
+
+/* For enum's: if given in hex then they are bit significant, i.e.            */
+/* only one bit is on for each enum                                           */
+
+#ifndef _PNP_
+#define _PNP_
+
+#ifndef __ASSEMBLY__
+#define MAX_MEM_REGISTERS 9
+#define MAX_IO_PORTS 20
+#define MAX_IRQS 7
+/*#define MAX_DMA_CHANNELS 7*/
+
+/* Interrupt controllers */
+
+#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
+#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
+#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
+#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
+#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
+
+/* Timers */
+
+#define PNPtimer0     "PNP0100"      /* AT Timer                              */
+#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
+#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
+
+/* DMA controllers */
+
+#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
+#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
+#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
+
+/* start of August 15, 1994 additions */
+/* CMOS */
+#define PNPCMOS       "IBM0009"      /* CMOS                                  */
+
+/* L2 Cache */
+#define PNPL2         "IBM0007"      /* L2 Cache                              */
+
+/* NVRAM */
+#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
+
+/* Power Management */
+#define PNPPM         "IBM0005"      /* Power Management                      */
+/* end of August 15, 1994 additions */
+
+/* Keyboards */
+
+#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
+#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
+#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
+#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
+#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
+#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
+#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
+#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
+
+/* Parallel port controllers */
+
+#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
+#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
+#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
+
+/* Serial port controllers */
+
+#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
+#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
+
+/* Disk controllers */
+
+#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
+#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
+#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
+
+/* Diskette controllers */
+
+#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
+
+/* Display controllers */
+
+#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
+#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
+#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
+#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
+#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
+#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
+#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
+#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
+#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
+#define PNPdisplay9  "PNP0909"       /* S3                                    */
+#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
+#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
+#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
+#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
+#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
+#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
+
+/* Peripheral busses */
+
+#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
+#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
+#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
+#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
+#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
+
+/* RTC, BIOS, planar devices */
+
+#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
+#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
+#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
+#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
+#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
+#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
+
+/* PCMCIA controller */
+
+#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
+
+/* Mice */
+
+#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
+#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
+#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
+#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
+#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
+#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
+#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
+#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
+#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
+#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
+#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
+#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
+
+/* Modems */
+
+#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
+
+/* Network controllers */
+
+#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
+#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
+#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
+#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
+#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
+#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
+#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
+#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
+
+/* SCSI controllers */
+
+#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
+#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
+#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
+#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
+#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
+#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
+#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
+
+/* Sound/Video, Multimedia */
+
+#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
+#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
+#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
+#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
+#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
+#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
+#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
+#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
+
+/* Operator Panel */
+#define PNPopctl     "IBM000B"       /* Operator's panel                      */
+
+/* Service Processor */
+#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
+#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
+#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
+
+/* Memory Controller */
+#define PNPmemctl    "IBM000A"       /* Memory controller                     */
+
+/* Graphics Assist */
+#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
+
+/* Miscellaneous Device Controllers */
+#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
+
+/* PNP Packet Handles */
+
+#define S1_Packet                0x0A   /* Version resource                   */
+#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
+#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
+#define S3_Packet                0x1C   /* Compatible device ID               */
+#define S4_Packet                0x22   /* IRQ resource (without flags)       */
+#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
+#define S5_Packet                0x2A   /* DMA resource                       */
+#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
+#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
+#define S7_Packet                0x38   /* Depend funct end                   */
+#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
+#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
+#define S14_Packet               0x71   /* Vendor defined                     */
+#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
+#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
+#define L1_Packet                0x81   /* Memory range                       */
+#define L1_Shadow                0x20   /* Memory is shadowable               */
+#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
+#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
+#define L1_Decode_Hi             0x04   /* decode supports high address       */
+#define L1_Cache                 0x02   /* read cacheable, write-through      */
+#define L1_Writeable             0x01   /* Memory is writeable                */
+#define L2_Packet                0x82   /* ANSI ID string                     */
+#define L3_Packet                0x83   /* Unicode ID string                  */
+#define L4_Packet                0x84   /* Vendor defined                     */
+#define L5_Packet                0x85   /* Large I/O                          */
+#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
+#define END_TAG                  0x78   /* End of resource                    */
+#define DF_START_TAG             0x30   /* Dependent function start           */
+#define DF_START_TAG_priority    0x31   /* Dependent function start           */
+#define DF_END_TAG               0x38   /* Dependent function end             */
+#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
+
+/* Device Base Type Codes */
+
+typedef enum _PnP_BASE_TYPE {
+  Reserved = 0,
+  MassStorageDevice = 1,
+  NetworkInterfaceController = 2,
+  DisplayController = 3,
+  MultimediaController = 4,
+  MemoryController = 5,
+  BridgeController = 6,
+  CommunicationsDevice = 7,
+  SystemPeripheral = 8,
+  InputDevice = 9,
+  ServiceProcessor = 0x0A,              /* 11/2/95                            */
+  } PnP_BASE_TYPE;
+
+/* Device Sub Type Codes */
+
+typedef enum _PnP_SUB_TYPE {
+  SCSIController = 0,
+  IDEController = 1,
+  FloppyController = 2,
+  IPIController = 3,
+  OtherMassStorageController = 0x80,
+
+  EthernetController = 0,
+  TokenRingController = 1,
+  FDDIController = 2,
+  OtherNetworkController = 0x80,
+
+  VGAController= 0,
+  SVGAController= 1,
+  XGAController= 2,
+  OtherDisplayController = 0x80,
+
+  VideoController = 0,
+  AudioController = 1,
+  OtherMultimediaController = 0x80,
+
+  RAM = 0,
+  FLASH = 1,
+  OtherMemoryDevice = 0x80,
+
+  HostProcessorBridge = 0,
+  ISABridge = 1,
+  EISABridge = 2,
+  MicroChannelBridge = 3,
+  PCIBridge = 4,
+  PCMCIABridge = 5,
+  VMEBridge = 6,
+  OtherBridgeDevice = 0x80,
+
+  RS232Device = 0,
+  ATCompatibleParallelPort = 1,
+  OtherCommunicationsDevice = 0x80,
+
+  ProgrammableInterruptController = 0,
+  DMAController = 1,
+  SystemTimer = 2,
+  RealTimeClock = 3,
+  L2Cache = 4,
+  NVRAM = 5,
+  PowerManagement = 6,
+  CMOS = 7,
+  OperatorPanel = 8,
+  ServiceProcessorClass1 = 9,
+  ServiceProcessorClass2 = 0xA,
+  ServiceProcessorClass3 = 0xB,
+  GraphicAssist = 0xC,
+  SystemPlanar = 0xF,                   /* 10/5/95                            */
+  OtherSystemPeripheral = 0x80,
+
+  KeyboardController = 0,
+  Digitizer = 1,
+  MouseController = 2,
+  TabletController = 3,                 /* 10/27/95                           */
+  OtherInputController = 0x80,
+
+  GeneralMemoryController = 0,
+  } PnP_SUB_TYPE;
+
+/* Device Interface Type Codes */
+
+typedef enum _PnP_INTERFACE {
+  General = 0,
+  GeneralSCSI = 0,
+  GeneralIDE = 0,
+  ATACompatible = 1,
+
+  GeneralFloppy = 0,
+  Compatible765 = 1,
+  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
+                                           register at port 398 and data
+                                           register at port 399               */
+  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
+  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
+  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
+  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
+
+  GeneralIPI = 0,
+
+  GeneralEther = 0,
+  GeneralToken = 0,
+  GeneralFDDI = 0,
+
+  GeneralVGA = 0,
+  GeneralSVGA = 0,
+  GeneralXGA = 0,
+
+  GeneralVideo = 0,
+  GeneralAudio = 0,
+  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
+
+  GeneralRAM = 0,
+  GeneralFLASH = 0,
+  PCIMemoryController = 0,              /* PCI Config Method                  */
+  RS6KMemoryController = 1,             /* RS6K Config Method                 */
+
+  GeneralHostBridge = 0,
+  GeneralISABridge = 0,
+  GeneralEISABridge = 0,
+  GeneralMCABridge = 0,
+  GeneralPCIBridge = 0,
+  PCIBridgeDirect = 0,
+  PCIBridgeIndirect = 1,
+  PCIBridgeRS6K = 2,
+  GeneralPCMCIABridge = 0,
+  GeneralVMEBridge = 0,
+
+  GeneralRS232 = 0,
+  COMx = 1,
+  Compatible16450 = 2,
+  Compatible16550 = 3,
+  NS398SerPort = 4,                     /* NS Super I/O wired to use index
+                                           register at port 398 and data
+                                           register at port 399               */
+  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
+  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
+  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
+
+  GeneralParPort = 0,
+  LPTx = 1,
+  NS398ParPort = 2,                     /* NS Super I/O wired to use index
+                                           register at port 398 and data
+                                           register at port 399               */
+  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
+  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
+  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
+
+  GeneralPIC = 0,
+  ISA_PIC = 1,
+  EISA_PIC = 2,
+  MPIC = 3,
+  RS6K_PIC = 4,
+
+  GeneralDMA = 0,
+  ISA_DMA = 1,
+  EISA_DMA = 2,
+
+  GeneralTimer = 0,
+  ISA_Timer = 1,
+  EISA_Timer = 2,
+  GeneralRTC = 0,
+  ISA_RTC = 1,
+
+  StoreThruOnly = 1,
+  StoreInEnabled = 2,
+  RS6KL2Cache = 3,
+
+  IndirectNVRAM = 0,                    /* Indirectly addressed               */
+  DirectNVRAM = 1,                      /* Memory Mapped                      */
+  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
+
+  GeneralPowerManagement = 0,
+  EPOWPowerManagement = 1,
+  PowerControl = 2,                    // d1378
+
+  GeneralCMOS = 0,
+
+  GeneralOPPanel = 0,
+  HarddiskLight = 1,
+  CDROMLight = 2,
+  PowerLight = 3,
+  KeyLock = 4,
+  ANDisplay = 5,                        /* AlphaNumeric Display               */
+  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
+  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
+
+  GeneralServiceProcessor = 0,
+
+  TransferData = 1,
+  IGMC32 = 2,
+  IGMC64 = 3,
+
+  GeneralSystemPlanar = 0,              /* 10/5/95                            */
+
+  } PnP_INTERFACE;
+
+/* PnP resources */
+
+/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
+
+typedef struct _SERIAL_ID {
+  unsigned char VendorID0;              /*    Bit(7)=0                        */
+                                        /*    Bits(6:2)=1st character in      */
+                                        /*       compressed ASCII             */
+                                        /*    Bits(1:0)=2nd character in      */
+                                        /*       compressed ASCII bits(4:3)   */
+  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
+                                        /*       compressed ASCII bits(2:0)   */
+                                        /*    Bits(4:0)=3rd character in      */
+                                        /*       compressed ASCII             */
+  unsigned char VendorID2;              /* Product number - vendor assigned   */
+  unsigned char VendorID3;              /* Product number - vendor assigned   */
+
+/* Serial number is to provide uniqueness if more than one board of same      */
+/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
+
+  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
+  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
+  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
+  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
+  unsigned char Checksum;
+  } SERIAL_ID;
+
+typedef enum _PnPItemName {
+  Unused = 0,
+  PnPVersion = 1,
+  LogicalDevice = 2,
+  CompatibleDevice = 3,
+  IRQFormat = 4,
+  DMAFormat = 5,
+  StartDepFunc = 6,
+  EndDepFunc = 7,
+  IOPort = 8,
+  FixedIOPort = 9,
+  Res1 = 10,
+  Res2 = 11,
+  Res3 = 12,
+  SmallVendorItem = 14,
+  EndTag = 15,
+  MemoryRange = 1,
+  ANSIIdentifier = 2,
+  UnicodeIdentifier = 3,
+  LargeVendorItem = 4,
+  MemoryRange32 = 5,
+  MemoryRangeFixed32 = 6,
+  } PnPItemName;
+
+/* Define a bunch of access functions for the bits in the tag field */
+
+/* Tag type - 0 = small; 1 = large */
+#define tag_type(t) (((t) & 0x80)>>7)
+#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
+
+/* Small item name is 4 bits - one of PnPItemName enum above */
+#define tag_small_item_name(t) (((t) & 0x78)>>3)
+#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
+
+/* Small item count is 3 bits - count of further bytes in packet */
+#define tag_small_count(t) ((t) & 0x07)
+#define set_tag_count(t,v) (t = (t & 0x78) | (v))
+
+/* Large item name is 7 bits - one of PnPItemName enum above */
+#define tag_large_item_name(t) ((t) & 0x7f)
+#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
+
+/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
+
+typedef union _PnP_TAG_PACKET {
+  struct _S1_Pack{                      /* VERSION PACKET                     */
+    unsigned char Tag;                  /* small tag = 0x0a                   */
+    unsigned char Version[2];           /* PnP version, Vendor version        */
+    } S1_Pack;
+
+  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
+    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
+    unsigned char DevId[4];             /* Logical device id                  */
+    unsigned char Flags[2];             /* bit(0) boot device;                */
+                                        /* bit(7:1) cmd in range x31-x37      */
+                                        /* bit(7:0) cmd in range x28-x3f (opt)*/
+    } S2_Pack;
+
+  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
+    unsigned char Tag;                  /* small tag = 0x1c                   */
+    unsigned char CompatId[4];          /* Compatible device id               */
+    } S3_Pack;
+
+  struct _S4_Pack{                      /* IRQ PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
+    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
+                                        /* bit(0) is IRQ8 ...                 */
+    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
+                                        /*  bit(0) - high true edge sensitive */
+                                        /*  bit(1) - low true edge sensitive  */
+                                        /*  bit(2) - high true level sensitive*/
+                                        /*  bit(3) - low true level sensitive */
+                                        /*  bit(7:4) - must be 0              */
+    } S4_Pack;
+
+  struct _S5_Pack{                      /* DMA PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x2a                   */
+    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
+    unsigned char DMAInfo;
+    } S5_Pack;
+
+  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
+    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
+    unsigned char Priority;             /* Optional; if missing then x01; else*/
+                                        /*  x00 = best possible               */
+                                        /*  x01 = acceptible                  */
+                                        /*  x02 = sub-optimal but functional  */
+    } S6_Pack;
+
+  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
+    unsigned char Tag;                  /* small tag = 0x38                   */
+    } S7_Pack;
+
+  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
+    unsigned char Tag;                  /* small tag x47                      */
+    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
+#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
+    unsigned char RangeMin[2];          /* Min base address                   */
+    unsigned char RangeMax[2];          /* Max base address                   */
+    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
+    unsigned char IONum;                /* number of contiguous I/O ports     */
+    } S8_Pack;
+
+  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
+    unsigned char Tag;                  /* small tag = 0x4b                   */
+    unsigned char Range[2];             /* base address 10 bits               */
+    unsigned char IONum;                /* number of contiguous I/O ports     */
+    } S9_Pack;
+
+  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
+    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
+    union _S14_Data{
+      unsigned char Data[7];            /* Vendor defined                     */
+      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
+         unsigned char Type;            /* 00=non-IBM                         */
+         unsigned char PPCData[6];      /* Vendor defined                     */
+        } S14_PPCPack;
+      } S14_Data;
+    } S14_Pack;
+
+  struct _S15_Pack{                     /* END PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
+    unsigned char Check;                /* optional - checksum                */
+    } S15_Pack;
+
+  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
+    unsigned char Tag;                  /* large tag = 0x81                   */
+    unsigned char Count0;               /* x09                                */
+    unsigned char Count1;               /* x00                                */
+    unsigned char Data[9];              /* a variable array of bytes,         */
+                                        /* count in tag                       */
+    } L1_Pack;
+
+  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
+    unsigned char Tag;                  /* large tag = 0x82                   */
+    unsigned char Count0;               /* Length of string                   */
+    unsigned char Count1;
+    unsigned char Identifier[1];        /* a variable array of bytes,         */
+                                        /* count in tag                       */
+    } L2_Pack;
+
+  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
+    unsigned char Tag;                  /* large tag = 0x83                   */
+    unsigned char Count0;               /* Length + 2 of string               */
+    unsigned char Count1;
+    unsigned char Country0;             /* TBD                                */
+    unsigned char Country1;             /* TBD                                */
+    unsigned char Identifier[1];        /* a variable array of bytes,         */
+                                        /* count in tag                       */
+    } L3_Pack;
+
+  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
+    unsigned char Tag;                  /* large tag = 0x84                   */
+    unsigned char Count0;
+    unsigned char Count1;
+    union _L4_Data{
+      unsigned char Data[1];            /* a variable array of bytes,         */
+                                        /* count in tag                       */
+      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
+         unsigned char Type;            /* 00=non-IBM                         */
+         unsigned char PPCData[1];      /* a variable array of bytes,         */
+                                        /* count in tag                       */
+        } L4_PPCPack;
+      } L4_Data;
+    } L4_Pack;
+
+  struct _L5_Pack{
+    unsigned char Tag;                  /* large tag = 0x85                   */
+    unsigned char Count0;               /* Count = 17                         */
+    unsigned char Count1;
+    unsigned char Data[17];
+    } L5_Pack;
+
+  struct _L6_Pack{
+    unsigned char Tag;                  /* large tag = 0x86                   */
+    unsigned char Count0;               /* Count = 9                          */
+    unsigned char Count1;
+    unsigned char Data[9];
+    } L6_Pack;
+
+  } PnP_TAG_PACKET;
+
+#endif /* __ASSEMBLY__ */
+#endif  /* ndef _PNP_ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/poll.h b/include/asm-ppc/poll.h
new file mode 100644
index 000000000000..be5024913c62
--- /dev/null
+++ b/include/asm-ppc/poll.h
@@ -0,0 +1,23 @@
+#ifndef __PPC_POLL_H
+#define __PPC_POLL_H
+
+#define POLLIN          0x0001
+#define POLLPRI         0x0002
+#define POLLOUT         0x0004
+#define POLLERR         0x0008
+#define POLLHUP         0x0010
+#define POLLNVAL        0x0020
+#define POLLRDNORM      0x0040
+#define POLLRDBAND      0x0080
+#define POLLWRNORM      0x0100
+#define POLLWRBAND      0x0200
+#define POLLMSG         0x0400
+#define POLLREMOVE      0x1000
+
+struct pollfd {
+        int fd;
+        short events;
+        short revents;
+};
+
+#endif
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
new file mode 100644
index 000000000000..a14a82abe8d2
--- /dev/null
+++ b/include/asm-ppc/posix_types.h
@@ -0,0 +1,111 @@
+#ifndef _PPC_POSIX_TYPES_H
+#define _PPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+typedef unsigned short  __kernel_nlink_t;
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef int             __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+typedef short             __kernel_ipc_pid_t;
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+
+typedef unsigned int    __kernel_old_uid_t;
+typedef unsigned int    __kernel_old_gid_t;
+typedef unsigned int    __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long       __kernel_loff_t;
+#endif
+
+typedef struct {
+        int     val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define __FD_ZERO(set)  \
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+        unsigned long _tmp = fd / __NFDBITS;
+        unsigned long _rem = fd % __NFDBITS;
+        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+        unsigned int *tmp = (unsigned int *)p->fds_bits;
+        int i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                        case 8:
+                                tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+                                tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+                                return;
+                }
+        }
+        i = __FDSET_LONGS;
+        while (i) {
+                i--;
+                *tmp = 0;
+                tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h
new file mode 100644
index 000000000000..8636cdbf6f8f
--- /dev/null
+++ b/include/asm-ppc/ppc4xx_dma.h
@@ -0,0 +1,583 @@
+/*
+ * include/asm-ppc/ppc4xx_dma.h
+ *
+ * IBM PPC4xx DMA engine library
+ *
+ * Copyright 2000-2004 MontaVista Software Inc.
+ *
+ * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org>
+ *
+ * Original code by Armin Kuster <akuster@mvista.com>
+ * and Pete Popov <ppopov@mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASMPPC_PPC4xx_DMA_H
+#define __ASMPPC_PPC4xx_DMA_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/mmu.h>
+#include <asm/ibm4xx.h>
+
+#undef DEBUG_4xxDMA
+
+#define MAX_PPC4xx_DMA_CHANNELS         4
+
+/* in arch/ppc/kernel/setup.c -- Cort */
+extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
+
+/*
+ * Function return status codes
+ * These values are used to indicate whether or not the function
+ * call was successful, or a bad/invalid parameter was passed.
+ */
+#define DMA_STATUS_GOOD                 0
+#define DMA_STATUS_BAD_CHANNEL          1
+#define DMA_STATUS_BAD_HANDLE           2
+#define DMA_STATUS_BAD_MODE             3
+#define DMA_STATUS_NULL_POINTER         4
+#define DMA_STATUS_OUT_OF_MEMORY        5
+#define DMA_STATUS_SGL_LIST_EMPTY       6
+#define DMA_STATUS_GENERAL_ERROR        7
+#define DMA_STATUS_CHANNEL_NOTFREE      8
+
+#define DMA_CHANNEL_BUSY                0x80000000
+
+/*
+ * These indicate status as returned from the DMA Status Register.
+ */
+#define DMA_STATUS_NO_ERROR     0
+#define DMA_STATUS_CS           1       /* Count Status        */
+#define DMA_STATUS_TS           2       /* Transfer Status     */
+#define DMA_STATUS_DMA_ERROR    3       /* DMA Error Occurred  */
+#define DMA_STATUS_DMA_BUSY     4       /* The channel is busy */
+
+
+/*
+ * DMA Channel Control Registers
+ */
+
+#ifdef CONFIG_44x
+#define PPC4xx_DMA_64BIT
+#define DMA_CR_OFFSET 1
+#else
+#define DMA_CR_OFFSET 0
+#endif
+
+#define DMA_CE_ENABLE        (1<<31)    /* DMA Channel Enable */
+#define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31)
+#define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31)
+
+#define DMA_CIE_ENABLE        (1<<30)   /* DMA Channel Interrupt Enable */
+#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
+#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
+
+#define DMA_TD                (1<<29)
+#define SET_DMA_TD(x)         (((x)&0x1)<<29)
+#define GET_DMA_TD(x)         (((x)&DMA_TD)>>29)
+
+#define DMA_PL                (1<<28)   /* Peripheral Location */
+#define SET_DMA_PL(x)         (((x)&0x1)<<28)
+#define GET_DMA_PL(x)         (((x)&DMA_PL)>>28)
+
+#define EXTERNAL_PERIPHERAL    0
+#define INTERNAL_PERIPHERAL    1
+
+#define SET_DMA_PW(x)     (((x)&0x3)<<(26-DMA_CR_OFFSET))       /* Peripheral Width */
+#define DMA_PW_MASK       SET_DMA_PW(3)
+#define   PW_8                 0
+#define   PW_16                1
+#define   PW_32                2
+#define   PW_64                3
+/* FIXME: Add PW_128 support for 440GP DMA block */
+#define GET_DMA_PW(x)     (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET))
+
+#define DMA_DAI           (1<<(25-DMA_CR_OFFSET))       /* Destination Address Increment */
+#define SET_DMA_DAI(x)    (((x)&0x1)<<(25-DMA_CR_OFFSET))
+
+#define DMA_SAI           (1<<(24-DMA_CR_OFFSET))       /* Source Address Increment */
+#define SET_DMA_SAI(x)    (((x)&0x1)<<(24-DMA_CR_OFFSET))
+
+#define DMA_BEN           (1<<(23-DMA_CR_OFFSET))       /* Buffer Enable */
+#define SET_DMA_BEN(x)    (((x)&0x1)<<(23-DMA_CR_OFFSET))
+
+#define SET_DMA_TM(x)     (((x)&0x3)<<(21-DMA_CR_OFFSET))       /* Transfer Mode */
+#define DMA_TM_MASK       SET_DMA_TM(3)
+#define   TM_PERIPHERAL        0        /* Peripheral */
+#define   TM_RESERVED          1        /* Reserved */
+#define   TM_S_MM              2        /* Memory to Memory */
+#define   TM_D_MM              3        /* Device Paced Memory to Memory */
+#define GET_DMA_TM(x)     (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET))
+
+#define SET_DMA_PSC(x)    (((x)&0x3)<<(19-DMA_CR_OFFSET))       /* Peripheral Setup Cycles */
+#define DMA_PSC_MASK      SET_DMA_PSC(3)
+#define GET_DMA_PSC(x)    (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET))
+
+#define SET_DMA_PWC(x)    (((x)&0x3F)<<(13-DMA_CR_OFFSET))      /* Peripheral Wait Cycles */
+#define DMA_PWC_MASK      SET_DMA_PWC(0x3F)
+#define GET_DMA_PWC(x)    (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET))
+
+#define SET_DMA_PHC(x)    (((x)&0x7)<<(10-DMA_CR_OFFSET))       /* Peripheral Hold Cycles */
+#define DMA_PHC_MASK      SET_DMA_PHC(0x7)
+#define GET_DMA_PHC(x)    (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET))
+
+#define DMA_ETD_OUTPUT     (1<<(9-DMA_CR_OFFSET))       /* EOT pin is a TC output */
+#define SET_DMA_ETD(x)     (((x)&0x1)<<(9-DMA_CR_OFFSET))
+
+#define DMA_TCE_ENABLE     (1<<(8-DMA_CR_OFFSET))
+#define SET_DMA_TCE(x)     (((x)&0x1)<<(8-DMA_CR_OFFSET))
+
+#define DMA_DEC            (1<<(2))     /* Address Decrement */
+#define SET_DMA_DEC(x)     (((x)&0x1)<<2)
+#define GET_DMA_DEC(x)     (((x)&DMA_DEC)>>2)
+
+
+/*
+ * Transfer Modes
+ * These modes are defined in a way that makes it possible to
+ * simply "or" in the value in the control register.
+ */
+
+#define DMA_MODE_MM             (SET_DMA_TM(TM_S_MM))   /* memory to memory */
+
+                                /* Device-paced memory to memory, */
+                                /* device is at source address    */
+#define DMA_MODE_MM_DEVATSRC    (DMA_TD | SET_DMA_TM(TM_D_MM))
+
+                                /* Device-paced memory to memory,      */
+                                /* device is at destination address    */
+#define DMA_MODE_MM_DEVATDST    (SET_DMA_TM(TM_D_MM))
+
+/* 405gp/440gp */
+#define SET_DMA_PREFETCH(x)   (((x)&0x3)<<(4-DMA_CR_OFFSET))    /* Memory Read Prefetch */
+#define DMA_PREFETCH_MASK      SET_DMA_PREFETCH(3)
+#define   PREFETCH_1           0        /* Prefetch 1 Double Word */
+#define   PREFETCH_2           1
+#define   PREFETCH_4           2
+#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET))
+
+#define DMA_PCE            (1<<(3-DMA_CR_OFFSET))       /* Parity Check Enable */
+#define SET_DMA_PCE(x)     (((x)&0x1)<<(3-DMA_CR_OFFSET))
+#define GET_DMA_PCE(x)     (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET))
+
+/* stb3x */
+
+#define DMA_ECE_ENABLE (1<<5)
+#define SET_DMA_ECE(x) (((x)&0x1)<<5)
+#define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5)
+
+#define DMA_TCD_DISABLE (1<<4)
+#define SET_DMA_TCD(x) (((x)&0x1)<<4)
+#define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4)
+
+typedef uint32_t sgl_handle_t;
+
+#ifdef CONFIG_PPC4xx_EDMA
+
+#define SGL_LIST_SIZE 4096
+#define DMA_PPC4xx_SIZE SGL_LIST_SIZE
+
+#define SET_DMA_PRIORITY(x)   (((x)&0x3)<<(6-DMA_CR_OFFSET))    /* DMA Channel Priority */
+#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
+#define PRIORITY_LOW           0
+#define PRIORITY_MID_LOW       1
+#define PRIORITY_MID_HIGH      2
+#define PRIORITY_HIGH          3
+#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET))
+
+/*
+ * DMA Polarity Configuration Register
+ */
+#define DMAReq_ActiveLow(chan) (1<<(31-(chan*3)))
+#define DMAAck_ActiveLow(chan) (1<<(30-(chan*3)))
+#define EOT_ActiveLow(chan)    (1<<(29-(chan*3)))       /* End of Transfer */
+
+/*
+ * DMA Sleep Mode Register
+ */
+#define SLEEP_MODE_ENABLE (1<<21)
+
+/*
+ * DMA Status Register
+ */
+#define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
+#define DMA_CS1           (1<<30)
+#define DMA_CS2           (1<<29)
+#define DMA_CS3           (1<<28)
+
+#define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
+#define DMA_TS1           (1<<26)
+#define DMA_TS2           (1<<25)
+#define DMA_TS3           (1<<24)
+
+#define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
+#define DMA_CH1_ERR       (1<<22)
+#define DMA_CH2_ERR       (1<<21)
+#define DMA_CH3_ERR       (1<<20)
+
+#define DMA_IN_DMA_REQ0   (1<<19)       /* Internal DMA Request is pending */
+#define DMA_IN_DMA_REQ1   (1<<18)
+#define DMA_IN_DMA_REQ2   (1<<17)
+#define DMA_IN_DMA_REQ3   (1<<16)
+
+#define DMA_EXT_DMA_REQ0  (1<<15)       /* External DMA Request is pending */
+#define DMA_EXT_DMA_REQ1  (1<<14)
+#define DMA_EXT_DMA_REQ2  (1<<13)
+#define DMA_EXT_DMA_REQ3  (1<<12)
+
+#define DMA_CH0_BUSY      (1<<11)       /* DMA Channel 0 Busy */
+#define DMA_CH1_BUSY      (1<<10)
+#define DMA_CH2_BUSY       (1<<9)
+#define DMA_CH3_BUSY       (1<<8)
+
+#define DMA_SG0            (1<<7)       /* DMA Channel 0 Scatter/Gather in progress */
+#define DMA_SG1            (1<<6)
+#define DMA_SG2            (1<<5)
+#define DMA_SG3            (1<<4)
+
+/* DMA Channel Count Register */
+#define DMA_CTC_BTEN     (1<<23)    /* Burst Enable/Disable bit */
+#define DMA_CTC_BSIZ_MSK (3<<21)    /* Mask of the Burst size bits */
+#define DMA_CTC_BSIZ_2   (0)
+#define DMA_CTC_BSIZ_4   (1<<21)
+#define DMA_CTC_BSIZ_8   (2<<21)
+#define DMA_CTC_BSIZ_16  (3<<21)
+
+/*
+ * DMA SG Command Register
+ */
+#define SSG_ENABLE(chan)        (1<<(31-chan))  /* Start Scatter Gather */
+#define SSG_MASK_ENABLE(chan)   (1<<(15-chan))  /* Enable writing to SSG0 bit */
+
+/*
+ * DMA Scatter/Gather Descriptor Bit fields
+ */
+#define SG_LINK            (1<<31)      /* Link */
+#define SG_TCI_ENABLE      (1<<29)      /* Enable Terminal Count Interrupt */
+#define SG_ETI_ENABLE      (1<<28)      /* Enable End of Transfer Interrupt */
+#define SG_ERI_ENABLE      (1<<27)      /* Enable Error Interrupt */
+#define SG_COUNT_MASK       0xFFFF      /* Count Field */
+
+#define SET_DMA_CONTROL \
+                (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable         */ \
+                SET_DMA_BEN(p_init->buffer_enable)     | /* buffer enable            */\
+                SET_DMA_ETD(p_init->etd_output)        | /* end of transfer pin      */ \
+                SET_DMA_TCE(p_init->tce_enable)        | /* terminal count enable    */ \
+                SET_DMA_PL(p_init->pl)                 | /* peripheral location      */ \
+                SET_DMA_DAI(p_init->dai)               | /* dest addr increment      */ \
+                SET_DMA_SAI(p_init->sai)               | /* src addr increment       */ \
+                SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */ \
+                SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
+                SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
+                SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
+                SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
+                SET_DMA_PREFETCH(p_init->pf)              /* read prefetch           */)
+
+#define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
+
+#elif defined(CONFIG_STBXXX_DMA)                /* stb03xxx */
+
+#define DMA_PPC4xx_SIZE 4096
+
+/*
+ * DMA Status Register
+ */
+
+#define SET_DMA_PRIORITY(x)   (((x)&0x00800001))        /* DMA Channel Priority */
+#define DMA_PRIORITY_MASK       0x00800001
+#define   PRIORITY_LOW          0x00000000
+#define   PRIORITY_MID_LOW      0x00000001
+#define   PRIORITY_MID_HIGH     0x00800000
+#define   PRIORITY_HIGH         0x00800001
+#define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001))
+
+#define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
+#define DMA_CS1           (1<<30)
+#define DMA_CS2           (1<<29)
+#define DMA_CS3           (1<<28)
+
+#define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
+#define DMA_TS1           (1<<26)
+#define DMA_TS2           (1<<25)
+#define DMA_TS3           (1<<24)
+
+#define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
+#define DMA_CH1_ERR       (1<<22)
+#define DMA_CH2_ERR       (1<<21)
+#define DMA_CH3_ERR       (1<<20)
+
+#define DMA_CT0           (1<<19)       /* Chained transfere */
+
+#define DMA_IN_DMA_REQ0   (1<<18)       /* Internal DMA Request is pending */
+#define DMA_IN_DMA_REQ1   (1<<17)
+#define DMA_IN_DMA_REQ2   (1<<16)
+#define DMA_IN_DMA_REQ3   (1<<15)
+
+#define DMA_EXT_DMA_REQ0  (1<<14)       /* External DMA Request is pending */
+#define DMA_EXT_DMA_REQ1  (1<<13)
+#define DMA_EXT_DMA_REQ2  (1<<12)
+#define DMA_EXT_DMA_REQ3  (1<<11)
+
+#define DMA_CH0_BUSY      (1<<10)       /* DMA Channel 0 Busy */
+#define DMA_CH1_BUSY      (1<<9)
+#define DMA_CH2_BUSY       (1<<8)
+#define DMA_CH3_BUSY       (1<<7)
+
+#define DMA_CT1            (1<<6)       /* Chained transfere */
+#define DMA_CT2            (1<<5)
+#define DMA_CT3            (1<<4)
+
+#define DMA_CH_ENABLE (1<<7)
+#define SET_DMA_CH(x) (((x)&0x1)<<7)
+#define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7)
+
+/* STBx25xxx dma unique */
+/* enable device port on a dma channel
+ * example ext 0 on dma 1
+ */
+
+#define SSP0_RECV       15
+#define SSP0_XMIT       14
+#define EXT_DMA_0       12
+#define SC1_XMIT        11
+#define SC1_RECV        10
+#define EXT_DMA_2       9
+#define EXT_DMA_3       8
+#define SERIAL2_XMIT    7
+#define SERIAL2_RECV    6
+#define SC0_XMIT        5
+#define SC0_RECV        4
+#define SERIAL1_XMIT    3
+#define SERIAL1_RECV    2
+#define SERIAL0_XMIT    1
+#define SERIAL0_RECV    0
+
+#define DMA_CHAN_0      1
+#define DMA_CHAN_1      2
+#define DMA_CHAN_2      3
+#define DMA_CHAN_3      4
+
+/* end STBx25xx */
+
+/*
+ * Bit 30 must be one for Redwoods, otherwise transfers may receive errors.
+ */
+#define DMA_CR_MB0 0x2
+
+#define SET_DMA_CONTROL \
+                (SET_DMA_CIE_ENABLE(p_init->int_enable) |  /* interrupt enable         */ \
+                SET_DMA_ETD(p_init->etd_output)        |  /* end of transfer pin      */ \
+                SET_DMA_TCE(p_init->tce_enable)        |  /* terminal count enable    */ \
+                SET_DMA_PL(p_init->pl)                 |  /* peripheral location      */ \
+                SET_DMA_DAI(p_init->dai)               |  /* dest addr increment      */ \
+                SET_DMA_SAI(p_init->sai)               |  /* src addr increment       */ \
+                SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */  \
+                SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
+                SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
+                SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
+                SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
+                SET_DMA_TCD(p_init->tcd_disable)          |  /* TC chain mode disable   */ \
+                SET_DMA_ECE(p_init->ece_enable)   |  /* ECE chanin mode enable  */ \
+                SET_DMA_CH(p_init->ch_enable)   |    /* Chain enable            */ \
+                DMA_CR_MB0                              /* must be one */)
+
+#define GET_DMA_POLARITY(chan) chan
+
+#endif
+
+typedef struct {
+        unsigned short in_use;  /* set when channel is being used, clr when
+                                 * available.
+                                 */
+        /*
+         * Valid polarity settings:
+         *   DMAReq_ActiveLow(n)
+         *   DMAAck_ActiveLow(n)
+         *   EOT_ActiveLow(n)
+         *
+         *   n is 0 to max dma chans
+         */
+        unsigned int polarity;
+
+        char buffer_enable;     /* Boolean: buffer enable            */
+        char tce_enable;        /* Boolean: terminal count enable    */
+        char etd_output;        /* Boolean: eot pin is a tc output   */
+        char pce;               /* Boolean: parity check enable      */
+
+        /*
+         * Peripheral location:
+         * INTERNAL_PERIPHERAL (UART0 on the 405GP)
+         * EXTERNAL_PERIPHERAL
+         */
+        char pl;                /* internal/external peripheral      */
+
+        /*
+         * Valid pwidth settings:
+         *   PW_8
+         *   PW_16
+         *   PW_32
+         *   PW_64
+         */
+        unsigned int pwidth;
+
+        char dai;               /* Boolean: dst address increment   */
+        char sai;               /* Boolean: src address increment   */
+
+        /*
+         * Valid psc settings: 0-3
+         */
+        unsigned int psc;       /* Peripheral Setup Cycles         */
+
+        /*
+         * Valid pwc settings:
+         * 0-63
+         */
+        unsigned int pwc;       /* Peripheral Wait Cycles          */
+
+        /*
+         * Valid phc settings:
+         * 0-7
+         */
+        unsigned int phc;       /* Peripheral Hold Cycles          */
+
+        /*
+         * Valid cp (channel priority) settings:
+         *   PRIORITY_LOW
+         *   PRIORITY_MID_LOW
+         *   PRIORITY_MID_HIGH
+         *   PRIORITY_HIGH
+         */
+        unsigned int cp;        /* channel priority                */
+
+        /*
+         * Valid pf (memory read prefetch) settings:
+         *
+         *   PREFETCH_1
+         *   PREFETCH_2
+         *   PREFETCH_4
+         */
+        unsigned int pf;        /* memory read prefetch            */
+
+        /*
+         * Boolean: channel interrupt enable
+         * NOTE: for sgl transfers, only the last descriptor will be setup to
+         * interrupt.
+         */
+        char int_enable;
+
+        char shift;             /* easy access to byte_count shift, based on */
+        /* the width of the channel                  */
+
+        uint32_t control;       /* channel control word                      */
+
+        /* These variabled are used ONLY in single dma transfers              */
+        unsigned int mode;      /* transfer mode                     */
+        phys_addr_t addr;
+        char ce;                /* channel enable */
+#ifdef CONFIG_STB03xxx
+        char ch_enable;
+        char tcd_disable;
+        char ece_enable;
+        char td;                /* transfer direction */
+#endif
+
+        char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */
+} ppc_dma_ch_t;
+
+/*
+ * PPC44x DMA implementations have a slightly different
+ * descriptor layout.  Probably moved about due to the
+ * change to 64-bit addresses and link pointer. I don't
+ * know why they didn't just leave control_count after
+ * the dst_addr.
+ */
+#ifdef PPC4xx_DMA_64BIT
+typedef struct {
+        uint32_t control;
+        uint32_t control_count;
+        phys_addr_t src_addr;
+        phys_addr_t dst_addr;
+        phys_addr_t next;
+} ppc_sgl_t;
+#else
+typedef struct {
+        uint32_t control;
+        phys_addr_t src_addr;
+        phys_addr_t dst_addr;
+        uint32_t control_count;
+        uint32_t next;
+} ppc_sgl_t;
+#endif
+
+typedef struct {
+        unsigned int dmanr;
+        uint32_t control;       /* channel ctrl word; loaded from each descrptr */
+        uint32_t sgl_control;   /* LK, TCI, ETI, and ERI bits in sgl descriptor */
+        dma_addr_t dma_addr;    /* dma (physical) address of this list          */
+        ppc_sgl_t *phead;
+        dma_addr_t phead_dma;
+        ppc_sgl_t *ptail;
+        dma_addr_t ptail_dma;
+} sgl_list_info_t;
+
+typedef struct {
+        phys_addr_t *src_addr;
+        phys_addr_t *dst_addr;
+        phys_addr_t dma_src_addr;
+        phys_addr_t dma_dst_addr;
+} pci_alloc_desc_t;
+
+extern ppc_dma_ch_t dma_channels[];
+
+/*
+ * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c
+ */
+extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *);
+extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *);
+extern int ppc4xx_set_channel_priority(unsigned int, unsigned int);
+extern unsigned int ppc4xx_get_peripheral_width(unsigned int);
+extern void ppc4xx_set_sg_addr(int, phys_addr_t);
+extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int);
+extern void ppc4xx_enable_dma_sgl(sgl_handle_t);
+extern void ppc4xx_disable_dma_sgl(sgl_handle_t);
+extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *);
+extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *);
+extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
+extern void ppc4xx_free_dma_handle(sgl_handle_t);
+extern int ppc4xx_get_dma_status(void);
+extern int ppc4xx_enable_burst(unsigned int);
+extern int ppc4xx_disable_burst(unsigned int);
+extern int ppc4xx_set_burst_size(unsigned int, unsigned int);
+extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
+extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
+extern void ppc4xx_enable_dma(unsigned int dmanr);
+extern void ppc4xx_disable_dma(unsigned int dmanr);
+extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count);
+extern int ppc4xx_get_dma_residue(unsigned int dmanr);
+extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
+                                 phys_addr_t dst_dma_addr);
+extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr);
+extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr);
+extern int ppc4xx_clr_dma_status(unsigned int dmanr);
+extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
+extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
+extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode);
+
+/* These are in kernel/dma.c: */
+
+/* reserve a DMA channel */
+extern int request_dma(unsigned int dmanr, const char *device_id);
+/* release it again */
+extern void free_dma(unsigned int dmanr);
+#endif
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h
new file mode 100644
index 000000000000..c16c7f81cfd8
--- /dev/null
+++ b/include/asm-ppc/ppc4xx_pic.h
@@ -0,0 +1,53 @@
+/*
+ * include/asm-ppc/ppc4xx_pic.h
+ *
+ * Interrupt controller driver for PowerPC 4xx-based processors.
+ *
+ * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PPC4XX_PIC_H__
+#define __PPC4XX_PIC_H__
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+
+/* "Fixed" UIC settings (they are chip, not board specific),
+ * e.g. polarity/triggerring for internal interrupt sources.
+ *
+ * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg
+ * with these "fixed" settings: .polarity contains exact value which will
+ * be written (masked with "ext_irq_mask") into UICx_PR register,
+ * .triggering - to UICx_TR.
+ *
+ * Settings for external IRQs can be specified separately by the
+ * board support code. In this case properly sized array of unsigned
+ * char named ppc4xx_uic_ext_irq_cfg should be filled with correct
+ * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines.
+ *
+ * If these arrays aren't provided, UIC initialization code keeps firmware
+ * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg
+ * is defined.
+ *
+ * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as
+ * "weak" symbols in ppc4xx_pic.c
+ *
+ */
+struct ppc4xx_uic_settings {
+        u32 polarity;
+        u32 triggering;
+        u32 ext_irq_mask;
+};
+
+extern void ppc4xx_pic_init(void);
+
+#endif                          /* __PPC4XX_PIC_H__ */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
new file mode 100644
index 000000000000..13fa8e7483c1
--- /dev/null
+++ b/include/asm-ppc/ppc_asm.h
@@ -0,0 +1,342 @@
+/*
+ * include/asm-ppc/ppc_asm.h
+ *
+ * Definitions used by various bits of low-level assembly code on PowerPC.
+ *
+ * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
+#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
+#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
+                                SAVE_10GPRS(22, base)
+#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
+                                REST_10GPRS(22, base)
+
+#define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
+#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
+#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
+#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
+#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
+#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
+#define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
+#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
+#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
+#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
+#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
+#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
+
+#define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
+#define SAVE_2VR(n,b,base)      SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
+#define SAVE_4VR(n,b,base)      SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
+#define SAVE_8VR(n,b,base)      SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
+#define SAVE_16VR(n,b,base)     SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
+#define SAVE_32VR(n,b,base)     SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
+#define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
+#define REST_2VR(n,b,base)      REST_VR(n,b,base); REST_VR(n+1,b,base)
+#define REST_4VR(n,b,base)      REST_2VR(n,b,base); REST_2VR(n+2,b,base)
+#define REST_8VR(n,b,base)      REST_4VR(n,b,base); REST_4VR(n+4,b,base)
+#define REST_16VR(n,b,base)     REST_8VR(n,b,base); REST_8VR(n+8,b,base)
+#define REST_32VR(n,b,base)     REST_16VR(n,b,base); REST_16VR(n+16,b,base)
+
+#define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
+#define SAVE_2EVR(n,s,base)     SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
+#define SAVE_4EVR(n,s,base)     SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
+#define SAVE_8EVR(n,s,base)     SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
+#define SAVE_16EVR(n,s,base)    SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
+#define SAVE_32EVR(n,s,base)    SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
+
+#define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
+#define REST_2EVR(n,s,base)     REST_EVR(n,s,base); REST_EVR(n+1,s,base)
+#define REST_4EVR(n,s,base)     REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
+#define REST_8EVR(n,s,base)     REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
+#define REST_16EVR(n,s,base)    REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
+#define REST_32EVR(n,s,base)    REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
+
+#ifdef CONFIG_PPC601_SYNC_FIX
+#define SYNC                            \
+BEGIN_FTR_SECTION                       \
+        sync;                           \
+        isync;                          \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define SYNC_601                        \
+BEGIN_FTR_SECTION                       \
+        sync;                           \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#define ISYNC_601                       \
+BEGIN_FTR_SECTION                       \
+        isync;                          \
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+#else
+#define SYNC
+#define SYNC_601
+#define ISYNC_601
+#endif
+
+#ifndef CONFIG_SMP
+#define TLBSYNC
+#else /* CONFIG_SMP */
+/* tlbsync is not implemented on 601 */
+#define TLBSYNC                         \
+BEGIN_FTR_SECTION                       \
+        tlbsync;                        \
+        sync;                           \
+END_FTR_SECTION_IFCLR(CPU_FTR_601)
+#endif
+
+/*
+ * This instruction is not implemented on the PPC 603 or 601; however, on
+ * the 403GCX and 405GP tlbia IS defined and tlbie is not.
+ * All of these instructions exist in the 8xx, they have magical powers,
+ * and they must be used.
+ */
+
+#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
+#define tlbia                                   \
+        li      r4,1024;                        \
+        mtctr   r4;                             \
+        lis     r4,KERNELBASE@h;                \
+0:      tlbie   r4;                             \
+        addi    r4,r4,0x1000;                   \
+        bdnz    0b
+#endif
+
+#ifdef CONFIG_BOOKE
+#define tophys(rd,rs)                           \
+        addis   rd,rs,0
+
+#define tovirt(rd,rs)                           \
+        addis   rd,rs,0
+
+#else  /* CONFIG_BOOKE */
+/*
+ * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
+ * physical base address of RAM at compile time.
+ */
+#define tophys(rd,rs)                           \
+0:      addis   rd,rs,-KERNELBASE@h;            \
+        .section ".vtop_fixup","aw";            \
+        .align  1;                              \
+        .long   0b;                             \
+        .previous
+
+#define tovirt(rd,rs)                           \
+0:      addis   rd,rs,KERNELBASE@h;             \
+        .section ".ptov_fixup","aw";            \
+        .align  1;                              \
+        .long   0b;                             \
+        .previous
+#endif  /* CONFIG_BOOKE */
+
+/*
+ * On 64-bit cpus, we use the rfid instruction instead of rfi, but
+ * we then have to make sure we preserve the top 32 bits except for
+ * the 64-bit mode bit, which we clear.
+ */
+#ifdef CONFIG_PPC64BRIDGE
+#define FIX_SRR1(ra, rb)        \
+        mr      rb,ra;          \
+        mfmsr   ra;             \
+        clrldi  ra,ra,1;                /* turn off 64-bit mode */ \
+        rldimi  ra,rb,0,32
+#define RFI             .long   0x4c000024      /* rfid instruction */
+#define MTMSRD(r)       .long   (0x7c000164 + ((r) << 21))      /* mtmsrd */
+#define CLR_TOP32(r)    rlwinm  (r),(r),0,0,31  /* clear top 32 bits */
+
+#else
+#define FIX_SRR1(ra, rb)
+#ifndef CONFIG_40x
+#define RFI             rfi
+#else
+#define RFI             rfi; b .        /* Prevent prefetch past rfi */
+#endif
+#define MTMSRD(r)       mtmsr   r
+#define CLR_TOP32(r)
+#endif /* CONFIG_PPC64BRIDGE */
+
+#define RFMCI           .long 0x4c00004c        /* rfmci instruction */
+
+#ifdef CONFIG_IBM405_ERR77
+#define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
+#define PPC405_ERR77_SYNC       sync;
+#else
+#define PPC405_ERR77(ra,rb)
+#define PPC405_ERR77_SYNC
+#endif
+
+/* The boring bits... */
+
+/* Condition Register Bit Fields */
+
+#define cr0     0
+#define cr1     1
+#define cr2     2
+#define cr3     3
+#define cr4     4
+#define cr5     5
+#define cr6     6
+#define cr7     7
+
+
+/* General Purpose Registers (GPRs) */
+
+#define r0      0
+#define r1      1
+#define r2      2
+#define r3      3
+#define r4      4
+#define r5      5
+#define r6      6
+#define r7      7
+#define r8      8
+#define r9      9
+#define r10     10
+#define r11     11
+#define r12     12
+#define r13     13
+#define r14     14
+#define r15     15
+#define r16     16
+#define r17     17
+#define r18     18
+#define r19     19
+#define r20     20
+#define r21     21
+#define r22     22
+#define r23     23
+#define r24     24
+#define r25     25
+#define r26     26
+#define r27     27
+#define r28     28
+#define r29     29
+#define r30     30
+#define r31     31
+
+
+/* Floating Point Registers (FPRs) */
+
+#define fr0     0
+#define fr1     1
+#define fr2     2
+#define fr3     3
+#define fr4     4
+#define fr5     5
+#define fr6     6
+#define fr7     7
+#define fr8     8
+#define fr9     9
+#define fr10    10
+#define fr11    11
+#define fr12    12
+#define fr13    13
+#define fr14    14
+#define fr15    15
+#define fr16    16
+#define fr17    17
+#define fr18    18
+#define fr19    19
+#define fr20    20
+#define fr21    21
+#define fr22    22
+#define fr23    23
+#define fr24    24
+#define fr25    25
+#define fr26    26
+#define fr27    27
+#define fr28    28
+#define fr29    29
+#define fr30    30
+#define fr31    31
+
+#define vr0     0
+#define vr1     1
+#define vr2     2
+#define vr3     3
+#define vr4     4
+#define vr5     5
+#define vr6     6
+#define vr7     7
+#define vr8     8
+#define vr9     9
+#define vr10    10
+#define vr11    11
+#define vr12    12
+#define vr13    13
+#define vr14    14
+#define vr15    15
+#define vr16    16
+#define vr17    17
+#define vr18    18
+#define vr19    19
+#define vr20    20
+#define vr21    21
+#define vr22    22
+#define vr23    23
+#define vr24    24
+#define vr25    25
+#define vr26    26
+#define vr27    27
+#define vr28    28
+#define vr29    29
+#define vr30    30
+#define vr31    31
+
+#define evr0    0
+#define evr1    1
+#define evr2    2
+#define evr3    3
+#define evr4    4
+#define evr5    5
+#define evr6    6
+#define evr7    7
+#define evr8    8
+#define evr9    9
+#define evr10   10
+#define evr11   11
+#define evr12   12
+#define evr13   13
+#define evr14   14
+#define evr15   15
+#define evr16   16
+#define evr17   17
+#define evr18   18
+#define evr19   19
+#define evr20   20
+#define evr21   21
+#define evr22   22
+#define evr23   23
+#define evr24   24
+#define evr25   25
+#define evr26   26
+#define evr27   27
+#define evr28   28
+#define evr29   29
+#define evr30   30
+#define evr31   31
+
+/* some stab codes */
+#define N_FUN   36
+#define N_RSYM  64
+#define N_SLINE 68
+#define N_SO    100
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
new file mode 100644
index 000000000000..24b991c42769
--- /dev/null
+++ b/include/asm-ppc/ppc_sys.h
@@ -0,0 +1,69 @@
+/*
+ * include/asm-ppc/ppc_sys.h
+ *
+ * PPC system definitions and library functions
+ *
+ * Maintainer: Kumar Gala <kumar.gala@freescale.com>
+ *
+ * Copyright 2005 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_SYS_H
+#define __ASM_PPC_SYS_H
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/types.h>
+
+#if defined(CONFIG_83xx)
+#include <asm/mpc83xx.h>
+#elif defined(CONFIG_85xx)
+#include <asm/mpc85xx.h>
+#elif defined(CONFIG_PPC_MPC52xx)
+#include <asm/mpc52xx.h>
+#else
+#error "need definition of ppc_sys_devices"
+#endif
+
+struct ppc_sys_spec {
+        /* PPC sys is matched via (ID & mask) == value, id could be
+         * PVR, SVR, IMMR, * etc. */
+        u32                     mask;
+        u32                     value;
+        u32                     num_devices;
+        char                    *ppc_sys_name;
+        enum ppc_sys_devices    *device_list;
+};
+
+/* describes all specific chips and which devices they have on them */
+extern struct ppc_sys_spec ppc_sys_specs[];
+extern struct ppc_sys_spec *cur_ppc_sys_spec;
+
+/* determine which specific SOC we are */
+extern void identify_ppc_sys_by_id(u32 id) __init;
+extern void identify_ppc_sys_by_name(char *name) __init;
+
+/* describes all devices that may exist in a given family of processors */
+extern struct platform_device ppc_sys_platform_devices[];
+
+/* allow any platform_device fixup to occur before device is registered */
+extern int (*ppc_sys_device_fixup) (struct platform_device * pdev);
+
+/* Update all memory resources by paddr, call before platform_device_register */
+extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev,
+                                       phys_addr_t paddr) __init;
+
+/* Get platform_data pointer out of platform device, call before platform_device_register */
+extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init;
+
+/* remove a device from the system */
+extern void ppc_sys_device_remove(enum ppc_sys_devices dev);
+
+#endif                          /* __ASM_PPC_SYS_H */
+#endif                          /* __KERNEL__ */
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h
new file mode 100644
index 000000000000..fe24e4520208
--- /dev/null
+++ b/include/asm-ppc/ppcboot.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_PPCBOOT_H__
+#define __ASM_PPCBOOT_H__
+
+/*
+ * Board information passed to kernel from PPCBoot
+ *
+ * include/asm-ppc/ppcboot.h
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+typedef struct bd_info {
+        unsigned long   bi_memstart;    /* start of DRAM memory */
+        unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
+        unsigned long   bi_flashstart;  /* start of FLASH memory */
+        unsigned long   bi_flashsize;   /* size  of FLASH memory */
+        unsigned long   bi_flashoffset; /* reserved area for startup monitor */
+        unsigned long   bi_sramstart;   /* start of SRAM memory */
+        unsigned long   bi_sramsize;    /* size  of SRAM memory */
+#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\
+        defined(CONFIG_83xx)
+        unsigned long   bi_immr_base;   /* base of IMMR register */
+#endif
+#if defined(CONFIG_PPC_MPC52xx)
+        unsigned long   bi_mbar_base;   /* base of internal registers */
+#endif
+        unsigned long   bi_bootflags;   /* boot / reboot flag (for LynxOS) */
+        unsigned long   bi_ip_addr;     /* IP Address */
+        unsigned char   bi_enetaddr[6]; /* Ethernet address */
+        unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
+        unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
+        unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+        unsigned long   bi_cpmfreq;     /* CPM_CLK Freq, in MHz */
+        unsigned long   bi_brgfreq;     /* BRG_CLK Freq, in MHz */
+        unsigned long   bi_sccfreq;     /* SCC_CLK Freq, in MHz */
+        unsigned long   bi_vco;         /* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_PPC_MPC52xx)
+        unsigned long   bi_ipbfreq;     /* IPB Bus Freq, in MHz */
+        unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
+#endif
+        unsigned long   bi_baudrate;    /* Console Baudrate */
+#if defined(CONFIG_4xx)
+        unsigned char   bi_s_version[4];        /* Version of this structure */
+        unsigned char   bi_r_version[32];       /* Version of the ROM (IBM) */
+        unsigned int    bi_procfreq;    /* CPU (Internal) Freq, in Hz */
+        unsigned int    bi_plb_busfreq; /* PLB Bus speed, in Hz */
+        unsigned int    bi_pci_busfreq; /* PCI Bus speed, in Hz */
+        unsigned char   bi_pci_enetaddr[6];     /* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+        hymod_conf_t    bi_hymod_conf;  /* hymod configuration information */
+#endif
+#if defined(CONFIG_EVB64260) || defined(CONFIG_44x) || defined(CONFIG_85xx) ||\
+        defined(CONFIG_83xx)
+        /* second onboard ethernet port */
+        unsigned char   bi_enet1addr[6];
+#endif
+#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) || defined(CONFIG_85xx)
+        /* third onboard ethernet ports */
+        unsigned char   bi_enet2addr[6];
+#endif
+#if defined(CONFIG_440GX)
+        /* fourth onboard ethernet ports */
+        unsigned char   bi_enet3addr[6];
+#endif
+#if defined(CONFIG_4xx)
+        unsigned int    bi_opbfreq;             /* OB clock in Hz */
+        int             bi_iic_fast[2];         /* Use fast i2c mode */
+#endif
+#if defined(CONFIG_440GX)
+        int             bi_phynum[4];           /* phy mapping */
+        int             bi_phymode[4];          /* phy mode */
+#endif
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+#endif  /* __ASM_PPCBOOT_H__ */
diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h
new file mode 100644
index 000000000000..6dbc36a84df2
--- /dev/null
+++ b/include/asm-ppc/prep_nvram.h
@@ -0,0 +1,153 @@
+/*
+ * PreP compliant NVRAM access
+ */
+
+/* Corey Minyard (minyard@acm.org) - Stolen from PReP book.   Per the
+   license I must say:
+     (C) Copyright (Corey Minyard), (1998).  All rights reserved
+ */
+
+/* Structure map for NVRAM on PowerPC Reference Platform */
+/* All fields are either character/byte strings which are valid either
+  endian or they are big-endian numbers.
+
+  There are a number of Date and Time fields which are in RTC format,
+  big-endian. These are stored in UT (GMT).
+
+  For enum's: if given in hex then they are bit significant, i.e. only
+  one bit is on for each enum.
+*/
+#ifdef __KERNEL__
+#ifndef _PPC_PREP_NVRAM_H
+#define _PPC_PREP_NVRAM_H
+
+#define MAX_PREP_NVRAM 0x8000
+#define PREP_NVRAM_AS0  0x74
+#define PREP_NVRAM_AS1  0x75
+#define PREP_NVRAM_DATA 0x77
+
+#define NVSIZE 4096     /* size of NVRAM */
+#define OSAREASIZE 512  /* size of OSArea space */
+#define CONFSIZE 1024   /* guess at size of Configuration space */
+
+typedef struct _SECURITY {
+  unsigned long BootErrCnt;         /* Count of boot password errors */
+  unsigned long ConfigErrCnt;       /* Count of config password errors */
+  unsigned long BootErrorDT[2];     /* Date&Time from RTC of last error in pw */
+  unsigned long ConfigErrorDT[2];   /* Date&Time from RTC of last error in pw */
+  unsigned long BootCorrectDT[2];   /* Date&Time from RTC of last correct pw */
+  unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */
+  unsigned long BootSetDT[2];       /* Date&Time from RTC of last set of pw */
+  unsigned long ConfigSetDT[2];     /* Date&Time from RTC of last set of pw */
+  unsigned char Serial[16];         /* Box serial number */
+} SECURITY;
+
+typedef enum _OS_ID {
+  Unknown = 0,
+  Firmware = 1,
+  AIX = 2,
+  NT = 3,
+  MKOS2 = 4,
+  MKAIX = 5,
+  Taligent = 6,
+  Solaris = 7,
+  MK = 12
+} OS_ID;
+
+typedef struct _ERROR_LOG {
+  unsigned char ErrorLogEntry[40]; /* To be architected */
+} ERROR_LOG;
+
+typedef enum _BOOT_STATUS {
+  BootStarted = 0x01,
+  BootFinished = 0x02,
+  RestartStarted = 0x04,
+  RestartFinished = 0x08,
+  PowerFailStarted = 0x10,
+  PowerFailFinished = 0x20,
+  ProcessorReady = 0x40,
+  ProcessorRunning = 0x80,
+  ProcessorStart = 0x0100
+} BOOT_STATUS;
+
+typedef struct _RESTART_BLOCK {
+  unsigned short Version;
+  unsigned short Revision;
+  unsigned long ResumeReserve1[2];
+  volatile unsigned long BootStatus;
+  unsigned long CheckSum; /* Checksum of RESTART_BLOCK */
+  void * RestartAddress;
+  void * SaveAreaAddr;
+  unsigned long SaveAreaLength;
+} RESTART_BLOCK;
+
+typedef enum _OSAREA_USAGE {
+  Empty = 0,
+  Used = 1
+} OSAREA_USAGE;
+
+typedef enum _PM_MODE {
+  Suspend = 0x80, /* Part of state is in memory */
+  Normal = 0x00   /* No power management in effect */
+} PMMODE;
+
+typedef struct _HEADER {
+  unsigned short Size;       /* NVRAM size in K(1024) */
+  unsigned char Version;     /* Structure map different */
+  unsigned char Revision;    /* Structure map the same -may
+                                be new values in old fields
+                                in other words old code still works */
+  unsigned short Crc1;       /* check sum from beginning of nvram to OSArea */
+  unsigned short Crc2;       /* check sum of config */
+  unsigned char LastOS;      /* OS_ID */
+  unsigned char Endian;      /* B if big endian, L if little endian */
+  unsigned char OSAreaUsage; /* OSAREA_USAGE */
+  unsigned char PMMode;      /* Shutdown mode */
+  RESTART_BLOCK RestartBlock;
+  SECURITY Security;
+  ERROR_LOG ErrorLog[2];
+
+  /* Global Environment information */
+  void * GEAddress;
+  unsigned long GELength;
+
+  /* Date&Time from RTC of last change to Global Environment */
+  unsigned long GELastWriteDT[2];
+
+  /* Configuration information */
+  void * ConfigAddress;
+  unsigned long ConfigLength;
+
+  /* Date&Time from RTC of last change to Configuration */
+  unsigned long ConfigLastWriteDT[2];
+  unsigned long ConfigCount; /* Count of entries in Configuration */
+
+  /* OS dependent temp area */
+  void * OSAreaAddress;
+  unsigned long OSAreaLength;
+
+  /* Date&Time from RTC of last change to OSAreaArea */
+  unsigned long OSAreaLastWriteDT[2];
+} HEADER;
+
+/* Here is the whole map of the NVRAM */
+typedef struct _NVRAM_MAP {
+  HEADER Header;
+  unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)];
+  unsigned char OSArea[OSAREASIZE];
+  unsigned char ConfigArea[CONFSIZE];
+} NVRAM_MAP;
+
+/* Routines to manipulate the NVRAM */
+void init_prep_nvram(void);
+char *prep_nvram_get_var(const char *name);
+char *prep_nvram_first_var(void);
+char *prep_nvram_next_var(char *name);
+
+/* Routines to read and write directly to the NVRAM */
+unsigned char prep_nvram_read_val(int addr);
+void prep_nvram_write_val(int           addr,
+                          unsigned char val);
+
+#endif /* _PPC_PREP_NVRAM_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
new file mode 100644
index 000000000000..b05b5d9cae20
--- /dev/null
+++ b/include/asm-ppc/processor.h
@@ -0,0 +1,201 @@
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_PROCESSOR_H
+#define __ASM_PPC_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <linux/config.h>
+#include <linux/stringify.h>
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+#include <asm/mpc8xx.h>
+#include <asm/reg.h>
+
+/* We only need to define a new _MACH_xxx for machines which are part of
+ * a configuration which supports more than one type of different machine.
+ * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
+ * -- Tom
+ */
+#define _MACH_prep      0x00000001
+#define _MACH_Pmac      0x00000002      /* pmac or pmac clone (non-chrp) */
+#define _MACH_chrp      0x00000004      /* chrp machine */
+
+/* see residual.h for these */
+#define _PREP_Motorola  0x01    /* motorola prep */
+#define _PREP_Firm      0x02    /* firmworks prep */
+#define _PREP_IBM       0x00    /* ibm prep */
+#define _PREP_Bull      0x03    /* bull prep */
+
+/* these are arbitrary */
+#define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
+#define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
+#define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
+
+#define _GLOBAL(n)\
+        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
+        .globl n;\
+n:
+
+/*
+ * this is the minimum allowable io space due to the location
+ * of the io areas on prep (first one at 0x80000000) but
+ * as soon as I get around to remapping the io areas with the BATs
+ * to match the mac we can raise this. -- Cort
+ */
+#define TASK_SIZE       (CONFIG_TASK_SIZE)
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC_MULTIPLATFORM
+extern int _machine;
+
+/* what kind of prep workstation we are */
+extern int _prep_type;
+extern int _chrp_type;
+
+/*
+ * This is used to identify the board type from a given PReP board
+ * vendor. Board revision is also made available.
+ */
+extern unsigned char ucSystemType;
+extern unsigned char ucBoardRev;
+extern unsigned char ucBoardRevMaj, ucBoardRevMin;
+#else
+#define _machine 0
+#endif /* CONFIG_PPC_MULTIPLATFORM */
+
+struct task_struct;
+void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
+void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+extern void prepare_to_copy(struct task_struct *tsk);
+
+/*
+ * Create a new kernel thread.
+ */
+extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Lazy FPU handling on uni-processor */
+extern struct task_struct *last_task_used_math;
+extern struct task_struct *last_task_used_altivec;
+extern struct task_struct *last_task_used_spe;
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+struct thread_struct {
+        unsigned long   ksp;            /* Kernel stack pointer */
+        struct pt_regs  *regs;          /* Pointer to saved register state */
+        mm_segment_t    fs;             /* for get_fs() validation */
+        void            *pgdir;         /* root of page-table tree */
+        int             fpexc_mode;     /* floating-point exception mode */
+        signed long     last_syscall;
+#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
+        unsigned long   dbcr0;          /* debug control register values */
+        unsigned long   dbcr1;
+#endif
+        double          fpr[32];        /* Complete floating point set */
+        unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
+        unsigned long   fpscr;          /* Floating point status */
+#ifdef CONFIG_ALTIVEC
+        /* Complete AltiVec register set */
+        vector128       vr[32] __attribute((aligned(16)));
+        /* AltiVec status */
+        vector128       vscr __attribute((aligned(16)));
+        unsigned long   vrsave;
+        int             used_vr;        /* set if process has used altivec */
+#endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_SPE
+        unsigned long   evr[32];        /* upper 32-bits of SPE regs */
+        u64             acc;            /* Accumulator */
+        unsigned long   spefscr;        /* SPE & eFP status */
+        int             used_spe;       /* set if process has used spe */
+#endif /* CONFIG_SPE */
+};
+
+#define ARCH_MIN_TASKALIGN 16
+
+#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
+
+#define INIT_THREAD { \
+        .ksp = INIT_SP, \
+        .fs = KERNEL_DS, \
+        .pgdir = swapper_pg_dir, \
+        .fpexc_mode = MSR_FE0 | MSR_FE1, \
+}
+
+/*
+ * Return saved PC of a blocked thread. For now, this is the "user" PC
+ */
+#define thread_saved_pc(tsk)    \
+        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
+#define KSTK_ESP(tsk)   ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
+
+/* Get/set floating-point exception mode */
+#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
+#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
+
+extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
+extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
+
+static inline unsigned int __unpack_fe01(unsigned int msr_bits)
+{
+        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
+}
+
+static inline unsigned int __pack_fe01(unsigned int fpmode)
+{
+        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
+}
+
+/* in process.c - for early bootup debug -- Cort */
+int ll_printk(const char *, ...);
+void ll_puts(const char *);
+
+/* In misc.c */
+void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+
+#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
+
+#define cpu_relax()     barrier()
+
+/*
+ * Prefetch macros.
+ */
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+#define ARCH_HAS_SPINLOCK_PREFETCH
+
+extern inline void prefetch(const void *x)
+{
+         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
+}
+
+extern inline void prefetchw(const void *x)
+{
+         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
+}
+
+#define spin_lock_prefetch(x)   prefetchw(x)
+
+extern int emulate_altivec(struct pt_regs *regs);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_PPC_PROCESSOR_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h
new file mode 100644
index 000000000000..56394c6cf52e
--- /dev/null
+++ b/include/asm-ppc/prom.h
@@ -0,0 +1,143 @@
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996 Paul Mackerras.
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_PROM_H
+#define _PPC_PROM_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+extern char *prom_display_paths[];
+extern unsigned int prom_num_displays;
+
+struct address_range {
+        unsigned int space;
+        unsigned int address;
+        unsigned int size;
+};
+
+struct interrupt_info {
+        int     line;
+        int     sense;          /* +ve/-ve logic, edge or level, etc. */
+};
+
+struct reg_property {
+        unsigned int address;
+        unsigned int size;
+};
+
+struct property {
+        char    *name;
+        int     length;
+        unsigned char *value;
+        struct property *next;
+};
+
+/*
+ * Note: don't change this structure for now or you'll break BootX !
+ */
+struct device_node {
+        char    *name;
+        char    *type;
+        phandle node;
+        int     n_addrs;
+        struct  address_range *addrs;
+        int     n_intrs;
+        struct  interrupt_info *intrs;
+        char    *full_name;
+        struct  property *properties;
+        struct  device_node *parent;
+        struct  device_node *child;
+        struct  device_node *sibling;
+        struct  device_node *next;      /* next device of same type */
+        struct  device_node *allnext;   /* next in list of all nodes */
+};
+
+struct prom_args;
+typedef void (*prom_entry)(struct prom_args *);
+
+/* OBSOLETE: Old style node lookup */
+extern struct device_node *find_devices(const char *name);
+extern struct device_node *find_type_devices(const char *type);
+extern struct device_node *find_path_device(const char *path);
+extern struct device_node *find_compatible_devices(const char *type,
+                                                   const char *compat);
+extern struct device_node *find_all_nodes(void);
+
+/* New style node lookup */
+extern struct device_node *of_find_node_by_name(struct device_node *from,
+        const char *name);
+extern struct device_node *of_find_node_by_type(struct device_node *from,
+        const char *type);
+extern struct device_node *of_find_compatible_node(struct device_node *from,
+        const char *type, const char *compat);
+extern struct device_node *of_find_node_by_path(const char *path);
+extern struct device_node *of_find_all_nodes(struct device_node *prev);
+extern struct device_node *of_get_parent(const struct device_node *node);
+extern struct device_node *of_get_next_child(const struct device_node *node,
+                                             struct device_node *prev);
+extern struct device_node *of_node_get(struct device_node *node);
+extern void of_node_put(struct device_node *node);
+
+/* Other Prototypes */
+extern void abort(void);
+extern unsigned long prom_init(int, int, prom_entry);
+extern void prom_print(const char *msg);
+extern void relocate_nodes(void);
+extern void finish_device_tree(void);
+extern int device_is_compatible(struct device_node *device, const char *);
+extern int machine_is_compatible(const char *compat);
+extern unsigned char *get_property(struct device_node *node, const char *name,
+                                   int *lenp);
+extern void prom_add_property(struct device_node* np, struct property* prop);
+extern void prom_get_irq_senses(unsigned char *, int, int);
+extern int prom_n_addr_cells(struct device_node* np);
+extern int prom_n_size_cells(struct device_node* np);
+
+extern struct resource*
+request_OF_resource(struct device_node* node, int index, const char* name_postfix);
+extern int release_OF_resource(struct device_node* node, int index);
+
+extern void print_properties(struct device_node *node);
+extern int call_rtas(const char *service, int nargs, int nret,
+                     unsigned long *outputs, ...);
+
+/*
+ * PCI <-> OF matching functions
+ */
+struct pci_bus;
+struct pci_dev;
+extern int pci_device_from_OF_node(struct device_node *node,
+                                   u8* bus, u8* devfn);
+extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
+extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
+extern void pci_create_OF_bus_map(void);
+
+/*
+ * When we call back to the Open Firmware client interface, we usually
+ * have to do that before the kernel is relocated to its final location
+ * (this is because we can't use OF after we have overwritten the
+ * exception vectors with our exception handlers).  These macros assist
+ * in performing the address calculations that we need to do to access
+ * data when the kernel is running at an address that is different from
+ * the address that the kernel is linked at.  The reloc_offset() function
+ * returns the difference between these two addresses and the macros
+ * simplify the process of adding or subtracting this offset to/from
+ * pointer values.  See arch/ppc/kernel/prom.c for how these are used.
+ */
+extern unsigned long reloc_offset(void);
+extern unsigned long add_reloc_offset(unsigned long);
+extern unsigned long sub_reloc_offset(unsigned long);
+
+#define PTRRELOC(x)     ((typeof(x))add_reloc_offset((unsigned long)(x)))
+#define PTRUNRELOC(x)   ((typeof(x))sub_reloc_offset((unsigned long)(x)))
+
+#endif /* _PPC_PROM_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
new file mode 100644
index 000000000000..9d4e4ea530c3
--- /dev/null
+++ b/include/asm-ppc/ptrace.h
@@ -0,0 +1,145 @@
+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/ppc/kernel/ptrace.c.
+ */
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+        unsigned long gpr[32];
+        unsigned long nip;
+        unsigned long msr;
+        unsigned long orig_gpr3;        /* Used for restarting system calls */
+        unsigned long ctr;
+        unsigned long link;
+        unsigned long xer;
+        unsigned long ccr;
+        unsigned long mq;               /* 601 only (not used at present) */
+                                        /* Used on APUS to hold IPL value. */
+        unsigned long trap;             /* Reason for being here */
+        /* N.B. for critical exceptions on 4xx, the dar and dsisr
+           fields are overloaded to hold srr0 and srr1. */
+        unsigned long dar;              /* Fault registers */
+        unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
+        unsigned long result;           /* Result of a system call */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+#define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE      64
+
+#ifndef __ASSEMBLY__
+#define instruction_pointer(regs) ((regs)->nip)
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *regs);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+#define force_successful_syscall_return()   \
+        do { \
+                current_thread_info()->local_flags |= _TIFL_FORCE_NOERROR; \
+        } while(0)
+
+/*
+ * We use the least-significant bit of the trap field to indicate
+ * whether we have saved the full set of registers, or only a
+ * partial set.  A 1 there means the partial set.
+ * On 4xx we use the next bit to indicate whether the exception
+ * is a critical exception (1 means it is).
+ */
+#define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
+#define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) == 0)
+#define TRAP(regs)              ((regs)->trap & ~0xF)
+
+#define CHECK_FULL_REGS(regs)                                                 \
+do {                                                                          \
+        if ((regs)->trap & 1)                                                 \
+                printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
+} while (0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0   0
+#define PT_R1   1
+#define PT_R2   2
+#define PT_R3   3
+#define PT_R4   4
+#define PT_R5   5
+#define PT_R6   6
+#define PT_R7   7
+#define PT_R8   8
+#define PT_R9   9
+#define PT_R10  10
+#define PT_R11  11
+#define PT_R12  12
+#define PT_R13  13
+#define PT_R14  14
+#define PT_R15  15
+#define PT_R16  16
+#define PT_R17  17
+#define PT_R18  18
+#define PT_R19  19
+#define PT_R20  20
+#define PT_R21  21
+#define PT_R22  22
+#define PT_R23  23
+#define PT_R24  24
+#define PT_R25  25
+#define PT_R26  26
+#define PT_R27  27
+#define PT_R28  28
+#define PT_R29  29
+#define PT_R30  30
+#define PT_R31  31
+
+#define PT_NIP  32
+#define PT_MSR  33
+#ifdef __KERNEL__
+#define PT_ORIG_R3 34
+#endif
+#define PT_CTR  35
+#define PT_LNK  36
+#define PT_XER  37
+#define PT_CCR  38
+#define PT_MQ   39
+
+#define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+/* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go */
+#define PTRACE_GETVRREGS        18
+#define PTRACE_SETVRREGS        19
+
+/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
+ * spefscr, in one go */
+#define PTRACE_GETEVRREGS       20
+#define PTRACE_SETEVRREGS       21
+
+#endif
diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h
new file mode 100644
index 000000000000..66f52cc0a03c
--- /dev/null
+++ b/include/asm-ppc/raven.h
@@ -0,0 +1,35 @@
+/*
+ *  include/asm-ppc/raven.h -- Raven MPIC chip.
+ *
+ *  Copyright (C) 1998 Johnnie Peters
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License.  See the file COPYING in the main directory of this archive
+ *  for more details.
+ */
+
+#ifdef __KERNEL__
+#ifndef _ASMPPC_RAVEN_H
+#define _ASMPPC_RAVEN_H
+
+#define MVME2600_INT_SIO                0
+#define MVME2600_INT_FALCN_ECC_ERR      1
+#define MVME2600_INT_PCI_ETHERNET       2
+#define MVME2600_INT_PCI_SCSI           3
+#define MVME2600_INT_PCI_GRAPHICS       4
+#define MVME2600_INT_PCI_VME0           5
+#define MVME2600_INT_PCI_VME1           6
+#define MVME2600_INT_PCI_VME2           7
+#define MVME2600_INT_PCI_VME3           8
+#define MVME2600_INT_PCI_INTA           9
+#define MVME2600_INT_PCI_INTB           10
+#define MVME2600_INT_PCI_INTC           11
+#define MVME2600_INT_PCI_INTD           12
+#define MVME2600_INT_LM_SIG0            13
+#define MVME2600_INT_LM_SIG1            14
+
+extern struct hw_interrupt_type raven_pic;
+
+extern int raven_init(void);
+#endif /* _ASMPPC_RAVEN_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
new file mode 100644
index 000000000000..3372dee36a8c
--- /dev/null
+++ b/include/asm-ppc/reg.h
@@ -0,0 +1,444 @@
+/*
+ * Contains the definition of registers common to all PowerPC variants.
+ * If a register definition has been changed in a different PowerPC
+ * variant, we will case it in #ifndef XXX ... #endif, and have the
+ * number used in the Programming Environments Manual For 32-Bit
+ * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_REGS_H__
+#define __ASM_PPC_REGS_H__
+
+#include <linux/stringify.h>
+
+/* Pickup Book E specific registers. */
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+#include <asm/reg_booke.h>
+#endif
+
+/* Machine State Register (MSR) Fields */
+#define MSR_SF          (1<<63)
+#define MSR_ISF         (1<<61)
+#define MSR_VEC         (1<<25)         /* Enable AltiVec */
+#define MSR_POW         (1<<18)         /* Enable Power Management */
+#define MSR_WE          (1<<18)         /* Wait State Enable */
+#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
+#define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
+#define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
+#define MSR_EE          (1<<15)         /* External Interrupt Enable */
+#define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
+#define MSR_FP          (1<<13)         /* Floating Point enable */
+#define MSR_ME          (1<<12)         /* Machine Check Enable */
+#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
+#define MSR_SE          (1<<10)         /* Single Step */
+#define MSR_BE          (1<<9)          /* Branch Trace */
+#define MSR_DE          (1<<9)          /* Debug Exception Enable */
+#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
+#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
+#define MSR_IR          (1<<5)          /* Instruction Relocate */
+#define MSR_DR          (1<<4)          /* Data Relocate */
+#define MSR_PE          (1<<3)          /* Protection Enable */
+#define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
+#define MSR_RI          (1<<1)          /* Recoverable Exception */
+#define MSR_LE          (1<<0)          /* Little Endian */
+
+/* Default MSR for kernel mode. */
+#ifdef CONFIG_APUS_FAST_EXCEPT
+#define MSR_KERNEL      (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
+#endif
+
+#ifndef MSR_KERNEL
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
+#endif
+
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+
+/* Floating Point Status and Control Register (FPSCR) Fields */
+#define FPSCR_FX        0x80000000      /* FPU exception summary */
+#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
+#define FPSCR_VX        0x20000000      /* Invalid operation summary */
+#define FPSCR_OX        0x10000000      /* Overflow exception summary */
+#define FPSCR_UX        0x08000000      /* Underflow exception summary */
+#define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
+#define FPSCR_XX        0x02000000      /* Inexact exception summary */
+#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
+#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
+#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
+#define FPSCR_FR        0x00040000      /* Fraction rounded */
+#define FPSCR_FI        0x00020000      /* Fraction inexact */
+#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
+#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
+#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
+#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
+#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
+#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
+#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
+#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
+#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
+#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
+#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
+#define FPSCR_RN        0x00000003      /* FPU rounding control */
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_CTR        0x009   /* Count Register */
+#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
+#define SPRN_DAR        0x013   /* Data Address Register */
+#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
+#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
+#define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
+#define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
+#define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
+#define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L     0x239   /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U     0x238   /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L     0x23B   /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U     0x23A   /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L     0x23D   /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U     0x23C   /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L     0x23F   /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U     0x23E   /* Data BAT 7 Upper Register */
+
+#define SPRN_DEC        0x016           /* Decrement Register */
+#define SPRN_DER        0x095           /* Debug Enable Regsiter */
+#define DER_RSTE        0x40000000      /* Reset Interrupt */
+#define DER_CHSTPE      0x20000000      /* Check Stop */
+#define DER_MCIE        0x10000000      /* Machine Check Interrupt */
+#define DER_EXTIE       0x02000000      /* External Interrupt */
+#define DER_ALIE        0x01000000      /* Alignment Interrupt */
+#define DER_PRIE        0x00800000      /* Program Interrupt */
+#define DER_FPUVIE      0x00400000      /* FP Unavailable Interrupt */
+#define DER_DECIE       0x00200000      /* Decrementer Interrupt */
+#define DER_SYSIE       0x00040000      /* System Call Interrupt */
+#define DER_TRE         0x00020000      /* Trace Interrupt */
+#define DER_SEIE        0x00004000      /* FP SW Emulation Interrupt */
+#define DER_ITLBMSE     0x00002000      /* Imp. Spec. Instruction TLB Miss */
+#define DER_ITLBERE     0x00001000      /* Imp. Spec. Instruction TLB Error */
+#define DER_DTLBMSE     0x00000800      /* Imp. Spec. Data TLB Miss */
+#define DER_DTLBERE     0x00000400      /* Imp. Spec. Data TLB Error */
+#define DER_LBRKE       0x00000008      /* Load/Store Breakpoint Interrupt */
+#define DER_IBRKE       0x00000004      /* Instruction Breakpoint Interrupt */
+#define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
+#define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
+#define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
+#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
+#define SPRN_EAR        0x11A           /* External Address Register */
+#define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
+#define SPRN_HASH2      0x3D3           /* Secondary Hash Address Resgister */
+#define SPRN_HID0       0x3F0           /* Hardware Implementation Register 0 */
+#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
+#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
+#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
+#define HID0_SBCLK      (1<<27)
+#define HID0_EICE       (1<<26)
+#define HID0_TBEN       (1<<26)         /* Timebase enable - 745x */
+#define HID0_ECLK       (1<<25)
+#define HID0_PAR        (1<<24)
+#define HID0_STEN       (1<<24)         /* Software table search enable - 745x */
+#define HID0_HIGH_BAT   (1<<23)         /* Enable high BATs - 7455 */
+#define HID0_DOZE       (1<<23)
+#define HID0_NAP        (1<<22)
+#define HID0_SLEEP      (1<<21)
+#define HID0_DPM        (1<<20)
+#define HID0_BHTCLR     (1<<18)         /* Clear branch history table - 7450 */
+#define HID0_XAEN       (1<<17)         /* Extended addressing enable - 7450 */
+#define HID0_NHR        (1<<16)         /* Not hard reset (software bit-7450)*/
+#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
+#define HID0_DCE        (1<<14)         /* Data Cache Enable */
+#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
+#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
+#define HID0_ICFI       (1<<11)         /* Instr. Cache Flash Invalidate */
+#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
+#define HID0_SPD        (1<<9)          /* Speculative disable */
+#define HID0_SGE        (1<<7)          /* Store Gathering Enable */
+#define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
+#define HID0_DFCA       (1<<6)          /* Data Cache Flush Assist */
+#define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
+#define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
+#define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
+#define HID0_FOLD       (1<<3)          /* Branch Folding enable - 745x */
+#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
+#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
+#define HID0_NOPDST     (1<<1)          /* No-op dst, dstt, etc. instr. */
+#define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
+
+#define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
+#define HID1_EMCP       (1<<31)         /* 7450 Machine Check Pin Enable */
+#define HID1_DFS        (1<<22)         /* 7447A Dynamic Frequency Scaling */
+#define HID1_PC0        (1<<16)         /* 7450 PLL_CFG[0] */
+#define HID1_PC1        (1<<15)         /* 7450 PLL_CFG[1] */
+#define HID1_PC2        (1<<14)         /* 7450 PLL_CFG[2] */
+#define HID1_PC3        (1<<13)         /* 7450 PLL_CFG[3] */
+#define HID1_SYNCBE     (1<<11)         /* 7450 ABE for sync, eieio */
+#define HID1_ABE        (1<<10)         /* 7450 Address Broadcast Enable */
+#define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
+#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
+#define SPRN_HID4       0x3F4           /* 970 HID4 */
+#define SPRN_HID5       0x3F6           /* 970 HID5 */
+#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
+#define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
+#define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
+#endif
+#define SPRN_IBAT0L     0x211           /* Instruction BAT 0 Lower Register */
+#define SPRN_IBAT0U     0x210           /* Instruction BAT 0 Upper Register */
+#define SPRN_IBAT1L     0x213           /* Instruction BAT 1 Lower Register */
+#define SPRN_IBAT1U     0x212           /* Instruction BAT 1 Upper Register */
+#define SPRN_IBAT2L     0x215           /* Instruction BAT 2 Lower Register */
+#define SPRN_IBAT2U     0x214           /* Instruction BAT 2 Upper Register */
+#define SPRN_IBAT3L     0x217           /* Instruction BAT 3 Lower Register */
+#define SPRN_IBAT3U     0x216           /* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L     0x231           /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U     0x230           /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L     0x233           /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U     0x232           /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L     0x235           /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U     0x234           /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L     0x237           /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U     0x236           /* Instruction BAT 7 Upper Register */
+#define SPRN_ICMP       0x3D5           /* Instruction TLB Compare Register */
+#define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
+#define SPRN_ICTRL      0x3F3   /* 1011 7450 icache and interrupt ctrl */
+#define ICTRL_EICE      0x08000000      /* enable icache parity errs */
+#define ICTRL_EDC       0x04000000      /* enable dcache parity errs */
+#define ICTRL_EICP      0x00000100      /* enable icache par. check */
+#define SPRN_IMISS      0x3D4           /* Instruction TLB Miss Register */
+#define SPRN_IMMR       0x27E           /* Internal Memory Map Register */
+#define SPRN_L2CR       0x3F9           /* Level 2 Cache Control Regsiter */
+#define SPRN_L2CR2      0x3f8
+#define L2CR_L2E                0x80000000      /* L2 enable */
+#define L2CR_L2PE               0x40000000      /* L2 parity enable */
+#define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
+#define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
+#define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
+#define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
+#define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
+#define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
+#define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
+#define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
+#define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
+#define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
+#define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
+#define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
+#define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
+#define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
+#define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
+#define L2CR_L2DO               0x00400000      /* L2 data only */
+#define L2CR_L2I                0x00200000      /* L2 global invalidate */
+#define L2CR_L2CTL              0x00100000      /* L2 RAM control */
+#define L2CR_L2WT               0x00080000      /* L2 write-through */
+#define L2CR_L2TS               0x00040000      /* L2 test support */
+#define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
+#define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
+#define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
+#define L2CR_L2SL               0x00008000      /* L2 DLL slow */
+#define L2CR_L2DF               0x00004000      /* L2 differential clock */
+#define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
+#define L2CR_L2IP               0x00000001      /* L2 GI in progress */
+#define L2CR_L2IO_745x          0x00100000      /* L2 instr. only (745x) */
+#define L2CR_L2DO_745x          0x00010000      /* L2 data only (745x) */
+#define L2CR_L2REP_745x         0x00001000      /* L2 repl. algorithm (745x) */
+#define L2CR_L2HWF_745x         0x00000800      /* L2 hardware flush (745x) */
+#define SPRN_L3CR               0x3FA   /* Level 3 Cache Control Regsiter */
+#define L3CR_L3E                0x80000000      /* L3 enable */
+#define L3CR_L3PE               0x40000000      /* L3 data parity enable */
+#define L3CR_L3APE              0x20000000      /* L3 addr parity enable */
+#define L3CR_L3SIZ              0x10000000      /* L3 size */
+#define L3CR_L3CLKEN            0x08000000      /* L3 clock enable */
+#define L3CR_L3RES              0x04000000      /* L3 special reserved bit */
+#define L3CR_L3CLKDIV           0x03800000      /* L3 clock divisor */
+#define L3CR_L3IO               0x00400000      /* L3 instruction only */
+#define L3CR_L3SPO              0x00040000      /* L3 sample point override */
+#define L3CR_L3CKSP             0x00030000      /* L3 clock sample point */
+#define L3CR_L3PSP              0x0000e000      /* L3 P-clock sample point */
+#define L3CR_L3REP              0x00001000      /* L3 replacement algorithm */
+#define L3CR_L3HWF              0x00000800      /* L3 hardware flush */
+#define L3CR_L3I                0x00000400      /* L3 global invalidate */
+#define L3CR_L3RT               0x00000300      /* L3 SRAM type */
+#define L3CR_L3NIRCA            0x00000080      /* L3 non-integer ratio clock adj. */
+#define L3CR_L3DO               0x00000040      /* L3 data only mode */
+#define L3CR_PMEN               0x00000004      /* L3 private memory enable */
+#define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
+#define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
+#define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
+#define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
+#define SPRN_LDSTDB     0x3f4   /* */
+#define SPRN_LR         0x008   /* Link Register */
+#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
+#ifndef SPRN_PIR
+#define SPRN_PIR        0x3FF   /* Processor Identification Register */
+#endif
+#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
+#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
+#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
+#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
+#define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
+#define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
+#define SPRN_PVR        0x11F   /* Processor Version Register */
+#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
+#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
+#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
+#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
+#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
+#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
+#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
+#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
+#define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
+#define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
+#define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
+#define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
+#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
+#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
+#ifndef SPRN_SVR
+#define SPRN_SVR        0x11E   /* System Version Register */
+#endif
+#define SPRN_THRM1      0x3FC           /* Thermal Management Register 1 */
+/* these bits were defined in inverted endian sense originally, ugh, confusing */
+#define THRM1_TIN       (1 << 31)
+#define THRM1_TIV       (1 << 30)
+#define THRM1_THRES(x)  ((x&0x7f)<<23)
+#define THRM3_SITV(x)   ((x&0x3fff)<<1)
+#define THRM1_TID       (1<<2)
+#define THRM1_TIE       (1<<1)
+#define THRM1_V         (1<<0)
+#define SPRN_THRM2      0x3FD           /* Thermal Management Register 2 */
+#define SPRN_THRM3      0x3FE           /* Thermal Management Register 3 */
+#define THRM3_E         (1<<0)
+#define SPRN_TLBMISS    0x3D4           /* 980 7450 TLB Miss Register */
+#define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
+#define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
+#define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
+#define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
+#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
+#define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
+#define SPRN_XER        0x001   /* Fixed Point Exception Register */
+
+/* Bit definitions for MMCR0 and PMC1 / PMC2. */
+#define MMCR0_PMC1_CYCLES       (1 << 7)
+#define MMCR0_PMC1_ICACHEMISS   (5 << 7)
+#define MMCR0_PMC1_DTLB         (6 << 7)
+#define MMCR0_PMC2_DCACHEMISS   0x6
+#define MMCR0_PMC2_CYCLES       0x1
+#define MMCR0_PMC2_ITLB         0x7
+#define MMCR0_PMC2_LOADMISSTIME 0x5
+#define MMCR0_PMXE      (1 << 26)
+
+/* Processor Version Register */
+
+/* Processor Version Register (PVR) field extraction */
+
+#define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
+#define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
+
+/*
+ * IBM has further subdivided the standard PowerPC 16-bit version and
+ * revision subfields of the PVR for the PowerPC 403s into the following:
+ */
+
+#define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
+#define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
+#define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
+#define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
+#define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
+#define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
+
+/* Processor Version Numbers */
+
+#define PVR_403GA       0x00200000
+#define PVR_403GB       0x00200100
+#define PVR_403GC       0x00200200
+#define PVR_403GCX      0x00201400
+#define PVR_405GP       0x40110000
+#define PVR_STB03XXX    0x40310000
+#define PVR_NP405H      0x41410000
+#define PVR_NP405L      0x41610000
+#define PVR_440GP_RB    0x40120440
+#define PVR_440GP_RC1   0x40120481
+#define PVR_440GP_RC2   0x40200481
+#define PVR_440GX_RA    0x51b21850
+#define PVR_440GX_RB    0x51b21851
+#define PVR_440GX_RC    0x51b21892
+#define PVR_601         0x00010000
+#define PVR_602         0x00050000
+#define PVR_603         0x00030000
+#define PVR_603e        0x00060000
+#define PVR_603ev       0x00070000
+#define PVR_603r        0x00071000
+#define PVR_604         0x00040000
+#define PVR_604e        0x00090000
+#define PVR_604r        0x000A0000
+#define PVR_620         0x00140000
+#define PVR_740         0x00080000
+#define PVR_750         PVR_740
+#define PVR_740P        0x10080000
+#define PVR_750P        PVR_740P
+#define PVR_7400        0x000C0000
+#define PVR_7410        0x800C0000
+#define PVR_7450        0x80000000
+#define PVR_8540        0x80200000
+#define PVR_8560        0x80200000
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_821         0x00500000
+#define PVR_823         PVR_821
+#define PVR_850         PVR_821
+#define PVR_860         PVR_821
+#define PVR_8240        0x00810100
+#define PVR_8245        0x80811014
+#define PVR_8260        PVR_8240
+
+#if 0
+/* Segment Registers */
+#define SR0     0
+#define SR1     1
+#define SR2     2
+#define SR3     3
+#define SR4     4
+#define SR5     5
+#define SR6     6
+#define SR7     7
+#define SR8     8
+#define SR9     9
+#define SR10    10
+#define SR11    11
+#define SR12    12
+#define SR13    13
+#define SR14    14
+#define SR15    15
+#endif
+
+/* Macros for setting and retrieving special purpose registers */
+#ifndef __ASSEMBLY__
+#define mfmsr()         ({unsigned int rval; \
+                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
+
+#define mfspr(rn)       ({unsigned int rval; \
+                        asm volatile("mfspr %0," __stringify(rn) \
+                                : "=r" (rval)); rval;})
+#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+
+#define mfsrin(v)       ({unsigned int rval; \
+                        asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
+                                        rval;})
+
+#define proc_trap()     asm volatile("trap")
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_PPC_REGS_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
new file mode 100644
index 000000000000..4b03f8e26b72
--- /dev/null
+++ b/include/asm-ppc/reg_booke.h
@@ -0,0 +1,484 @@
+/*
+ * Contains register definitions common to the Book E PowerPC
+ * specification.  Notice that while the IBM-40x series of CPUs
+ * are not true Book E PowerPCs, they borrowed a number of features
+ * before Book E was finalized, and are included here as well.  Unfortunatly,
+ * they sometimes used different locations than true Book E CPUs did.
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_PPC_REG_BOOKE_H__
+#define __ASM_PPC_REG_BOOKE_H__
+
+#ifndef __ASSEMBLY__
+/* Device Control Registers */
+void __mtdcr(int reg, unsigned int val);
+unsigned int __mfdcr(int reg);
+#define mfdcr(rn)                                               \
+        ({unsigned int rval;                                    \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mfdcr %0," __stringify(rn)        \
+                              : "=r" (rval));                   \
+        else                                                    \
+                rval = __mfdcr(rn);                             \
+        rval;})
+
+#define mtdcr(rn, v)                                            \
+do {                                                            \
+        if (__builtin_constant_p(rn))                           \
+                asm volatile("mtdcr " __stringify(rn) ",%0"     \
+                              : : "r" (v));                     \
+        else                                                    \
+                __mtdcr(rn, v);                                 \
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+#define mfdcri(base, reg)                       \
+({                                              \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mfdcr(base ## _CFGDATA);                        \
+})
+
+#define mtdcri(base, reg, data)                 \
+do {                                            \
+        mtdcr(base ## _CFGADDR, base ## _ ## reg);      \
+        mtdcr(base ## _CFGDATA, data);          \
+} while (0)
+
+/* Performance Monitor Registers */
+#define mfpmr(rn)       ({unsigned int rval; \
+                        asm volatile("mfpmr %0," __stringify(rn) \
+                                     : "=r" (rval)); rval;})
+#define mtpmr(rn, v)    asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
+#endif /* __ASSEMBLY__ */
+
+/* Freescale Book E Performance Monitor APU Registers */
+#define PMRN_PMC0       0x010   /* Performance Monitor Counter 0 */
+#define PMRN_PMC1       0x011   /* Performance Monitor Counter 1 */
+#define PMRN_PMC2       0x012   /* Performance Monitor Counter 1 */
+#define PMRN_PMC3       0x013   /* Performance Monitor Counter 1 */
+#define PMRN_PMLCA0     0x090   /* PM Local Control A0 */
+#define PMRN_PMLCA1     0x091   /* PM Local Control A1 */
+#define PMRN_PMLCA2     0x092   /* PM Local Control A2 */
+#define PMRN_PMLCA3     0x093   /* PM Local Control A3 */
+
+#define PMLCA_FC        0x80000000      /* Freeze Counter */
+#define PMLCA_FCS       0x40000000      /* Freeze in Supervisor */
+#define PMLCA_FCU       0x20000000      /* Freeze in User */
+#define PMLCA_FCM1      0x10000000      /* Freeze when PMM==1 */
+#define PMLCA_FCM0      0x08000000      /* Freeze when PMM==0 */
+#define PMLCA_CE        0x04000000      /* Condition Enable */
+
+#define PMLCA_EVENT_MASK 0x007f0000     /* Event field */
+#define PMLCA_EVENT_SHIFT       16
+
+#define PMRN_PMLCB0     0x110   /* PM Local Control B0 */
+#define PMRN_PMLCB1     0x111   /* PM Local Control B1 */
+#define PMRN_PMLCB2     0x112   /* PM Local Control B2 */
+#define PMRN_PMLCB3     0x113   /* PM Local Control B3 */
+
+#define PMLCB_THRESHMUL_MASK    0x0700  /* Threshhold Multiple Field */
+#define PMLCB_THRESHMUL_SHIFT   8
+
+#define PMLCB_THRESHOLD_MASK    0x003f  /* Threshold Field */
+#define PMLCB_THRESHOLD_SHIFT   0
+
+#define PMRN_PMGC0      0x190   /* PM Global Control 0 */
+
+#define PMGC0_FAC       0x80000000      /* Freeze all Counters */
+#define PMGC0_PMIE      0x40000000      /* Interrupt Enable */
+#define PMGC0_FCECE     0x20000000      /* Freeze countes on
+                                           Enabled Condition or
+                                           Event */
+
+#define PMRN_UPMC0      0x000   /* User Performance Monitor Counter 0 */
+#define PMRN_UPMC1      0x001   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC2      0x002   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMC3      0x003   /* User Performance Monitor Counter 1 */
+#define PMRN_UPMLCA0    0x080   /* User PM Local Control A0 */
+#define PMRN_UPMLCA1    0x081   /* User PM Local Control A1 */
+#define PMRN_UPMLCA2    0x082   /* User PM Local Control A2 */
+#define PMRN_UPMLCA3    0x083   /* User PM Local Control A3 */
+#define PMRN_UPMLCB0    0x100   /* User PM Local Control B0 */
+#define PMRN_UPMLCB1    0x101   /* User PM Local Control B1 */
+#define PMRN_UPMLCB2    0x102   /* User PM Local Control B2 */
+#define PMRN_UPMLCB3    0x103   /* User PM Local Control B3 */
+#define PMRN_UPMGC0     0x180   /* User PM Global Control 0 */
+
+
+/* Machine State Register (MSR) Fields */
+#define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
+#define MSR_SPE         (1<<25) /* Enable SPE */
+#define MSR_DWE         (1<<10) /* Debug Wait Enable */
+#define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
+#define MSR_IS          MSR_IR  /* Instruction Space */
+#define MSR_DS          MSR_DR  /* Data Space */
+#define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
+
+/* Default MSR for kernel mode. */
+#if defined (CONFIG_40x)
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
+#elif defined(CONFIG_BOOKE)
+#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
+#endif
+
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
+#define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R     0x107   /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W     0x114   /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
+#define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
+#define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
+#define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
+#define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
+#define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3      0x193   /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4      0x194   /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5      0x195   /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6      0x196   /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7      0x197   /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8      0x198   /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9      0x199   /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10     0x19A   /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11     0x19B   /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12     0x19C   /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
+#define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
+#define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
+#define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
+#define SPRN_MCSRR0     0x23A   /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
+#define SPRN_MCSR       0x23C   /* Machine Check Status Register */
+#define SPRN_MCAR       0x23D   /* Machine Check Address Register */
+#define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
+#define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
+#define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
+#define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
+#define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
+#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
+#define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
+#define SPRN_PID1       0x279   /* Process ID Register 1 */
+#define SPRN_PID2       0x27A   /* Process ID Register 2 */
+#define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
+#define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
+#define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
+#define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
+#define SPRN_MMUCR      0x3B2   /* MMU Control Register */
+#define SPRN_CCR0       0x3B3   /* Core Configuration Register 0 */
+#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
+#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
+#define SPRN_SLER       0x3BB   /* Little-endian real mode */
+#define SPRN_SU0R       0x3BC   /* "User 0" real mode (40x) */
+#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
+#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
+#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
+#define SPRN_L1CSR0     0x3F2   /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
+#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
+#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
+#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
+#define SPRN_SVR        0x3FF   /* System Version Register */
+
+/*
+ * SPRs which have conflicting definitions on true Book E versus classic,
+ * or IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID        0x030   /* Process ID */
+#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
+#define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
+#define SPRN_DEAR       0x03D   /* Data Error Address Register */
+#define SPRN_ESR        0x03E   /* Exception Syndrome Register */
+#define SPRN_PIR        0x11E   /* Processor Identification Register */
+#define SPRN_DBSR       0x130   /* Debug Status Register */
+#define SPRN_DBCR0      0x134   /* Debug Control Register 0 */
+#define SPRN_DBCR1      0x135   /* Debug Control Register 1 */
+#define SPRN_IAC1       0x138   /* Instruction Address Compare 1 */
+#define SPRN_IAC2       0x139   /* Instruction Address Compare 2 */
+#define SPRN_DAC1       0x13C   /* Data Address Compare 1 */
+#define SPRN_DAC2       0x13D   /* Data Address Compare 2 */
+#define SPRN_TSR        0x150   /* Timer Status Register */
+#define SPRN_TCR        0x154   /* Timer Control Register */
+#endif /* Book E */
+#ifdef CONFIG_40x
+#define SPRN_PID        0x3B1   /* Process ID */
+#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */          
+#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
+#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
+#define SPRN_TSR        0x3D8   /* Timer Status Register */
+#define SPRN_TCR        0x3DA   /* Timer Control Register */
+#define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
+#define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
+#define SPRN_DBSR       0x3F0   /* Debug Status Register */             
+#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
+#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
+#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
+#define SPRN_CSRR0      SPRN_SRR2 /* Critical Save and Restore Register 0 */
+#define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
+#endif
+
+/* Bit definitions for CCR1. */
+#define CCR1_TCS        0x00000080 /* Timer Clock Select */
+
+/* Bit definitions for the MCSR. */
+#ifdef CONFIG_440A
+#define MCSR_MCS        0x80000000 /* Machine Check Summary */
+#define MCSR_IB         0x40000000 /* Instruction PLB Error */
+#define MCSR_DRB        0x20000000 /* Data Read PLB Error */
+#define MCSR_DWB        0x10000000 /* Data Write PLB Error */
+#define MCSR_TLBP       0x08000000 /* TLB Parity Error */
+#define MCSR_ICP        0x04000000 /* I-Cache Parity Error */
+#define MCSR_DCSP       0x02000000 /* D-Cache Search Parity Error */
+#define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
+#define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
+#endif
+#ifdef CONFIG_E500
+#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
+#define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
+#define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
+#define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
+#define MCSR_GL_CI      0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
+#define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
+#define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
+#define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
+#define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
+#define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
+#define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
+#define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
+#define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
+#endif
+
+/* Bit definitions for the DBSR. */
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IC         0x08000000      /* Instruction Completion */
+#define DBSR_BT         0x04000000      /* Branch Taken */
+#define DBSR_TIE        0x01000000      /* Trap Instruction Event */
+#define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
+#define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
+#define DBSR_IAC3       0x00200000      /* Instr Address Compare 3 Event */
+#define DBSR_IAC4       0x00100000      /* Instr Address Compare 4 Event */
+#define DBSR_DAC1R      0x00080000      /* Data Addr Compare 1 Read Event */
+#define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
+#define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
+#define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
+#endif
+#ifdef CONFIG_40x
+#define DBSR_IC         0x80000000      /* Instruction Completion */
+#define DBSR_BT         0x40000000      /* Branch taken */
+#define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
+#define DBSR_IAC1       0x00800000      /* Instruction Address Compare 1 Event */
+#define DBSR_IAC2       0x00400000      /* Instruction Address Compare 2 Event */
+#define DBSR_IAC3       0x00200000      /* Instruction Address Compare 3 Event */
+#define DBSR_IAC4       0x00100000      /* Instruction Address Compare 4 Event */
+#define DBSR_DAC1R      0x00080000      /* Data Address Compare 1 Read Event */
+#define DBSR_DAC1W      0x00040000      /* Data Address Compare 1 Write Event */
+#define DBSR_DAC2R      0x00020000      /* Data Address Compare 2 Read Event */
+#define DBSR_DAC2W      0x00010000      /* Data Address Compare 2 Write Event */
+#endif
+
+/* Bit definitions related to the ESR. */
+#define ESR_MCI         0x80000000      /* Machine Check - Instruction */
+#define ESR_IMCP        0x80000000      /* Instr. Machine Check - Protection */
+#define ESR_IMCN        0x40000000      /* Instr. Machine Check - Non-config */
+#define ESR_IMCB        0x20000000      /* Instr. Machine Check - Bus error */
+#define ESR_IMCT        0x10000000      /* Instr. Machine Check - Timeout */
+#define ESR_PIL         0x08000000      /* Program Exception - Illegal */
+#define ESR_PPR         0x04000000      /* Program Exception - Priveleged */
+#define ESR_PTR         0x02000000      /* Program Exception - Trap */
+#define ESR_DST         0x00800000      /* Storage Exception - Data miss */
+#define ESR_DIZ         0x00400000      /* Storage Exception - Zone fault */
+#define ESR_ST          0x00800000      /* Store Operation */
+#define ESR_DLK         0x00200000      /* Data Cache Locking */
+#define ESR_ILK         0x00100000      /* Instr. Cache Locking */
+#define ESR_BO          0x00020000      /* Byte Ordering */
+
+/* Bit definitions related to the DBCR0. */
+#define DBCR0_EDM       0x80000000      /* External Debug Mode */
+#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
+#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
+#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
+#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
+#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
+#define DBCR0_RST_NONE  0x00000000      /* No Reset */
+#define DBCR0_IC        0x08000000      /* Instruction Completion */
+#define DBCR0_BT        0x04000000      /* Branch Taken */
+#define DBCR0_EDE       0x02000000      /* Exception Debug Event */
+#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
+#define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
+#define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
+#define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
+#define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
+#define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
+#define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
+#define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
+#define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
+#define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
+#define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
+#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+
+/* Bit definitions related to the TCR. */
+#define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
+#define TCR_WP_MASK     TCR_WP(3)
+#define WP_2_17         0               /* 2^17 clocks */
+#define WP_2_21         1               /* 2^21 clocks */
+#define WP_2_25         2               /* 2^25 clocks */
+#define WP_2_29         3               /* 2^29 clocks */
+#define TCR_WRC(x)      (((x)&0x3)<<28) /* WDT Reset Control */
+#define TCR_WRC_MASK    TCR_WRC(3)
+#define WRC_NONE        0               /* No reset will occur */
+#define WRC_CORE        1               /* Core reset will occur */
+#define WRC_CHIP        2               /* Chip reset will occur */
+#define WRC_SYSTEM      3               /* System reset will occur */
+#define TCR_WIE         0x08000000      /* WDT Interrupt Enable */
+#define TCR_PIE         0x04000000      /* PIT Interrupt Enable */
+#define TCR_DIE         TCR_PIE         /* DEC Interrupt Enable */
+#define TCR_FP(x)       (((x)&0x3)<<24) /* FIT Period */
+#define TCR_FP_MASK     TCR_FP(3)
+#define FP_2_9          0               /* 2^9 clocks */
+#define FP_2_13         1               /* 2^13 clocks */
+#define FP_2_17         2               /* 2^17 clocks */
+#define FP_2_21         3               /* 2^21 clocks */
+#define TCR_FIE         0x00800000      /* FIT Interrupt Enable */
+#define TCR_ARE         0x00400000      /* Auto Reload Enable */
+
+/* Bit definitions for the TSR. */
+#define TSR_ENW         0x80000000      /* Enable Next Watchdog */
+#define TSR_WIS         0x40000000      /* WDT Interrupt Status */
+#define TSR_WRS(x)      (((x)&0x3)<<28) /* WDT Reset Status */
+#define WRS_NONE        0               /* No WDT reset occurred */
+#define WRS_CORE        1               /* WDT forced core reset */
+#define WRS_CHIP        2               /* WDT forced chip reset */
+#define WRS_SYSTEM      3               /* WDT forced system reset */
+#define TSR_PIS         0x08000000      /* PIT Interrupt Status */
+#define TSR_DIS         TSR_PIS         /* DEC Interrupt Status */
+#define TSR_FIS         0x04000000      /* FIT Interrupt Status */
+
+/* Bit definitions for the DCCR. */
+#define DCCR_NOCACHE    0               /* Noncacheable */
+#define DCCR_CACHE      1               /* Cacheable */
+
+/* Bit definitions for DCWR. */
+#define DCWR_COPY       0               /* Copy-back */
+#define DCWR_WRITE      1               /* Write-through */
+
+/* Bit definitions for ICCR. */
+#define ICCR_NOCACHE    0               /* Noncacheable */
+#define ICCR_CACHE      1               /* Cacheable */
+
+/* Bit definitions for L1CSR0. */
+#define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
+#define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
+
+/* Bit definitions for L1CSR0. */
+#define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
+#define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
+#define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
+
+/* Bit definitions for SGR. */
+#define SGR_NORMAL      0               /* Speculative fetching allowed. */
+#define SGR_GUARDED     1               /* Speculative fetching disallowed. */
+
+/* Bit definitions for SPEFSCR. */
+#define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
+#define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
+#define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
+#define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
+#define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
+#define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
+#define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
+#define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
+#define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
+#define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
+#define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
+#define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
+#define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
+#define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
+#define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
+#define SPEFSCR_OV      0x00004000      /* Integer overflow */
+#define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
+#define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
+#define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
+#define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
+#define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
+#define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
+#define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
+#define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
+#define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
+#define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
+#define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
+#define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
+
+/*
+ * The IBM-403 is an even more odd special case, as it is much
+ * older than the IBM-405 series.  We put these down here incase someone
+ * wishes to support these machines again.
+ */
+#ifdef CONFIG_403GCX
+/* Special Purpose Registers (SPRNs)*/
+#define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
+#define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
+#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
+#define SPRN_TBHI       0x3DC   /* Time Base High */
+#define SPRN_TBLO       0x3DD   /* Time Base Low */
+#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
+#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
+#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
+#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
+#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
+
+
+/* Bit definitions for the DBCR. */
+#define DBCR_EDM        DBCR0_EDM
+#define DBCR_IDM        DBCR0_IDM
+#define DBCR_RST(x)     (((x) & 0x3) << 28)
+#define DBCR_RST_NONE   0
+#define DBCR_RST_CORE   1
+#define DBCR_RST_CHIP   2
+#define DBCR_RST_SYSTEM 3
+#define DBCR_IC         DBCR0_IC        /* Instruction Completion Debug Evnt */
+#define DBCR_BT         DBCR0_BT        /* Branch Taken Debug Event */
+#define DBCR_EDE        DBCR0_EDE       /* Exception Debug Event */
+#define DBCR_TDE        DBCR0_TDE       /* TRAP Debug Event */
+#define DBCR_FER        0x00F80000      /* First Events Remaining Mask */
+#define DBCR_FT         0x00040000      /* Freeze Timers on Debug Event */
+#define DBCR_IA1        0x00020000      /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2        0x00010000      /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R        0x00008000      /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W        0x00004000      /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x)     (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
+#define DAC_BYTE        0
+#define DAC_HALF        1
+#define DAC_WORD        2
+#define DAC_QUAD        3
+#define DBCR_D2R        0x00000800      /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W        0x00000400      /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x)     (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
+#define DBCR_SBT        0x00000040      /* Second Branch Taken Debug Event */
+#define DBCR_SED        0x00000020      /* Second Exception Debug Event */
+#define DBCR_STD        0x00000010      /* Second Trap Debug Event */
+#define DBCR_SIA        0x00000008      /* Second IAC Enable */
+#define DBCR_SDA        0x00000004      /* Second DAC Enable */
+#define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
+#endif /* 403GCX */
+#endif /* __ASM_PPC_REG_BOOKE_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h
new file mode 100644
index 000000000000..934810d25667
--- /dev/null
+++ b/include/asm-ppc/residual.h
@@ -0,0 +1,350 @@
+/* 7/18/95                                                                    */
+/*----------------------------------------------------------------------------*/
+/*      Residual Data header definitions and prototypes                       */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
+/* residual.h - Residual data structure passed in r3.                         */
+/*              Load point passed in r4 to boot image.                        */
+/* For enum's: if given in hex then they are bit significant,                 */
+/*             i.e. only one bit is on for each enum                          */
+/* Reserved fields must be filled with zeros.                                */
+
+#ifdef __KERNEL__
+#ifndef _RESIDUAL_
+#define _RESIDUAL_
+
+#ifndef __ASSEMBLY__
+
+#define MAX_CPUS 32                     /* These should be set to the maximum */
+#define MAX_MEMS 64                     /* number possible for this system.   */
+#define MAX_DEVICES 256                 /* Changing these will change the     */
+#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
+#define MAX_MEM_SEGS 64                 /* this header file.                  */
+
+/*----------------------------------------------------------------------------*/
+/*               Public structures...                                         */
+/*----------------------------------------------------------------------------*/
+
+#include <asm/pnp.h>
+
+typedef enum _L1CACHE_TYPE {
+  NoneCAC = 0,
+  SplitCAC = 1,
+  CombinedCAC = 2
+  } L1CACHE_TYPE;
+
+typedef enum _TLB_TYPE {
+  NoneTLB = 0,
+  SplitTLB = 1,
+  CombinedTLB = 2
+  } TLB_TYPE;
+
+typedef enum _FIRMWARE_SUPPORT {
+  Conventional = 0x01,
+  OpenFirmware = 0x02,
+  Diagnostics = 0x04,
+  LowDebug = 0x08,
+  Multiboot = 0x10,
+  LowClient = 0x20,
+  Hex41 = 0x40,
+  FAT = 0x80,
+  ISO9660 = 0x0100,
+  SCSI_InitiatorID_Override = 0x0200,
+  Tape_Boot = 0x0400,
+  FW_Boot_Path = 0x0800
+  } FIRMWARE_SUPPORT;
+
+typedef enum _FIRMWARE_SUPPLIERS {
+  IBMFirmware = 0x00,
+  MotoFirmware = 0x01,                  /* 7/18/95                            */
+  FirmWorks = 0x02,                     /* 10/5/95                            */
+  Bull = 0x03,                          /* 04/03/96                           */
+  } FIRMWARE_SUPPLIERS;
+
+typedef enum _ENDIAN_SWITCH_METHODS {
+  UsePort92 = 0x01,
+  UsePCIConfigA8 = 0x02,
+  UseFF001030 = 0x03,
+  } ENDIAN_SWITCH_METHODS;
+
+typedef enum _SPREAD_IO_METHODS {
+  UsePort850 = 0x00,
+/*UsePCIConfigA8 = 0x02,*/
+  } SPREAD_IO_METHODS;
+
+typedef struct _VPD {
+
+  /* Box dependent stuff */
+  unsigned char PrintableModel[32];     /* Null terminated string.
+                                           Must be of the form:
+                                           vvv,<20h>,<model designation>,<0x0>
+                                           where vvv is the vendor ID
+                                           e.g. IBM PPS MODEL 6015<0x0>       */
+  unsigned char Serial[16];             /* 12/94:
+                                           Serial Number; must be of the form:
+                                           vvv<serial number> where vvv is the
+                                           vendor ID.
+                                           e.g. IBM60151234567<20h><20h>      */
+  unsigned char Reserved[48];
+  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
+  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
+  unsigned long NvramSize;              /* Size of nvram in bytes             */
+  unsigned long NumSIMMSlots;
+  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
+  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
+  unsigned long SmpIar;
+  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
+  unsigned long Reserved5;
+  unsigned long Reserved6;
+  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
+  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
+  unsigned long Reserved7;
+  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
+  unsigned long WordWidth;              /* Word width in bits                 */
+  unsigned long PageSize;               /* Page size in bytes                 */
+  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
+                                           for which coherency is maintained;
+                                           normally <= CacheLineSize.         */
+  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
+                                        /*   false sharing of locks.          */
+
+  /* L1 Cache variables */
+  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
+                                        /*   total size of the L1, whether    */
+                                        /*   combined or split                */
+  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
+  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
+                                           for combined cache. If split, put
+                                           zeros here.                        */
+  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
+                                           for combined cache. If split, put
+                                           zeros here.                        */
+  /* For split L1 Cache: (= combined if combined cache) */
+  unsigned long I_CacheSize;
+  unsigned long I_CacheAssoc;
+  unsigned long I_CacheLineSize;
+  unsigned long D_CacheSize;
+  unsigned long D_CacheAssoc;
+  unsigned long D_CacheLineSize;
+
+  /* Translation Lookaside Buffer variables */
+  unsigned long TLBSize;                /* Total number of TLBs on the system */
+  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
+  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
+                                           combined TLB. If split, put zeros
+                                           here.                              */
+  /* For split TLB: (= combined if combined TLB) */
+  unsigned long I_TLBSize;
+  unsigned long I_TLBAssoc;
+  unsigned long D_TLBSize;
+  unsigned long D_TLBAssoc;
+
+  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
+                                           null if unused                     */
+  } VPD;
+
+typedef enum _DEVICE_FLAGS {
+  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
+  Integrated = 0x2000,
+  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
+  Static = 0x0800,                      /* 0 - dynamically configurable
+                                           1 - static                         */
+  Dock = 0x0400,                        /* 0 - not a docking station device
+                                           1 - is a docking station device    */
+  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
+                                           1 - can be a BOOT device           */
+  Configurable = 0x0100,                /* 1 - device is configurable         */
+  Disableable = 0x80,                   /* 1 - device can be disabled         */
+  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
+  ReadOnly = 0x20,                      /* 1 - device is read only            */
+  Removable = 0x10,                     /* 1 - device is removable            */
+  ConsoleIn = 0x08,
+  ConsoleOut = 0x04,
+  Input = 0x02,
+  Output = 0x01
+  } DEVICE_FLAGS;
+
+typedef enum _BUS_ID {
+  ISADEVICE = 0x01,
+  EISADEVICE = 0x02,
+  PCIDEVICE = 0x04,
+  PCMCIADEVICE = 0x08,
+  PNPISADEVICE = 0x10,
+  MCADEVICE = 0x20,
+  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
+  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
+  VMEDEVICE = 0x100,
+  } BUS_ID;
+
+typedef struct _DEVICE_ID {
+  unsigned long BusId;                  /* See BUS_ID enum above              */
+  unsigned long DevId;                  /* Big Endian format                  */
+  unsigned long SerialNum;              /* For multiple usage of a single
+                                           DevId                              */
+  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
+  unsigned char BaseType;               /* See pnp.h for bit definitions      */
+  unsigned char SubType;                /* See pnp.h for bit definitions      */
+  unsigned char Interface;              /* See pnp.h for bit definitions      */
+  unsigned char Spare;
+  } DEVICE_ID;
+
+typedef union _BUS_ACCESS {
+  struct _PnPAccess{
+    unsigned char CSN;
+    unsigned char LogicalDevNumber;
+    unsigned short ReadDataPort;
+    } PnPAccess;
+  struct _ISAAccess{
+    unsigned char SlotNumber;           /* ISA Slot Number generally not
+                                           available; 0 if unknown            */
+    unsigned char LogicalDevNumber;
+    unsigned short ISAReserved;
+    } ISAAccess;
+  struct _MCAAccess{
+    unsigned char SlotNumber;
+    unsigned char LogicalDevNumber;
+    unsigned short MCAReserved;
+    } MCAAccess;
+  struct _PCMCIAAccess{
+    unsigned char SlotNumber;
+    unsigned char LogicalDevNumber;
+    unsigned short PCMCIAReserved;
+    } PCMCIAAccess;
+  struct _EISAAccess{
+    unsigned char SlotNumber;
+    unsigned char FunctionNumber;
+    unsigned short EISAReserved;
+    } EISAAccess;
+  struct _PCIAccess{
+    unsigned char BusNumber;
+    unsigned char DevFuncNumber;
+    unsigned short PCIReserved;
+    } PCIAccess;
+  struct _ProcBusAccess{
+    unsigned char BusNumber;
+    unsigned char BUID;
+    unsigned short ProcBusReserved;
+    } ProcBusAccess;
+  } BUS_ACCESS;
+
+/* Per logical device information */
+typedef struct _PPC_DEVICE {
+  DEVICE_ID DeviceId;
+  BUS_ACCESS BusAccess;
+
+  /* The following three are offsets into the DevicePnPHeap */
+  /* All are in PnP compressed format                       */
+  unsigned long AllocatedOffset;        /* Allocated resource description     */
+  unsigned long PossibleOffset;         /* Possible resource description      */
+  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
+  } PPC_DEVICE;
+
+typedef enum _CPU_STATE {
+  CPU_GOOD = 0,                         /* CPU is present, and active         */
+  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
+  CPU_OFF = 2,                          /* CPU is present, but inactive       */
+  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
+  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
+  } CPU_STATE;
+
+typedef struct _PPC_CPU {
+  unsigned long CpuType;                /* Result of mfspr from Processor
+                                           Version Register (PVR).
+                                           PVR(0-15) = Version (e.g. 601)
+                                           PVR(16-31 = EC Level               */
+  unsigned char CpuNumber;              /* CPU Number for this processor      */
+  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
+  unsigned short Reserved;
+  } PPC_CPU;
+
+typedef struct _PPC_MEM {
+  unsigned long SIMMSize;               /* 0 - absent or bad
+                                           8M, 32M (in MB)                    */
+  } PPC_MEM;
+
+typedef enum _MEM_USAGE {
+  Other = 0x8000,
+  ResumeBlock = 0x4000,                 /* for use by power management        */
+  SystemROM = 0x2000,                   /* Flash memory (populated)           */
+  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
+  IOMemory = 0x0800,
+  SystemIO = 0x0400,
+  SystemRegs = 0x0200,
+  PCIAddr = 0x0100,
+  PCIConfig = 0x80,
+  ISAAddr = 0x40,
+  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
+  Free = 0x10,                          /* Free part of System Memory         */
+  BootImage = 0x08,                     /* BootImage part of System Memory    */
+  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
+  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
+  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
+  } MEM_USAGE;
+
+typedef struct _MEM_MAP {
+  unsigned long Usage;                  /* See MEM_USAGE above                */
+  unsigned long BasePage;               /* Page number measured in 4KB pages  */
+  unsigned long PageCount;              /* Page count measured in 4KB pages   */
+  } MEM_MAP;
+
+typedef struct _RESIDUAL {
+  unsigned long ResidualLength;         /* Length of Residual                 */
+  unsigned char Version;                /* of this data structure             */
+  unsigned char Revision;               /* of this data structure             */
+  unsigned short EC;                    /* of this data structure             */
+  /* VPD */
+  VPD VitalProductData;
+  /* CPU */
+  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
+  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
+                                        /* that there are unpopulated or      */
+                                        /* otherwise unusable cpu locations   */
+  PPC_CPU Cpus[MAX_CPUS];
+  /* Memory */
+  unsigned long TotalMemory;            /* Total amount of memory installed   */
+  unsigned long GoodMemory;             /* Total amount of good memory        */
+  unsigned long ActualNumMemSegs;
+  MEM_MAP Segs[MAX_MEM_SEGS];
+  unsigned long ActualNumMemories;
+  PPC_MEM Memories[MAX_MEMS];
+  /* Devices */
+  unsigned long ActualNumDevices;
+  PPC_DEVICE Devices[MAX_DEVICES];
+  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
+  } RESIDUAL;
+
+
+/*
+ * Forward declaration - we can't include <linux/pci.h> because it
+ * breaks the boot loader
+ */
+struct pci_dev;
+
+extern RESIDUAL *res;
+extern void print_residual_device_info(void);
+extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
+                                        unsigned char * DevID, int BaseType,
+                                        int SubType, int Interface, int n);
+extern int residual_pcidev_irq(struct pci_dev *dev);
+extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
+extern unsigned int residual_isapic_addr(void);
+extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
+                                       int n);
+extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
+                                                    unsigned packet_type,
+                                                    int n);
+extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
+                                                    unsigned packet_type,
+                                                    int n);
+
+#ifdef CONFIG_PREP_RESIDUAL
+#define have_residual_data      (res && res->ResidualLength)
+#else
+#define have_residual_data      0
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* ndef _RESIDUAL_ */
+
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/resource.h b/include/asm-ppc/resource.h
new file mode 100644
index 000000000000..86a1ea23a6ed
--- /dev/null
+++ b/include/asm-ppc/resource.h
@@ -0,0 +1,6 @@
+#ifndef _PPC_RESOURCE_H
+#define _PPC_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif
diff --git a/include/asm-ppc/rheap.h b/include/asm-ppc/rheap.h
new file mode 100644
index 000000000000..e6ca1f67cedc
--- /dev/null
+++ b/include/asm-ppc/rheap.h
@@ -0,0 +1,85 @@
+/*
+ * include/asm-ppc/rheap.c
+ *
+ * Header file for the implementation of a remote heap.
+ *
+ * Author: Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2004 (c) INTRACOM S.A. Greece. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_PPC_RHEAP_H__
+#define __ASM_PPC_RHEAP_H__
+
+#include <linux/list.h>
+
+typedef struct _rh_block {
+        struct list_head list;
+        void *start;
+        int size;
+        const char *owner;
+} rh_block_t;
+
+typedef struct _rh_info {
+        unsigned int alignment;
+        int max_blocks;
+        int empty_slots;
+        rh_block_t *block;
+        struct list_head empty_list;
+        struct list_head free_list;
+        struct list_head taken_list;
+        unsigned int flags;
+} rh_info_t;
+
+#define RHIF_STATIC_INFO        0x1
+#define RHIF_STATIC_BLOCK       0x2
+
+typedef struct rh_stats_t {
+        void *start;
+        int size;
+        const char *owner;
+} rh_stats_t;
+
+#define RHGS_FREE       0
+#define RHGS_TAKEN      1
+
+/* Create a remote heap dynamically */
+extern rh_info_t *rh_create(unsigned int alignment);
+
+/* Destroy a remote heap, created by rh_create() */
+extern void rh_destroy(rh_info_t * info);
+
+/* Initialize in place a remote info block */
+extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
+                    rh_block_t * block);
+
+/* Attach a free region to manage */
+extern int rh_attach_region(rh_info_t * info, void *start, int size);
+
+/* Detach a free region */
+extern void *rh_detach_region(rh_info_t * info, void *start, int size);
+
+/* Allocate the given size from the remote heap */
+extern void *rh_alloc(rh_info_t * info, int size, const char *owner);
+
+/* Allocate the given size from the given address */
+extern void *rh_alloc_fixed(rh_info_t * info, void *start, int size,
+                            const char *owner);
+
+/* Free the allocated area */
+extern int rh_free(rh_info_t * info, void *start);
+
+/* Get stats for debugging purposes */
+extern int rh_get_stats(rh_info_t * info, int what, int max_stats,
+                        rh_stats_t * stats);
+
+/* Simple dump of remote heap info */
+extern void rh_dump(rh_info_t * info);
+
+/* Set owner of taken block */
+extern int rh_set_owner(rh_info_t * info, void *start, const char *owner);
+
+#endif                          /* __ASM_PPC_RHEAP_H__ */
diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h
new file mode 100644
index 000000000000..05fbf912ab4d
--- /dev/null
+++ b/include/asm-ppc/rtc.h
@@ -0,0 +1,95 @@
+/*
+ * inclue/asm-ppc/rtc.h
+ *
+ * Author: Tom Rini <trini@mvista.com>
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Based on:
+ * include/asm-m68k/rtc.h
+ *
+ * Copyright Richard Zidlicky
+ * implementation details for genrtc/q40rtc driver
+ *
+ * And the old drivers/macintosh/rtc.c which was heavily based on:
+ * Linux/SPARC Real Time Clock Driver
+ * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
+ *
+ * With additional work by Paul Mackerras and Franz Sirl.
+ */
+
+#ifndef __ASM_RTC_H__
+#define __ASM_RTC_H__
+
+#ifdef __KERNEL__
+
+#include <linux/rtc.h>
+
+#include <asm/machdep.h>
+#include <asm/time.h>
+
+#define RTC_PIE 0x40            /* periodic interrupt enable */
+#define RTC_AIE 0x20            /* alarm interrupt enable */
+#define RTC_UIE 0x10            /* update-finished interrupt enable */
+
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+static inline unsigned int get_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.get_rtc_time) {
+                unsigned long nowtime;
+
+                nowtime = (ppc_md.get_rtc_time)();
+
+                to_tm(nowtime, time);
+
+                time->tm_year -= 1900;
+                time->tm_mon -= 1; /* Make sure userland has a 0-based month */
+        }
+        return RTC_24H;
+}
+
+/* Set the current date and time in the real time clock. */
+static inline int set_rtc_time(struct rtc_time *time)
+{
+        if (ppc_md.get_rtc_time) {
+                unsigned long nowtime;
+
+                nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
+                                time->tm_mday, time->tm_hour, time->tm_min,
+                                time->tm_sec);
+
+                (ppc_md.set_rtc_time)(nowtime);
+
+                return 0;
+        } else
+                return -EINVAL;
+}
+
+static inline unsigned int get_rtc_ss(void)
+{
+        struct rtc_time h;
+
+        get_rtc_time(&h);
+        return h.tm_sec;
+}
+
+static inline int get_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+static inline int set_rtc_pll(struct rtc_pll_info *pll)
+{
+        return -EINVAL;
+}
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_RTC_H__ */
diff --git a/include/asm-ppc/rwsem.h b/include/asm-ppc/rwsem.h
new file mode 100644
index 000000000000..3e738f483c11
--- /dev/null
+++ b/include/asm-ppc/rwsem.h
@@ -0,0 +1,172 @@
+/*
+ * include/asm-ppc/rwsem.h: R/W semaphores for PPC using the stuff
+ * in lib/rwsem.c.  Adapted largely from include/asm-i386/rwsem.h
+ * by Paul Mackerras <paulus@samba.org>.
+ */
+
+#ifndef _PPC_RWSEM_H
+#define _PPC_RWSEM_H
+
+#ifdef __KERNEL__
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/*
+ * the semaphore definition
+ */
+struct rw_semaphore {
+        /* XXX this should be able to be an atomic_t  -- paulus */
+        signed long             count;
+#define RWSEM_UNLOCKED_VALUE            0x00000000
+#define RWSEM_ACTIVE_BIAS               0x00000001
+#define RWSEM_ACTIVE_MASK               0x0000ffff
+#define RWSEM_WAITING_BIAS              (-0x00010000)
+#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
+#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+        spinlock_t              wait_lock;
+        struct list_head        wait_list;
+#if RWSEM_DEBUG
+        int                     debug;
+#endif
+};
+
+/*
+ * initialisation
+ */
+#if RWSEM_DEBUG
+#define __RWSEM_DEBUG_INIT      , 0
+#else
+#define __RWSEM_DEBUG_INIT      /* */
+#endif
+
+#define __RWSEM_INITIALIZER(name) \
+        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
+          LIST_HEAD_INIT((name).wait_list) \
+          __RWSEM_DEBUG_INIT }
+
+#define DECLARE_RWSEM(name)             \
+        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
+
+extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
+extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
+
+static inline void init_rwsem(struct rw_semaphore *sem)
+{
+        sem->count = RWSEM_UNLOCKED_VALUE;
+        spin_lock_init(&sem->wait_lock);
+        INIT_LIST_HEAD(&sem->wait_list);
+#if RWSEM_DEBUG
+        sem->debug = 0;
+#endif
+}
+
+/*
+ * lock for reading
+ */
+static inline void __down_read(struct rw_semaphore *sem)
+{
+        if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
+                smp_wmb();
+        else
+                rwsem_down_read_failed(sem);
+}
+
+static inline int __down_read_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        while ((tmp = sem->count) >= 0) {
+                if (tmp == cmpxchg(&sem->count, tmp,
+                                   tmp + RWSEM_ACTIVE_READ_BIAS)) {
+                        smp_wmb();
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * lock for writing
+ */
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
+                                (atomic_t *)(&sem->count));
+        if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
+                smp_wmb();
+        else
+                rwsem_down_write_failed(sem);
+}
+
+static inline int __down_write_trylock(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+                      RWSEM_ACTIVE_WRITE_BIAS);
+        smp_wmb();
+        return tmp == RWSEM_UNLOCKED_VALUE;
+}
+
+/*
+ * unlock after reading
+ */
+static inline void __up_read(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_dec_return((atomic_t *)(&sem->count));
+        if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * unlock after writing
+ */
+static inline void __up_write(struct rw_semaphore *sem)
+{
+        smp_wmb();
+        if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
+                              (atomic_t *)(&sem->count)) < 0)
+                rwsem_wake(sem);
+}
+
+/*
+ * implement atomic add functionality
+ */
+static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+{
+        atomic_add(delta, (atomic_t *)(&sem->count));
+}
+
+/*
+ * downgrade write lock to read lock
+ */
+static inline void __downgrade_write(struct rw_semaphore *sem)
+{
+        int tmp;
+
+        smp_wmb();
+        tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
+        if (tmp < 0)
+                rwsem_downgrade_wake(sem);
+}
+
+/*
+ * implement exchange and add functionality
+ */
+static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+{
+        smp_mb();
+        return atomic_add_return(delta, (atomic_t *)(&sem->count));
+}
+
+#endif /* __KERNEL__ */
+#endif /* _PPC_RWSEM_XADD_H */
diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h
new file mode 100644
index 000000000000..f21f18f56548
--- /dev/null
+++ b/include/asm-ppc/scatterlist.h
@@ -0,0 +1,25 @@
+#ifdef __KERNEL__
+#ifndef _PPC_SCATTERLIST_H
+#define _PPC_SCATTERLIST_H
+
+#include <asm/dma.h>
+
+struct scatterlist {
+        struct page     *page;
+        unsigned int    offset;
+        dma_addr_t      dma_address;
+        unsigned int    length;
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#endif /* !(_PPC_SCATTERLIST_H) */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/sections.h b/include/asm-ppc/sections.h
new file mode 100644
index 000000000000..ba8f43ac9bf3
--- /dev/null
+++ b/include/asm-ppc/sections.h
@@ -0,0 +1,33 @@
+#ifdef __KERNEL__
+#ifndef _PPC_SECTIONS_H
+#define _PPC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#define __pmac __attribute__ ((__section__ (".pmac.text")))
+#define __pmacdata __attribute__ ((__section__ (".pmac.data")))
+#define __pmacfunc(__argpmac) \
+        __argpmac __pmac; \
+        __argpmac
+        
+#define __prep __attribute__ ((__section__ (".prep.text")))
+#define __prepdata __attribute__ ((__section__ (".prep.data")))
+#define __prepfunc(__argprep) \
+        __argprep __prep; \
+        __argprep
+
+#define __chrp __attribute__ ((__section__ (".chrp.text")))
+#define __chrpdata __attribute__ ((__section__ (".chrp.data")))
+#define __chrpfunc(__argchrp) \
+        __argchrp __chrp; \
+        __argchrp
+
+/* this is actually just common chrp/pmac code, not OF code -- Cort */
+#define __openfirmware __attribute__ ((__section__ (".openfirmware.text")))
+#define __openfirmwaredata __attribute__ ((__section__ (".openfirmware.data")))
+#define __openfirmwarefunc(__argopenfirmware) \
+        __argopenfirmware __openfirmware; \
+        __argopenfirmware
+        
+#endif /* _PPC_SECTIONS_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/segment.h b/include/asm-ppc/segment.h
new file mode 100644
index 000000000000..0f2f7428d437
--- /dev/null
+++ b/include/asm-ppc/segment.h
@@ -0,0 +1 @@
+#include <asm/uaccess.h>
diff --git a/include/asm-ppc/semaphore.h b/include/asm-ppc/semaphore.h
new file mode 100644
index 000000000000..89e6e73be08c
--- /dev/null
+++ b/include/asm-ppc/semaphore.h
@@ -0,0 +1,111 @@
+#ifndef _PPC_SEMAPHORE_H
+#define _PPC_SEMAPHORE_H
+
+/*
+ * Swiped from asm-sparc/semaphore.h and modified
+ * -- Cort (cort@cs.nmt.edu)
+ *
+ * Stole some rw spinlock-based semaphore stuff from asm-alpha/semaphore.h
+ * -- Ani Joshi (ajoshi@unixbox.com)
+ *
+ * Remove spinlock-based RW semaphores; RW semaphore definitions are
+ * now in rwsem.h and we use the generic lib/rwsem.c implementation.
+ * Rework semaphores to use atomic_dec_if_positive.
+ * -- Paul Mackerras (paulus@samba.org)
+ */
+
+#ifdef __KERNEL__
+
+#include <asm/atomic.h>
+#include <asm/system.h>
+#include <linux/wait.h>
+#include <linux/rwsem.h>
+
+struct semaphore {
+        /*
+         * Note that any negative value of count is equivalent to 0,
+         * but additionally indicates that some process(es) might be
+         * sleeping on `wait'.
+         */
+        atomic_t count;
+        wait_queue_head_t wait;
+};
+
+#define __SEMAPHORE_INITIALIZER(name, n)                                \
+{                                                                       \
+        .count          = ATOMIC_INIT(n),                               \
+        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
+}
+
+#define __MUTEX_INITIALIZER(name) \
+        __SEMAPHORE_INITIALIZER(name, 1)
+
+#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
+        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
+
+#define DECLARE_MUTEX(name)             __DECLARE_SEMAPHORE_GENERIC(name, 1)
+#define DECLARE_MUTEX_LOCKED(name)      __DECLARE_SEMAPHORE_GENERIC(name, 0)
+
+static inline void sema_init (struct semaphore *sem, int val)
+{
+        atomic_set(&sem->count, val);
+        init_waitqueue_head(&sem->wait);
+}
+
+static inline void init_MUTEX (struct semaphore *sem)
+{
+        sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED (struct semaphore *sem)
+{
+        sema_init(sem, 0);
+}
+
+extern void __down(struct semaphore * sem);
+extern int  __down_interruptible(struct semaphore * sem);
+extern void __up(struct semaphore * sem);
+
+extern inline void down(struct semaphore * sem)
+{
+        might_sleep();
+
+        /*
+         * Try to get the semaphore, take the slow path if we fail.
+         */
+        if (atomic_dec_return(&sem->count) < 0)
+                __down(sem);
+        smp_wmb();
+}
+
+extern inline int down_interruptible(struct semaphore * sem)
+{
+        int ret = 0;
+
+        might_sleep();
+
+        if (atomic_dec_return(&sem->count) < 0)
+                ret = __down_interruptible(sem);
+        smp_wmb();
+        return ret;
+}
+
+extern inline int down_trylock(struct semaphore * sem)
+{
+        int ret;
+
+        ret = atomic_dec_if_positive(&sem->count) < 0;
+        smp_wmb();
+        return ret;
+}
+
+extern inline void up(struct semaphore * sem)
+{
+        smp_wmb();
+        if (atomic_inc_return(&sem->count) <= 0)
+                __up(sem);
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* !(_PPC_SEMAPHORE_H) */
diff --git a/include/asm-ppc/sembuf.h b/include/asm-ppc/sembuf.h
new file mode 100644
index 000000000000..883f682f85b8
--- /dev/null
+++ b/include/asm-ppc/sembuf.h
@@ -0,0 +1,19 @@
+#ifndef _PPC_SEMBUF_H
+#define _PPC_SEMBUF_H
+
+/*
+ * The semid64_ds structure for PPC architecture.
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        unsigned int    __unused1;
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned int    __unused2;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _PPC_SEMBUF_H */
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
new file mode 100644
index 000000000000..6d47438be58c
--- /dev/null
+++ b/include/asm-ppc/serial.h
@@ -0,0 +1,57 @@
+/*
+ * include/asm-ppc/serial.h
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_SERIAL_H__
+#define __ASM_SERIAL_H__
+
+#include <linux/config.h>
+
+#if defined(CONFIG_EV64260)
+#include <platforms/ev64260.h>
+#elif defined(CONFIG_CHESTNUT)
+#include <platforms/chestnut.h>
+#elif defined(CONFIG_GEMINI)
+#include <platforms/gemini_serial.h>
+#elif defined(CONFIG_POWERPMC250)
+#include <platforms/powerpmc250.h>
+#elif defined(CONFIG_LOPEC)
+#include <platforms/lopec.h>
+#elif defined(CONFIG_MCPN765)
+#include <platforms/mcpn765.h>
+#elif defined(CONFIG_MVME5100)
+#include <platforms/mvme5100.h>
+#elif defined(CONFIG_PAL4)
+#include <platforms/pal4_serial.h>
+#elif defined(CONFIG_PRPMC750)
+#include <platforms/prpmc750.h>
+#elif defined(CONFIG_PRPMC800)
+#include <platforms/prpmc800.h>
+#elif defined(CONFIG_SANDPOINT)
+#include <platforms/sandpoint.h>
+#elif defined(CONFIG_SPRUCE)
+#include <platforms/spruce.h>
+#elif defined(CONFIG_4xx)
+#include <asm/ibm4xx.h>
+#elif defined(CONFIG_83xx)
+#include <asm/mpc83xx.h>
+#elif defined(CONFIG_85xx)
+#include <asm/mpc85xx.h>
+#elif defined(CONFIG_RADSTONE_PPC7D)
+#include <platforms/radstone_ppc7d.h>
+#else
+
+/*
+ * XXX Assume for now it has PC-style ISA serial ports.
+ * This is true for PReP and CHRP at least.
+ */
+#include <asm/pc_serial.h>
+
+#if defined(CONFIG_MAC_SERIAL)
+#define SERIAL_DEV_OFFSET       ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2)
+#endif
+
+#endif /* !CONFIG_GEMINI and others */
+#endif /* __ASM_SERIAL_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/setup.h b/include/asm-ppc/setup.h
new file mode 100644
index 000000000000..d2d19ee103df
--- /dev/null
+++ b/include/asm-ppc/setup.h
@@ -0,0 +1,14 @@
+#ifdef __KERNEL__
+#ifndef _PPC_SETUP_H
+#define _PPC_SETUP_H
+
+#define m68k_num_memory num_memory
+#define m68k_memory memory
+
+#include <asm-m68k/setup.h>
+/* We have a bigger command line buffer. */
+#undef COMMAND_LINE_SIZE
+#define COMMAND_LINE_SIZE       512
+
+#endif /* _PPC_SETUP_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/shmbuf.h b/include/asm-ppc/shmbuf.h
new file mode 100644
index 000000000000..7ac0bd38cbd8
--- /dev/null
+++ b/include/asm-ppc/shmbuf.h
@@ -0,0 +1,37 @@
+#ifndef _PPC_SHMBUF_H
+#define _PPC_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for PPC architecture.
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        unsigned int            __unused1;
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned int            __unused2;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned int            __unused3;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned int            __unused4;
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused5;
+        unsigned long           __unused6;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _PPC_SHMBUF_H */
diff --git a/include/asm-ppc/shmparam.h b/include/asm-ppc/shmparam.h
new file mode 100644
index 000000000000..d6250602ae64
--- /dev/null
+++ b/include/asm-ppc/shmparam.h
@@ -0,0 +1,6 @@
+#ifndef _PPC_SHMPARAM_H
+#define _PPC_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
+
+#endif /* _PPC_SHMPARAM_H */
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
new file mode 100644
index 000000000000..fc5e358c65f1
--- /dev/null
+++ b/include/asm-ppc/sigcontext.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_PPC_SIGCONTEXT_H
+#define _ASM_PPC_SIGCONTEXT_H
+
+#include <asm/ptrace.h>
+
+
+struct sigcontext {
+        unsigned long   _unused[4];
+        int             signal;
+        unsigned long   handler;
+        unsigned long   oldmask;
+        struct pt_regs  *regs;
+};
+
+#endif
diff --git a/include/asm-ppc/siginfo.h b/include/asm-ppc/siginfo.h
new file mode 100644
index 000000000000..4b9435bb9049
--- /dev/null
+++ b/include/asm-ppc/siginfo.h
@@ -0,0 +1,6 @@
+#ifndef _PPC_SIGINFO_H
+#define _PPC_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif
diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h
new file mode 100644
index 000000000000..8cc8b88d4edd
--- /dev/null
+++ b/include/asm-ppc/signal.h
@@ -0,0 +1,179 @@
+#ifndef _ASMPPC_SIGNAL_H
+#define _ASMPPC_SIGNAL_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#endif /* __KERNEL__ */
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+#define SA_INTERRUPT    0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER     0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE                SA_ONESHOT
+#define SA_SAMPLE_RANDOM        SA_RESTART
+#define SA_SHIRQ                0x04000000
+#endif /* __KERNEL__ */
+
+#define SIG_BLOCK          0    /* for blocking signals */
+#define SIG_UNBLOCK        1    /* for unblocking signals */
+#define SIG_SETMASK        2    /* for setting the signal mask */
+
+/* Type of a signal handler.  */
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+typedef void __restorefn_t(void);
+typedef __restorefn_t __user *__sigrestore_t;
+
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+#endif /* __KERNEL__ */
+
+/*
+ * These are parameters to dbg_sigreturn syscall.  They enable or
+ * disable certain debugging things that can be done from signal
+ * handlers.  The dbg_sigreturn syscall *must* be called from a
+ * SA_SIGINFO signal so the ucontext can be passed to it.  It takes an
+ * array of struct sig_dbg_op, which has the debug operations to
+ * perform before returning from the signal.
+ */
+struct sig_dbg_op {
+        int dbg_type;
+        unsigned long dbg_value;
+};
+
+/* Enable or disable single-stepping.  The value sets the state. */
+#define SIG_DBG_SINGLE_STEPPING         1
+
+/* Enable or disable branch tracing.  The value sets the state. */
+#define SIG_DBG_BRANCH_TRACING          2
+
+#endif
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
new file mode 100644
index 000000000000..ebfb614f55f6
--- /dev/null
+++ b/include/asm-ppc/smp.h
@@ -0,0 +1,70 @@
+/* smp.h: PPC specific SMP stuff.
+ *
+ * Original was a copy of sparc smp.h.  Now heavily modified
+ * for PPC.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_SMP_H
+#define _PPC_SMP_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/cpumask.h>
+#include <linux/threads.h>
+
+#ifdef CONFIG_SMP
+
+#ifndef __ASSEMBLY__
+
+struct cpuinfo_PPC {
+        unsigned long loops_per_jiffy;
+        unsigned long pvr;
+        unsigned long *pgd_cache;
+        unsigned long *pte_cache;
+        unsigned long pgtable_cache_sz;
+};
+
+extern struct cpuinfo_PPC cpu_data[];
+extern cpumask_t cpu_online_map;
+extern cpumask_t cpu_possible_map;
+extern unsigned long smp_proc_in_lock[];
+extern volatile unsigned long cpu_callin_map[];
+extern int smp_tb_synchronized;
+
+extern void smp_send_tlb_invalidate(int);
+extern void smp_send_xmon_break(int cpu);
+struct pt_regs;
+extern void smp_message_recv(int, struct pt_regs *);
+
+#define NO_PROC_ID              0xFF            /* No processor magic marker */
+#define PROC_CHANGE_PENALTY     20
+
+#define smp_processor_id() (current_thread_info()->cpu)
+
+extern int __cpu_up(unsigned int cpu);
+
+extern int smp_hw_index[];
+#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
+
+struct klock_info_struct {
+        unsigned long kernel_flag;
+        unsigned char akp;
+};
+
+extern struct klock_info_struct klock_info;
+#define KLOCK_HELD       0xffffffff
+#define KLOCK_CLEAR      0x0
+
+#endif /* __ASSEMBLY__ */
+
+#else /* !(CONFIG_SMP) */
+
+#endif /* !(CONFIG_SMP) */
+
+#endif /* !(_PPC_SMP_H) */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/socket.h b/include/asm-ppc/socket.h
new file mode 100644
index 000000000000..4134376b0f66
--- /dev/null
+++ b/include/asm-ppc/socket.h
@@ -0,0 +1,56 @@
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp */
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_RCVLOWAT     16
+#define SO_SNDLOWAT     17
+#define SO_RCVTIMEO     18
+#define SO_SNDTIMEO     19
+#define SO_PASSCRED     20
+#define SO_PEERCRED     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+
+#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-ppc/sockios.h b/include/asm-ppc/sockios.h
new file mode 100644
index 000000000000..385aedc55ceb
--- /dev/null
+++ b/include/asm-ppc/sockios.h
@@ -0,0 +1,17 @@
+#ifndef _ASM_PPC_SOCKIOS_H
+#define _ASM_PPC_SOCKIOS_H
+
+#if 0 /* These are defined this way on Alpha - maybe later. */
+/* Socket-level I/O control calls. */
+
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      0x8906          /* Get stamp - linux-specific */
+#endif
+
+#endif /* _ASM_PPC_SOCKIOS_H */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
new file mode 100644
index 000000000000..909199aae104
--- /dev/null
+++ b/include/asm-ppc/spinlock.h
@@ -0,0 +1,215 @@
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+
+#include <asm/system.h>
+
+/*
+ * Simple spin lock operations.
+ */
+
+typedef struct {
+        volatile unsigned long lock;
+#ifdef CONFIG_DEBUG_SPINLOCK
+        volatile unsigned long owner_pc;
+        volatile unsigned long owner_cpu;
+#endif
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} spinlock_t;
+
+#ifdef __KERNEL__
+#ifdef CONFIG_DEBUG_SPINLOCK
+#define SPINLOCK_DEBUG_INIT     , 0, 0
+#else
+#define SPINLOCK_DEBUG_INIT     /* */
+#endif
+
+#define SPIN_LOCK_UNLOCKED      (spinlock_t) { 0 SPINLOCK_DEBUG_INIT }
+
+#define spin_lock_init(x)       do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
+#define spin_is_locked(x)       ((x)->lock != 0)
+#define spin_unlock_wait(x)     do { barrier(); } while(spin_is_locked(x))
+#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
+
+#ifndef CONFIG_DEBUG_SPINLOCK
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+        "b      1f              # spin_lock\n\
+2:      lwzx    %0,0,%1\n\
+        cmpwi   0,%0,0\n\
+        bne+    2b\n\
+1:      lwarx   %0,0,%1\n\
+        cmpwi   0,%0,0\n\
+        bne-    2b\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %2,0,%1\n\
+        bne-    2b\n\
+        isync"
+        : "=&r"(tmp)
+        : "r"(&lock->lock), "r"(1)
+        : "cr0", "memory");
+}
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+        __asm__ __volatile__("eieio             # spin_unlock": : :"memory");
+        lock->lock = 0;
+}
+
+#define _raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
+
+#else
+
+extern void _raw_spin_lock(spinlock_t *lock);
+extern void _raw_spin_unlock(spinlock_t *lock);
+extern int _raw_spin_trylock(spinlock_t *lock);
+
+#endif
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+typedef struct {
+        volatile signed int lock;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
+#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0)
+
+#define read_can_lock(rw)       ((rw)->lock >= 0)
+#define write_can_lock(rw)      (!(rw)->lock)
+
+#ifndef CONFIG_DEBUG_SPINLOCK
+
+static __inline__ int _raw_read_trylock(rwlock_t *rw)
+{
+        signed int tmp;
+
+        __asm__ __volatile__(
+"2:     lwarx   %0,0,%1         # read_trylock\n\
+        addic.  %0,%0,1\n\
+        ble-    1f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    2b\n\
+        isync\n\
+1:"
+        : "=&r"(tmp)
+        : "r"(&rw->lock)
+        : "cr0", "memory");
+
+        return tmp > 0;
+}
+
+static __inline__ void _raw_read_lock(rwlock_t *rw)
+{
+        signed int tmp;
+
+        __asm__ __volatile__(
+        "b      2f              # read_lock\n\
+1:      lwzx    %0,0,%1\n\
+        cmpwi   0,%0,0\n\
+        blt+    1b\n\
+2:      lwarx   %0,0,%1\n\
+        addic.  %0,%0,1\n\
+        ble-    1b\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    2b\n\
+        isync"
+        : "=&r"(tmp)
+        : "r"(&rw->lock)
+        : "cr0", "memory");
+}
+
+static __inline__ void _raw_read_unlock(rwlock_t *rw)
+{
+        signed int tmp;
+
+        __asm__ __volatile__(
+        "eieio                  # read_unlock\n\
+1:      lwarx   %0,0,%1\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %0,0,%1\n\
+        bne-    1b"
+        : "=&r"(tmp)
+        : "r"(&rw->lock)
+        : "cr0", "memory");
+}
+
+static __inline__ int _raw_write_trylock(rwlock_t *rw)
+{
+        signed int tmp;
+
+        __asm__ __volatile__(
+"2:     lwarx   %0,0,%1         # write_trylock\n\
+        cmpwi   0,%0,0\n\
+        bne-    1f\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %2,0,%1\n\
+        bne-    2b\n\
+        isync\n\
+1:"
+        : "=&r"(tmp)
+        : "r"(&rw->lock), "r"(-1)
+        : "cr0", "memory");
+
+        return tmp == 0;
+}
+
+static __inline__ void _raw_write_lock(rwlock_t *rw)
+{
+        signed int tmp;
+
+        __asm__ __volatile__(
+        "b      2f              # write_lock\n\
+1:      lwzx    %0,0,%1\n\
+        cmpwi   0,%0,0\n\
+        bne+    1b\n\
+2:      lwarx   %0,0,%1\n\
+        cmpwi   0,%0,0\n\
+        bne-    1b\n"
+        PPC405_ERR77(0,%1)
+"       stwcx.  %2,0,%1\n\
+        bne-    2b\n\
+        isync"
+        : "=&r"(tmp)
+        : "r"(&rw->lock), "r"(-1)
+        : "cr0", "memory");
+}
+
+static __inline__ void _raw_write_unlock(rwlock_t *rw)
+{
+        __asm__ __volatile__("eieio             # write_unlock": : :"memory");
+        rw->lock = 0;
+}
+
+#else
+
+extern void _raw_read_lock(rwlock_t *rw);
+extern void _raw_read_unlock(rwlock_t *rw);
+extern void _raw_write_lock(rwlock_t *rw);
+extern void _raw_write_unlock(rwlock_t *rw);
+extern int _raw_read_trylock(rwlock_t *rw);
+extern int _raw_write_trylock(rwlock_t *rw);
+
+#endif
+
+#endif /* __ASM_SPINLOCK_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/stat.h b/include/asm-ppc/stat.h
new file mode 100644
index 000000000000..cadb34298496
--- /dev/null
+++ b/include/asm-ppc/stat.h
@@ -0,0 +1,69 @@
+#ifndef _PPC_STAT_H
+#define _PPC_STAT_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#endif /* __KERNEL__ */
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+#define STAT_HAVE_NSEC 1
+
+struct stat {
+        unsigned        st_dev;
+        ino_t           st_ino;
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned        st_rdev;
+        off_t           st_size;
+        unsigned long   st_blksize;
+        unsigned long   st_blocks;
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+        unsigned long   __unused4;
+        unsigned long   __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1.
+ */
+struct stat64 {
+        unsigned long long st_dev;      /* Device.  */
+        unsigned long long st_ino;      /* File serial number.  */
+        unsigned int st_mode;           /* File mode.  */
+        unsigned int st_nlink;          /* Link count.  */
+        unsigned int st_uid;            /* User ID of the file's owner.  */
+        unsigned int st_gid;            /* Group ID of the file's group. */
+        unsigned long long st_rdev;     /* Device number, if device.  */
+        unsigned short int __pad2;
+        long long st_size;              /* Size of file, in bytes.  */
+        long st_blksize;                /* Optimal block size for I/O.  */
+
+        long long st_blocks;            /* Number 512-byte blocks allocated. */
+        long st_atime;                  /* Time of last access.  */
+        unsigned long st_atime_nsec;
+        long st_mtime;                  /* Time of last modification.  */
+        unsigned long int st_mtime_nsec;
+        long st_ctime;                  /* Time of last status change.  */
+        unsigned long int st_ctime_nsec;
+        unsigned long int __unused4;
+        unsigned long int __unused5;
+};
+#endif
diff --git a/include/asm-ppc/statfs.h b/include/asm-ppc/statfs.h
new file mode 100644
index 000000000000..807c69954a1b
--- /dev/null
+++ b/include/asm-ppc/statfs.h
@@ -0,0 +1,8 @@
+#ifndef _PPC_STATFS_H
+#define _PPC_STATFS_H
+
+#include <asm-generic/statfs.h>
+#endif
+
+
+
diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h
new file mode 100644
index 000000000000..225575997392
--- /dev/null
+++ b/include/asm-ppc/string.h
@@ -0,0 +1,32 @@
+#ifndef _PPC_STRING_H_
+#define _PPC_STRING_H_
+
+#ifdef __KERNEL__
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, int);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h
new file mode 100644
index 000000000000..3df9f32bd834
--- /dev/null
+++ b/include/asm-ppc/suspend.h
@@ -0,0 +1,12 @@
+static inline int arch_prepare_suspend(void)
+{
+        return 0;
+}
+
+static inline void save_processor_state(void)
+{
+}
+
+static inline void restore_processor_state(void)
+{
+}
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
new file mode 100644
index 000000000000..82395f30004b
--- /dev/null
+++ b/include/asm-ppc/system.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
+ */
+#ifndef __PPC_SYSTEM_H
+#define __PPC_SYSTEM_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+
+#include <asm/atomic.h>
+#include <asm/hw_irq.h>
+
+/*
+ * Memory barrier.
+ * The sync instruction guarantees that all memory accesses initiated
+ * by this processor have been performed (with respect to all other
+ * mechanisms that access memory).  The eieio instruction is a barrier
+ * providing an ordering (separately) for (a) cacheable stores and (b)
+ * loads and stores to non-cacheable memory (e.g. I/O devices).
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ * read_barrier_depends() prevents data-dependent loads being reordered
+ *      across this point (nop on PPC).
+ *
+ * We can use the eieio instruction for wmb, but since it doesn't
+ * give any ordering guarantees about loads, we have to use the
+ * stronger but slower sync instruction for mb and rmb.
+ */
+#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
+#define read_barrier_depends()  do { } while(0)
+
+#define set_mb(var, value)      do { var = value; mb(); } while (0)
+#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif /* CONFIG_SMP */
+
+#ifdef __KERNEL__
+struct task_struct;
+struct pt_regs;
+
+extern void print_backtrace(unsigned long *);
+extern void show_regs(struct pt_regs * regs);
+extern void flush_instruction_cache(void);
+extern void hard_reset_now(void);
+extern void poweroff_now(void);
+#ifdef CONFIG_6xx
+extern long _get_L2CR(void);
+extern long _get_L3CR(void);
+extern void _set_L2CR(unsigned long);
+extern void _set_L3CR(unsigned long);
+#else
+#define _get_L2CR()     0L
+#define _get_L3CR()     0L
+#define _set_L2CR(val)  do { } while(0)
+#define _set_L3CR(val)  do { } while(0)
+#endif
+extern void via_cuda_init(void);
+extern void pmac_nvram_init(void);
+extern void read_rtc_time(void);
+extern void pmac_find_display(void);
+extern void giveup_fpu(struct task_struct *);
+extern void enable_kernel_fp(void);
+extern void enable_kernel_altivec(void);
+extern void giveup_altivec(struct task_struct *);
+extern void load_up_altivec(struct task_struct *);
+extern void giveup_spe(struct task_struct *);
+extern void load_up_spe(struct task_struct *);
+extern int fix_alignment(struct pt_regs *);
+extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
+extern void cvt_df(double *from, float *to, unsigned long *fpscr);
+extern int call_rtas(const char *, int, int, unsigned long *, ...);
+extern void cacheable_memzero(void *p, unsigned int nb);
+extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
+extern void bad_page_fault(struct pt_regs *, unsigned long, int);
+extern void die(const char *, struct pt_regs *, long);
+
+struct device_node;
+extern void note_scsi_host(struct device_node *, void *);
+
+extern struct task_struct *__switch_to(struct task_struct *,
+        struct task_struct *);
+#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
+
+struct thread_struct;
+extern struct task_struct *_switch(struct thread_struct *prev,
+                                   struct thread_struct *next);
+
+extern unsigned int rtas_data;
+
+static __inline__ unsigned long
+xchg_u32(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__ ("\n\
+1:      lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
+        : "cc", "memory");
+
+        return prev;
+}
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid xchg().
+ */
+extern void __xchg_called_with_bad_pointer(void);
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr) (xchg((ptr),1))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+        switch (size) {
+        case 4:
+                return (unsigned long) xchg_u32(ptr, x);
+#if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
+        case 8:
+                return (unsigned long) xchg_u64(ptr, x);
+#endif /* 0 */
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+
+
+}
+
+extern inline void * xchg_ptr(void * m, void * val)
+{
+        return (void *) xchg_u32(m, (unsigned long) val);
+}
+
+
+#define __HAVE_ARCH_CMPXCHG     1
+
+static __inline__ unsigned long
+__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
+{
+        unsigned int prev;
+
+        __asm__ __volatile__ ("\n\
+1:      lwarx   %0,0,%2 \n\
+        cmpw    0,%0,%3 \n\
+        bne     2f \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2 \n\
+        bne-    1b\n"
+#ifdef CONFIG_SMP
+"       sync\n"
+#endif /* CONFIG_SMP */
+"2:"
+        : "=&r" (prev), "=m" (*p)
+        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "cc", "memory");
+
+        return prev;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid cmpxchg().  */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32(ptr, old, new);
+#if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
+        case 8:
+                return __cmpxchg_u64(ptr, old, new);
+#endif /* 0 */
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                 \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+#endif /* __PPC_SYSTEM_H */
diff --git a/include/asm-ppc/termbits.h b/include/asm-ppc/termbits.h
new file mode 100644
index 000000000000..c343fb7bdfed
--- /dev/null
+++ b/include/asm-ppc/termbits.h
@@ -0,0 +1,185 @@
+#ifndef _PPC_TERMBITS_H
+#define _PPC_TERMBITS_H
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+/*
+ * termios type and macro definitions.  Be careful about adding stuff
+ * to this file since it's used in GNU libc and there are strict rules
+ * concerning namespace pollution.
+ */
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_cc[NCCS];                /* control characters */
+        cc_t c_line;                    /* line discipline (== c_cc[19]) */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR   0
+#define VQUIT   1
+#define VERASE  2
+#define VKILL   3
+#define VEOF    4
+#define VMIN    5
+#define VEOL    6
+#define VTIME   7
+#define VEOL2   8
+#define VSWTC   9
+
+#define VWERASE         10
+#define VREPRINT        11
+#define VSUSP           12
+#define VSTART          13
+#define VSTOP           14
+#define VLNEXT          15
+#define VDISCARD        16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IXON    0001000
+#define IXOFF   0002000
+#define IXANY           0004000
+#define IUCLC           0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define ONLCR   0000002
+#define OLCUC   0000004
+
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+
+#define OFILL   00000100
+#define OFDEL   00000200
+#define NLDLY   00001400
+#define   NL0   00000000
+#define   NL1   00000400
+#define   NL2   00001000
+#define   NL3   00001400
+#define TABDLY  00006000
+#define   TAB0  00000000
+#define   TAB1  00002000
+#define   TAB2  00004000
+#define   TAB3  00006000
+#define   XTABS 00006000        /* required by POSIX to == TAB3 */
+#define CRDLY   00030000
+#define   CR0   00000000
+#define   CR1   00010000
+#define   CR2   00020000
+#define   CR3   00030000
+#define FFDLY   00040000
+#define   FF0   00000000
+#define   FF1   00040000
+#define BSDLY   00100000
+#define   BS0   00000000
+#define   BS1   00100000
+#define VTDLY   00200000
+#define   VT0   00000000
+#define   VT1   00200000
+
+/* c_cflag bit meaning */
+#define CBAUD   0000377
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CBAUDEX 0000000
+#define  B57600   00020
+#define  B115200  00021
+#define  B230400  00022
+#define  B460800  00023
+#define  B500000  00024
+#define  B576000  00025
+#define  B921600  00026
+#define B1000000  00027
+#define B1152000  00030
+#define B1500000  00031
+#define B2000000  00032
+#define B2500000  00033
+#define B3000000  00034
+#define B3500000  00035
+#define B4000000  00036
+
+#define CSIZE   00001400
+#define   CS5   00000000
+#define   CS6   00000400
+#define   CS7   00001000
+#define   CS8   00001400
+
+#define CSTOPB  00002000
+#define CREAD   00004000
+#define PARENB  00010000
+#define PARODD  00020000
+#define HUPCL   00040000
+
+#define CLOCAL  00100000
+#define CRTSCTS   020000000000          /* flow control */
+
+/* c_lflag bits */
+#define ISIG    0x00000080
+#define ICANON  0x00000100
+#define XCASE   0x00004000
+#define ECHO    0x00000008
+#define ECHOE   0x00000002
+#define ECHOK   0x00000004
+#define ECHONL  0x00000010
+#define NOFLSH  0x80000000
+#define TOSTOP  0x00400000
+#define ECHOCTL 0x00000040
+#define ECHOPRT 0x00000020
+#define ECHOKE  0x00000001
+#define FLUSHO  0x00800000
+#define PENDIN  0x20000000
+#define IEXTEN  0x00000400
+
+/* Values for the ACTION argument to `tcflow'.  */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* Values for the QUEUE_SELECTOR argument to `tcflush'.  */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'.  */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif /* _PPC_TERMBITS_H */
diff --git a/include/asm-ppc/termios.h b/include/asm-ppc/termios.h
new file mode 100644
index 000000000000..97c6287a6cba
--- /dev/null
+++ b/include/asm-ppc/termios.h
@@ -0,0 +1,232 @@
+#ifndef _PPC_TERMIOS_H
+#define _PPC_TERMIOS_H
+
+/*
+ * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
+ * fields have been reordered so that termio & termios share the
+ * common subset in the same order (for brain dead programs that don't
+ * know or care about the differences).
+ */
+
+#include <asm/ioctls.h>
+#include <asm/termbits.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        short   sg_flags;
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;
+        char    t_dsuspc;
+        char    t_rprntc;
+        char    t_flushc;
+        char    t_werasc;
+        char    t_lnextc;
+};
+
+#define FIOCLEX         _IO('f', 1)
+#define FIONCLEX        _IO('f', 2)
+#define FIOASYNC        _IOW('f', 125, int)
+#define FIONBIO         _IOW('f', 126, int)
+#define FIONREAD        _IOR('f', 127, int)
+#define TIOCINQ         FIONREAD
+#define FIOQSIZE        _IOR('f', 128, loff_t)
+
+#define TIOCGETP        _IOR('t', 8, struct sgttyb)
+#define TIOCSETP        _IOW('t', 9, struct sgttyb)
+#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
+
+#define TIOCSETC        _IOW('t', 17, struct tchars)
+#define TIOCGETC        _IOR('t', 18, struct tchars)
+#define TCGETS          _IOR('t', 19, struct termios)
+#define TCSETS          _IOW('t', 20, struct termios)
+#define TCSETSW         _IOW('t', 21, struct termios)
+#define TCSETSF         _IOW('t', 22, struct termios)
+
+#define TCGETA          _IOR('t', 23, struct termio)
+#define TCSETA          _IOW('t', 24, struct termio)
+#define TCSETAW         _IOW('t', 25, struct termio)
+#define TCSETAF         _IOW('t', 28, struct termio)
+
+#define TCSBRK          _IO('t', 29)
+#define TCXONC          _IO('t', 30)
+#define TCFLSH          _IO('t', 31)
+
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
+#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
+#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
+#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
+
+#define TIOCGLTC        _IOR('t', 116, struct ltchars)
+#define TIOCSLTC        _IOW('t', 117, struct ltchars)
+#define TIOCSPGRP       _IOW('t', 118, int)
+#define TIOCGPGRP       _IOR('t', 119, int)
+
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+
+#define TIOCSTI         0x5412
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 10
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* c_cc characters */
+#define _VINTR  0
+#define _VQUIT  1
+#define _VERASE 2
+#define _VKILL  3
+#define _VEOF   4
+#define _VMIN   5
+#define _VEOL   6
+#define _VTIME  7
+#define _VEOL2  8
+#define _VSWTC  9
+
+#ifdef __KERNEL__
+/*                   ^C  ^\ del  ^U  ^D   1   0   0   0   0  ^W  ^R  ^Z  ^Q  ^S  ^V  ^U  */
+#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025"
+#endif  /* __KERNEL__ */
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+/* line disciplines */
+#define N_TTY           0
+#define N_SLIP          1
+#define N_MOUSE         2
+#define N_PPP           3
+#define N_STRIP         4
+#define N_AX25          5
+#define N_X25           6       /* X.25 async */
+#define N_6PACK         7
+#define N_MASC          8       /* Reserved for Mobitex module <kaz@cafe.net> */
+#define N_R3964         9       /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA          11      /* Linux IrDa - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC          13      /* synchronous HDLC */
+#define N_SYNC_PPP      14
+#define N_HCI           15  /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+        unsigned short __tmp; \
+        get_user(__tmp,&(termio)->x); \
+        (termios)->x = (0xffff0000 & (termios)->x) | __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif  /* _PPC_TERMIOS_H */
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
new file mode 100644
index 000000000000..f7f01524e8a8
--- /dev/null
+++ b/include/asm-ppc/thread_info.h
@@ -0,0 +1,99 @@
+/* thread_info.h: PPC low-level thread information
+ * adapted from the i386 version by Paul Mackerras
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+/*
+ * low level task data.
+ * If you change this, change the TI_* offsets below to match.
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        unsigned long           local_flags;    /* non-racy flags */
+        int                     cpu;            /* cpu we're on */
+        int                     preempt_count;
+        struct restart_block    restart_block;
+};
+
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task =         &tsk,                   \
+        .exec_domain =  &default_exec_domain,   \
+        .flags =        0,                      \
+        .local_flags =  0,                      \
+        .cpu =          0,                      \
+        .preempt_count = 1,                     \
+        .restart_block = {                      \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+        __asm__("rlwinm %0,1,0,0,18" : "=r"(ti));
+        return ti;
+}
+
+/* thread information allocation */
+#define alloc_thread_info(tsk) ((struct thread_info *) \
+                                __get_free_pages(GFP_KERNEL, 1))
+#define free_thread_info(ti)    free_pages((unsigned long) (ti), 1)
+#define get_thread_info(ti)     get_task_struct((ti)->task)
+#define put_thread_info(ti)     put_task_struct((ti)->task)
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Size of kernel stack for each process.
+ */
+#define THREAD_SIZE             8192    /* 2 pages */
+
+#define PREEMPT_ACTIVE          0x10000000
+
+/*
+ * thread information flag bit numbers
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
+                                           TIF_NEED_RESCHED */
+#define TIF_MEMDIE              5
+/* as above, but as bit values */
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+
+/*
+ * Non racy (local) flags bit numbers
+ */
+#define TIFL_FORCE_NOERROR      0       /* don't return error from current
+                                           syscall even if result < 0 */
+
+/* as above, but as bit values */
+#define _TIFL_FORCE_NOERROR     (1<<TIFL_FORCE_NOERROR)
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h
new file mode 100644
index 000000000000..ce09b47fa819
--- /dev/null
+++ b/include/asm-ppc/time.h
@@ -0,0 +1,157 @@
+/*
+ * Common time prototypes and such for all ppc machines.
+ *
+ * Written by Cort Dougan (cort@fsmlabs.com) to merge
+ * Paul Mackerras' version and mine for PReP and Pmac.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_TIME_H__
+#define __ASM_TIME_H__
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/rtc.h>
+#include <linux/threads.h>
+
+#include <asm/reg.h>
+
+/* time.c */
+extern unsigned tb_ticks_per_jiffy;
+extern unsigned tb_to_us;
+extern unsigned tb_last_stamp;
+extern unsigned long disarm_decr[NR_CPUS];
+
+extern void to_tm(int tim, struct rtc_time * tm);
+extern time_t last_rtc_update;
+
+extern void set_dec_cpu6(unsigned int val);
+
+int via_calibrate_decr(void);
+
+/* Accessor functions for the decrementer register.
+ * The 4xx doesn't even have a decrementer.  I tried to use the
+ * generic timer interrupt code, which seems OK, with the 4xx PIT
+ * in auto-reload mode.  The problem is PIT stops counting when it
+ * hits zero.  If it would wrap, we could use it just like a decrementer.
+ */
+static __inline__ unsigned int get_dec(void)
+{
+#if defined(CONFIG_40x)
+        return (mfspr(SPRN_PIT));
+#else
+        return (mfspr(SPRN_DEC));
+#endif
+}
+
+static __inline__ void set_dec(unsigned int val)
+{
+#if defined(CONFIG_40x)
+        return;         /* Have to let it auto-reload */
+#elif defined(CONFIG_8xx_CPU6)
+        set_dec_cpu6(val);
+#else
+        mtspr(SPRN_DEC, val);
+#endif
+}
+
+/* Accessor functions for the timebase (RTC on 601) registers. */
+/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
+#ifdef CONFIG_6xx
+extern __inline__ int const __USE_RTC(void) {
+        return (mfspr(SPRN_PVR)>>16) == 1;
+}
+#else
+#define __USE_RTC() 0
+#endif
+
+extern __inline__ unsigned long get_tbl(void) {
+        unsigned long tbl;
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
+#else
+        asm volatile("mftb %0" : "=r" (tbl));
+#endif
+        return tbl;
+}
+
+extern __inline__ unsigned long get_tbu(void) {
+        unsigned long tbl;
+#if defined(CONFIG_403GCX)
+        asm volatile("mfspr %0, 0x3dc" : "=r" (tbl));
+#else
+        asm volatile("mftbu %0" : "=r" (tbl));
+#endif
+        return tbl;
+}
+
+extern __inline__ void set_tb(unsigned int upper, unsigned int lower)
+{
+        mtspr(SPRN_TBWL, 0);
+        mtspr(SPRN_TBWU, upper);
+        mtspr(SPRN_TBWL, lower);
+}
+
+extern __inline__ unsigned long get_rtcl(void) {
+        unsigned long rtcl;
+        asm volatile("mfrtcl %0" : "=r" (rtcl));
+        return rtcl;
+}
+
+extern __inline__ unsigned long get_rtcu(void)
+{
+        unsigned long rtcu;
+        asm volatile("mfrtcu %0" : "=r" (rtcu));
+        return rtcu;
+}
+
+extern __inline__ unsigned get_native_tbl(void) {
+        if (__USE_RTC())
+                return get_rtcl();
+        else
+                return get_tbl();
+}
+
+/* On machines with RTC, this function can only be used safely
+ * after the timestamp and for 1 second. It is only used by gettimeofday
+ * however so it should not matter.
+ */
+extern __inline__ unsigned tb_ticks_since(unsigned tstamp) {
+        if (__USE_RTC()) {
+                int delta = get_rtcl() - tstamp;
+                return delta<0 ? delta + 1000000000 : delta;
+        } else {
+                return get_tbl() - tstamp;
+        }
+}
+
+#if 0
+extern __inline__ unsigned long get_bin_rtcl(void) {
+      unsigned long rtcl, rtcu1, rtcu2;
+      asm volatile("\
+1:    mfrtcu  %0\n\
+      mfrtcl  %1\n\
+      mfrtcu  %2\n\
+      cmpw    %0,%2\n\
+      bne-    1b\n"
+      : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2)
+      : : "cr0");
+      return rtcu2*1000000000+rtcl;
+}
+
+extern __inline__ unsigned binary_tbl(void) {
+      if (__USE_RTC())
+              return get_bin_rtcl();
+      else
+              return get_tbl();
+}
+#endif
+
+/* Use mulhwu to scale processor timebase to timeval */
+/* Specifically, this computes (x * y) / 2^32.  -- paulus */
+#define mulhwu(x,y) \
+({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
+
+unsigned mulhwu_scale_factor(unsigned, unsigned);
+#endif /* __ASM_TIME_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/timex.h b/include/asm-ppc/timex.h
new file mode 100644
index 000000000000..cffc8712077c
--- /dev/null
+++ b/include/asm-ppc/timex.h
@@ -0,0 +1,40 @@
+/*
+ * include/asm-ppc/timex.h
+ *
+ * ppc architecture timex specifications
+ */
+#ifdef __KERNEL__
+#ifndef _ASMppc_TIMEX_H
+#define _ASMppc_TIMEX_H
+
+#include <linux/config.h>
+#include <asm/cputable.h>
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+
+typedef unsigned long cycles_t;
+
+/*
+ * For the "cycle" counter we use the timebase lower half.
+ * Currently only used on SMP.
+ */
+
+static inline cycles_t get_cycles(void)
+{
+        cycles_t ret = 0;
+
+        __asm__ __volatile__(
+                "98:    mftb %0\n"
+                "99:\n"
+                ".section __ftr_fixup,\"a\"\n"
+                "       .long %1\n"
+                "       .long 0\n"
+                "       .long 98b\n"
+                "       .long 99b\n"
+                ".previous"
+                : "=r" (ret) : "i" (CPU_FTR_601));
+        return ret;
+}
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/tlb.h b/include/asm-ppc/tlb.h
new file mode 100644
index 000000000000..2c142c5d8584
--- /dev/null
+++ b/include/asm-ppc/tlb.h
@@ -0,0 +1,57 @@
+/*
+ *      TLB shootdown specifics for PPC
+ *
+ * Copyright (C) 2002 Paul Mackerras, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _PPC_TLB_H
+#define _PPC_TLB_H
+
+#include <linux/config.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_STD_MMU
+/* Classic PPC with hash-table based MMU... */
+
+struct mmu_gather;
+extern void tlb_flush(struct mmu_gather *tlb);
+
+/* Get the generic bits... */
+#include <asm-generic/tlb.h>
+
+/* Nothing needed here in fact... */
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+
+extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
+                             unsigned long address);
+
+static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
+                                        unsigned long address)
+{
+        if (pte_val(*ptep) & _PAGE_HASHPTE)
+                flush_hash_entry(tlb->mm, ptep, address);
+}
+
+#else
+/* Embedded PPC with software-loaded TLB, very simple... */
+
+#define tlb_start_vma(tlb, vma)         do { } while (0)
+#define tlb_end_vma(tlb, vma)           do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
+#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
+
+/* Get the generic bits... */
+#include <asm-generic/tlb.h>
+
+#endif /* CONFIG_PPC_STD_MMU */
+
+#endif /* __PPC_TLB_H */
diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h
new file mode 100644
index 000000000000..9850f53f54b0
--- /dev/null
+++ b/include/asm-ppc/tlbflush.h
@@ -0,0 +1,115 @@
+/*
+ * include/asm-ppc/tlbflush.h
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifdef __KERNEL__
+#ifndef _PPC_TLBFLUSH_H
+#define _PPC_TLBFLUSH_H
+
+#include <linux/config.h>
+#include <linux/mm.h>
+
+extern void _tlbie(unsigned long address);
+extern void _tlbia(void);
+
+#if defined(CONFIG_4xx)
+
+#ifndef CONFIG_44x
+#define __tlbia()       asm volatile ("sync; tlbia; isync" : : : "memory")
+#else
+#define __tlbia         _tlbia
+#endif
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+        { __tlbia(); }
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                unsigned long start, unsigned long end)
+        { __tlbia(); }
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                unsigned long end)
+        { __tlbia(); }
+
+#elif defined(CONFIG_FSL_BOOKE)
+
+/* TODO: determine if flush_tlb_range & flush_tlb_kernel_range
+ * are best implemented as tlbia vs specific tlbie's */
+
+#define __tlbia()       _tlbia()
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+        { __tlbia(); }
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                unsigned long start, unsigned long end)
+        { __tlbia(); }
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                unsigned long end)
+        { __tlbia(); }
+
+#elif defined(CONFIG_8xx)
+#define __tlbia()       asm volatile ("tlbia; sync" : : : "memory")
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+        { __tlbia(); }
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+                                         unsigned long vmaddr)
+        { _tlbie(vmaddr); }
+static inline void flush_tlb_range(struct mm_struct *mm,
+                                unsigned long start, unsigned long end)
+        { __tlbia(); }
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                unsigned long end)
+        { __tlbia(); }
+
+#else   /* 6xx, 7xx, 7xxx cpus */
+struct mm_struct;
+struct vm_area_struct;
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
+extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+                            unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+#endif
+
+/*
+ * This is called in munmap when we have freed up some page-table
+ * pages.  We don't need to do anything here, there's nothing special
+ * about our page-table pages.  -- paulus
+ */
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
+                                      unsigned long start, unsigned long end)
+{
+}
+
+/*
+ * This gets called at the end of handling a page fault, when
+ * the kernel has put a new PTE into the page table for the process.
+ * We use it to ensure coherency between the i-cache and d-cache
+ * for the page which has just been mapped in.
+ * On machines which use an MMU hash table, we use this to put a
+ * corresponding HPTE into the hash table ahead of time, instead of
+ * waiting for the inevitable extra hash-table miss exception.
+ */
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+
+#endif /* _PPC_TLBFLUSH_H */
+#endif /*__KERNEL__ */
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h
new file mode 100644
index 000000000000..84bae7d76814
--- /dev/null
+++ b/include/asm-ppc/todc.h
@@ -0,0 +1,490 @@
+/*
+ * include/asm-ppc/todc.h
+ *
+ * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
+ * Clock chips.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
+ * Purpose is to make one generic file that handles all of these chips instead
+ * of every platform implementing the same code over & over again.
+ */
+
+#ifndef __PPC_KERNEL_TODC_H
+#define __PPC_KERNEL_TODC_H
+
+typedef struct {
+        uint rtc_type;          /* your particular chip */
+
+        /*
+         * Following are the addresses of the AS0, AS1, and DATA registers
+         * of these chips.  Note that these are board-specific.
+         */
+        unsigned int nvram_as0;
+        unsigned int nvram_as1;
+        unsigned int nvram_data;
+
+        /*
+         * Define bits to stop external set of regs from changing so
+         * the chip can be read/written reliably.
+         */
+        unsigned char enable_read;
+        unsigned char enable_write;
+
+        /*
+         * Following is the number of AS0 address bits.  This is normally
+         * 8 but some bad hardware routes address lines incorrectly.
+         */
+        int as0_bits;
+
+        int nvram_size; /* Size of NVRAM on chip */
+        int sw_flags;   /* Software control flags */
+
+        /* Following are the register offsets for the particular chip */
+        int year;
+        int month;
+        int day_of_month;
+        int day_of_week;
+        int hours;
+        int minutes;
+        int seconds;
+        int control_b;
+        int control_a;
+        int watchdog;
+        int interrupts;
+        int alarm_date;
+        int alarm_hour;
+        int alarm_minutes;
+        int alarm_seconds;
+        int century;
+        int flags;
+
+        /*
+         * Some RTC chips have their NVRAM buried behind a addr/data pair of
+         * regs on the first level/clock registers.  The following fields
+         * are the addresses for those addr/data regs.
+         */
+        int nvram_addr_reg;
+        int nvram_data_reg;
+} todc_info_t;
+
+/*
+ * Define the types of TODC/RTC variants that are supported in
+ * arch/ppc/kernel/todc_time.c
+ * Make a new one of these for any chip somehow differs from what's already
+ * defined.  That way, if you ever need to put in code to touch those
+ * bits/registers in todc_time.c, you can put it inside an
+ * 'if (todc_info->rtc_type ==  TODC_TYPE_XXX)' so you won't break
+ * anyone else.
+ */
+#define TODC_TYPE_MK48T35               1
+#define TODC_TYPE_MK48T37               2
+#define TODC_TYPE_MK48T59               3
+#define TODC_TYPE_DS1693                4       /* Dallas DS1693 RTC */
+#define TODC_TYPE_DS1743                5       /* Dallas DS1743 RTC */
+#define TODC_TYPE_DS1746                6       /* Dallas DS1746 RTC */
+#define TODC_TYPE_DS1747                7       /* Dallas DS1747 RTC */
+#define TODC_TYPE_DS1501                8       /* Dallas DS1501 RTC */
+#define TODC_TYPE_DS1643                9       /* Dallas DS1643 RTC */
+#define TODC_TYPE_PC97307               10      /* PC97307 internal RTC */
+#define TODC_TYPE_DS1557                11      /* Dallas DS1557 RTC */
+#define TODC_TYPE_DS17285               12      /* Dallas DS17285 RTC */
+#define TODC_TYPE_DS1553                13      /* Dallas DS1553 RTC */
+#define TODC_TYPE_MC146818              100     /* Leave room for m48txx's */
+
+/*
+ * Bit to clear/set to enable reads/writes to the chip
+ */
+#define TODC_MK48TXX_CNTL_A_R           0x40
+#define TODC_MK48TXX_CNTL_A_W           0x80
+#define TODC_MK48TXX_DAY_CB             0x80
+
+#define TODC_DS1501_CNTL_B_TE           0x80
+
+/*
+ * Define flag bits used by todc routines.
+ */
+#define TODC_FLAG_2_LEVEL_NVRAM         0x00000001
+
+/*
+ * Define the values for the various RTC's that should to into the todc_info
+ * table.
+ * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
+ * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
+ */
+#define TODC_TYPE_MK48T35_NVRAM_SIZE            0x7ff8
+#define TODC_TYPE_MK48T35_SW_FLAGS              0
+#define TODC_TYPE_MK48T35_YEAR                  0x7fff
+#define TODC_TYPE_MK48T35_MONTH                 0x7ffe
+#define TODC_TYPE_MK48T35_DOM                   0x7ffd  /* Day of Month */
+#define TODC_TYPE_MK48T35_DOW                   0x7ffc  /* Day of Week */
+#define TODC_TYPE_MK48T35_HOURS                 0x7ffb
+#define TODC_TYPE_MK48T35_MINUTES               0x7ffa
+#define TODC_TYPE_MK48T35_SECONDS               0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_B                0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_A                0x7ff8
+#define TODC_TYPE_MK48T35_WATCHDOG              0x0000
+#define TODC_TYPE_MK48T35_INTERRUPTS            0x0000
+#define TODC_TYPE_MK48T35_ALARM_DATE            0x0000
+#define TODC_TYPE_MK48T35_ALARM_HOUR            0x0000
+#define TODC_TYPE_MK48T35_ALARM_MINUTES         0x0000
+#define TODC_TYPE_MK48T35_ALARM_SECONDS         0x0000
+#define TODC_TYPE_MK48T35_CENTURY               0x0000
+#define TODC_TYPE_MK48T35_FLAGS                 0x0000
+#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T35_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_MK48T37_NVRAM_SIZE            0x7ff0
+#define TODC_TYPE_MK48T37_SW_FLAGS              0
+#define TODC_TYPE_MK48T37_YEAR                  0x7fff
+#define TODC_TYPE_MK48T37_MONTH                 0x7ffe
+#define TODC_TYPE_MK48T37_DOM                   0x7ffd  /* Day of Month */
+#define TODC_TYPE_MK48T37_DOW                   0x7ffc  /* Day of Week */
+#define TODC_TYPE_MK48T37_HOURS                 0x7ffb
+#define TODC_TYPE_MK48T37_MINUTES               0x7ffa
+#define TODC_TYPE_MK48T37_SECONDS               0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_B                0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_A                0x7ff8
+#define TODC_TYPE_MK48T37_WATCHDOG              0x7ff7
+#define TODC_TYPE_MK48T37_INTERRUPTS            0x7ff6
+#define TODC_TYPE_MK48T37_ALARM_DATE            0x7ff5
+#define TODC_TYPE_MK48T37_ALARM_HOUR            0x7ff4
+#define TODC_TYPE_MK48T37_ALARM_MINUTES         0x7ff3
+#define TODC_TYPE_MK48T37_ALARM_SECONDS         0x7ff2
+#define TODC_TYPE_MK48T37_CENTURY               0x7ff1
+#define TODC_TYPE_MK48T37_FLAGS                 0x7ff0
+#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T37_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_MK48T59_NVRAM_SIZE            0x1ff0
+#define TODC_TYPE_MK48T59_SW_FLAGS              0
+#define TODC_TYPE_MK48T59_YEAR                  0x1fff
+#define TODC_TYPE_MK48T59_MONTH                 0x1ffe
+#define TODC_TYPE_MK48T59_DOM                   0x1ffd  /* Day of Month */
+#define TODC_TYPE_MK48T59_DOW                   0x1ffc  /* Day of Week */
+#define TODC_TYPE_MK48T59_HOURS                 0x1ffb
+#define TODC_TYPE_MK48T59_MINUTES               0x1ffa
+#define TODC_TYPE_MK48T59_SECONDS               0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_B                0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_A                0x1ff8
+#define TODC_TYPE_MK48T59_WATCHDOG              0x1fff
+#define TODC_TYPE_MK48T59_INTERRUPTS            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_DATE            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_HOUR            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_MINUTES         0x1fff
+#define TODC_TYPE_MK48T59_ALARM_SECONDS         0x1fff
+#define TODC_TYPE_MK48T59_CENTURY               0x1fff
+#define TODC_TYPE_MK48T59_FLAGS                 0x1fff
+#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T59_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_DS1501_NVRAM_SIZE     0x100
+#define TODC_TYPE_DS1501_SW_FLAGS       TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS1501_YEAR           (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS1501_MONTH          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS1501_DOM            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS1501_DOW            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS1501_HOURS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS1501_MINUTES        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS1501_SECONDS        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS1501_CNTL_B         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_CNTL_A         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_WATCHDOG       (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_INTERRUPTS     (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_ALARM_DATE     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
+#define TODC_TYPE_DS1501_ALARM_HOUR     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
+#define TODC_TYPE_DS1501_ALARM_MINUTES  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS1501_ALARM_SECONDS  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS1501_CENTURY        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS1501_FLAGS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
+#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
+
+#define TODC_TYPE_DS1553_NVRAM_SIZE             0x1ff0
+#define TODC_TYPE_DS1553_SW_FLAGS               0
+#define TODC_TYPE_DS1553_YEAR                   0x1fff
+#define TODC_TYPE_DS1553_MONTH                  0x1ffe
+#define TODC_TYPE_DS1553_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1553_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1553_HOURS                  0x1ffb
+#define TODC_TYPE_DS1553_MINUTES                0x1ffa
+#define TODC_TYPE_DS1553_SECONDS                0x1ff9
+#define TODC_TYPE_DS1553_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1553_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1553_WATCHDOG               0x1ff7
+#define TODC_TYPE_DS1553_INTERRUPTS             0x1ff6
+#define TODC_TYPE_DS1553_ALARM_DATE             0x1ff5
+#define TODC_TYPE_DS1553_ALARM_HOUR             0x1ff4
+#define TODC_TYPE_DS1553_ALARM_MINUTES          0x1ff3
+#define TODC_TYPE_DS1553_ALARM_SECONDS          0x1ff2
+#define TODC_TYPE_DS1553_CENTURY                0x1ff8
+#define TODC_TYPE_DS1553_FLAGS                  0x1ff0
+#define TODC_TYPE_DS1553_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1553_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1557_NVRAM_SIZE             0x7fff0
+#define TODC_TYPE_DS1557_SW_FLAGS               0
+#define TODC_TYPE_DS1557_YEAR                   0x7ffff
+#define TODC_TYPE_DS1557_MONTH                  0x7fffe
+#define TODC_TYPE_DS1557_DOM                    0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1557_DOW                    0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1557_HOURS                  0x7fffb
+#define TODC_TYPE_DS1557_MINUTES                0x7fffa
+#define TODC_TYPE_DS1557_SECONDS                0x7fff9
+#define TODC_TYPE_DS1557_CNTL_B                 0x7fff9
+#define TODC_TYPE_DS1557_CNTL_A                 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1557_WATCHDOG               0x7fff7
+#define TODC_TYPE_DS1557_INTERRUPTS             0x7fff6
+#define TODC_TYPE_DS1557_ALARM_DATE             0x7fff5
+#define TODC_TYPE_DS1557_ALARM_HOUR             0x7fff4
+#define TODC_TYPE_DS1557_ALARM_MINUTES          0x7fff3
+#define TODC_TYPE_DS1557_ALARM_SECONDS          0x7fff2
+#define TODC_TYPE_DS1557_CENTURY                0x7fff8
+#define TODC_TYPE_DS1557_FLAGS                  0x7fff0
+#define TODC_TYPE_DS1557_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1557_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1643_NVRAM_SIZE             0x1ff8
+#define TODC_TYPE_DS1643_SW_FLAGS               0
+#define TODC_TYPE_DS1643_YEAR                   0x1fff
+#define TODC_TYPE_DS1643_MONTH                  0x1ffe
+#define TODC_TYPE_DS1643_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1643_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1643_HOURS                  0x1ffb
+#define TODC_TYPE_DS1643_MINUTES                0x1ffa
+#define TODC_TYPE_DS1643_SECONDS                0x1ff9
+#define TODC_TYPE_DS1643_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1643_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1643_WATCHDOG               0x1fff
+#define TODC_TYPE_DS1643_INTERRUPTS             0x1fff
+#define TODC_TYPE_DS1643_ALARM_DATE             0x1fff
+#define TODC_TYPE_DS1643_ALARM_HOUR             0x1fff
+#define TODC_TYPE_DS1643_ALARM_MINUTES          0x1fff
+#define TODC_TYPE_DS1643_ALARM_SECONDS          0x1fff
+#define TODC_TYPE_DS1643_CENTURY                0x1ff8
+#define TODC_TYPE_DS1643_FLAGS                  0x1fff
+#define TODC_TYPE_DS1643_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1643_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1693_NVRAM_SIZE             0 /* Not handled yet */
+#define TODC_TYPE_DS1693_SW_FLAGS               0
+#define TODC_TYPE_DS1693_YEAR                   0x09
+#define TODC_TYPE_DS1693_MONTH                  0x08
+#define TODC_TYPE_DS1693_DOM                    0x07    /* Day of Month */
+#define TODC_TYPE_DS1693_DOW                    0x06    /* Day of Week */
+#define TODC_TYPE_DS1693_HOURS                  0x04
+#define TODC_TYPE_DS1693_MINUTES                0x02
+#define TODC_TYPE_DS1693_SECONDS                0x00
+#define TODC_TYPE_DS1693_CNTL_B                 0x0b
+#define TODC_TYPE_DS1693_CNTL_A                 0x0a
+#define TODC_TYPE_DS1693_WATCHDOG               0xff
+#define TODC_TYPE_DS1693_INTERRUPTS             0xff
+#define TODC_TYPE_DS1693_ALARM_DATE             0x49
+#define TODC_TYPE_DS1693_ALARM_HOUR             0x05
+#define TODC_TYPE_DS1693_ALARM_MINUTES          0x03
+#define TODC_TYPE_DS1693_ALARM_SECONDS          0x01
+#define TODC_TYPE_DS1693_CENTURY                0x48
+#define TODC_TYPE_DS1693_FLAGS                  0xff
+#define TODC_TYPE_DS1693_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1693_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1743_NVRAM_SIZE             0x1ff8
+#define TODC_TYPE_DS1743_SW_FLAGS               0
+#define TODC_TYPE_DS1743_YEAR                   0x1fff
+#define TODC_TYPE_DS1743_MONTH                  0x1ffe
+#define TODC_TYPE_DS1743_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1743_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1743_HOURS                  0x1ffb
+#define TODC_TYPE_DS1743_MINUTES                0x1ffa
+#define TODC_TYPE_DS1743_SECONDS                0x1ff9
+#define TODC_TYPE_DS1743_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1743_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1743_WATCHDOG               0x1fff
+#define TODC_TYPE_DS1743_INTERRUPTS             0x1fff
+#define TODC_TYPE_DS1743_ALARM_DATE             0x1fff
+#define TODC_TYPE_DS1743_ALARM_HOUR             0x1fff
+#define TODC_TYPE_DS1743_ALARM_MINUTES          0x1fff
+#define TODC_TYPE_DS1743_ALARM_SECONDS          0x1fff
+#define TODC_TYPE_DS1743_CENTURY                0x1ff8
+#define TODC_TYPE_DS1743_FLAGS                  0x1fff
+#define TODC_TYPE_DS1743_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1743_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1746_NVRAM_SIZE             0x1fff8
+#define TODC_TYPE_DS1746_SW_FLAGS               0
+#define TODC_TYPE_DS1746_YEAR                   0x1ffff
+#define TODC_TYPE_DS1746_MONTH                  0x1fffe
+#define TODC_TYPE_DS1746_DOM                    0x1fffd /* Day of Month */
+#define TODC_TYPE_DS1746_DOW                    0x1fffc /* Day of Week */
+#define TODC_TYPE_DS1746_HOURS                  0x1fffb
+#define TODC_TYPE_DS1746_MINUTES                0x1fffa
+#define TODC_TYPE_DS1746_SECONDS                0x1fff9
+#define TODC_TYPE_DS1746_CNTL_B                 0x1fff9
+#define TODC_TYPE_DS1746_CNTL_A                 0x1fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1746_WATCHDOG               0x00000
+#define TODC_TYPE_DS1746_INTERRUPTS             0x00000
+#define TODC_TYPE_DS1746_ALARM_DATE             0x00000
+#define TODC_TYPE_DS1746_ALARM_HOUR             0x00000
+#define TODC_TYPE_DS1746_ALARM_MINUTES          0x00000
+#define TODC_TYPE_DS1746_ALARM_SECONDS          0x00000
+#define TODC_TYPE_DS1746_CENTURY                0x00000
+#define TODC_TYPE_DS1746_FLAGS                  0x00000
+#define TODC_TYPE_DS1746_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1746_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1747_NVRAM_SIZE             0x7fff8
+#define TODC_TYPE_DS1747_SW_FLAGS               0
+#define TODC_TYPE_DS1747_YEAR                   0x7ffff
+#define TODC_TYPE_DS1747_MONTH                  0x7fffe
+#define TODC_TYPE_DS1747_DOM                    0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1747_DOW                    0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1747_HOURS                  0x7fffb
+#define TODC_TYPE_DS1747_MINUTES                0x7fffa
+#define TODC_TYPE_DS1747_SECONDS                0x7fff9
+#define TODC_TYPE_DS1747_CNTL_B                 0x7fff9
+#define TODC_TYPE_DS1747_CNTL_A                 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1747_WATCHDOG               0x00000
+#define TODC_TYPE_DS1747_INTERRUPTS             0x00000
+#define TODC_TYPE_DS1747_ALARM_DATE             0x00000
+#define TODC_TYPE_DS1747_ALARM_HOUR             0x00000
+#define TODC_TYPE_DS1747_ALARM_MINUTES          0x00000
+#define TODC_TYPE_DS1747_ALARM_SECONDS          0x00000
+#define TODC_TYPE_DS1747_CENTURY                0x00000
+#define TODC_TYPE_DS1747_FLAGS                  0x00000
+#define TODC_TYPE_DS1747_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1747_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS17285_NVRAM_SIZE            (0x1000-0x80)    /* 4Kx8 NVRAM (minus RTC regs) */
+#define TODC_TYPE_DS17285_SW_FLAGS              TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS17285_SECONDS               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS17285_ALARM_SECONDS         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS17285_MINUTES               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS17285_ALARM_MINUTES         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS17285_HOURS                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS17285_ALARM_HOUR            (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS17285_DOW                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS17285_DOM                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS17285_MONTH                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS17285_YEAR                  (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS17285_CNTL_A                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
+#define TODC_TYPE_DS17285_CNTL_B                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
+#define TODC_TYPE_DS17285_CNTL_C                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
+#define TODC_TYPE_DS17285_CNTL_D                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
+#define TODC_TYPE_DS17285_WATCHDOG              0
+#define TODC_TYPE_DS17285_INTERRUPTS            0
+#define TODC_TYPE_DS17285_ALARM_DATE            0
+#define TODC_TYPE_DS17285_CENTURY               0
+#define TODC_TYPE_DS17285_FLAGS                 0
+#define TODC_TYPE_DS17285_NVRAM_ADDR_REG        0x50
+#define TODC_TYPE_DS17285_NVRAM_DATA_REG        0x53
+ 
+#define TODC_TYPE_MC146818_NVRAM_SIZE           0       /* XXXX */
+#define TODC_TYPE_MC146818_SW_FLAGS             0
+#define TODC_TYPE_MC146818_YEAR                 0x09
+#define TODC_TYPE_MC146818_MONTH                0x08
+#define TODC_TYPE_MC146818_DOM                  0x07    /* Day of Month */
+#define TODC_TYPE_MC146818_DOW                  0x06    /* Day of Week */
+#define TODC_TYPE_MC146818_HOURS                0x04
+#define TODC_TYPE_MC146818_MINUTES              0x02
+#define TODC_TYPE_MC146818_SECONDS              0x00
+#define TODC_TYPE_MC146818_CNTL_B               0x0a
+#define TODC_TYPE_MC146818_CNTL_A               0x0b    /* control_a R/W regs */
+#define TODC_TYPE_MC146818_WATCHDOG             0
+#define TODC_TYPE_MC146818_INTERRUPTS           0x0c
+#define TODC_TYPE_MC146818_ALARM_DATE           0xff
+#define TODC_TYPE_MC146818_ALARM_HOUR           0x05
+#define TODC_TYPE_MC146818_ALARM_MINUTES        0x03
+#define TODC_TYPE_MC146818_ALARM_SECONDS        0x01
+#define TODC_TYPE_MC146818_CENTURY              0xff
+#define TODC_TYPE_MC146818_FLAGS                0xff
+#define TODC_TYPE_MC146818_NVRAM_ADDR_REG       0
+#define TODC_TYPE_MC146818_NVRAM_DATA_REG       0
+  
+#define TODC_TYPE_PC97307_NVRAM_SIZE            0       /* No NVRAM? */
+#define TODC_TYPE_PC97307_SW_FLAGS              0
+#define TODC_TYPE_PC97307_YEAR                  0x09
+#define TODC_TYPE_PC97307_MONTH                 0x08
+#define TODC_TYPE_PC97307_DOM                   0x07    /* Day of Month */
+#define TODC_TYPE_PC97307_DOW                   0x06    /* Day of Week */
+#define TODC_TYPE_PC97307_HOURS                 0x04
+#define TODC_TYPE_PC97307_MINUTES               0x02
+#define TODC_TYPE_PC97307_SECONDS               0x00
+#define TODC_TYPE_PC97307_CNTL_B                0x0a
+#define TODC_TYPE_PC97307_CNTL_A                0x0b    /* control_a R/W regs */
+#define TODC_TYPE_PC97307_WATCHDOG              0x0c
+#define TODC_TYPE_PC97307_INTERRUPTS            0x0d
+#define TODC_TYPE_PC97307_ALARM_DATE            0xff
+#define TODC_TYPE_PC97307_ALARM_HOUR            0x05
+#define TODC_TYPE_PC97307_ALARM_MINUTES         0x03
+#define TODC_TYPE_PC97307_ALARM_SECONDS         0x01
+#define TODC_TYPE_PC97307_CENTURY               0xff
+#define TODC_TYPE_PC97307_FLAGS                 0xff
+#define TODC_TYPE_PC97307_NVRAM_ADDR_REG        0
+#define TODC_TYPE_PC97307_NVRAM_DATA_REG        0
+
+/*
+ * Define macros to allocate and init the todc_info_t table that will
+ * be used by the todc_time.c routines.
+ */
+#define TODC_ALLOC()                                                    \
+        static todc_info_t todc_info_alloc;                             \
+        todc_info_t *todc_info = &todc_info_alloc;
+
+#define TODC_INIT(clock_type, as0, as1, data, bits) {                   \
+        todc_info->rtc_type = clock_type;                               \
+                                                                        \
+        todc_info->nvram_as0  = (unsigned int)(as0);                    \
+        todc_info->nvram_as1  = (unsigned int)(as1);                    \
+        todc_info->nvram_data = (unsigned int)(data);                   \
+                                                                        \
+        todc_info->as0_bits = (bits);                                   \
+                                                                        \
+        todc_info->nvram_size     = clock_type ##_NVRAM_SIZE;           \
+        todc_info->sw_flags       = clock_type ##_SW_FLAGS;             \
+                                                                        \
+        todc_info->year           = clock_type ##_YEAR;                 \
+        todc_info->month          = clock_type ##_MONTH;                \
+        todc_info->day_of_month   = clock_type ##_DOM;                  \
+        todc_info->day_of_week    = clock_type ##_DOW;                  \
+        todc_info->hours          = clock_type ##_HOURS;                \
+        todc_info->minutes        = clock_type ##_MINUTES;              \
+        todc_info->seconds        = clock_type ##_SECONDS;              \
+        todc_info->control_b      = clock_type ##_CNTL_B;               \
+        todc_info->control_a      = clock_type ##_CNTL_A;               \
+        todc_info->watchdog       = clock_type ##_WATCHDOG;             \
+        todc_info->interrupts     = clock_type ##_INTERRUPTS;           \
+        todc_info->alarm_date     = clock_type ##_ALARM_DATE;           \
+        todc_info->alarm_hour     = clock_type ##_ALARM_HOUR;           \
+        todc_info->alarm_minutes  = clock_type ##_ALARM_MINUTES;        \
+        todc_info->alarm_seconds  = clock_type ##_ALARM_SECONDS;        \
+        todc_info->century        = clock_type ##_CENTURY;              \
+        todc_info->flags          = clock_type ##_FLAGS;                \
+                                                                        \
+        todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;       \
+        todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;       \
+}
+
+extern todc_info_t *todc_info;
+
+unsigned char todc_direct_read_val(int addr);
+void todc_direct_write_val(int addr, unsigned char val);
+unsigned char todc_m48txx_read_val(int addr);
+void todc_m48txx_write_val(int addr, unsigned char val);
+unsigned char todc_mc146818_read_val(int addr);
+void todc_mc146818_write_val(int addr, unsigned char val);
+
+long todc_time_init(void);
+unsigned long todc_get_rtc_time(void);
+int todc_set_rtc_time(unsigned long nowtime);
+void todc_calibrate_decr(void);
+
+#endif                          /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-ppc/topology.h b/include/asm-ppc/topology.h
new file mode 100644
index 000000000000..6a029bbba6e1
--- /dev/null
+++ b/include/asm-ppc/topology.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_PPC_TOPOLOGY_H
+#define _ASM_PPC_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_PPC_TOPOLOGY_H */
diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h
new file mode 100644
index 000000000000..68e7326b56f1
--- /dev/null
+++ b/include/asm-ppc/traps.h
@@ -0,0 +1 @@
+#include <asm-m68k/traps.h>
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
new file mode 100644
index 000000000000..a787bc032587
--- /dev/null
+++ b/include/asm-ppc/types.h
@@ -0,0 +1,71 @@
+#ifndef _PPC_TYPES_H
+#define _PPC_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+        __u32 u[4];
+} __vector128;
+
+/*
+ * XXX allowed outside of __KERNEL__ for now, until glibc gets
+ * a proper set of asm headers of its own.  -- paulus
+ */
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+typedef __vector128 vector128;
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+typedef u64 dma64_addr_t;
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+typedef unsigned int kmem_bufctl_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h
new file mode 100644
index 000000000000..b044ae03ac56
--- /dev/null
+++ b/include/asm-ppc/uaccess.h
@@ -0,0 +1,400 @@
+#ifdef __KERNEL__
+#ifndef _PPC_UACCESS_H
+#define _PPC_UACCESS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <asm/processor.h>
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ *
+ * The fs/ds values are now the highest legal address in the "segment".
+ * This simplifies the checking in the routines below.
+ */
+
+#define KERNEL_DS       ((mm_segment_t) { ~0UL })
+#define USER_DS         ((mm_segment_t) { TASK_SIZE - 1 })
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current->thread.fs)
+#define set_fs(val)     (current->thread.fs = (val))
+
+#define segment_eq(a,b) ((a).seg == (b).seg)
+
+#define __access_ok(addr,size)                                              \
+        ((addr) <= current->thread.fs.seg                                   \
+         && ((size) == 0 || (size) - 1 <= current->thread.fs.seg - (addr)))
+
+#define access_ok(type, addr, size) \
+        (__chk_user_ptr(addr),__access_ok((unsigned long)(addr),(size)))
+
+/* this function will go away soon - use access_ok() instead */
+extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size)
+{
+        return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+        unsigned long insn, fixup;
+};
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on the
+ * PowerPC, we can just do these as direct assignments.  (Of course, the
+ * exception handling means that it's no longer "just"...)
+ *
+ * The "user64" versions of the user access functions are versions that 
+ * allow access of 64-bit data. The "get_user" functions do not 
+ * properly handle 64-bit data because the value gets down cast to a long. 
+ * The "put_user" functions already handle 64-bit data properly but we add 
+ * "user64" versions for completeness
+ */
+#define get_user(x,ptr) \
+  __get_user_check((x),(ptr),sizeof(*(ptr)))
+#define get_user64(x,ptr) \
+  __get_user64_check((x),(ptr),sizeof(*(ptr)))
+#define put_user(x,ptr) \
+  __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+#define put_user64(x,ptr) put_user(x,ptr)
+
+#define __get_user(x,ptr) \
+  __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
+#define __get_user64(x,ptr) \
+  __get_user64_nocheck((x),(ptr),sizeof(*(ptr)))
+#define __put_user(x,ptr) \
+  __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
+#define __put_user64(x,ptr) __put_user(x,ptr)
+
+extern long __put_user_bad(void);
+
+#define __put_user_nocheck(x,ptr,size)                  \
+({                                                      \
+        long __pu_err;                                  \
+        __chk_user_ptr(ptr);                            \
+        __put_user_size((x),(ptr),(size),__pu_err);     \
+        __pu_err;                                       \
+})
+
+#define __put_user_check(x,ptr,size)                            \
+({                                                              \
+        long __pu_err = -EFAULT;                                \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
+        if (access_ok(VERIFY_WRITE,__pu_addr,size))             \
+                __put_user_size((x),__pu_addr,(size),__pu_err); \
+        __pu_err;                                               \
+})
+
+#define __put_user_size(x,ptr,size,retval)              \
+do {                                                    \
+        retval = 0;                                     \
+        switch (size) {                                 \
+        case 1:                                         \
+                __put_user_asm(x, ptr, retval, "stb");  \
+                break;                                  \
+        case 2:                                         \
+                __put_user_asm(x, ptr, retval, "sth");  \
+                break;                                  \
+        case 4:                                         \
+                __put_user_asm(x, ptr, retval, "stw");  \
+                break;                                  \
+        case 8:                                         \
+                __put_user_asm2(x, ptr, retval);        \
+                break;                                  \
+        default:                                        \
+                __put_user_bad();                       \
+        }                                               \
+} while (0)
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ */
+#define __put_user_asm(x, addr, err, op)                        \
+        __asm__ __volatile__(                                   \
+                "1:     "op" %1,0(%2)\n"                        \
+                "2:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "3:     li %0,%3\n"                             \
+                "       b 2b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                "       .align 2\n"                             \
+                "       .long 1b,3b\n"                          \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+
+#define __put_user_asm2(x, addr, err)                           \
+        __asm__ __volatile__(                                   \
+                "1:     stw %1,0(%2)\n"                         \
+                "2:     stw %1+1,4(%2)\n"                       \
+                "3:\n"                                          \
+                ".section .fixup,\"ax\"\n"                      \
+                "4:     li %0,%3\n"                             \
+                "       b 3b\n"                                 \
+                ".previous\n"                                   \
+                ".section __ex_table,\"a\"\n"                   \
+                "       .align 2\n"                             \
+                "       .long 1b,4b\n"                          \
+                "       .long 2b,4b\n"                          \
+                ".previous"                                     \
+                : "=r" (err)                                    \
+                : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
+
+#define __get_user_nocheck(x, ptr, size)                        \
+({                                                              \
+        long __gu_err;                                          \
+        unsigned long __gu_val;                                 \
+        __chk_user_ptr(ptr);                                    \
+        __get_user_size(__gu_val, (ptr), (size), __gu_err);     \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#define __get_user64_nocheck(x, ptr, size)                      \
+({                                                              \
+        long __gu_err;                                          \
+        long long __gu_val;                                     \
+        __chk_user_ptr(ptr);                                    \
+        __get_user_size64(__gu_val, (ptr), (size), __gu_err);   \
+        (x) = (__typeof__(*(ptr)))__gu_val;                     \
+        __gu_err;                                               \
+})
+
+#define __get_user_check(x, ptr, size)                                  \
+({                                                                      \
+        long __gu_err = -EFAULT;                                        \
+        unsigned long  __gu_val = 0;                                    \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
+        if (access_ok(VERIFY_READ, __gu_addr, (size)))                  \
+                __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+        __gu_err;                                                       \
+})
+
+#define __get_user64_check(x, ptr, size)                                  \
+({                                                                        \
+        long __gu_err = -EFAULT;                                          \
+        long long __gu_val = 0;                                           \
+        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);               \
+        if (access_ok(VERIFY_READ, __gu_addr, (size)))                    \
+                __get_user_size64(__gu_val, __gu_addr, (size), __gu_err); \
+        (x) = (__typeof__(*(ptr)))__gu_val;                               \
+        __gu_err;                                                         \
+})
+
+extern long __get_user_bad(void);
+
+#define __get_user_size(x, ptr, size, retval)                   \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                __get_user_asm(x, ptr, retval, "lbz");          \
+                break;                                          \
+        case 2:                                                 \
+                __get_user_asm(x, ptr, retval, "lhz");          \
+                break;                                          \
+        case 4:                                                 \
+                __get_user_asm(x, ptr, retval, "lwz");          \
+                break;                                          \
+        default:                                                \
+                x = __get_user_bad();                           \
+        }                                                       \
+} while (0)
+
+#define __get_user_size64(x, ptr, size, retval)                 \
+do {                                                            \
+        retval = 0;                                             \
+        switch (size) {                                         \
+        case 1:                                                 \
+                __get_user_asm(x, ptr, retval, "lbz");          \
+                break;                                          \
+        case 2:                                                 \
+                __get_user_asm(x, ptr, retval, "lhz");          \
+                break;                                          \
+        case 4:                                                 \
+                __get_user_asm(x, ptr, retval, "lwz");          \
+                break;                                          \
+        case 8:                                                 \
+                __get_user_asm2(x, ptr, retval);                \
+                break;                                          \
+        default:                                                \
+                x = __get_user_bad();                           \
+        }                                                       \
+} while (0)
+
+#define __get_user_asm(x, addr, err, op)                \
+        __asm__ __volatile__(                           \
+                "1:     "op" %1,0(%2)\n"                \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       b 2b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align 2\n"                     \
+                "       .long 1b,3b\n"                  \
+                ".previous"                             \
+                : "=r"(err), "=r"(x)                    \
+                : "b"(addr), "i"(-EFAULT), "0"(err))
+
+#define __get_user_asm2(x, addr, err)                   \
+        __asm__ __volatile__(                           \
+                "1:     lwz %1,0(%2)\n"                 \
+                "2:     lwz %1+1,4(%2)\n"               \
+                "3:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "4:     li %0,%3\n"                     \
+                "       li %1,0\n"                      \
+                "       li %1+1,0\n"                    \
+                "       b 3b\n"                         \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                "       .align 2\n"                     \
+                "       .long 1b,4b\n"                  \
+                "       .long 2b,4b\n"                  \
+                ".previous"                             \
+                : "=r"(err), "=&r"(x)                   \
+                : "b"(addr), "i"(-EFAULT), "0"(err))
+
+/* more complex routines */
+
+extern int __copy_tofrom_user(void __user *to, const void __user *from,
+                              unsigned long size);
+
+extern inline unsigned long
+copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        unsigned long over;
+
+        if (access_ok(VERIFY_READ, from, n))
+                return __copy_tofrom_user((__force void __user *)to, from, n);
+        if ((unsigned long)from < TASK_SIZE) {
+                over = (unsigned long)from + n - TASK_SIZE;
+                return __copy_tofrom_user((__force void __user *)to, from, n - over) + over;
+        }
+        return n;
+}
+
+extern inline unsigned long
+copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        unsigned long over;
+
+        if (access_ok(VERIFY_WRITE, to, n))
+                return __copy_tofrom_user(to, (__force void __user *) from, n);
+        if ((unsigned long)to < TASK_SIZE) {
+                over = (unsigned long)to + n - TASK_SIZE;
+                return __copy_tofrom_user(to, (__force void __user *) from, n - over) + over;
+        }
+        return n;
+}
+
+static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long size)
+{
+        return __copy_tofrom_user((__force void __user *)to, from, size);
+}
+
+static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long size)
+{
+        return __copy_tofrom_user(to, (__force void __user *)from, size);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+extern unsigned long __clear_user(void __user *addr, unsigned long size);
+
+extern inline unsigned long
+clear_user(void __user *addr, unsigned long size)
+{
+        if (access_ok(VERIFY_WRITE, addr, size))
+                return __clear_user(addr, size);
+        if ((unsigned long)addr < TASK_SIZE) {
+                unsigned long over = (unsigned long)addr + size - TASK_SIZE;
+                return __clear_user(addr, size - over) + over;
+        }
+        return size;
+}
+
+extern int __strncpy_from_user(char *dst, const char __user *src, long count);
+
+extern inline long
+strncpy_from_user(char *dst, const char __user *src, long count)
+{
+        if (access_ok(VERIFY_READ, src, 1))
+                return __strncpy_from_user(dst, src, count);
+        return -EFAULT;
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 for error
+ */
+
+extern int __strnlen_user(const char __user *str, long len, unsigned long top);
+
+/*
+ * Returns the length of the string at str (including the null byte),
+ * or 0 if we hit a page we can't access,
+ * or something > len if we didn't find a null byte.
+ *
+ * The `top' parameter to __strnlen_user is to make sure that
+ * we can never overflow from the user area into kernel space.
+ */
+extern __inline__ int strnlen_user(const char __user *str, long len)
+{
+        unsigned long top = current->thread.fs.seg;
+
+        if ((unsigned long)str > top)
+                return 0;
+        return __strnlen_user(str, len, top);
+}
+
+#define strlen_user(str)        strnlen_user((str), 0x7ffffffe)
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _PPC_UACCESS_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ucontext.h b/include/asm-ppc/ucontext.h
new file mode 100644
index 000000000000..664bc984d51f
--- /dev/null
+++ b/include/asm-ppc/ucontext.h
@@ -0,0 +1,27 @@
+#ifndef _ASMPPC_UCONTEXT_H
+#define _ASMPPC_UCONTEXT_H
+
+#include <asm/elf.h>
+#include <asm/signal.h>
+
+struct mcontext {
+        elf_gregset_t   mc_gregs;
+        elf_fpregset_t  mc_fregs;
+        unsigned long   mc_pad[2];
+        elf_vrregset_t  mc_vregs __attribute__((__aligned__(16)));
+};
+
+struct ucontext {
+        unsigned long    uc_flags;
+        struct ucontext __user *uc_link;
+        stack_t          uc_stack;
+        int              uc_pad[7];
+        struct mcontext __user *uc_regs;/* points to uc_mcontext field */
+        sigset_t         uc_sigmask;
+        /* glibc has 1024-bit signal masks, ours are 64-bit */
+        int              uc_maskext[30];
+        int              uc_pad2[3];
+        struct mcontext  uc_mcontext;
+};
+
+#endif /* !_ASMPPC_UCONTEXT_H */
diff --git a/include/asm-ppc/unaligned.h b/include/asm-ppc/unaligned.h
new file mode 100644
index 000000000000..45520d9b85d1
--- /dev/null
+++ b/include/asm-ppc/unaligned.h
@@ -0,0 +1,18 @@
+#ifdef __KERNEL__
+#ifndef __PPC_UNALIGNED_H
+#define __PPC_UNALIGNED_H
+
+/*
+ * The PowerPC can do unaligned accesses itself in big endian mode.
+ *
+ * The strange macros are there to make sure these can't
+ * be misused in a way that makes them not work on other
+ * architectures where unaligned accesses aren't as simple.
+ */
+
+#define get_unaligned(ptr) (*(ptr))
+
+#define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/uninorth.h b/include/asm-ppc/uninorth.h
new file mode 100644
index 000000000000..f737732c3861
--- /dev/null
+++ b/include/asm-ppc/uninorth.h
@@ -0,0 +1,229 @@
+/*
+ * uninorth.h: definitions for using the "UniNorth" host bridge chip
+ *             from Apple. This chip is used on "Core99" machines
+ *             This also includes U2 used on more recent MacRISC2/3
+ *             machines and U3 (G5) 
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __ASM_UNINORTH_H__
+#define __ASM_UNINORTH_H__
+
+/*
+ * Uni-N and U3 config space reg. definitions
+ *
+ * (Little endian)
+ */
+
+/* Address ranges selection. This one should work with Bandit too */
+/* Not U3 */
+#define UNI_N_ADDR_SELECT               0x48
+#define UNI_N_ADDR_COARSE_MASK          0xffff0000      /* 256Mb regions at *0000000 */
+#define UNI_N_ADDR_FINE_MASK            0x0000ffff      /*  16Mb regions at f*000000 */
+
+/* AGP registers */
+/* Not U3 */
+#define UNI_N_CFG_GART_BASE             0x8c
+#define UNI_N_CFG_AGP_BASE              0x90
+#define UNI_N_CFG_GART_CTRL             0x94
+#define UNI_N_CFG_INTERNAL_STATUS       0x98
+#define UNI_N_CFG_GART_DUMMY_PAGE       0xa4
+
+/* UNI_N_CFG_GART_CTRL bits definitions */
+#define UNI_N_CFG_GART_INVAL            0x00000001
+#define UNI_N_CFG_GART_ENABLE           0x00000100
+#define UNI_N_CFG_GART_2xRESET          0x00010000
+#define UNI_N_CFG_GART_DISSBADET        0x00020000
+/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
+#define U3_N_CFG_GART_SYNCMODE          0x00040000
+#define U3_N_CFG_GART_PERFRD            0x00080000
+#define U3_N_CFG_GART_B2BGNT            0x00200000
+#define U3_N_CFG_GART_FASTDDR           0x00400000
+
+/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
+ * revision 1.5 (x4 AGP) may need further changes.
+ *
+ * AGP_BASE register contains the base address of the AGP aperture on
+ * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
+ * even if decoding of this address range is enabled in the address select
+ * register. Apparently, the only supported bases are 256Mb multiples
+ * (high 4 bits of that register).
+ *
+ * GART_BASE register appear to contain the physical address of the GART
+ * in system memory in the high address bits (page aligned), and the
+ * GART size in the low order bits (number of GART pages)
+ *
+ * The GART format itself is one 32bits word per physical memory page.
+ * This word contains, in little-endian format (!!!), the physical address
+ * of the page in the high bits, and what appears to be an "enable" bit
+ * in the LSB bit (0) that must be set to 1 when the entry is valid.
+ *
+ * Obviously, the GART is not cache coherent and so any change to it
+ * must be flushed to memory (or maybe just make the GART space non
+ * cachable). AGP memory itself doens't seem to be cache coherent neither.
+ *
+ * In order to invalidate the GART (which is probably necessary to inval
+ * the bridge internal TLBs), the following sequence has to be written,
+ * in order, to the GART_CTRL register:
+ *
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
+ *   UNI_N_CFG_GART_ENABLE
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
+ *   UNI_N_CFG_GART_ENABLE
+ *
+ * As far as AGP "features" are concerned, it looks like fast write may
+ * not be supported but this has to be confirmed.
+ *
+ * Turning on AGP seem to require a double invalidate operation, one before
+ * setting the AGP command register, on after.
+ *
+ * Turning off AGP seems to require the following sequence: first wait
+ * for the AGP to be idle by reading the internal status register, then
+ * write in that order to the GART_CTRL register:
+ *
+ *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
+ *   0
+ *   UNI_N_CFG_GART_2xRESET
+ *   0
+ */
+
+/*
+ * Uni-N memory mapped reg. definitions
+ *
+ * Those registers are Big-Endian !!
+ *
+ * Their meaning come from either Darwin and/or from experiments I made with
+ * the bootrom, I'm not sure about their exact meaning yet
+ *
+ */
+
+/* Version of the UniNorth chip */
+#define UNI_N_VERSION                   0x0000          /* Known versions: 3,7 and 8 */
+
+#define UNI_N_VERSION_107               0x0003          /* 1.0.7 */
+#define UNI_N_VERSION_10A               0x0007          /* 1.0.10 */
+#define UNI_N_VERSION_150               0x0011          /* 1.5 */
+#define UNI_N_VERSION_200               0x0024          /* 2.0 */
+#define UNI_N_VERSION_PANGEA            0x00C0          /* Integrated U1 + K */
+#define UNI_N_VERSION_INTREPID          0x00D2          /* Integrated U2 + K */
+#define UNI_N_VERSION_300               0x0030          /* 3.0 (U3 on G5) */
+
+/* This register is used to enable/disable various clocks */
+#define UNI_N_CLOCK_CNTL                0x0020
+#define UNI_N_CLOCK_CNTL_PCI            0x00000001      /* PCI2 clock control */
+#define UNI_N_CLOCK_CNTL_GMAC           0x00000002      /* GMAC clock control */
+#define UNI_N_CLOCK_CNTL_FW             0x00000004      /* FireWire clock control */
+#define UNI_N_CLOCK_CNTL_ATA100         0x00000010      /* ATA-100 clock control (U2) */
+
+/* Power Management control */
+#define UNI_N_POWER_MGT                 0x0030
+#define UNI_N_POWER_MGT_NORMAL          0x00
+#define UNI_N_POWER_MGT_IDLE2           0x01
+#define UNI_N_POWER_MGT_SLEEP           0x02
+
+/* This register is configured by Darwin depending on the UniN
+ * revision
+ */
+#define UNI_N_ARB_CTRL                  0x0040
+#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
+#define UNI_N_ARB_CTRL_QACK_DELAY_MASK  0x0e1f8000
+#define UNI_N_ARB_CTRL_QACK_DELAY       0x30
+#define UNI_N_ARB_CTRL_QACK_DELAY105    0x00
+
+/* This one _might_ return the CPU number of the CPU reading it;
+ * the bootROM decides whether to boot or to sleep/spinloop depending
+ * on this register beeing 0 or not
+ */
+#define UNI_N_CPU_NUMBER                0x0050
+
+/* This register appear to be read by the bootROM to decide what
+ *  to do on a non-recoverable reset (powerup or wakeup)
+ */
+#define UNI_N_HWINIT_STATE              0x0070
+#define UNI_N_HWINIT_STATE_SLEEPING     0x01
+#define UNI_N_HWINIT_STATE_RUNNING      0x02
+/* This last bit appear to be used by the bootROM to know the second
+ * CPU has started and will enter it's sleep loop with IP=0
+ */
+#define UNI_N_HWINIT_STATE_CPU1_FLAG    0x10000000
+
+/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
+ * is in low speed mode.
+ */
+#define UNI_N_AACK_DELAY                0x0100
+#define UNI_N_AACK_DELAY_ENABLE         0x00000001
+
+/* Clock status for Intrepid */
+#define UNI_N_CLOCK_STOP_STATUS0        0x0150
+#define UNI_N_CLOCK_STOPPED_EXTAGP      0x00200000
+#define UNI_N_CLOCK_STOPPED_AGPDEL      0x00100000
+#define UNI_N_CLOCK_STOPPED_I2S0_45_49  0x00080000
+#define UNI_N_CLOCK_STOPPED_I2S0_18     0x00040000
+#define UNI_N_CLOCK_STOPPED_I2S1_45_49  0x00020000
+#define UNI_N_CLOCK_STOPPED_I2S1_18     0x00010000
+#define UNI_N_CLOCK_STOPPED_TIMER       0x00008000
+#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
+#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
+#define UNI_N_CLOCK_STOPPED_SCC_VIA32   0x00001000
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT0   0x00000800
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT1   0x00000400
+#define UNI_N_CLOCK_STOPPED_SCC_SLOT2   0x00000200
+#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO  0x00000100
+#define UNI_N_CLOCK_STOPPED_VEO0        0x00000080
+#define UNI_N_CLOCK_STOPPED_VEO1        0x00000040
+#define UNI_N_CLOCK_STOPPED_USB0        0x00000020
+#define UNI_N_CLOCK_STOPPED_USB1        0x00000010
+#define UNI_N_CLOCK_STOPPED_USB2        0x00000008
+#define UNI_N_CLOCK_STOPPED_32          0x00000004
+#define UNI_N_CLOCK_STOPPED_45          0x00000002
+#define UNI_N_CLOCK_STOPPED_49          0x00000001
+
+#define UNI_N_CLOCK_STOP_STATUS1        0x0160
+#define UNI_N_CLOCK_STOPPED_PLL4REF     0x00080000
+#define UNI_N_CLOCK_STOPPED_CPUDEL      0x00040000
+#define UNI_N_CLOCK_STOPPED_CPU         0x00020000
+#define UNI_N_CLOCK_STOPPED_BUF_REFCKO  0x00010000
+#define UNI_N_CLOCK_STOPPED_PCI2        0x00008000
+#define UNI_N_CLOCK_STOPPED_FW          0x00004000
+#define UNI_N_CLOCK_STOPPED_GB          0x00002000
+#define UNI_N_CLOCK_STOPPED_ATA66       0x00001000
+#define UNI_N_CLOCK_STOPPED_ATA100      0x00000800
+#define UNI_N_CLOCK_STOPPED_MAX         0x00000400
+#define UNI_N_CLOCK_STOPPED_PCI1        0x00000200
+#define UNI_N_CLOCK_STOPPED_KLPCI       0x00000100
+#define UNI_N_CLOCK_STOPPED_USB0PCI     0x00000080
+#define UNI_N_CLOCK_STOPPED_USB1PCI     0x00000040
+#define UNI_N_CLOCK_STOPPED_USB2PCI     0x00000020
+#define UNI_N_CLOCK_STOPPED_7PCI1       0x00000008
+#define UNI_N_CLOCK_STOPPED_AGP         0x00000004
+#define UNI_N_CLOCK_STOPPED_PCI0        0x00000002
+#define UNI_N_CLOCK_STOPPED_18          0x00000001
+
+/* Intrepid registe to OF do-platform-clockspreading */
+#define UNI_N_CLOCK_SPREADING           0x190
+
+/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
+
+
+/*
+ * U3 specific registers
+ */
+
+
+/* U3 Toggle */
+#define U3_TOGGLE_REG                   0x00e0
+#define U3_PMC_START_STOP               0x0001
+#define U3_MPIC_RESET                   0x0002
+#define U3_MPIC_OUTPUT_ENABLE           0x0004
+
+/* U3 API PHY Config 1 */
+#define U3_API_PHY_CONFIG_1             0x23030
+
+/* U3 HyperTransport registers */
+#define U3_HT_CONFIG_BASE               0x70000
+#define U3_HT_LINK_COMMAND              0x100
+#define U3_HT_LINK_CONFIG               0x110
+#define U3_HT_LINK_FREQ                 0x120
+
+#endif /* __ASM_UNINORTH_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
new file mode 100644
index 000000000000..cc51e5c9acc2
--- /dev/null
+++ b/include/asm-ppc/unistd.h
@@ -0,0 +1,488 @@
+#ifndef _ASM_PPC_UNISTD_H_
+#define _ASM_PPC_UNISTD_H_
+
+/*
+ * This file contains the system call numbers.
+ */
+#define __NR_restart_syscall      0
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+#define __NR_waitpid              7
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_lchown              16
+#define __NR_break               17
+#define __NR_oldstat             18
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+#define __NR_umount              22
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+#define __NR_oldfstat            28
+#define __NR_pause               29
+#define __NR_utime               30
+#define __NR_stty                31
+#define __NR_gtty                32
+#define __NR_access              33
+#define __NR_nice                34
+#define __NR_ftime               35
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+#define __NR_prof                44
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+#define __NR_signal              48
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+#define __NR_lock                53
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+#define __NR_mpx                 56
+#define __NR_setpgid             57
+#define __NR_ulimit              58
+#define __NR_oldolduname         59
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+#define __NR_sigaction           67
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+#define __NR_sigsuspend          72
+#define __NR_sigpending          73
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+#define __NR_getrlimit           76
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+#define __NR_select              82
+#define __NR_symlink             83
+#define __NR_oldlstat            84
+#define __NR_readlink            85
+#define __NR_uselib              86
+#define __NR_swapon              87
+#define __NR_reboot              88
+#define __NR_readdir             89
+#define __NR_mmap                90
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+#define __NR_profil              98
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+#define __NR_ioperm             101
+#define __NR_socketcall         102
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+#define __NR_olduname           109
+#define __NR_iopl               110
+#define __NR_vhangup            111
+#define __NR_idle               112
+#define __NR_vm86               113
+#define __NR_wait4              114
+#define __NR_swapoff            115
+#define __NR_sysinfo            116
+#define __NR_ipc                117
+#define __NR_fsync              118
+#define __NR_sigreturn          119
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+#define __NR_modify_ldt         123
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+#define __NR_sigprocmask        126
+#define __NR_create_module      127
+#define __NR_init_module        128
+#define __NR_delete_module      129
+#define __NR_get_kernel_syms    130
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+#define __NR_sysfs              135
+#define __NR_personality        136
+#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+#define __NR__newselect         142
+#define __NR_flock              143
+#define __NR_msync              144
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+#define __NR_mlock              150
+#define __NR_munlock            151
+#define __NR_mlockall           152
+#define __NR_munlockall         153
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+#define __NR_mremap             163
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+#define __NR_query_module       166
+#define __NR_poll               167
+#define __NR_nfsservctl         168
+#define __NR_setresgid          169
+#define __NR_getresgid          170
+#define __NR_prctl              171
+#define __NR_rt_sigreturn       172
+#define __NR_rt_sigaction       173
+#define __NR_rt_sigprocmask     174
+#define __NR_rt_sigpending      175
+#define __NR_rt_sigtimedwait    176
+#define __NR_rt_sigqueueinfo    177
+#define __NR_rt_sigsuspend      178
+#define __NR_pread64            179
+#define __NR_pwrite64           180
+#define __NR_chown              181
+#define __NR_getcwd             182
+#define __NR_capget             183
+#define __NR_capset             184
+#define __NR_sigaltstack        185
+#define __NR_sendfile           186
+#define __NR_getpmsg            187     /* some people actually want streams */
+#define __NR_putpmsg            188     /* some people actually want streams */
+#define __NR_vfork              189
+#define __NR_ugetrlimit         190     /* SuS compliant getrlimit */
+#define __NR_readahead          191
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_pciconfig_read     198
+#define __NR_pciconfig_write    199
+#define __NR_pciconfig_iobase   200
+#define __NR_multiplexer        201
+#define __NR_getdents64         202
+#define __NR_pivot_root         203
+#define __NR_fcntl64            204
+#define __NR_madvise            205
+#define __NR_mincore            206
+#define __NR_gettid             207
+#define __NR_tkill              208
+#define __NR_setxattr           209
+#define __NR_lsetxattr          210
+#define __NR_fsetxattr          211
+#define __NR_getxattr           212
+#define __NR_lgetxattr          213
+#define __NR_fgetxattr          214
+#define __NR_listxattr          215
+#define __NR_llistxattr         216
+#define __NR_flistxattr         217
+#define __NR_removexattr        218
+#define __NR_lremovexattr       219
+#define __NR_fremovexattr       220
+#define __NR_futex              221
+#define __NR_sched_setaffinity  222
+#define __NR_sched_getaffinity  223
+/* 224 currently unused */
+#define __NR_tuxcall            225
+#define __NR_sendfile64         226
+#define __NR_io_setup           227
+#define __NR_io_destroy         228
+#define __NR_io_getevents       229
+#define __NR_io_submit          230
+#define __NR_io_cancel          231
+#define __NR_set_tid_address    232
+#define __NR_fadvise64          233
+#define __NR_exit_group         234
+#define __NR_lookup_dcookie     235
+#define __NR_epoll_create       236
+#define __NR_epoll_ctl          237
+#define __NR_epoll_wait         238
+#define __NR_remap_file_pages   239
+#define __NR_timer_create       240
+#define __NR_timer_settime      241
+#define __NR_timer_gettime      242
+#define __NR_timer_getoverrun   243
+#define __NR_timer_delete       244
+#define __NR_clock_settime      245
+#define __NR_clock_gettime      246
+#define __NR_clock_getres       247
+#define __NR_clock_nanosleep    248
+#define __NR_swapcontext        249
+#define __NR_tgkill             250
+#define __NR_utimes             251
+#define __NR_statfs64           252
+#define __NR_fstatfs64          253
+#define __NR_fadvise64_64       254
+#define __NR_rtas               255
+#define __NR_sys_debug_setcontext 256
+/* Number 257 is reserved for vserver */
+/* Number 258 is reserved for new sys_remap_file_pages */
+/* Number 259 is reserved for new sys_mbind */
+/* Number 260 is reserved for new sys_get_mempolicy */
+/* Number 261 is reserved for new sys_set_mempolicy */
+#define __NR_mq_open            262
+#define __NR_mq_unlink          263
+#define __NR_mq_timedsend       264
+#define __NR_mq_timedreceive    265
+#define __NR_mq_notify          266
+#define __NR_mq_getsetattr      267
+#define __NR_kexec_load         268
+#define __NR_add_key            269
+#define __NR_request_key        270
+#define __NR_keyctl             271
+#define __NR_waitid             272
+
+#define __NR_syscalls           273
+
+#define __NR(n) #n
+
+/* On powerpc a system call basically clobbers the same registers like a
+ * function call, with the exception of LR (which is needed for the
+ * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
+ * an error return status).
+ */
+
+#define __syscall_nr(nr, type, name, args...)                           \
+        unsigned long __sc_ret, __sc_err;                               \
+        {                                                               \
+                register unsigned long __sc_0  __asm__ ("r0");          \
+                register unsigned long __sc_3  __asm__ ("r3");          \
+                register unsigned long __sc_4  __asm__ ("r4");          \
+                register unsigned long __sc_5  __asm__ ("r5");          \
+                register unsigned long __sc_6  __asm__ ("r6");          \
+                register unsigned long __sc_7  __asm__ ("r7");          \
+                register unsigned long __sc_8  __asm__ ("r8");          \
+                                                                        \
+                __sc_loadargs_##nr(name, args);                         \
+                __asm__ __volatile__                                    \
+                        ("sc           \n\t"                            \
+                         "mfcr %0      "                                \
+                        : "=&r" (__sc_0),                               \
+                          "=&r" (__sc_3),  "=&r" (__sc_4),              \
+                          "=&r" (__sc_5),  "=&r" (__sc_6),              \
+                          "=&r" (__sc_7),  "=&r" (__sc_8)               \
+                        : __sc_asm_input_##nr                           \
+                        : "cr0", "ctr", "memory",                       \
+                          "r9", "r10","r11", "r12");                    \
+                __sc_ret = __sc_3;                                      \
+                __sc_err = __sc_0;                                      \
+        }                                                               \
+        if (__sc_err & 0x10000000)                                      \
+        {                                                               \
+                errno = __sc_ret;                                       \
+                __sc_ret = -1;                                          \
+        }                                                               \
+        return (type) __sc_ret
+
+#define __sc_loadargs_0(name, dummy...)                                 \
+        __sc_0 = __NR_##name
+#define __sc_loadargs_1(name, arg1)                                     \
+        __sc_loadargs_0(name);                                          \
+        __sc_3 = (unsigned long) (arg1)
+#define __sc_loadargs_2(name, arg1, arg2)                               \
+        __sc_loadargs_1(name, arg1);                                    \
+        __sc_4 = (unsigned long) (arg2)
+#define __sc_loadargs_3(name, arg1, arg2, arg3)                         \
+        __sc_loadargs_2(name, arg1, arg2);                              \
+        __sc_5 = (unsigned long) (arg3)
+#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4)                   \
+        __sc_loadargs_3(name, arg1, arg2, arg3);                        \
+        __sc_6 = (unsigned long) (arg4)
+#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5)             \
+        __sc_loadargs_4(name, arg1, arg2, arg3, arg4);                  \
+        __sc_7 = (unsigned long) (arg5)
+#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6)       \
+        __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5);            \
+        __sc_8 = (unsigned long) (arg6)
+
+#define __sc_asm_input_0 "0" (__sc_0)
+#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
+#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
+#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
+#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
+#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
+#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
+
+#define _syscall0(type,name)                                            \
+type name(void)                                                         \
+{                                                                       \
+        __syscall_nr(0, type, name);                                    \
+}
+
+#define _syscall1(type,name,type1,arg1)                                 \
+type name(type1 arg1)                                                   \
+{                                                                       \
+        __syscall_nr(1, type, name, arg1);                              \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2)                      \
+type name(type1 arg1, type2 arg2)                                       \
+{                                                                       \
+        __syscall_nr(2, type, name, arg1, arg2);                        \
+}
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
+type name(type1 arg1, type2 arg2, type3 arg3)                           \
+{                                                                       \
+        __syscall_nr(3, type, name, arg1, arg2, arg3);                  \
+}
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4)               \
+{                                                                       \
+        __syscall_nr(4, type, name, arg1, arg2, arg3, arg4);            \
+}
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)   \
+{                                                                       \
+        __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5);      \
+}
+
+#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
+{                                                                       \
+        __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6); \
+}
+
+#ifdef __KERNEL__
+
+#define __NR__exit __NR_exit
+#define NR_syscalls     __NR_syscalls
+
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+
+/*
+ * Forking from kernel space will result in the child getting a new,
+ * empty kernel stack area.  Thus the child cannot access automatic
+ * variables set in the parent unless they are in registers, and the
+ * procedure where the fork was done cannot return to its caller in
+ * the child.
+ */
+
+#ifdef __KERNEL_SYSCALLS__
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/*
+ * System call prototypes.
+ */
+extern pid_t setsid(void);
+extern int write(int fd, const char *buf, off_t count);
+extern int read(int fd, char *buf, off_t count);
+extern off_t lseek(int fd, off_t offset, int count);
+extern int dup(int fd);
+extern int execve(const char *file, char **argv, char **envp);
+extern int open(const char *file, int flag, int mode);
+extern int close(int fd);
+extern pid_t waitpid(pid_t pid, int *wait_stat, int options);
+
+unsigned long sys_mmap(unsigned long addr, size_t len,
+                        unsigned long prot, unsigned long flags,
+                        unsigned long fd, off_t offset);
+unsigned long sys_mmap2(unsigned long addr, size_t len,
+                        unsigned long prot, unsigned long flags,
+                        unsigned long fd, unsigned long pgoff);
+struct pt_regs;
+int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
+                unsigned long a3, unsigned long a4, unsigned long a5,
+                struct pt_regs *regs);
+int sys_clone(unsigned long clone_flags, unsigned long usp,
+              int __user *parent_tidp, void __user *child_threadptr,
+              int __user *child_tidp, int p6,
+              struct pt_regs *regs);
+int sys_fork(int p1, int p2, int p3, int p4, int p5, int p6,
+                struct pt_regs *regs);
+int sys_vfork(int p1, int p2, int p3, int p4, int p5, int p6,
+                struct pt_regs *regs);
+int sys_pipe(int __user *fildes);
+int sys_ptrace(long request, long pid, long addr, long data);
+struct sigaction;
+long sys_rt_sigaction(int sig,
+                      const struct sigaction __user *act,
+                      struct sigaction __user *oact,
+                      size_t sigsetsize);
+
+#endif /* __KERNEL_SYSCALLS__ */
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc/user.h b/include/asm-ppc/user.h
new file mode 100644
index 000000000000..d662b2151370
--- /dev/null
+++ b/include/asm-ppc/user.h
@@ -0,0 +1,54 @@
+#ifdef __KERNEL__
+#ifndef _PPC_USER_H
+#define _PPC_USER_H
+
+/* Adapted from <asm-alpha/user.h> */
+
+#include <linux/ptrace.h>
+#include <asm/page.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
+ * are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+struct user {
+        struct pt_regs  regs;                   /* entire machine state */
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        struct regs *   u_ar0;                  /* help gdb find registers */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _PPC_USER_H */
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h
new file mode 100644
index 000000000000..c5864734e3e1
--- /dev/null
+++ b/include/asm-ppc/vga.h
@@ -0,0 +1,46 @@
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+
+#ifdef __KERNEL__
+#ifndef _LINUX_ASM_VGA_H_
+#define _LINUX_ASM_VGA_H_
+
+#include <asm/io.h>
+
+#include <linux/config.h>
+
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
+
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+extern inline void scr_writew(u16 val, volatile u16 *addr)
+{
+    st_le16(addr, val);
+}
+
+extern inline u16 scr_readw(volatile const u16 *addr)
+{
+    return ld_le16(addr);
+}
+
+#define VT_BUF_HAVE_MEMCPYW
+#define scr_memcpyw     memcpy
+
+#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
+
+extern unsigned long vgacon_remap_base;
+#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
+#define vga_readb(x) (*(x))
+#define vga_writeb(x,y) (*(y) = (x))
+
+#endif
+#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/xmon.h b/include/asm-ppc/xmon.h
new file mode 100644
index 000000000000..042b83e6680d
--- /dev/null
+++ b/include/asm-ppc/xmon.h
@@ -0,0 +1,17 @@
+#ifndef __PPC_XMON_H
+#define __PPC_XMON_H
+#ifdef __KERNEL__
+
+struct pt_regs;
+
+extern void xmon(struct pt_regs *excp);
+extern void xmon_printf(const char *fmt, ...);
+extern void xmon_map_scc(void);
+extern int xmon_bpt(struct pt_regs *regs);
+extern int xmon_sstep(struct pt_regs *regs);
+extern int xmon_iabr_match(struct pt_regs *regs);
+extern int xmon_dabr_match(struct pt_regs *regs);
+extern void (*xmon_fault_handler)(struct pt_regs *regs);
+
+#endif
+#endif
diff --git a/include/asm-ppc/xor.h b/include/asm-ppc/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/include/asm-ppc/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/include/asm-ppc/xparameters.h b/include/asm-ppc/xparameters.h
new file mode 100644
index 000000000000..fe4eac629139
--- /dev/null
+++ b/include/asm-ppc/xparameters.h
@@ -0,0 +1,18 @@
+/*
+ * include/asm-ppc/xparameters.h
+ *
+ * This file includes the correct xparameters.h for the CONFIG'ed board
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * 2004 (c) MontaVista Software, Inc.  This file is licensed under the terms
+ * of the GNU General Public License version 2.  This program is licensed
+ * "as is" without any warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_XILINX_ML300)
+#include <platforms/4xx/xparameters/xparameters_ml300.h>
+#endif
diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h
new file mode 100644
index 000000000000..1e5fbc65e77b
--- /dev/null
+++ b/include/asm-ppc/zorro.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_PPC_ZORRO_H
+#define _ASM_PPC_ZORRO_H
+
+#include <asm/io.h>
+
+#define z_readb in_8
+#define z_readw in_be16
+#define z_readl in_be32
+
+#define z_writeb(val, port) out_8((port), (val))
+#define z_writew(val, port) out_be16((port), (val))
+#define z_writel(val, port) out_be32((port), (val))
+
+#define z_memset_io(a,b,c)      memset((void *)(a),(b),(c))
+#define z_memcpy_fromio(a,b,c)  memcpy((a),(void *)(b),(c))
+#define z_memcpy_toio(a,b,c)    memcpy((void *)(a),(b),(c))
+
+extern void *__ioremap(unsigned long address, unsigned long size,
+                       unsigned long flags);
+
+extern void *ioremap(unsigned long address, unsigned long size);
+extern void iounmap(void *addr);
+
+extern void *__ioremap(unsigned long address, unsigned long size,
+                       unsigned long flags);
+
+#define z_ioremap ioremap
+#define z_iounmap iounmap
+
+#endif /* _ASM_PPC_ZORRO_H */