diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ppc |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-ppc')
177 files changed, 26140 insertions, 0 deletions
diff --git a/include/asm-ppc/8253pit.h b/include/asm-ppc/8253pit.h new file mode 100644 index 000000000000..285f78488ccb --- /dev/null +++ b/include/asm-ppc/8253pit.h | |||
@@ -0,0 +1,10 @@ | |||
1 | /* | ||
2 | * 8253/8254 Programmable Interval Timer | ||
3 | */ | ||
4 | |||
5 | #ifndef _8253PIT_H | ||
6 | #define _8253PIT_H | ||
7 | |||
8 | #define PIT_TICK_RATE 1193182UL | ||
9 | |||
10 | #endif | ||
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h new file mode 100644 index 000000000000..1311cefdfd30 --- /dev/null +++ b/include/asm-ppc/8xx_immap.h | |||
@@ -0,0 +1,564 @@ | |||
1 | /* | ||
2 | * MPC8xx Internal Memory Map | ||
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | ||
4 | * | ||
5 | * The I/O on the MPC860 is comprised of blocks of special registers | ||
6 | * and the dual port ram for the Communication Processor Module. | ||
7 | * Within this space are functional units such as the SIU, memory | ||
8 | * controller, system timers, and other control functions. It is | ||
9 | * a combination that I found difficult to separate into logical | ||
10 | * functional files.....but anyone else is welcome to try. -- Dan | ||
11 | */ | ||
12 | #ifdef __KERNEL__ | ||
13 | #ifndef __IMMAP_8XX__ | ||
14 | #define __IMMAP_8XX__ | ||
15 | |||
16 | /* System configuration registers. | ||
17 | */ | ||
18 | typedef struct sys_conf { | ||
19 | uint sc_siumcr; | ||
20 | uint sc_sypcr; | ||
21 | uint sc_swt; | ||
22 | char res1[2]; | ||
23 | ushort sc_swsr; | ||
24 | uint sc_sipend; | ||
25 | uint sc_simask; | ||
26 | uint sc_siel; | ||
27 | uint sc_sivec; | ||
28 | uint sc_tesr; | ||
29 | char res2[0xc]; | ||
30 | uint sc_sdcr; | ||
31 | char res3[0x4c]; | ||
32 | } sysconf8xx_t; | ||
33 | |||
34 | /* PCMCIA configuration registers. | ||
35 | */ | ||
36 | typedef struct pcmcia_conf { | ||
37 | uint pcmc_pbr0; | ||
38 | uint pcmc_por0; | ||
39 | uint pcmc_pbr1; | ||
40 | uint pcmc_por1; | ||
41 | uint pcmc_pbr2; | ||
42 | uint pcmc_por2; | ||
43 | uint pcmc_pbr3; | ||
44 | uint pcmc_por3; | ||
45 | uint pcmc_pbr4; | ||
46 | uint pcmc_por4; | ||
47 | uint pcmc_pbr5; | ||
48 | uint pcmc_por5; | ||
49 | uint pcmc_pbr6; | ||
50 | uint pcmc_por6; | ||
51 | uint pcmc_pbr7; | ||
52 | uint pcmc_por7; | ||
53 | char res1[0x20]; | ||
54 | uint pcmc_pgcra; | ||
55 | uint pcmc_pgcrb; | ||
56 | uint pcmc_pscr; | ||
57 | char res2[4]; | ||
58 | uint pcmc_pipr; | ||
59 | char res3[4]; | ||
60 | uint pcmc_per; | ||
61 | char res4[4]; | ||
62 | } pcmconf8xx_t; | ||
63 | |||
64 | /* Memory controller registers. | ||
65 | */ | ||
66 | typedef struct mem_ctlr { | ||
67 | uint memc_br0; | ||
68 | uint memc_or0; | ||
69 | uint memc_br1; | ||
70 | uint memc_or1; | ||
71 | uint memc_br2; | ||
72 | uint memc_or2; | ||
73 | uint memc_br3; | ||
74 | uint memc_or3; | ||
75 | uint memc_br4; | ||
76 | uint memc_or4; | ||
77 | uint memc_br5; | ||
78 | uint memc_or5; | ||
79 | uint memc_br6; | ||
80 | uint memc_or6; | ||
81 | uint memc_br7; | ||
82 | uint memc_or7; | ||
83 | char res1[0x24]; | ||
84 | uint memc_mar; | ||
85 | uint memc_mcr; | ||
86 | char res2[4]; | ||
87 | uint memc_mamr; | ||
88 | uint memc_mbmr; | ||
89 | ushort memc_mstat; | ||
90 | ushort memc_mptpr; | ||
91 | uint memc_mdr; | ||
92 | char res3[0x80]; | ||
93 | } memctl8xx_t; | ||
94 | |||
95 | /*----------------------------------------------------------------------- | ||
96 | * BR - Memory Controler: Base Register 16-9 | ||
97 | */ | ||
98 | #define BR_BA_MSK 0xffff8000 /* Base Address Mask */ | ||
99 | #define BR_AT_MSK 0x00007000 /* Address Type Mask */ | ||
100 | #define BR_PS_MSK 0x00000c00 /* Port Size Mask */ | ||
101 | #define BR_PS_32 0x00000000 /* 32 bit port size */ | ||
102 | #define BR_PS_16 0x00000800 /* 16 bit port size */ | ||
103 | #define BR_PS_8 0x00000400 /* 8 bit port size */ | ||
104 | #define BR_PARE 0x00000200 /* Parity Enable */ | ||
105 | #define BR_WP 0x00000100 /* Write Protect */ | ||
106 | #define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ | ||
107 | #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ | ||
108 | #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ | ||
109 | #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ | ||
110 | #define BR_V 0x00000001 /* Bank Valid */ | ||
111 | |||
112 | /*----------------------------------------------------------------------- | ||
113 | * OR - Memory Controler: Option Register 16-11 | ||
114 | */ | ||
115 | #define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ | ||
116 | #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ | ||
117 | #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ | ||
118 | /* Address Multiplex */ | ||
119 | #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ | ||
120 | #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ | ||
121 | #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ | ||
122 | #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ | ||
123 | #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ | ||
124 | #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ | ||
125 | #define OR_BI 0x00000100 /* Burst inhibit */ | ||
126 | #define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ | ||
127 | #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ | ||
128 | #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ | ||
129 | #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ | ||
130 | #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ | ||
131 | #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ | ||
132 | #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ | ||
133 | #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ | ||
134 | #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ | ||
135 | #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ | ||
136 | #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ | ||
137 | #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ | ||
138 | #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ | ||
139 | #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ | ||
140 | #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ | ||
141 | #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ | ||
142 | #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ | ||
143 | #define OR_SETA 0x00000008 /* External Transfer Acknowledge */ | ||
144 | #define OR_TRLX 0x00000004 /* Timing Relaxed */ | ||
145 | #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ | ||
146 | |||
147 | /* System Integration Timers. | ||
148 | */ | ||
149 | typedef struct sys_int_timers { | ||
150 | ushort sit_tbscr; | ||
151 | char res0[0x02]; | ||
152 | uint sit_tbreff0; | ||
153 | uint sit_tbreff1; | ||
154 | char res1[0x14]; | ||
155 | ushort sit_rtcsc; | ||
156 | char res2[0x02]; | ||
157 | uint sit_rtc; | ||
158 | uint sit_rtsec; | ||
159 | uint sit_rtcal; | ||
160 | char res3[0x10]; | ||
161 | ushort sit_piscr; | ||
162 | char res4[2]; | ||
163 | uint sit_pitc; | ||
164 | uint sit_pitr; | ||
165 | char res5[0x34]; | ||
166 | } sit8xx_t; | ||
167 | |||
168 | #define TBSCR_TBIRQ_MASK ((ushort)0xff00) | ||
169 | #define TBSCR_REFA ((ushort)0x0080) | ||
170 | #define TBSCR_REFB ((ushort)0x0040) | ||
171 | #define TBSCR_REFAE ((ushort)0x0008) | ||
172 | #define TBSCR_REFBE ((ushort)0x0004) | ||
173 | #define TBSCR_TBF ((ushort)0x0002) | ||
174 | #define TBSCR_TBE ((ushort)0x0001) | ||
175 | |||
176 | #define RTCSC_RTCIRQ_MASK ((ushort)0xff00) | ||
177 | #define RTCSC_SEC ((ushort)0x0080) | ||
178 | #define RTCSC_ALR ((ushort)0x0040) | ||
179 | #define RTCSC_38K ((ushort)0x0010) | ||
180 | #define RTCSC_SIE ((ushort)0x0008) | ||
181 | #define RTCSC_ALE ((ushort)0x0004) | ||
182 | #define RTCSC_RTF ((ushort)0x0002) | ||
183 | #define RTCSC_RTE ((ushort)0x0001) | ||
184 | |||
185 | #define PISCR_PIRQ_MASK ((ushort)0xff00) | ||
186 | #define PISCR_PS ((ushort)0x0080) | ||
187 | #define PISCR_PIE ((ushort)0x0004) | ||
188 | #define PISCR_PTF ((ushort)0x0002) | ||
189 | #define PISCR_PTE ((ushort)0x0001) | ||
190 | |||
191 | /* Clocks and Reset. | ||
192 | */ | ||
193 | typedef struct clk_and_reset { | ||
194 | uint car_sccr; | ||
195 | uint car_plprcr; | ||
196 | uint car_rsr; | ||
197 | char res[0x74]; /* Reserved area */ | ||
198 | } car8xx_t; | ||
199 | |||
200 | /* System Integration Timers keys. | ||
201 | */ | ||
202 | typedef struct sitk { | ||
203 | uint sitk_tbscrk; | ||
204 | uint sitk_tbreff0k; | ||
205 | uint sitk_tbreff1k; | ||
206 | uint sitk_tbk; | ||
207 | char res1[0x10]; | ||
208 | uint sitk_rtcsck; | ||
209 | uint sitk_rtck; | ||
210 | uint sitk_rtseck; | ||
211 | uint sitk_rtcalk; | ||
212 | char res2[0x10]; | ||
213 | uint sitk_piscrk; | ||
214 | uint sitk_pitck; | ||
215 | char res3[0x38]; | ||
216 | } sitk8xx_t; | ||
217 | |||
218 | /* Clocks and reset keys. | ||
219 | */ | ||
220 | typedef struct cark { | ||
221 | uint cark_sccrk; | ||
222 | uint cark_plprcrk; | ||
223 | uint cark_rsrk; | ||
224 | char res[0x474]; | ||
225 | } cark8xx_t; | ||
226 | |||
227 | /* The key to unlock registers maintained by keep-alive power. | ||
228 | */ | ||
229 | #define KAPWR_KEY ((unsigned int)0x55ccaa33) | ||
230 | |||
231 | /* Video interface. MPC823 Only. | ||
232 | */ | ||
233 | typedef struct vid823 { | ||
234 | ushort vid_vccr; | ||
235 | ushort res1; | ||
236 | u_char vid_vsr; | ||
237 | u_char res2; | ||
238 | u_char vid_vcmr; | ||
239 | u_char res3; | ||
240 | uint vid_vbcb; | ||
241 | uint res4; | ||
242 | uint vid_vfcr0; | ||
243 | uint vid_vfaa0; | ||
244 | uint vid_vfba0; | ||
245 | uint vid_vfcr1; | ||
246 | uint vid_vfaa1; | ||
247 | uint vid_vfba1; | ||
248 | u_char res5[0x18]; | ||
249 | } vid823_t; | ||
250 | |||
251 | /* LCD interface. 823 Only. | ||
252 | */ | ||
253 | typedef struct lcd { | ||
254 | uint lcd_lccr; | ||
255 | uint lcd_lchcr; | ||
256 | uint lcd_lcvcr; | ||
257 | char res1[4]; | ||
258 | uint lcd_lcfaa; | ||
259 | uint lcd_lcfba; | ||
260 | char lcd_lcsr; | ||
261 | char res2[0x7]; | ||
262 | } lcd823_t; | ||
263 | |||
264 | /* I2C | ||
265 | */ | ||
266 | typedef struct i2c { | ||
267 | u_char i2c_i2mod; | ||
268 | char res1[3]; | ||
269 | u_char i2c_i2add; | ||
270 | char res2[3]; | ||
271 | u_char i2c_i2brg; | ||
272 | char res3[3]; | ||
273 | u_char i2c_i2com; | ||
274 | char res4[3]; | ||
275 | u_char i2c_i2cer; | ||
276 | char res5[3]; | ||
277 | u_char i2c_i2cmr; | ||
278 | char res6[0x8b]; | ||
279 | } i2c8xx_t; | ||
280 | |||
281 | /* DMA control/status registers. | ||
282 | */ | ||
283 | typedef struct sdma_csr { | ||
284 | char res1[4]; | ||
285 | uint sdma_sdar; | ||
286 | u_char sdma_sdsr; | ||
287 | char res3[3]; | ||
288 | u_char sdma_sdmr; | ||
289 | char res4[3]; | ||
290 | u_char sdma_idsr1; | ||
291 | char res5[3]; | ||
292 | u_char sdma_idmr1; | ||
293 | char res6[3]; | ||
294 | u_char sdma_idsr2; | ||
295 | char res7[3]; | ||
296 | u_char sdma_idmr2; | ||
297 | char res8[0x13]; | ||
298 | } sdma8xx_t; | ||
299 | |||
300 | /* Communication Processor Module Interrupt Controller. | ||
301 | */ | ||
302 | typedef struct cpm_ic { | ||
303 | ushort cpic_civr; | ||
304 | char res[0xe]; | ||
305 | uint cpic_cicr; | ||
306 | uint cpic_cipr; | ||
307 | uint cpic_cimr; | ||
308 | uint cpic_cisr; | ||
309 | } cpic8xx_t; | ||
310 | |||
311 | /* Input/Output Port control/status registers. | ||
312 | */ | ||
313 | typedef struct io_port { | ||
314 | ushort iop_padir; | ||
315 | ushort iop_papar; | ||
316 | ushort iop_paodr; | ||
317 | ushort iop_padat; | ||
318 | char res1[8]; | ||
319 | ushort iop_pcdir; | ||
320 | ushort iop_pcpar; | ||
321 | ushort iop_pcso; | ||
322 | ushort iop_pcdat; | ||
323 | ushort iop_pcint; | ||
324 | char res2[6]; | ||
325 | ushort iop_pddir; | ||
326 | ushort iop_pdpar; | ||
327 | char res3[2]; | ||
328 | ushort iop_pddat; | ||
329 | uint utmode; | ||
330 | char res4[4]; | ||
331 | } iop8xx_t; | ||
332 | |||
333 | /* Communication Processor Module Timers | ||
334 | */ | ||
335 | typedef struct cpm_timers { | ||
336 | ushort cpmt_tgcr; | ||
337 | char res1[0xe]; | ||
338 | ushort cpmt_tmr1; | ||
339 | ushort cpmt_tmr2; | ||
340 | ushort cpmt_trr1; | ||
341 | ushort cpmt_trr2; | ||
342 | ushort cpmt_tcr1; | ||
343 | ushort cpmt_tcr2; | ||
344 | ushort cpmt_tcn1; | ||
345 | ushort cpmt_tcn2; | ||
346 | ushort cpmt_tmr3; | ||
347 | ushort cpmt_tmr4; | ||
348 | ushort cpmt_trr3; | ||
349 | ushort cpmt_trr4; | ||
350 | ushort cpmt_tcr3; | ||
351 | ushort cpmt_tcr4; | ||
352 | ushort cpmt_tcn3; | ||
353 | ushort cpmt_tcn4; | ||
354 | ushort cpmt_ter1; | ||
355 | ushort cpmt_ter2; | ||
356 | ushort cpmt_ter3; | ||
357 | ushort cpmt_ter4; | ||
358 | char res2[8]; | ||
359 | } cpmtimer8xx_t; | ||
360 | |||
361 | /* Finally, the Communication Processor stuff..... | ||
362 | */ | ||
363 | typedef struct scc { /* Serial communication channels */ | ||
364 | uint scc_gsmrl; | ||
365 | uint scc_gsmrh; | ||
366 | ushort scc_psmr; | ||
367 | char res1[2]; | ||
368 | ushort scc_todr; | ||
369 | ushort scc_dsr; | ||
370 | ushort scc_scce; | ||
371 | char res2[2]; | ||
372 | ushort scc_sccm; | ||
373 | char res3; | ||
374 | u_char scc_sccs; | ||
375 | char res4[8]; | ||
376 | } scc_t; | ||
377 | |||
378 | typedef struct smc { /* Serial management channels */ | ||
379 | char res1[2]; | ||
380 | ushort smc_smcmr; | ||
381 | char res2[2]; | ||
382 | u_char smc_smce; | ||
383 | char res3[3]; | ||
384 | u_char smc_smcm; | ||
385 | char res4[5]; | ||
386 | } smc_t; | ||
387 | |||
388 | /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but | ||
389 | * it fits within the address space. | ||
390 | */ | ||
391 | |||
392 | typedef struct fec { | ||
393 | uint fec_addr_low; /* lower 32 bits of station address */ | ||
394 | ushort fec_addr_high; /* upper 16 bits of station address */ | ||
395 | ushort res1; /* reserved */ | ||
396 | uint fec_hash_table_high; /* upper 32-bits of hash table */ | ||
397 | uint fec_hash_table_low; /* lower 32-bits of hash table */ | ||
398 | uint fec_r_des_start; /* beginning of Rx descriptor ring */ | ||
399 | uint fec_x_des_start; /* beginning of Tx descriptor ring */ | ||
400 | uint fec_r_buff_size; /* Rx buffer size */ | ||
401 | uint res2[9]; /* reserved */ | ||
402 | uint fec_ecntrl; /* ethernet control register */ | ||
403 | uint fec_ievent; /* interrupt event register */ | ||
404 | uint fec_imask; /* interrupt mask register */ | ||
405 | uint fec_ivec; /* interrupt level and vector status */ | ||
406 | uint fec_r_des_active; /* Rx ring updated flag */ | ||
407 | uint fec_x_des_active; /* Tx ring updated flag */ | ||
408 | uint res3[10]; /* reserved */ | ||
409 | uint fec_mii_data; /* MII data register */ | ||
410 | uint fec_mii_speed; /* MII speed control register */ | ||
411 | uint res4[17]; /* reserved */ | ||
412 | uint fec_r_bound; /* end of RAM (read-only) */ | ||
413 | uint fec_r_fstart; /* Rx FIFO start address */ | ||
414 | uint res5[6]; /* reserved */ | ||
415 | uint fec_x_fstart; /* Tx FIFO start address */ | ||
416 | uint res6[17]; /* reserved */ | ||
417 | uint fec_fun_code; /* fec SDMA function code */ | ||
418 | uint res7[3]; /* reserved */ | ||
419 | uint fec_r_cntrl; /* Rx control register */ | ||
420 | uint fec_r_hash; /* Rx hash register */ | ||
421 | uint res8[14]; /* reserved */ | ||
422 | uint fec_x_cntrl; /* Tx control register */ | ||
423 | uint res9[0x1e]; /* reserved */ | ||
424 | } fec_t; | ||
425 | |||
426 | /* The FEC and LCD color map share the same address space.... | ||
427 | * I guess we will never see an 823T :-). | ||
428 | */ | ||
429 | union fec_lcd { | ||
430 | fec_t fl_un_fec; | ||
431 | u_char fl_un_cmap[0x200]; | ||
432 | }; | ||
433 | |||
434 | typedef struct comm_proc { | ||
435 | /* General control and status registers. | ||
436 | */ | ||
437 | ushort cp_cpcr; | ||
438 | u_char res1[2]; | ||
439 | ushort cp_rccr; | ||
440 | u_char res2; | ||
441 | u_char cp_rmds; | ||
442 | u_char res3[4]; | ||
443 | ushort cp_cpmcr1; | ||
444 | ushort cp_cpmcr2; | ||
445 | ushort cp_cpmcr3; | ||
446 | ushort cp_cpmcr4; | ||
447 | u_char res4[2]; | ||
448 | ushort cp_rter; | ||
449 | u_char res5[2]; | ||
450 | ushort cp_rtmr; | ||
451 | u_char res6[0x14]; | ||
452 | |||
453 | /* Baud rate generators. | ||
454 | */ | ||
455 | uint cp_brgc1; | ||
456 | uint cp_brgc2; | ||
457 | uint cp_brgc3; | ||
458 | uint cp_brgc4; | ||
459 | |||
460 | /* Serial Communication Channels. | ||
461 | */ | ||
462 | scc_t cp_scc[4]; | ||
463 | |||
464 | /* Serial Management Channels. | ||
465 | */ | ||
466 | smc_t cp_smc[2]; | ||
467 | |||
468 | /* Serial Peripheral Interface. | ||
469 | */ | ||
470 | ushort cp_spmode; | ||
471 | u_char res7[4]; | ||
472 | u_char cp_spie; | ||
473 | u_char res8[3]; | ||
474 | u_char cp_spim; | ||
475 | u_char res9[2]; | ||
476 | u_char cp_spcom; | ||
477 | u_char res10[2]; | ||
478 | |||
479 | /* Parallel Interface Port. | ||
480 | */ | ||
481 | u_char res11[2]; | ||
482 | ushort cp_pipc; | ||
483 | u_char res12[2]; | ||
484 | ushort cp_ptpr; | ||
485 | uint cp_pbdir; | ||
486 | uint cp_pbpar; | ||
487 | u_char res13[2]; | ||
488 | ushort cp_pbodr; | ||
489 | uint cp_pbdat; | ||
490 | |||
491 | /* Port E - MPC87x/88x only. | ||
492 | */ | ||
493 | uint cp_pedir; | ||
494 | uint cp_pepar; | ||
495 | uint cp_peso; | ||
496 | uint cp_peodr; | ||
497 | uint cp_pedat; | ||
498 | |||
499 | /* Communications Processor Timing Register - | ||
500 | Contains RMII Timing for the FECs on MPC87x/88x only. | ||
501 | */ | ||
502 | uint cp_cptr; | ||
503 | |||
504 | /* Serial Interface and Time Slot Assignment. | ||
505 | */ | ||
506 | uint cp_simode; | ||
507 | u_char cp_sigmr; | ||
508 | u_char res15; | ||
509 | u_char cp_sistr; | ||
510 | u_char cp_sicmr; | ||
511 | u_char res16[4]; | ||
512 | uint cp_sicr; | ||
513 | uint cp_sirp; | ||
514 | u_char res17[0xc]; | ||
515 | |||
516 | /* 256 bytes of MPC823 video controller RAM array. | ||
517 | */ | ||
518 | u_char cp_vcram[0x100]; | ||
519 | u_char cp_siram[0x200]; | ||
520 | |||
521 | /* The fast ethernet controller is not really part of the CPM, | ||
522 | * but it resides in the address space. | ||
523 | * The LCD color map is also here. | ||
524 | */ | ||
525 | union fec_lcd fl_un; | ||
526 | #define cp_fec fl_un.fl_un_fec | ||
527 | #define lcd_cmap fl_un.fl_un_cmap | ||
528 | char res18[0xE00]; | ||
529 | |||
530 | /* The DUET family has a second FEC here */ | ||
531 | fec_t cp_fec2; | ||
532 | #define cp_fec1 cp_fec /* consistency macro */ | ||
533 | |||
534 | /* Dual Ported RAM follows. | ||
535 | * There are many different formats for this memory area | ||
536 | * depending upon the devices used and options chosen. | ||
537 | * Some processors don't have all of it populated. | ||
538 | */ | ||
539 | u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ | ||
540 | u_char cp_dparam[0x400]; /* Parameter RAM */ | ||
541 | } cpm8xx_t; | ||
542 | |||
543 | /* Internal memory map. | ||
544 | */ | ||
545 | typedef struct immap { | ||
546 | sysconf8xx_t im_siu_conf; /* SIU Configuration */ | ||
547 | pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ | ||
548 | memctl8xx_t im_memctl; /* Memory Controller */ | ||
549 | sit8xx_t im_sit; /* System integration timers */ | ||
550 | car8xx_t im_clkrst; /* Clocks and reset */ | ||
551 | sitk8xx_t im_sitk; /* Sys int timer keys */ | ||
552 | cark8xx_t im_clkrstk; /* Clocks and reset keys */ | ||
553 | vid823_t im_vid; /* Video (823 only) */ | ||
554 | lcd823_t im_lcd; /* LCD (823 only) */ | ||
555 | i2c8xx_t im_i2c; /* I2C control/status */ | ||
556 | sdma8xx_t im_sdma; /* SDMA control/status */ | ||
557 | cpic8xx_t im_cpic; /* CPM Interrupt Controller */ | ||
558 | iop8xx_t im_ioport; /* IO Port control/status */ | ||
559 | cpmtimer8xx_t im_cpmtimer; /* CPM timers */ | ||
560 | cpm8xx_t im_cpm; /* Communication processor */ | ||
561 | } immap_t; | ||
562 | |||
563 | #endif /* __IMMAP_8XX__ */ | ||
564 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/a.out.h b/include/asm-ppc/a.out.h new file mode 100644 index 000000000000..8979a94c4a81 --- /dev/null +++ b/include/asm-ppc/a.out.h | |||
@@ -0,0 +1,26 @@ | |||
1 | #ifndef __PPC_A_OUT_H__ | ||
2 | #define __PPC_A_OUT_H__ | ||
3 | |||
4 | /* grabbed from the intel stuff */ | ||
5 | #define STACK_TOP TASK_SIZE | ||
6 | |||
7 | |||
8 | struct exec | ||
9 | { | ||
10 | unsigned long a_info; /* Use macros N_MAGIC, etc for access */ | ||
11 | unsigned a_text; /* length of text, in bytes */ | ||
12 | unsigned a_data; /* length of data, in bytes */ | ||
13 | unsigned a_bss; /* length of uninitialized data area for file, in bytes */ | ||
14 | unsigned a_syms; /* length of symbol table data in file, in bytes */ | ||
15 | unsigned a_entry; /* start address */ | ||
16 | unsigned a_trsize; /* length of relocation info for text, in bytes */ | ||
17 | unsigned a_drsize; /* length of relocation info for data, in bytes */ | ||
18 | }; | ||
19 | |||
20 | |||
21 | #define N_TRSIZE(a) ((a).a_trsize) | ||
22 | #define N_DRSIZE(a) ((a).a_drsize) | ||
23 | #define N_SYMSIZE(a) ((a).a_syms) | ||
24 | |||
25 | |||
26 | #endif | ||
diff --git a/include/asm-ppc/agp.h b/include/asm-ppc/agp.h new file mode 100644 index 000000000000..be27cfa8c5b0 --- /dev/null +++ b/include/asm-ppc/agp.h | |||
@@ -0,0 +1,13 @@ | |||
1 | #ifndef AGP_H | ||
2 | #define AGP_H 1 | ||
3 | |||
4 | #include <asm/io.h> | ||
5 | |||
6 | /* nothing much needed here */ | ||
7 | |||
8 | #define map_page_into_agp(page) | ||
9 | #define unmap_page_from_agp(page) | ||
10 | #define flush_agp_mappings() | ||
11 | #define flush_agp_cache() mb() | ||
12 | |||
13 | #endif | ||
diff --git a/include/asm-ppc/amigahw.h b/include/asm-ppc/amigahw.h new file mode 100644 index 000000000000..8c98945e7dc1 --- /dev/null +++ b/include/asm-ppc/amigahw.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef __ASMPPC_AMIGAHW_H | ||
3 | #define __ASMPPC_AMIGAHW_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <asm-m68k/amigahw.h> | ||
7 | |||
8 | #undef CHIP_PHYSADDR | ||
9 | #ifdef CONFIG_APUS_FAST_EXCEPT | ||
10 | #define CHIP_PHYSADDR (0x000000) | ||
11 | #else | ||
12 | #define CHIP_PHYSADDR (0x004000) | ||
13 | #endif | ||
14 | |||
15 | |||
16 | #endif /* __ASMPPC_AMIGAHW_H */ | ||
17 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/amigaints.h b/include/asm-ppc/amigaints.h new file mode 100644 index 000000000000..aa3ff6349e81 --- /dev/null +++ b/include/asm-ppc/amigaints.h | |||
@@ -0,0 +1,133 @@ | |||
1 | /* | ||
2 | ** amigaints.h -- Amiga Linux interrupt handling structs and prototypes | ||
3 | ** | ||
4 | ** Copyright 1992 by Greg Harp | ||
5 | ** | ||
6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
7 | ** License. See the file COPYING in the main directory of this archive | ||
8 | ** for more details. | ||
9 | ** | ||
10 | ** Created 10/2/92 by Greg Harp | ||
11 | */ | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | #ifndef _ASMm68k_AMIGAINTS_H_ | ||
15 | #define _ASMm68k_AMIGAINTS_H_ | ||
16 | |||
17 | /* | ||
18 | ** Amiga Interrupt sources. | ||
19 | ** | ||
20 | */ | ||
21 | |||
22 | #define AUTO_IRQS (8) | ||
23 | #define AMI_STD_IRQS (14) | ||
24 | #define CIA_IRQS (5) | ||
25 | #define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */ | ||
26 | |||
27 | /* vertical blanking interrupt */ | ||
28 | #define IRQ_AMIGA_VERTB 0 | ||
29 | |||
30 | /* copper interrupt */ | ||
31 | #define IRQ_AMIGA_COPPER 1 | ||
32 | |||
33 | /* Audio interrupts */ | ||
34 | #define IRQ_AMIGA_AUD0 2 | ||
35 | #define IRQ_AMIGA_AUD1 3 | ||
36 | #define IRQ_AMIGA_AUD2 4 | ||
37 | #define IRQ_AMIGA_AUD3 5 | ||
38 | |||
39 | /* Blitter done interrupt */ | ||
40 | #define IRQ_AMIGA_BLIT 6 | ||
41 | |||
42 | /* floppy disk interrupts */ | ||
43 | #define IRQ_AMIGA_DSKSYN 7 | ||
44 | #define IRQ_AMIGA_DSKBLK 8 | ||
45 | |||
46 | /* builtin serial port interrupts */ | ||
47 | #define IRQ_AMIGA_RBF 9 | ||
48 | #define IRQ_AMIGA_TBE 10 | ||
49 | |||
50 | /* software interrupts */ | ||
51 | #define IRQ_AMIGA_SOFT 11 | ||
52 | |||
53 | /* interrupts from external hardware */ | ||
54 | #define IRQ_AMIGA_PORTS 12 | ||
55 | #define IRQ_AMIGA_EXTER 13 | ||
56 | |||
57 | /* CIA interrupt sources */ | ||
58 | #define IRQ_AMIGA_CIAA 14 | ||
59 | #define IRQ_AMIGA_CIAA_TA 14 | ||
60 | #define IRQ_AMIGA_CIAA_TB 15 | ||
61 | #define IRQ_AMIGA_CIAA_ALRM 16 | ||
62 | #define IRQ_AMIGA_CIAA_SP 17 | ||
63 | #define IRQ_AMIGA_CIAA_FLG 18 | ||
64 | #define IRQ_AMIGA_CIAB 19 | ||
65 | #define IRQ_AMIGA_CIAB_TA 19 | ||
66 | #define IRQ_AMIGA_CIAB_TB 20 | ||
67 | #define IRQ_AMIGA_CIAB_ALRM 21 | ||
68 | #define IRQ_AMIGA_CIAB_SP 22 | ||
69 | #define IRQ_AMIGA_CIAB_FLG 23 | ||
70 | |||
71 | /* auto-vector interrupts */ | ||
72 | #define IRQ_AMIGA_AUTO 24 | ||
73 | #define IRQ_AMIGA_AUTO_0 24 /* This is just a dummy */ | ||
74 | #define IRQ_AMIGA_AUTO_1 25 | ||
75 | #define IRQ_AMIGA_AUTO_2 26 | ||
76 | #define IRQ_AMIGA_AUTO_3 27 | ||
77 | #define IRQ_AMIGA_AUTO_4 28 | ||
78 | #define IRQ_AMIGA_AUTO_5 29 | ||
79 | #define IRQ_AMIGA_AUTO_6 30 | ||
80 | #define IRQ_AMIGA_AUTO_7 31 | ||
81 | |||
82 | #define IRQ_FLOPPY IRQ_AMIGA_DSKBLK | ||
83 | |||
84 | /* INTREQR masks */ | ||
85 | #define IRQ1_MASK 0x0007 /* INTREQR mask for IRQ 1 */ | ||
86 | #define IRQ2_MASK 0x0008 /* INTREQR mask for IRQ 2 */ | ||
87 | #define IRQ3_MASK 0x0070 /* INTREQR mask for IRQ 3 */ | ||
88 | #define IRQ4_MASK 0x0780 /* INTREQR mask for IRQ 4 */ | ||
89 | #define IRQ5_MASK 0x1800 /* INTREQR mask for IRQ 5 */ | ||
90 | #define IRQ6_MASK 0x2000 /* INTREQR mask for IRQ 6 */ | ||
91 | #define IRQ7_MASK 0x4000 /* INTREQR mask for IRQ 7 */ | ||
92 | |||
93 | #define IF_SETCLR 0x8000 /* set/clr bit */ | ||
94 | #define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */ | ||
95 | #define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */ | ||
96 | #define IF_DSKSYN 0x1000 /* disk sync interrupt */ | ||
97 | #define IF_RBF 0x0800 /* serial receive buffer full interrupt */ | ||
98 | #define IF_AUD3 0x0400 /* audio channel 3 done interrupt */ | ||
99 | #define IF_AUD2 0x0200 /* audio channel 2 done interrupt */ | ||
100 | #define IF_AUD1 0x0100 /* audio channel 1 done interrupt */ | ||
101 | #define IF_AUD0 0x0080 /* audio channel 0 done interrupt */ | ||
102 | #define IF_BLIT 0x0040 /* blitter done interrupt */ | ||
103 | #define IF_VERTB 0x0020 /* vertical blanking interrupt */ | ||
104 | #define IF_COPER 0x0010 /* copper interrupt */ | ||
105 | #define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */ | ||
106 | #define IF_SOFT 0x0004 /* software initiated interrupt */ | ||
107 | #define IF_DSKBLK 0x0002 /* diskblock DMA finished */ | ||
108 | #define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */ | ||
109 | |||
110 | extern void amiga_do_irq(int irq, struct pt_regs *fp); | ||
111 | extern void amiga_do_irq_list(int irq, struct pt_regs *fp); | ||
112 | |||
113 | /* CIA interrupt control register bits */ | ||
114 | |||
115 | #define CIA_ICR_TA 0x01 | ||
116 | #define CIA_ICR_TB 0x02 | ||
117 | #define CIA_ICR_ALRM 0x04 | ||
118 | #define CIA_ICR_SP 0x08 | ||
119 | #define CIA_ICR_FLG 0x10 | ||
120 | #define CIA_ICR_ALL 0x1f | ||
121 | #define CIA_ICR_SETCLR 0x80 | ||
122 | |||
123 | /* to access the interrupt control registers of CIA's use only | ||
124 | ** these functions, they behave exactly like the amiga os routines | ||
125 | */ | ||
126 | |||
127 | extern struct ciabase ciaa_base, ciab_base; | ||
128 | |||
129 | extern unsigned char cia_set_irq(unsigned int irq, int set); | ||
130 | extern unsigned char cia_able_irq(unsigned int irq, int enable); | ||
131 | |||
132 | #endif /* asm-m68k/amigaints.h */ | ||
133 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h new file mode 100644 index 000000000000..35114ce5135f --- /dev/null +++ b/include/asm-ppc/amigappc.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | ** asm-ppc/amigappc.h -- This header defines some values and pointers for | ||
3 | ** the Phase 5 PowerUp card. | ||
4 | ** | ||
5 | ** Copyright 1997, 1998 by Phase5, Germany. | ||
6 | ** | ||
7 | ** This file is subject to the terms and conditions of the GNU General Public | ||
8 | ** License. See the file COPYING in the main directory of this archive | ||
9 | ** for more details. | ||
10 | ** | ||
11 | ** Created: 7/22/97 by Jesper Skov | ||
12 | */ | ||
13 | |||
14 | #ifdef __KERNEL__ | ||
15 | #ifndef _M68K_AMIGAPPC_H | ||
16 | #define _M68K_AMIGAPPC_H | ||
17 | |||
18 | #ifndef __ASSEMBLY__ | ||
19 | |||
20 | /* #include <asm/system.h> */ | ||
21 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | ||
22 | |||
23 | #define APUS_WRITE(_a_, _v_) \ | ||
24 | do { \ | ||
25 | (*((volatile unsigned char *)(_a_)) = (_v_)); \ | ||
26 | mb(); \ | ||
27 | } while (0) | ||
28 | |||
29 | #define APUS_READ(_a_, _v_) \ | ||
30 | do { \ | ||
31 | (_v_) = (*((volatile unsigned char *)(_a_))); \ | ||
32 | mb(); \ | ||
33 | } while (0) | ||
34 | #endif /* ndef __ASSEMBLY__ */ | ||
35 | |||
36 | /* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */ | ||
37 | #define zTwoBase (0x80000000) | ||
38 | |||
39 | #define APUS_IPL_BASE (zTwoBase + 0x00f60000) | ||
40 | #define APUS_REG_RESET (APUS_IPL_BASE + 0x00) | ||
41 | #define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10) | ||
42 | #define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18) | ||
43 | #define APUS_REG_LOCK (APUS_IPL_BASE + 0x20) | ||
44 | #define APUS_REG_INT (APUS_IPL_BASE + 0x28) | ||
45 | #define APUS_IPL_EMU (APUS_IPL_BASE + 0x30) | ||
46 | #define APUS_INT_LVL (APUS_IPL_BASE + 0x38) | ||
47 | |||
48 | #define REGSHADOW_SETRESET (0x80) | ||
49 | #define REGSHADOW_SELFRESET (0x40) | ||
50 | |||
51 | #define REGLOCK_SETRESET (0x80) | ||
52 | #define REGLOCK_BLACKMAGICK1 (0x40) | ||
53 | #define REGLOCK_BLACKMAGICK2 (0x20) | ||
54 | #define REGLOCK_BLACKMAGICK3 (0x10) | ||
55 | |||
56 | #define REGWAITSTATE_SETRESET (0x80) | ||
57 | #define REGWAITSTATE_PPCW (0x08) | ||
58 | #define REGWAITSTATE_PPCR (0x04) | ||
59 | |||
60 | #define REGRESET_SETRESET (0x80) | ||
61 | #define REGRESET_PPCRESET (0x10) | ||
62 | #define REGRESET_M68KRESET (0x08) | ||
63 | #define REGRESET_AMIGARESET (0x04) | ||
64 | #define REGRESET_AUXRESET (0x02) | ||
65 | #define REGRESET_SCSIRESET (0x01) | ||
66 | |||
67 | #define REGINT_SETRESET (0x80) | ||
68 | #define REGINT_ENABLEIPL (0x02) | ||
69 | #define REGINT_INTMASTER (0x01) | ||
70 | |||
71 | #define IPLEMU_SETRESET (0x80) | ||
72 | #define IPLEMU_DISABLEINT (0x40) | ||
73 | #define IPLEMU_IPL2 (0x20) | ||
74 | #define IPLEMU_IPL1 (0x10) | ||
75 | #define IPLEMU_IPL0 (0x08) | ||
76 | #define IPLEMU_PPCIPL2 (0x04) | ||
77 | #define IPLEMU_PPCIPL1 (0x02) | ||
78 | #define IPLEMU_PPCIPL0 (0x01) | ||
79 | #define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0) | ||
80 | |||
81 | #define INTLVL_SETRESET (0x80) | ||
82 | #define INTLVL_MASK (0x7f) | ||
83 | |||
84 | #endif /* _M68k_AMIGAPPC_H */ | ||
85 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h new file mode 100644 index 000000000000..1fe0b87859b0 --- /dev/null +++ b/include/asm-ppc/amigayle.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-m68k/amigayle.h> | |||
diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h new file mode 100644 index 000000000000..3f65f63f508f --- /dev/null +++ b/include/asm-ppc/amipcmcia.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-m68k/amipcmcia.h> | |||
diff --git a/include/asm-ppc/ans-lcd.h b/include/asm-ppc/ans-lcd.h new file mode 100644 index 000000000000..d795b9fd2db6 --- /dev/null +++ b/include/asm-ppc/ans-lcd.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef _PPC_ANS_LCD_H | ||
2 | #define _PPC_ANS_LCD_H | ||
3 | |||
4 | #define ANSLCD_MINOR 156 | ||
5 | |||
6 | #define ANSLCD_CLEAR 0x01 | ||
7 | #define ANSLCD_SENDCTRL 0x02 | ||
8 | #define ANSLCD_SETSHORTDELAY 0x03 | ||
9 | #define ANSLCD_SETLONGDELAY 0x04 | ||
10 | |||
11 | #endif | ||
diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h new file mode 100644 index 000000000000..eeafd505836e --- /dev/null +++ b/include/asm-ppc/atomic.h | |||
@@ -0,0 +1,214 @@ | |||
1 | /* | ||
2 | * PowerPC atomic operations | ||
3 | */ | ||
4 | |||
5 | #ifndef _ASM_PPC_ATOMIC_H_ | ||
6 | #define _ASM_PPC_ATOMIC_H_ | ||
7 | |||
8 | typedef struct { volatile int counter; } atomic_t; | ||
9 | |||
10 | #ifdef __KERNEL__ | ||
11 | |||
12 | #define ATOMIC_INIT(i) { (i) } | ||
13 | |||
14 | #define atomic_read(v) ((v)->counter) | ||
15 | #define atomic_set(v,i) (((v)->counter) = (i)) | ||
16 | |||
17 | extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); | ||
18 | |||
19 | #ifdef CONFIG_SMP | ||
20 | #define SMP_SYNC "sync" | ||
21 | #define SMP_ISYNC "\n\tisync" | ||
22 | #else | ||
23 | #define SMP_SYNC "" | ||
24 | #define SMP_ISYNC | ||
25 | #endif | ||
26 | |||
27 | /* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx. | ||
28 | * The old ATOMIC_SYNC_FIX covered some but not all of this. | ||
29 | */ | ||
30 | #ifdef CONFIG_IBM405_ERR77 | ||
31 | #define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";" | ||
32 | #else | ||
33 | #define PPC405_ERR77(ra,rb) | ||
34 | #endif | ||
35 | |||
36 | static __inline__ void atomic_add(int a, atomic_t *v) | ||
37 | { | ||
38 | int t; | ||
39 | |||
40 | __asm__ __volatile__( | ||
41 | "1: lwarx %0,0,%3 # atomic_add\n\ | ||
42 | add %0,%2,%0\n" | ||
43 | PPC405_ERR77(0,%3) | ||
44 | " stwcx. %0,0,%3 \n\ | ||
45 | bne- 1b" | ||
46 | : "=&r" (t), "=m" (v->counter) | ||
47 | : "r" (a), "r" (&v->counter), "m" (v->counter) | ||
48 | : "cc"); | ||
49 | } | ||
50 | |||
51 | static __inline__ int atomic_add_return(int a, atomic_t *v) | ||
52 | { | ||
53 | int t; | ||
54 | |||
55 | __asm__ __volatile__( | ||
56 | "1: lwarx %0,0,%2 # atomic_add_return\n\ | ||
57 | add %0,%1,%0\n" | ||
58 | PPC405_ERR77(0,%2) | ||
59 | " stwcx. %0,0,%2 \n\ | ||
60 | bne- 1b" | ||
61 | SMP_ISYNC | ||
62 | : "=&r" (t) | ||
63 | : "r" (a), "r" (&v->counter) | ||
64 | : "cc", "memory"); | ||
65 | |||
66 | return t; | ||
67 | } | ||
68 | |||
69 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | ||
70 | |||
71 | static __inline__ void atomic_sub(int a, atomic_t *v) | ||
72 | { | ||
73 | int t; | ||
74 | |||
75 | __asm__ __volatile__( | ||
76 | "1: lwarx %0,0,%3 # atomic_sub\n\ | ||
77 | subf %0,%2,%0\n" | ||
78 | PPC405_ERR77(0,%3) | ||
79 | " stwcx. %0,0,%3 \n\ | ||
80 | bne- 1b" | ||
81 | : "=&r" (t), "=m" (v->counter) | ||
82 | : "r" (a), "r" (&v->counter), "m" (v->counter) | ||
83 | : "cc"); | ||
84 | } | ||
85 | |||
86 | static __inline__ int atomic_sub_return(int a, atomic_t *v) | ||
87 | { | ||
88 | int t; | ||
89 | |||
90 | __asm__ __volatile__( | ||
91 | "1: lwarx %0,0,%2 # atomic_sub_return\n\ | ||
92 | subf %0,%1,%0\n" | ||
93 | PPC405_ERR77(0,%2) | ||
94 | " stwcx. %0,0,%2 \n\ | ||
95 | bne- 1b" | ||
96 | SMP_ISYNC | ||
97 | : "=&r" (t) | ||
98 | : "r" (a), "r" (&v->counter) | ||
99 | : "cc", "memory"); | ||
100 | |||
101 | return t; | ||
102 | } | ||
103 | |||
104 | static __inline__ void atomic_inc(atomic_t *v) | ||
105 | { | ||
106 | int t; | ||
107 | |||
108 | __asm__ __volatile__( | ||
109 | "1: lwarx %0,0,%2 # atomic_inc\n\ | ||
110 | addic %0,%0,1\n" | ||
111 | PPC405_ERR77(0,%2) | ||
112 | " stwcx. %0,0,%2 \n\ | ||
113 | bne- 1b" | ||
114 | : "=&r" (t), "=m" (v->counter) | ||
115 | : "r" (&v->counter), "m" (v->counter) | ||
116 | : "cc"); | ||
117 | } | ||
118 | |||
119 | static __inline__ int atomic_inc_return(atomic_t *v) | ||
120 | { | ||
121 | int t; | ||
122 | |||
123 | __asm__ __volatile__( | ||
124 | "1: lwarx %0,0,%1 # atomic_inc_return\n\ | ||
125 | addic %0,%0,1\n" | ||
126 | PPC405_ERR77(0,%1) | ||
127 | " stwcx. %0,0,%1 \n\ | ||
128 | bne- 1b" | ||
129 | SMP_ISYNC | ||
130 | : "=&r" (t) | ||
131 | : "r" (&v->counter) | ||
132 | : "cc", "memory"); | ||
133 | |||
134 | return t; | ||
135 | } | ||
136 | |||
137 | /* | ||
138 | * atomic_inc_and_test - increment and test | ||
139 | * @v: pointer of type atomic_t | ||
140 | * | ||
141 | * Atomically increments @v by 1 | ||
142 | * and returns true if the result is zero, or false for all | ||
143 | * other cases. | ||
144 | */ | ||
145 | #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) | ||
146 | |||
147 | static __inline__ void atomic_dec(atomic_t *v) | ||
148 | { | ||
149 | int t; | ||
150 | |||
151 | __asm__ __volatile__( | ||
152 | "1: lwarx %0,0,%2 # atomic_dec\n\ | ||
153 | addic %0,%0,-1\n" | ||
154 | PPC405_ERR77(0,%2)\ | ||
155 | " stwcx. %0,0,%2\n\ | ||
156 | bne- 1b" | ||
157 | : "=&r" (t), "=m" (v->counter) | ||
158 | : "r" (&v->counter), "m" (v->counter) | ||
159 | : "cc"); | ||
160 | } | ||
161 | |||
162 | static __inline__ int atomic_dec_return(atomic_t *v) | ||
163 | { | ||
164 | int t; | ||
165 | |||
166 | __asm__ __volatile__( | ||
167 | "1: lwarx %0,0,%1 # atomic_dec_return\n\ | ||
168 | addic %0,%0,-1\n" | ||
169 | PPC405_ERR77(0,%1) | ||
170 | " stwcx. %0,0,%1\n\ | ||
171 | bne- 1b" | ||
172 | SMP_ISYNC | ||
173 | : "=&r" (t) | ||
174 | : "r" (&v->counter) | ||
175 | : "cc", "memory"); | ||
176 | |||
177 | return t; | ||
178 | } | ||
179 | |||
180 | #define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) | ||
181 | #define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) | ||
182 | |||
183 | /* | ||
184 | * Atomically test *v and decrement if it is greater than 0. | ||
185 | * The function returns the old value of *v minus 1. | ||
186 | */ | ||
187 | static __inline__ int atomic_dec_if_positive(atomic_t *v) | ||
188 | { | ||
189 | int t; | ||
190 | |||
191 | __asm__ __volatile__( | ||
192 | "1: lwarx %0,0,%1 # atomic_dec_if_positive\n\ | ||
193 | addic. %0,%0,-1\n\ | ||
194 | blt- 2f\n" | ||
195 | PPC405_ERR77(0,%1) | ||
196 | " stwcx. %0,0,%1\n\ | ||
197 | bne- 1b" | ||
198 | SMP_ISYNC | ||
199 | "\n\ | ||
200 | 2:" : "=&r" (t) | ||
201 | : "r" (&v->counter) | ||
202 | : "cc", "memory"); | ||
203 | |||
204 | return t; | ||
205 | } | ||
206 | |||
207 | #define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory") | ||
208 | #define smp_mb__before_atomic_dec() __MB | ||
209 | #define smp_mb__after_atomic_dec() __MB | ||
210 | #define smp_mb__before_atomic_inc() __MB | ||
211 | #define smp_mb__after_atomic_inc() __MB | ||
212 | |||
213 | #endif /* __KERNEL__ */ | ||
214 | #endif /* _ASM_PPC_ATOMIC_H_ */ | ||
diff --git a/include/asm-ppc/backlight.h b/include/asm-ppc/backlight.h new file mode 100644 index 000000000000..3a1c3dede2a0 --- /dev/null +++ b/include/asm-ppc/backlight.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Routines for handling backlight control on PowerBooks | ||
3 | * | ||
4 | * For now, implementation resides in arch/ppc/kernel/pmac_support.c | ||
5 | * | ||
6 | */ | ||
7 | #ifdef __KERNEL__ | ||
8 | #ifndef __ASM_PPC_BACKLIGHT_H | ||
9 | #define __ASM_PPC_BACKLIGHT_H | ||
10 | |||
11 | /* Abstract values */ | ||
12 | #define BACKLIGHT_OFF 0 | ||
13 | #define BACKLIGHT_MIN 1 | ||
14 | #define BACKLIGHT_MAX 0xf | ||
15 | |||
16 | struct backlight_controller { | ||
17 | int (*set_enable)(int enable, int level, void *data); | ||
18 | int (*set_level)(int level, void *data); | ||
19 | }; | ||
20 | |||
21 | extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type); | ||
22 | extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data); | ||
23 | |||
24 | extern int set_backlight_enable(int enable); | ||
25 | extern int get_backlight_enable(void); | ||
26 | extern int set_backlight_level(int level); | ||
27 | extern int get_backlight_level(void); | ||
28 | |||
29 | #endif | ||
30 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h new file mode 100644 index 000000000000..e30f536fd830 --- /dev/null +++ b/include/asm-ppc/bitops.h | |||
@@ -0,0 +1,460 @@ | |||
1 | /* | ||
2 | * bitops.h: Bit string operations on the ppc | ||
3 | */ | ||
4 | |||
5 | #ifdef __KERNEL__ | ||
6 | #ifndef _PPC_BITOPS_H | ||
7 | #define _PPC_BITOPS_H | ||
8 | |||
9 | #include <linux/config.h> | ||
10 | #include <linux/compiler.h> | ||
11 | #include <asm/byteorder.h> | ||
12 | #include <asm/atomic.h> | ||
13 | |||
14 | /* | ||
15 | * The test_and_*_bit operations are taken to imply a memory barrier | ||
16 | * on SMP systems. | ||
17 | */ | ||
18 | #ifdef CONFIG_SMP | ||
19 | #define SMP_WMB "eieio\n" | ||
20 | #define SMP_MB "\nsync" | ||
21 | #else | ||
22 | #define SMP_WMB | ||
23 | #define SMP_MB | ||
24 | #endif /* CONFIG_SMP */ | ||
25 | |||
26 | static __inline__ void set_bit(int nr, volatile unsigned long * addr) | ||
27 | { | ||
28 | unsigned long old; | ||
29 | unsigned long mask = 1 << (nr & 0x1f); | ||
30 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
31 | |||
32 | __asm__ __volatile__("\n\ | ||
33 | 1: lwarx %0,0,%3 \n\ | ||
34 | or %0,%0,%2 \n" | ||
35 | PPC405_ERR77(0,%3) | ||
36 | " stwcx. %0,0,%3 \n\ | ||
37 | bne- 1b" | ||
38 | : "=&r" (old), "=m" (*p) | ||
39 | : "r" (mask), "r" (p), "m" (*p) | ||
40 | : "cc" ); | ||
41 | } | ||
42 | |||
43 | /* | ||
44 | * non-atomic version | ||
45 | */ | ||
46 | static __inline__ void __set_bit(int nr, volatile unsigned long *addr) | ||
47 | { | ||
48 | unsigned long mask = 1 << (nr & 0x1f); | ||
49 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
50 | |||
51 | *p |= mask; | ||
52 | } | ||
53 | |||
54 | /* | ||
55 | * clear_bit doesn't imply a memory barrier | ||
56 | */ | ||
57 | #define smp_mb__before_clear_bit() smp_mb() | ||
58 | #define smp_mb__after_clear_bit() smp_mb() | ||
59 | |||
60 | static __inline__ void clear_bit(int nr, volatile unsigned long *addr) | ||
61 | { | ||
62 | unsigned long old; | ||
63 | unsigned long mask = 1 << (nr & 0x1f); | ||
64 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
65 | |||
66 | __asm__ __volatile__("\n\ | ||
67 | 1: lwarx %0,0,%3 \n\ | ||
68 | andc %0,%0,%2 \n" | ||
69 | PPC405_ERR77(0,%3) | ||
70 | " stwcx. %0,0,%3 \n\ | ||
71 | bne- 1b" | ||
72 | : "=&r" (old), "=m" (*p) | ||
73 | : "r" (mask), "r" (p), "m" (*p) | ||
74 | : "cc"); | ||
75 | } | ||
76 | |||
77 | /* | ||
78 | * non-atomic version | ||
79 | */ | ||
80 | static __inline__ void __clear_bit(int nr, volatile unsigned long *addr) | ||
81 | { | ||
82 | unsigned long mask = 1 << (nr & 0x1f); | ||
83 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
84 | |||
85 | *p &= ~mask; | ||
86 | } | ||
87 | |||
88 | static __inline__ void change_bit(int nr, volatile unsigned long *addr) | ||
89 | { | ||
90 | unsigned long old; | ||
91 | unsigned long mask = 1 << (nr & 0x1f); | ||
92 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
93 | |||
94 | __asm__ __volatile__("\n\ | ||
95 | 1: lwarx %0,0,%3 \n\ | ||
96 | xor %0,%0,%2 \n" | ||
97 | PPC405_ERR77(0,%3) | ||
98 | " stwcx. %0,0,%3 \n\ | ||
99 | bne- 1b" | ||
100 | : "=&r" (old), "=m" (*p) | ||
101 | : "r" (mask), "r" (p), "m" (*p) | ||
102 | : "cc"); | ||
103 | } | ||
104 | |||
105 | /* | ||
106 | * non-atomic version | ||
107 | */ | ||
108 | static __inline__ void __change_bit(int nr, volatile unsigned long *addr) | ||
109 | { | ||
110 | unsigned long mask = 1 << (nr & 0x1f); | ||
111 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
112 | |||
113 | *p ^= mask; | ||
114 | } | ||
115 | |||
116 | /* | ||
117 | * test_and_*_bit do imply a memory barrier (?) | ||
118 | */ | ||
119 | static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr) | ||
120 | { | ||
121 | unsigned int old, t; | ||
122 | unsigned int mask = 1 << (nr & 0x1f); | ||
123 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
124 | |||
125 | __asm__ __volatile__(SMP_WMB "\n\ | ||
126 | 1: lwarx %0,0,%4 \n\ | ||
127 | or %1,%0,%3 \n" | ||
128 | PPC405_ERR77(0,%4) | ||
129 | " stwcx. %1,0,%4 \n\ | ||
130 | bne 1b" | ||
131 | SMP_MB | ||
132 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
133 | : "r" (mask), "r" (p), "m" (*p) | ||
134 | : "cc", "memory"); | ||
135 | |||
136 | return (old & mask) != 0; | ||
137 | } | ||
138 | |||
139 | /* | ||
140 | * non-atomic version | ||
141 | */ | ||
142 | static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr) | ||
143 | { | ||
144 | unsigned long mask = 1 << (nr & 0x1f); | ||
145 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
146 | unsigned long old = *p; | ||
147 | |||
148 | *p = old | mask; | ||
149 | return (old & mask) != 0; | ||
150 | } | ||
151 | |||
152 | static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
153 | { | ||
154 | unsigned int old, t; | ||
155 | unsigned int mask = 1 << (nr & 0x1f); | ||
156 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
157 | |||
158 | __asm__ __volatile__(SMP_WMB "\n\ | ||
159 | 1: lwarx %0,0,%4 \n\ | ||
160 | andc %1,%0,%3 \n" | ||
161 | PPC405_ERR77(0,%4) | ||
162 | " stwcx. %1,0,%4 \n\ | ||
163 | bne 1b" | ||
164 | SMP_MB | ||
165 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
166 | : "r" (mask), "r" (p), "m" (*p) | ||
167 | : "cc", "memory"); | ||
168 | |||
169 | return (old & mask) != 0; | ||
170 | } | ||
171 | |||
172 | /* | ||
173 | * non-atomic version | ||
174 | */ | ||
175 | static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr) | ||
176 | { | ||
177 | unsigned long mask = 1 << (nr & 0x1f); | ||
178 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
179 | unsigned long old = *p; | ||
180 | |||
181 | *p = old & ~mask; | ||
182 | return (old & mask) != 0; | ||
183 | } | ||
184 | |||
185 | static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr) | ||
186 | { | ||
187 | unsigned int old, t; | ||
188 | unsigned int mask = 1 << (nr & 0x1f); | ||
189 | volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5); | ||
190 | |||
191 | __asm__ __volatile__(SMP_WMB "\n\ | ||
192 | 1: lwarx %0,0,%4 \n\ | ||
193 | xor %1,%0,%3 \n" | ||
194 | PPC405_ERR77(0,%4) | ||
195 | " stwcx. %1,0,%4 \n\ | ||
196 | bne 1b" | ||
197 | SMP_MB | ||
198 | : "=&r" (old), "=&r" (t), "=m" (*p) | ||
199 | : "r" (mask), "r" (p), "m" (*p) | ||
200 | : "cc", "memory"); | ||
201 | |||
202 | return (old & mask) != 0; | ||
203 | } | ||
204 | |||
205 | /* | ||
206 | * non-atomic version | ||
207 | */ | ||
208 | static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr) | ||
209 | { | ||
210 | unsigned long mask = 1 << (nr & 0x1f); | ||
211 | unsigned long *p = ((unsigned long *)addr) + (nr >> 5); | ||
212 | unsigned long old = *p; | ||
213 | |||
214 | *p = old ^ mask; | ||
215 | return (old & mask) != 0; | ||
216 | } | ||
217 | |||
218 | static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr) | ||
219 | { | ||
220 | return ((addr[nr >> 5] >> (nr & 0x1f)) & 1) != 0; | ||
221 | } | ||
222 | |||
223 | /* Return the bit position of the most significant 1 bit in a word */ | ||
224 | static __inline__ int __ilog2(unsigned long x) | ||
225 | { | ||
226 | int lz; | ||
227 | |||
228 | asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); | ||
229 | return 31 - lz; | ||
230 | } | ||
231 | |||
232 | static __inline__ int ffz(unsigned long x) | ||
233 | { | ||
234 | if ((x = ~x) == 0) | ||
235 | return 32; | ||
236 | return __ilog2(x & -x); | ||
237 | } | ||
238 | |||
239 | static inline int __ffs(unsigned long x) | ||
240 | { | ||
241 | return __ilog2(x & -x); | ||
242 | } | ||
243 | |||
244 | /* | ||
245 | * ffs: find first bit set. This is defined the same way as | ||
246 | * the libc and compiler builtin ffs routines, therefore | ||
247 | * differs in spirit from the above ffz (man ffs). | ||
248 | */ | ||
249 | static __inline__ int ffs(int x) | ||
250 | { | ||
251 | return __ilog2(x & -x) + 1; | ||
252 | } | ||
253 | |||
254 | /* | ||
255 | * fls: find last (most-significant) bit set. | ||
256 | * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. | ||
257 | */ | ||
258 | static __inline__ int fls(unsigned int x) | ||
259 | { | ||
260 | int lz; | ||
261 | |||
262 | asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x)); | ||
263 | return 32 - lz; | ||
264 | } | ||
265 | |||
266 | /* | ||
267 | * hweightN: returns the hamming weight (i.e. the number | ||
268 | * of bits set) of a N-bit word | ||
269 | */ | ||
270 | |||
271 | #define hweight32(x) generic_hweight32(x) | ||
272 | #define hweight16(x) generic_hweight16(x) | ||
273 | #define hweight8(x) generic_hweight8(x) | ||
274 | |||
275 | /* | ||
276 | * Find the first bit set in a 140-bit bitmap. | ||
277 | * The first 100 bits are unlikely to be set. | ||
278 | */ | ||
279 | static inline int sched_find_first_bit(const unsigned long *b) | ||
280 | { | ||
281 | if (unlikely(b[0])) | ||
282 | return __ffs(b[0]); | ||
283 | if (unlikely(b[1])) | ||
284 | return __ffs(b[1]) + 32; | ||
285 | if (unlikely(b[2])) | ||
286 | return __ffs(b[2]) + 64; | ||
287 | if (b[3]) | ||
288 | return __ffs(b[3]) + 96; | ||
289 | return __ffs(b[4]) + 128; | ||
290 | } | ||
291 | |||
292 | /** | ||
293 | * find_next_bit - find the next set bit in a memory region | ||
294 | * @addr: The address to base the search on | ||
295 | * @offset: The bitnumber to start searching at | ||
296 | * @size: The maximum size to search | ||
297 | */ | ||
298 | static __inline__ unsigned long find_next_bit(const unsigned long *addr, | ||
299 | unsigned long size, unsigned long offset) | ||
300 | { | ||
301 | unsigned int *p = ((unsigned int *) addr) + (offset >> 5); | ||
302 | unsigned int result = offset & ~31UL; | ||
303 | unsigned int tmp; | ||
304 | |||
305 | if (offset >= size) | ||
306 | return size; | ||
307 | size -= result; | ||
308 | offset &= 31UL; | ||
309 | if (offset) { | ||
310 | tmp = *p++; | ||
311 | tmp &= ~0UL << offset; | ||
312 | if (size < 32) | ||
313 | goto found_first; | ||
314 | if (tmp) | ||
315 | goto found_middle; | ||
316 | size -= 32; | ||
317 | result += 32; | ||
318 | } | ||
319 | while (size >= 32) { | ||
320 | if ((tmp = *p++) != 0) | ||
321 | goto found_middle; | ||
322 | result += 32; | ||
323 | size -= 32; | ||
324 | } | ||
325 | if (!size) | ||
326 | return result; | ||
327 | tmp = *p; | ||
328 | |||
329 | found_first: | ||
330 | tmp &= ~0UL >> (32 - size); | ||
331 | if (tmp == 0UL) /* Are any bits set? */ | ||
332 | return result + size; /* Nope. */ | ||
333 | found_middle: | ||
334 | return result + __ffs(tmp); | ||
335 | } | ||
336 | |||
337 | /** | ||
338 | * find_first_bit - find the first set bit in a memory region | ||
339 | * @addr: The address to start the search at | ||
340 | * @size: The maximum size to search | ||
341 | * | ||
342 | * Returns the bit-number of the first set bit, not the number of the byte | ||
343 | * containing a bit. | ||
344 | */ | ||
345 | #define find_first_bit(addr, size) \ | ||
346 | find_next_bit((addr), (size), 0) | ||
347 | |||
348 | /* | ||
349 | * This implementation of find_{first,next}_zero_bit was stolen from | ||
350 | * Linus' asm-alpha/bitops.h. | ||
351 | */ | ||
352 | #define find_first_zero_bit(addr, size) \ | ||
353 | find_next_zero_bit((addr), (size), 0) | ||
354 | |||
355 | static __inline__ unsigned long find_next_zero_bit(const unsigned long *addr, | ||
356 | unsigned long size, unsigned long offset) | ||
357 | { | ||
358 | unsigned int * p = ((unsigned int *) addr) + (offset >> 5); | ||
359 | unsigned int result = offset & ~31UL; | ||
360 | unsigned int tmp; | ||
361 | |||
362 | if (offset >= size) | ||
363 | return size; | ||
364 | size -= result; | ||
365 | offset &= 31UL; | ||
366 | if (offset) { | ||
367 | tmp = *p++; | ||
368 | tmp |= ~0UL >> (32-offset); | ||
369 | if (size < 32) | ||
370 | goto found_first; | ||
371 | if (tmp != ~0U) | ||
372 | goto found_middle; | ||
373 | size -= 32; | ||
374 | result += 32; | ||
375 | } | ||
376 | while (size >= 32) { | ||
377 | if ((tmp = *p++) != ~0U) | ||
378 | goto found_middle; | ||
379 | result += 32; | ||
380 | size -= 32; | ||
381 | } | ||
382 | if (!size) | ||
383 | return result; | ||
384 | tmp = *p; | ||
385 | found_first: | ||
386 | tmp |= ~0UL << size; | ||
387 | if (tmp == ~0UL) /* Are any bits zero? */ | ||
388 | return result + size; /* Nope. */ | ||
389 | found_middle: | ||
390 | return result + ffz(tmp); | ||
391 | } | ||
392 | |||
393 | |||
394 | #define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr)) | ||
395 | #define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr)) | ||
396 | #define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr)) | ||
397 | #define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr)) | ||
398 | |||
399 | static __inline__ int ext2_test_bit(int nr, __const__ void * addr) | ||
400 | { | ||
401 | __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; | ||
402 | |||
403 | return (ADDR[nr >> 3] >> (nr & 7)) & 1; | ||
404 | } | ||
405 | |||
406 | /* | ||
407 | * This implementation of ext2_find_{first,next}_zero_bit was stolen from | ||
408 | * Linus' asm-alpha/bitops.h and modified for a big-endian machine. | ||
409 | */ | ||
410 | |||
411 | #define ext2_find_first_zero_bit(addr, size) \ | ||
412 | ext2_find_next_zero_bit((addr), (size), 0) | ||
413 | |||
414 | static __inline__ unsigned long ext2_find_next_zero_bit(const void *addr, | ||
415 | unsigned long size, unsigned long offset) | ||
416 | { | ||
417 | unsigned int *p = ((unsigned int *) addr) + (offset >> 5); | ||
418 | unsigned int result = offset & ~31UL; | ||
419 | unsigned int tmp; | ||
420 | |||
421 | if (offset >= size) | ||
422 | return size; | ||
423 | size -= result; | ||
424 | offset &= 31UL; | ||
425 | if (offset) { | ||
426 | tmp = cpu_to_le32p(p++); | ||
427 | tmp |= ~0UL >> (32-offset); | ||
428 | if (size < 32) | ||
429 | goto found_first; | ||
430 | if (tmp != ~0U) | ||
431 | goto found_middle; | ||
432 | size -= 32; | ||
433 | result += 32; | ||
434 | } | ||
435 | while (size >= 32) { | ||
436 | if ((tmp = cpu_to_le32p(p++)) != ~0U) | ||
437 | goto found_middle; | ||
438 | result += 32; | ||
439 | size -= 32; | ||
440 | } | ||
441 | if (!size) | ||
442 | return result; | ||
443 | tmp = cpu_to_le32p(p); | ||
444 | found_first: | ||
445 | tmp |= ~0U << size; | ||
446 | if (tmp == ~0UL) /* Are any bits zero? */ | ||
447 | return result + size; /* Nope. */ | ||
448 | found_middle: | ||
449 | return result + ffz(tmp); | ||
450 | } | ||
451 | |||
452 | /* Bitmap functions for the minix filesystem. */ | ||
453 | #define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr) | ||
454 | #define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr)) | ||
455 | #define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr) | ||
456 | #define minix_test_bit(nr,addr) ext2_test_bit(nr,addr) | ||
457 | #define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size) | ||
458 | |||
459 | #endif /* _PPC_BITOPS_H */ | ||
460 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h new file mode 100644 index 000000000000..93d955c70d65 --- /dev/null +++ b/include/asm-ppc/bootinfo.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Non-machine dependent bootinfo structure. Basic idea | ||
3 | * borrowed from the m68k. | ||
4 | * | ||
5 | * Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org> | ||
6 | */ | ||
7 | |||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef _PPC_BOOTINFO_H | ||
10 | #define _PPC_BOOTINFO_H | ||
11 | |||
12 | #include <linux/config.h> | ||
13 | #include <asm/page.h> | ||
14 | |||
15 | #if defined(CONFIG_APUS) && !defined(__BOOTER__) | ||
16 | #include <asm-m68k/bootinfo.h> | ||
17 | #else | ||
18 | |||
19 | struct bi_record { | ||
20 | unsigned long tag; /* tag ID */ | ||
21 | unsigned long size; /* size of record (in bytes) */ | ||
22 | unsigned long data[0]; /* data */ | ||
23 | }; | ||
24 | |||
25 | #define BI_FIRST 0x1010 /* first record - marker */ | ||
26 | #define BI_LAST 0x1011 /* last record - marker */ | ||
27 | #define BI_CMD_LINE 0x1012 | ||
28 | #define BI_BOOTLOADER_ID 0x1013 | ||
29 | #define BI_INITRD 0x1014 | ||
30 | #define BI_SYSMAP 0x1015 | ||
31 | #define BI_MACHTYPE 0x1016 | ||
32 | #define BI_MEMSIZE 0x1017 | ||
33 | #define BI_BOARD_INFO 0x1018 | ||
34 | |||
35 | extern struct bi_record *find_bootinfo(void); | ||
36 | extern void bootinfo_init(struct bi_record *rec); | ||
37 | extern void bootinfo_append(unsigned long tag, unsigned long size, void * data); | ||
38 | extern void parse_bootinfo(struct bi_record *rec); | ||
39 | extern unsigned long boot_mem_size; | ||
40 | |||
41 | static inline struct bi_record * | ||
42 | bootinfo_addr(unsigned long offset) | ||
43 | { | ||
44 | |||
45 | return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1, | ||
46 | (1 << 20)); | ||
47 | } | ||
48 | #endif /* CONFIG_APUS */ | ||
49 | |||
50 | |||
51 | #endif /* _PPC_BOOTINFO_H */ | ||
52 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h new file mode 100644 index 000000000000..b0c51b45d7a2 --- /dev/null +++ b/include/asm-ppc/bootx.h | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * This file describes the structure passed from the BootX application | ||
3 | * (for MacOS) when it is used to boot Linux. | ||
4 | * | ||
5 | * Written by Benjamin Herrenschmidt. | ||
6 | */ | ||
7 | |||
8 | |||
9 | #ifndef __ASM_BOOTX_H__ | ||
10 | #define __ASM_BOOTX_H__ | ||
11 | |||
12 | #ifdef macintosh | ||
13 | #include <Types.h> | ||
14 | #include "linux_type_defs.h" | ||
15 | #endif | ||
16 | |||
17 | #ifdef macintosh | ||
18 | /* All this requires PowerPC alignment */ | ||
19 | #pragma options align=power | ||
20 | #endif | ||
21 | |||
22 | /* On kernel entry: | ||
23 | * | ||
24 | * r3 = 0x426f6f58 ('BooX') | ||
25 | * r4 = pointer to boot_infos | ||
26 | * r5 = NULL | ||
27 | * | ||
28 | * Data and instruction translation disabled, interrupts | ||
29 | * disabled, kernel loaded at physical 0x00000000 on PCI | ||
30 | * machines (will be different on NuBus). | ||
31 | */ | ||
32 | |||
33 | #define BOOT_INFO_VERSION 5 | ||
34 | #define BOOT_INFO_COMPATIBLE_VERSION 1 | ||
35 | |||
36 | /* Bit in the architecture flag mask. More to be defined in | ||
37 | future versions. Note that either BOOT_ARCH_PCI or | ||
38 | BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are | ||
39 | set additionally when BOOT_ARCH_NUBUS is set. | ||
40 | */ | ||
41 | #define BOOT_ARCH_PCI 0x00000001UL | ||
42 | #define BOOT_ARCH_NUBUS 0x00000002UL | ||
43 | #define BOOT_ARCH_NUBUS_PDM 0x00000010UL | ||
44 | #define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL | ||
45 | #define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL | ||
46 | |||
47 | /* Maximum number of ranges in phys memory map */ | ||
48 | #define MAX_MEM_MAP_SIZE 26 | ||
49 | |||
50 | /* This is the format of an element in the physical memory map. Note that | ||
51 | the map is optional and current BootX will only build it for pre-PCI | ||
52 | machines */ | ||
53 | typedef struct boot_info_map_entry | ||
54 | { | ||
55 | __u32 physAddr; /* Physical starting address */ | ||
56 | __u32 size; /* Size in bytes */ | ||
57 | } boot_info_map_entry_t; | ||
58 | |||
59 | |||
60 | /* Here are the boot informations that are passed to the bootstrap | ||
61 | * Note that the kernel arguments and the device tree are appended | ||
62 | * at the end of this structure. */ | ||
63 | typedef struct boot_infos | ||
64 | { | ||
65 | /* Version of this structure */ | ||
66 | __u32 version; | ||
67 | /* backward compatible down to version: */ | ||
68 | __u32 compatible_version; | ||
69 | |||
70 | /* NEW (vers. 2) this holds the current _logical_ base addr of | ||
71 | the frame buffer (for use by early boot message) */ | ||
72 | __u8* logicalDisplayBase; | ||
73 | |||
74 | /* NEW (vers. 4) Apple's machine identification */ | ||
75 | __u32 machineID; | ||
76 | |||
77 | /* NEW (vers. 4) Detected hw architecture */ | ||
78 | __u32 architecture; | ||
79 | |||
80 | /* The device tree (internal addresses relative to the beginning of the tree, | ||
81 | * device tree offset relative to the beginning of this structure). | ||
82 | * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this | ||
83 | * field is 0. | ||
84 | */ | ||
85 | __u32 deviceTreeOffset; /* Device tree offset */ | ||
86 | __u32 deviceTreeSize; /* Size of the device tree */ | ||
87 | |||
88 | /* Some infos about the current MacOS display */ | ||
89 | __u32 dispDeviceRect[4]; /* left,top,right,bottom */ | ||
90 | __u32 dispDeviceDepth; /* (8, 16 or 32) */ | ||
91 | __u8* dispDeviceBase; /* base address (physical) */ | ||
92 | __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ | ||
93 | __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ | ||
94 | /* Optional offset in the registry to the current | ||
95 | * MacOS display. (Can be 0 when not detected) */ | ||
96 | __u32 dispDeviceRegEntryOffset; | ||
97 | |||
98 | /* Optional pointer to boot ramdisk (offset from this structure) */ | ||
99 | __u32 ramDisk; | ||
100 | __u32 ramDiskSize; /* size of ramdisk image */ | ||
101 | |||
102 | /* Kernel command line arguments (offset from this structure) */ | ||
103 | __u32 kernelParamsOffset; | ||
104 | |||
105 | /* ALL BELOW NEW (vers. 4) */ | ||
106 | |||
107 | /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag | ||
108 | (non-PCI) only. On PCI, memory is contiguous and it's size is in the | ||
109 | device-tree. */ | ||
110 | boot_info_map_entry_t | ||
111 | physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ | ||
112 | __u32 physMemoryMapSize; /* How many entries in map */ | ||
113 | |||
114 | |||
115 | /* The framebuffer size (optional, currently 0) */ | ||
116 | __u32 frameBufferSize; /* Represents a max size, can be 0. */ | ||
117 | |||
118 | /* NEW (vers. 5) */ | ||
119 | |||
120 | /* Total params size (args + colormap + device tree + ramdisk) */ | ||
121 | __u32 totalParamsSize; | ||
122 | |||
123 | } boot_infos_t; | ||
124 | |||
125 | /* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented | ||
126 | * by 3 short words containing a 16 bits (unsigned) color component. | ||
127 | * Later versions may contain the gamma table for direct-color devices here. | ||
128 | */ | ||
129 | #define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) | ||
130 | |||
131 | #ifdef macintosh | ||
132 | #pragma options align=reset | ||
133 | #endif | ||
134 | |||
135 | #endif | ||
diff --git a/include/asm-ppc/bseip.h b/include/asm-ppc/bseip.h new file mode 100644 index 000000000000..691f4a52b0a5 --- /dev/null +++ b/include/asm-ppc/bseip.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * A collection of structures, addresses, and values associated with | ||
3 | * the Bright Star Engineering ip-Engine board. Copied from the MBX stuff. | ||
4 | * | ||
5 | * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) | ||
6 | */ | ||
7 | #ifndef __MACH_BSEIP_DEFS | ||
8 | #define __MACH_BSEIP_DEFS | ||
9 | |||
10 | #ifndef __ASSEMBLY__ | ||
11 | /* A Board Information structure that is given to a program when | ||
12 | * prom starts it up. | ||
13 | */ | ||
14 | typedef struct bd_info { | ||
15 | unsigned int bi_memstart; /* Memory start address */ | ||
16 | unsigned int bi_memsize; /* Memory (end) size in bytes */ | ||
17 | unsigned int bi_intfreq; /* Internal Freq, in Hz */ | ||
18 | unsigned int bi_busfreq; /* Bus Freq, in Hz */ | ||
19 | unsigned char bi_enetaddr[6]; | ||
20 | unsigned int bi_baudrate; | ||
21 | } bd_t; | ||
22 | |||
23 | extern bd_t m8xx_board_info; | ||
24 | |||
25 | /* Memory map is configured by the PROM startup. | ||
26 | * All we need to get started is the IMMR. | ||
27 | */ | ||
28 | #define IMAP_ADDR ((uint)0xff000000) | ||
29 | #define IMAP_SIZE ((uint)(64 * 1024)) | ||
30 | #define PCMCIA_MEM_ADDR ((uint)0x04000000) | ||
31 | #define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) | ||
32 | #endif /* !__ASSEMBLY__ */ | ||
33 | |||
34 | /* We don't use the 8259. | ||
35 | */ | ||
36 | #define NR_8259_INTS 0 | ||
37 | |||
38 | #endif | ||
diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h new file mode 100644 index 000000000000..36c7640d00f2 --- /dev/null +++ b/include/asm-ppc/btext.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Definitions for using the procedures in btext.c. | ||
3 | * | ||
4 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> | ||
5 | */ | ||
6 | #ifndef __PPC_BTEXT_H | ||
7 | #define __PPC_BTEXT_H | ||
8 | #ifdef __KERNEL__ | ||
9 | |||
10 | #include <asm/bootx.h> | ||
11 | |||
12 | extern void btext_clearscreen(void); | ||
13 | extern void btext_flushscreen(void); | ||
14 | |||
15 | extern unsigned long disp_BAT[2]; | ||
16 | |||
17 | extern boot_infos_t disp_bi; | ||
18 | extern int boot_text_mapped; | ||
19 | |||
20 | void btext_init(boot_infos_t *bi); | ||
21 | void btext_welcome(void); | ||
22 | void btext_prepare_BAT(void); | ||
23 | void btext_setup_display(int width, int height, int depth, int pitch, | ||
24 | unsigned long address); | ||
25 | void map_boot_text(void); | ||
26 | void btext_update_display(unsigned long phys, int width, int height, | ||
27 | int depth, int pitch); | ||
28 | |||
29 | void btext_drawchar(char c); | ||
30 | void btext_drawstring(const char *str); | ||
31 | void btext_drawhex(unsigned long v); | ||
32 | |||
33 | #endif /* __KERNEL__ */ | ||
34 | #endif /* __PPC_BTEXT_H */ | ||
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h new file mode 100644 index 000000000000..e99c6cb9d618 --- /dev/null +++ b/include/asm-ppc/bug.h | |||
@@ -0,0 +1,55 @@ | |||
1 | #ifndef _PPC_BUG_H | ||
2 | #define _PPC_BUG_H | ||
3 | |||
4 | struct bug_entry { | ||
5 | unsigned long bug_addr; | ||
6 | int line; | ||
7 | const char *file; | ||
8 | const char *function; | ||
9 | }; | ||
10 | |||
11 | /* | ||
12 | * If this bit is set in the line number it means that the trap | ||
13 | * is for WARN_ON rather than BUG or BUG_ON. | ||
14 | */ | ||
15 | #define BUG_WARNING_TRAP 0x1000000 | ||
16 | |||
17 | #define BUG() do { \ | ||
18 | __asm__ __volatile__( \ | ||
19 | "1: twi 31,0,0\n" \ | ||
20 | ".section __bug_table,\"a\"\n\t" \ | ||
21 | " .long 1b,%0,%1,%2\n" \ | ||
22 | ".previous" \ | ||
23 | : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \ | ||
24 | } while (0) | ||
25 | |||
26 | #define BUG_ON(x) do { \ | ||
27 | if (!__builtin_constant_p(x) || (x)) { \ | ||
28 | __asm__ __volatile__( \ | ||
29 | "1: twnei %0,0\n" \ | ||
30 | ".section __bug_table,\"a\"\n\t" \ | ||
31 | " .long 1b,%1,%2,%3\n" \ | ||
32 | ".previous" \ | ||
33 | : : "r" (x), "i" (__LINE__), "i" (__FILE__), \ | ||
34 | "i" (__FUNCTION__)); \ | ||
35 | } \ | ||
36 | } while (0) | ||
37 | |||
38 | #define WARN_ON(x) do { \ | ||
39 | if (!__builtin_constant_p(x) || (x)) { \ | ||
40 | __asm__ __volatile__( \ | ||
41 | "1: twnei %0,0\n" \ | ||
42 | ".section __bug_table,\"a\"\n\t" \ | ||
43 | " .long 1b,%1,%2,%3\n" \ | ||
44 | ".previous" \ | ||
45 | : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \ | ||
46 | "i" (__FILE__), "i" (__FUNCTION__)); \ | ||
47 | } \ | ||
48 | } while (0) | ||
49 | |||
50 | #define HAVE_ARCH_BUG | ||
51 | #define HAVE_ARCH_BUG_ON | ||
52 | #define HAVE_ARCH_WARN_ON | ||
53 | #include <asm-generic/bug.h> | ||
54 | |||
55 | #endif | ||
diff --git a/include/asm-ppc/bugs.h b/include/asm-ppc/bugs.h new file mode 100644 index 000000000000..8dce1e290fd0 --- /dev/null +++ b/include/asm-ppc/bugs.h | |||
@@ -0,0 +1,6 @@ | |||
1 | /* | ||
2 | * This file is included by 'init/main.c' | ||
3 | */ | ||
4 | |||
5 | extern void | ||
6 | check_bugs(void); | ||
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h new file mode 100644 index 000000000000..c63c81ec7968 --- /dev/null +++ b/include/asm-ppc/byteorder.h | |||
@@ -0,0 +1,76 @@ | |||
1 | #ifndef _PPC_BYTEORDER_H | ||
2 | #define _PPC_BYTEORDER_H | ||
3 | |||
4 | #include <asm/types.h> | ||
5 | #include <linux/compiler.h> | ||
6 | |||
7 | #ifdef __GNUC__ | ||
8 | #ifdef __KERNEL__ | ||
9 | |||
10 | extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) | ||
11 | { | ||
12 | unsigned val; | ||
13 | |||
14 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); | ||
15 | return val; | ||
16 | } | ||
17 | |||
18 | extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) | ||
19 | { | ||
20 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); | ||
21 | } | ||
22 | |||
23 | extern __inline__ unsigned ld_le32(const volatile unsigned *addr) | ||
24 | { | ||
25 | unsigned val; | ||
26 | |||
27 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); | ||
28 | return val; | ||
29 | } | ||
30 | |||
31 | extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) | ||
32 | { | ||
33 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); | ||
34 | } | ||
35 | |||
36 | static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value) | ||
37 | { | ||
38 | __u16 result; | ||
39 | |||
40 | __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value)); | ||
41 | return result; | ||
42 | } | ||
43 | |||
44 | static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value) | ||
45 | { | ||
46 | __u32 result; | ||
47 | |||
48 | __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value)); | ||
49 | __asm__("rlwimi %0,%2,8,8,15" : "=&r" (result) : "0" (result), "r" (value)); | ||
50 | __asm__("rlwimi %0,%2,24,0,7" : "=&r" (result) : "0" (result), "r" (value)); | ||
51 | |||
52 | return result; | ||
53 | } | ||
54 | #define __arch__swab32(x) ___arch__swab32(x) | ||
55 | #define __arch__swab16(x) ___arch__swab16(x) | ||
56 | |||
57 | /* The same, but returns converted value from the location pointer by addr. */ | ||
58 | #define __arch__swab16p(addr) ld_le16(addr) | ||
59 | #define __arch__swab32p(addr) ld_le32(addr) | ||
60 | |||
61 | /* The same, but do the conversion in situ, ie. put the value back to addr. */ | ||
62 | #define __arch__swab16s(addr) st_le16(addr,*addr) | ||
63 | #define __arch__swab32s(addr) st_le32(addr,*addr) | ||
64 | |||
65 | #endif /* __KERNEL__ */ | ||
66 | |||
67 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
68 | # define __BYTEORDER_HAS_U64__ | ||
69 | # define __SWAB_64_THRU_32__ | ||
70 | #endif | ||
71 | |||
72 | #endif /* __GNUC__ */ | ||
73 | |||
74 | #include <linux/byteorder/big_endian.h> | ||
75 | |||
76 | #endif /* _PPC_BYTEORDER_H */ | ||
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h new file mode 100644 index 000000000000..38f2f1be4a87 --- /dev/null +++ b/include/asm-ppc/cache.h | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/cache.h | ||
3 | */ | ||
4 | #ifdef __KERNEL__ | ||
5 | #ifndef __ARCH_PPC_CACHE_H | ||
6 | #define __ARCH_PPC_CACHE_H | ||
7 | |||
8 | #include <linux/config.h> | ||
9 | |||
10 | /* bytes per L1 cache line */ | ||
11 | #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) | ||
12 | #define L1_CACHE_LINE_SIZE 16 | ||
13 | #define LG_L1_CACHE_LINE_SIZE 4 | ||
14 | #define MAX_COPY_PREFETCH 1 | ||
15 | #elif defined(CONFIG_PPC64BRIDGE) | ||
16 | #define L1_CACHE_LINE_SIZE 128 | ||
17 | #define LG_L1_CACHE_LINE_SIZE 7 | ||
18 | #define MAX_COPY_PREFETCH 1 | ||
19 | #else | ||
20 | #define L1_CACHE_LINE_SIZE 32 | ||
21 | #define LG_L1_CACHE_LINE_SIZE 5 | ||
22 | #define MAX_COPY_PREFETCH 4 | ||
23 | #endif | ||
24 | |||
25 | #define L1_CACHE_BYTES L1_CACHE_LINE_SIZE | ||
26 | #define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE | ||
27 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | ||
28 | #define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ | ||
29 | |||
30 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | ||
31 | #define L1_CACHE_PAGES 8 | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | extern void clean_dcache_range(unsigned long start, unsigned long stop); | ||
35 | extern void flush_dcache_range(unsigned long start, unsigned long stop); | ||
36 | extern void invalidate_dcache_range(unsigned long start, unsigned long stop); | ||
37 | extern void flush_dcache_all(void); | ||
38 | #endif /* __ASSEMBLY__ */ | ||
39 | |||
40 | /* prep registers for L2 */ | ||
41 | #define CACHECRBA 0x80000823 /* Cache configuration register address */ | ||
42 | #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ | ||
43 | #define L2CACHE_512KB 0x00 /* 512KB */ | ||
44 | #define L2CACHE_256KB 0x01 /* 256KB */ | ||
45 | #define L2CACHE_1MB 0x02 /* 1MB */ | ||
46 | #define L2CACHE_NONE 0x03 /* NONE */ | ||
47 | #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ | ||
48 | |||
49 | #ifdef CONFIG_8xx | ||
50 | /* Cache control on the MPC8xx is provided through some additional | ||
51 | * special purpose registers. | ||
52 | */ | ||
53 | #define SPRN_IC_CST 560 /* Instruction cache control/status */ | ||
54 | #define SPRN_IC_ADR 561 /* Address needed for some commands */ | ||
55 | #define SPRN_IC_DAT 562 /* Read-only data register */ | ||
56 | #define SPRN_DC_CST 568 /* Data cache control/status */ | ||
57 | #define SPRN_DC_ADR 569 /* Address needed for some commands */ | ||
58 | #define SPRN_DC_DAT 570 /* Read-only data register */ | ||
59 | |||
60 | /* Commands. Only the first few are available to the instruction cache. | ||
61 | */ | ||
62 | #define IDC_ENABLE 0x02000000 /* Cache enable */ | ||
63 | #define IDC_DISABLE 0x04000000 /* Cache disable */ | ||
64 | #define IDC_LDLCK 0x06000000 /* Load and lock */ | ||
65 | #define IDC_UNLINE 0x08000000 /* Unlock line */ | ||
66 | #define IDC_UNALL 0x0a000000 /* Unlock all */ | ||
67 | #define IDC_INVALL 0x0c000000 /* Invalidate all */ | ||
68 | |||
69 | #define DC_FLINE 0x0e000000 /* Flush data cache line */ | ||
70 | #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ | ||
71 | #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ | ||
72 | #define DC_SLES 0x05000000 /* Set little endian swap mode */ | ||
73 | #define DC_CLES 0x07000000 /* Clear little endian swap mode */ | ||
74 | |||
75 | /* Status. | ||
76 | */ | ||
77 | #define IDC_ENABLED 0x80000000 /* Cache is enabled */ | ||
78 | #define IDC_CERR1 0x00200000 /* Cache error 1 */ | ||
79 | #define IDC_CERR2 0x00100000 /* Cache error 2 */ | ||
80 | #define IDC_CERR3 0x00080000 /* Cache error 3 */ | ||
81 | |||
82 | #define DC_DFWT 0x40000000 /* Data cache is forced write through */ | ||
83 | #define DC_LES 0x20000000 /* Caches are little endian mode */ | ||
84 | #endif /* CONFIG_8xx */ | ||
85 | |||
86 | #endif | ||
87 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/cacheflush.h b/include/asm-ppc/cacheflush.h new file mode 100644 index 000000000000..6a243efb3317 --- /dev/null +++ b/include/asm-ppc/cacheflush.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/cacheflush.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation; either version | ||
7 | * 2 of the License, or (at your option) any later version. | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef _PPC_CACHEFLUSH_H | ||
11 | #define _PPC_CACHEFLUSH_H | ||
12 | |||
13 | #include <linux/mm.h> | ||
14 | |||
15 | /* | ||
16 | * No cache flushing is required when address mappings are | ||
17 | * changed, because the caches on PowerPCs are physically | ||
18 | * addressed. -- paulus | ||
19 | * Also, when SMP we use the coherency (M) bit of the | ||
20 | * BATs and PTEs. -- Cort | ||
21 | */ | ||
22 | #define flush_cache_all() do { } while (0) | ||
23 | #define flush_cache_mm(mm) do { } while (0) | ||
24 | #define flush_cache_range(vma, a, b) do { } while (0) | ||
25 | #define flush_cache_page(vma, p, pfn) do { } while (0) | ||
26 | #define flush_icache_page(vma, page) do { } while (0) | ||
27 | #define flush_cache_vmap(start, end) do { } while (0) | ||
28 | #define flush_cache_vunmap(start, end) do { } while (0) | ||
29 | |||
30 | extern void flush_dcache_page(struct page *page); | ||
31 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
32 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
33 | |||
34 | extern void flush_icache_range(unsigned long, unsigned long); | ||
35 | extern void flush_icache_user_range(struct vm_area_struct *vma, | ||
36 | struct page *page, unsigned long addr, int len); | ||
37 | |||
38 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
39 | do { memcpy(dst, src, len); \ | ||
40 | flush_icache_user_range(vma, page, vaddr, len); \ | ||
41 | } while (0) | ||
42 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
43 | memcpy(dst, src, len) | ||
44 | |||
45 | extern void __flush_dcache_icache(void *page_va); | ||
46 | extern void __flush_dcache_icache_phys(unsigned long physaddr); | ||
47 | extern void flush_dcache_icache_page(struct page *page); | ||
48 | #endif /* _PPC_CACHEFLUSH_H */ | ||
49 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/checksum.h b/include/asm-ppc/checksum.h new file mode 100644 index 000000000000..cf953a92c7ab --- /dev/null +++ b/include/asm-ppc/checksum.h | |||
@@ -0,0 +1,107 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_CHECKSUM_H | ||
3 | #define _PPC_CHECKSUM_H | ||
4 | |||
5 | |||
6 | /* | ||
7 | * computes the checksum of a memory block at buff, length len, | ||
8 | * and adds in "sum" (32-bit) | ||
9 | * | ||
10 | * returns a 32-bit number suitable for feeding into itself | ||
11 | * or csum_tcpudp_magic | ||
12 | * | ||
13 | * this function must be called with even lengths, except | ||
14 | * for the last fragment, which may be odd | ||
15 | * | ||
16 | * it's best to have buff aligned on a 32-bit boundary | ||
17 | */ | ||
18 | extern unsigned int csum_partial(const unsigned char * buff, int len, | ||
19 | unsigned int sum); | ||
20 | |||
21 | /* | ||
22 | * Computes the checksum of a memory block at src, length len, | ||
23 | * and adds in "sum" (32-bit), while copying the block to dst. | ||
24 | * If an access exception occurs on src or dst, it stores -EFAULT | ||
25 | * to *src_err or *dst_err respectively (if that pointer is not | ||
26 | * NULL), and, for an error on src, zeroes the rest of dst. | ||
27 | * | ||
28 | * Like csum_partial, this must be called with even lengths, | ||
29 | * except for the last fragment. | ||
30 | */ | ||
31 | extern unsigned int csum_partial_copy_generic(const char *src, char *dst, | ||
32 | int len, unsigned int sum, | ||
33 | int *src_err, int *dst_err); | ||
34 | |||
35 | #define csum_partial_copy_from_user(src, dst, len, sum, errp) \ | ||
36 | csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL) | ||
37 | |||
38 | /* FIXME: this needs to be written to really do no check -- Cort */ | ||
39 | #define csum_partial_copy_nocheck(src, dst, len, sum) \ | ||
40 | csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL) | ||
41 | |||
42 | /* | ||
43 | * turns a 32-bit partial checksum (e.g. from csum_partial) into a | ||
44 | * 1's complement 16-bit checksum. | ||
45 | */ | ||
46 | static inline unsigned int csum_fold(unsigned int sum) | ||
47 | { | ||
48 | unsigned int tmp; | ||
49 | |||
50 | /* swap the two 16-bit halves of sum */ | ||
51 | __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum)); | ||
52 | /* if there is a carry from adding the two 16-bit halves, | ||
53 | it will carry from the lower half into the upper half, | ||
54 | giving us the correct sum in the upper half. */ | ||
55 | sum = ~(sum + tmp) >> 16; | ||
56 | return sum; | ||
57 | } | ||
58 | |||
59 | /* | ||
60 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
61 | * in icmp.c | ||
62 | */ | ||
63 | static inline unsigned short ip_compute_csum(unsigned char * buff, int len) | ||
64 | { | ||
65 | return csum_fold(csum_partial(buff, len, 0)); | ||
66 | } | ||
67 | |||
68 | /* | ||
69 | * FIXME: I swiped this one from the sparc and made minor modifications. | ||
70 | * It may not be correct. -- Cort | ||
71 | */ | ||
72 | static inline unsigned long csum_tcpudp_nofold(unsigned long saddr, | ||
73 | unsigned long daddr, | ||
74 | unsigned short len, | ||
75 | unsigned short proto, | ||
76 | unsigned int sum) | ||
77 | { | ||
78 | __asm__("\n\ | ||
79 | addc %0,%0,%1 \n\ | ||
80 | adde %0,%0,%2 \n\ | ||
81 | adde %0,%0,%3 \n\ | ||
82 | addze %0,%0 \n\ | ||
83 | " | ||
84 | : "=r" (sum) | ||
85 | : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum)); | ||
86 | return sum; | ||
87 | } | ||
88 | |||
89 | /* | ||
90 | * This is a version of ip_compute_csum() optimized for IP headers, | ||
91 | * which always checksum on 4 octet boundaries. ihl is the number | ||
92 | * of 32-bit words and is always >= 5. | ||
93 | */ | ||
94 | extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl); | ||
95 | |||
96 | /* | ||
97 | * computes the checksum of the TCP/UDP pseudo-header | ||
98 | * returns a 16-bit checksum, already complemented | ||
99 | */ | ||
100 | extern unsigned short csum_tcpudp_magic(unsigned long saddr, | ||
101 | unsigned long daddr, | ||
102 | unsigned short len, | ||
103 | unsigned short proto, | ||
104 | unsigned int sum); | ||
105 | |||
106 | #endif | ||
107 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h new file mode 100644 index 000000000000..5bbb8e2c1c6d --- /dev/null +++ b/include/asm-ppc/commproc.h | |||
@@ -0,0 +1,695 @@ | |||
1 | /* | ||
2 | * MPC8xx Communication Processor Module. | ||
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | ||
4 | * | ||
5 | * This file contains structures and information for the communication | ||
6 | * processor channels. Some CPM control and status is available | ||
7 | * throught the MPC8xx internal memory map. See immap.h for details. | ||
8 | * This file only contains what I need for the moment, not the total | ||
9 | * CPM capabilities. I (or someone else) will add definitions as they | ||
10 | * are needed. -- Dan | ||
11 | * | ||
12 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | ||
13 | * bytes of the DP RAM and relocates the I2C parameter area to the | ||
14 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | ||
15 | * or other use. | ||
16 | */ | ||
17 | #ifndef __CPM_8XX__ | ||
18 | #define __CPM_8XX__ | ||
19 | |||
20 | #include <linux/config.h> | ||
21 | #include <asm/8xx_immap.h> | ||
22 | #include <asm/ptrace.h> | ||
23 | |||
24 | /* CPM Command register. | ||
25 | */ | ||
26 | #define CPM_CR_RST ((ushort)0x8000) | ||
27 | #define CPM_CR_OPCODE ((ushort)0x0f00) | ||
28 | #define CPM_CR_CHAN ((ushort)0x00f0) | ||
29 | #define CPM_CR_FLG ((ushort)0x0001) | ||
30 | |||
31 | /* Some commands (there are more...later) | ||
32 | */ | ||
33 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | ||
34 | #define CPM_CR_INIT_RX ((ushort)0x0001) | ||
35 | #define CPM_CR_INIT_TX ((ushort)0x0002) | ||
36 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | ||
37 | #define CPM_CR_STOP_TX ((ushort)0x0004) | ||
38 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | ||
39 | #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) | ||
40 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | ||
41 | #define CPM_CR_SET_TIMER CPM_CR_SET_GADDR | ||
42 | |||
43 | /* Channel numbers. | ||
44 | */ | ||
45 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) | ||
46 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | ||
47 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | ||
48 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ | ||
49 | #define CPM_CR_CH_TIMER CPM_CR_CH_SPI | ||
50 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | ||
51 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | ||
52 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | ||
53 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | ||
54 | |||
55 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | ||
56 | |||
57 | /* The dual ported RAM is multi-functional. Some areas can be (and are | ||
58 | * being) used for microcode. There is an area that can only be used | ||
59 | * as data ram for buffer descriptors, which is all we use right now. | ||
60 | * Currently the first 512 and last 256 bytes are used for microcode. | ||
61 | */ | ||
62 | #define CPM_DATAONLY_BASE ((uint)0x0800) | ||
63 | #define CPM_DATAONLY_SIZE ((uint)0x0700) | ||
64 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | ||
65 | |||
66 | static inline long IS_DPERR(const uint offset) | ||
67 | { | ||
68 | return (uint)offset > (uint)-1000L; | ||
69 | } | ||
70 | |||
71 | /* Export the base address of the communication processor registers | ||
72 | * and dual port ram. | ||
73 | */ | ||
74 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ | ||
75 | extern uint cpm_dpalloc(uint size, uint align); | ||
76 | extern int cpm_dpfree(uint offset); | ||
77 | extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); | ||
78 | extern void cpm_dpdump(void); | ||
79 | extern void *cpm_dpram_addr(uint offset); | ||
80 | extern void cpm_setbrg(uint brg, uint rate); | ||
81 | |||
82 | extern uint m8xx_cpm_hostalloc(uint size); | ||
83 | extern int m8xx_cpm_hostfree(uint start); | ||
84 | extern void m8xx_cpm_hostdump(void); | ||
85 | |||
86 | /* Buffer descriptors used by many of the CPM protocols. | ||
87 | */ | ||
88 | typedef struct cpm_buf_desc { | ||
89 | ushort cbd_sc; /* Status and Control */ | ||
90 | ushort cbd_datlen; /* Data length in buffer */ | ||
91 | uint cbd_bufaddr; /* Buffer address in host memory */ | ||
92 | } cbd_t; | ||
93 | |||
94 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | ||
95 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | ||
96 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | ||
97 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | ||
98 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | ||
99 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | ||
100 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | ||
101 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | ||
102 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | ||
103 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | ||
104 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | ||
105 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | ||
106 | #define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ | ||
107 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | ||
108 | #define BD_SC_UN ((ushort)0x0002) /* Underrun */ | ||
109 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | ||
110 | #define BD_SC_CL ((ushort)0x0001) /* Collision */ | ||
111 | |||
112 | /* Parameter RAM offsets. | ||
113 | */ | ||
114 | #define PROFF_SCC1 ((uint)0x0000) | ||
115 | #define PROFF_IIC ((uint)0x0080) | ||
116 | #define PROFF_SCC2 ((uint)0x0100) | ||
117 | #define PROFF_SPI ((uint)0x0180) | ||
118 | #define PROFF_SCC3 ((uint)0x0200) | ||
119 | #define PROFF_SMC1 ((uint)0x0280) | ||
120 | #define PROFF_SCC4 ((uint)0x0300) | ||
121 | #define PROFF_SMC2 ((uint)0x0380) | ||
122 | |||
123 | /* Define enough so I can at least use the serial port as a UART. | ||
124 | * The MBX uses SMC1 as the host serial port. | ||
125 | */ | ||
126 | typedef struct smc_uart { | ||
127 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | ||
128 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | ||
129 | u_char smc_rfcr; /* Rx function code */ | ||
130 | u_char smc_tfcr; /* Tx function code */ | ||
131 | ushort smc_mrblr; /* Max receive buffer length */ | ||
132 | uint smc_rstate; /* Internal */ | ||
133 | uint smc_idp; /* Internal */ | ||
134 | ushort smc_rbptr; /* Internal */ | ||
135 | ushort smc_ibc; /* Internal */ | ||
136 | uint smc_rxtmp; /* Internal */ | ||
137 | uint smc_tstate; /* Internal */ | ||
138 | uint smc_tdp; /* Internal */ | ||
139 | ushort smc_tbptr; /* Internal */ | ||
140 | ushort smc_tbc; /* Internal */ | ||
141 | uint smc_txtmp; /* Internal */ | ||
142 | ushort smc_maxidl; /* Maximum idle characters */ | ||
143 | ushort smc_tmpidl; /* Temporary idle counter */ | ||
144 | ushort smc_brklen; /* Last received break length */ | ||
145 | ushort smc_brkec; /* rcv'd break condition counter */ | ||
146 | ushort smc_brkcr; /* xmt break count register */ | ||
147 | ushort smc_rmask; /* Temporary bit mask */ | ||
148 | char res1[8]; /* Reserved */ | ||
149 | ushort smc_rpbase; /* Relocation pointer */ | ||
150 | } smc_uart_t; | ||
151 | |||
152 | /* Function code bits. | ||
153 | */ | ||
154 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
155 | |||
156 | /* SMC uart mode register. | ||
157 | */ | ||
158 | #define SMCMR_REN ((ushort)0x0001) | ||
159 | #define SMCMR_TEN ((ushort)0x0002) | ||
160 | #define SMCMR_DM ((ushort)0x000c) | ||
161 | #define SMCMR_SM_GCI ((ushort)0x0000) | ||
162 | #define SMCMR_SM_UART ((ushort)0x0020) | ||
163 | #define SMCMR_SM_TRANS ((ushort)0x0030) | ||
164 | #define SMCMR_SM_MASK ((ushort)0x0030) | ||
165 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | ||
166 | #define SMCMR_REVD SMCMR_PM_EVEN | ||
167 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | ||
168 | #define SMCMR_BS SMCMR_PEN | ||
169 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | ||
170 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | ||
171 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | ||
172 | |||
173 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | ||
174 | * it can only receive or transmit. The parameter ram values for | ||
175 | * each direction are either unique or properly overlap, so we can | ||
176 | * include them in one structure. | ||
177 | */ | ||
178 | typedef struct smc_centronics { | ||
179 | ushort scent_rbase; | ||
180 | ushort scent_tbase; | ||
181 | u_char scent_cfcr; | ||
182 | u_char scent_smask; | ||
183 | ushort scent_mrblr; | ||
184 | uint scent_rstate; | ||
185 | uint scent_r_ptr; | ||
186 | ushort scent_rbptr; | ||
187 | ushort scent_r_cnt; | ||
188 | uint scent_rtemp; | ||
189 | uint scent_tstate; | ||
190 | uint scent_t_ptr; | ||
191 | ushort scent_tbptr; | ||
192 | ushort scent_t_cnt; | ||
193 | uint scent_ttemp; | ||
194 | ushort scent_max_sl; | ||
195 | ushort scent_sl_cnt; | ||
196 | ushort scent_character1; | ||
197 | ushort scent_character2; | ||
198 | ushort scent_character3; | ||
199 | ushort scent_character4; | ||
200 | ushort scent_character5; | ||
201 | ushort scent_character6; | ||
202 | ushort scent_character7; | ||
203 | ushort scent_character8; | ||
204 | ushort scent_rccm; | ||
205 | ushort scent_rccr; | ||
206 | } smc_cent_t; | ||
207 | |||
208 | /* Centronics Status Mask Register. | ||
209 | */ | ||
210 | #define SMC_CENT_F ((u_char)0x08) | ||
211 | #define SMC_CENT_PE ((u_char)0x04) | ||
212 | #define SMC_CENT_S ((u_char)0x02) | ||
213 | |||
214 | /* SMC Event and Mask register. | ||
215 | */ | ||
216 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | ||
217 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | ||
218 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | ||
219 | #define SMCM_BSY ((unsigned char)0x04) | ||
220 | #define SMCM_TX ((unsigned char)0x02) | ||
221 | #define SMCM_RX ((unsigned char)0x01) | ||
222 | |||
223 | /* Baud rate generators. | ||
224 | */ | ||
225 | #define CPM_BRG_RST ((uint)0x00020000) | ||
226 | #define CPM_BRG_EN ((uint)0x00010000) | ||
227 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | ||
228 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | ||
229 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | ||
230 | #define CPM_BRG_ATB ((uint)0x00002000) | ||
231 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | ||
232 | #define CPM_BRG_DIV16 ((uint)0x00000001) | ||
233 | |||
234 | /* SI Clock Route Register | ||
235 | */ | ||
236 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | ||
237 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | ||
238 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | ||
239 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | ||
240 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | ||
241 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | ||
242 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | ||
243 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | ||
244 | |||
245 | /* SCCs. | ||
246 | */ | ||
247 | #define SCC_GSMRH_IRP ((uint)0x00040000) | ||
248 | #define SCC_GSMRH_GDE ((uint)0x00010000) | ||
249 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | ||
250 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | ||
251 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | ||
252 | #define SCC_GSMRH_REVD ((uint)0x00002000) | ||
253 | #define SCC_GSMRH_TRX ((uint)0x00001000) | ||
254 | #define SCC_GSMRH_TTX ((uint)0x00000800) | ||
255 | #define SCC_GSMRH_CDP ((uint)0x00000400) | ||
256 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | ||
257 | #define SCC_GSMRH_CDS ((uint)0x00000100) | ||
258 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | ||
259 | #define SCC_GSMRH_TFL ((uint)0x00000040) | ||
260 | #define SCC_GSMRH_RFW ((uint)0x00000020) | ||
261 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | ||
262 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | ||
263 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | ||
264 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | ||
265 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | ||
266 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | ||
267 | |||
268 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | ||
269 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | ||
270 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | ||
271 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | ||
272 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | ||
273 | #define SCC_GSMRL_TCI ((uint)0x10000000) | ||
274 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | ||
275 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | ||
276 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | ||
277 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | ||
278 | #define SCC_GSMRL_RINV ((uint)0x02000000) | ||
279 | #define SCC_GSMRL_TINV ((uint)0x01000000) | ||
280 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | ||
281 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | ||
282 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | ||
283 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | ||
284 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | ||
285 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | ||
286 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | ||
287 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | ||
288 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | ||
289 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | ||
290 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | ||
291 | #define SCC_GSMRL_TEND ((uint)0x00040000) | ||
292 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | ||
293 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | ||
294 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | ||
295 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | ||
296 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | ||
297 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | ||
298 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | ||
299 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | ||
300 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | ||
301 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | ||
302 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | ||
303 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | ||
304 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | ||
305 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | ||
306 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | ||
307 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | ||
308 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | ||
309 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | ||
310 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | ||
311 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | ||
312 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | ||
313 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | ||
314 | #define SCC_GSMRL_ENR ((uint)0x00000020) | ||
315 | #define SCC_GSMRL_ENT ((uint)0x00000010) | ||
316 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | ||
317 | #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) | ||
318 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | ||
319 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | ||
320 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | ||
321 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | ||
322 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | ||
323 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | ||
324 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | ||
325 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | ||
326 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | ||
327 | |||
328 | #define SCC_TODR_TOD ((ushort)0x8000) | ||
329 | |||
330 | /* SCC Event and Mask register. | ||
331 | */ | ||
332 | #define SCCM_TXE ((unsigned char)0x10) | ||
333 | #define SCCM_BSY ((unsigned char)0x04) | ||
334 | #define SCCM_TX ((unsigned char)0x02) | ||
335 | #define SCCM_RX ((unsigned char)0x01) | ||
336 | |||
337 | typedef struct scc_param { | ||
338 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | ||
339 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | ||
340 | u_char scc_rfcr; /* Rx function code */ | ||
341 | u_char scc_tfcr; /* Tx function code */ | ||
342 | ushort scc_mrblr; /* Max receive buffer length */ | ||
343 | uint scc_rstate; /* Internal */ | ||
344 | uint scc_idp; /* Internal */ | ||
345 | ushort scc_rbptr; /* Internal */ | ||
346 | ushort scc_ibc; /* Internal */ | ||
347 | uint scc_rxtmp; /* Internal */ | ||
348 | uint scc_tstate; /* Internal */ | ||
349 | uint scc_tdp; /* Internal */ | ||
350 | ushort scc_tbptr; /* Internal */ | ||
351 | ushort scc_tbc; /* Internal */ | ||
352 | uint scc_txtmp; /* Internal */ | ||
353 | uint scc_rcrc; /* Internal */ | ||
354 | uint scc_tcrc; /* Internal */ | ||
355 | } sccp_t; | ||
356 | |||
357 | /* Function code bits. | ||
358 | */ | ||
359 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
360 | |||
361 | /* CPM Ethernet through SCCx. | ||
362 | */ | ||
363 | typedef struct scc_enet { | ||
364 | sccp_t sen_genscc; | ||
365 | uint sen_cpres; /* Preset CRC */ | ||
366 | uint sen_cmask; /* Constant mask for CRC */ | ||
367 | uint sen_crcec; /* CRC Error counter */ | ||
368 | uint sen_alec; /* alignment error counter */ | ||
369 | uint sen_disfc; /* discard frame counter */ | ||
370 | ushort sen_pads; /* Tx short frame pad character */ | ||
371 | ushort sen_retlim; /* Retry limit threshold */ | ||
372 | ushort sen_retcnt; /* Retry limit counter */ | ||
373 | ushort sen_maxflr; /* maximum frame length register */ | ||
374 | ushort sen_minflr; /* minimum frame length register */ | ||
375 | ushort sen_maxd1; /* maximum DMA1 length */ | ||
376 | ushort sen_maxd2; /* maximum DMA2 length */ | ||
377 | ushort sen_maxd; /* Rx max DMA */ | ||
378 | ushort sen_dmacnt; /* Rx DMA counter */ | ||
379 | ushort sen_maxb; /* Max BD byte count */ | ||
380 | ushort sen_gaddr1; /* Group address filter */ | ||
381 | ushort sen_gaddr2; | ||
382 | ushort sen_gaddr3; | ||
383 | ushort sen_gaddr4; | ||
384 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | ||
385 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | ||
386 | uint sen_tbuf0rba; /* Internal */ | ||
387 | uint sen_tbuf0crc; /* Internal */ | ||
388 | ushort sen_tbuf0bcnt; /* Internal */ | ||
389 | ushort sen_paddrh; /* physical address (MSB) */ | ||
390 | ushort sen_paddrm; | ||
391 | ushort sen_paddrl; /* physical address (LSB) */ | ||
392 | ushort sen_pper; /* persistence */ | ||
393 | ushort sen_rfbdptr; /* Rx first BD pointer */ | ||
394 | ushort sen_tfbdptr; /* Tx first BD pointer */ | ||
395 | ushort sen_tlbdptr; /* Tx last BD pointer */ | ||
396 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | ||
397 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | ||
398 | uint sen_tbuf1rba; /* Internal */ | ||
399 | uint sen_tbuf1crc; /* Internal */ | ||
400 | ushort sen_tbuf1bcnt; /* Internal */ | ||
401 | ushort sen_txlen; /* Tx Frame length counter */ | ||
402 | ushort sen_iaddr1; /* Individual address filter */ | ||
403 | ushort sen_iaddr2; | ||
404 | ushort sen_iaddr3; | ||
405 | ushort sen_iaddr4; | ||
406 | ushort sen_boffcnt; /* Backoff counter */ | ||
407 | |||
408 | /* NOTE: Some versions of the manual have the following items | ||
409 | * incorrectly documented. Below is the proper order. | ||
410 | */ | ||
411 | ushort sen_taddrh; /* temp address (MSB) */ | ||
412 | ushort sen_taddrm; | ||
413 | ushort sen_taddrl; /* temp address (LSB) */ | ||
414 | } scc_enet_t; | ||
415 | |||
416 | /* SCC Event register as used by Ethernet. | ||
417 | */ | ||
418 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
419 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
420 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
421 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | ||
422 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
423 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
424 | |||
425 | /* SCC Mode Register (PMSR) as used by Ethernet. | ||
426 | */ | ||
427 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | ||
428 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | ||
429 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | ||
430 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | ||
431 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | ||
432 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | ||
433 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | ||
434 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | ||
435 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | ||
436 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | ||
437 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | ||
438 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | ||
439 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | ||
440 | |||
441 | /* Buffer descriptor control/status used by Ethernet receive. | ||
442 | */ | ||
443 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | ||
444 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | ||
445 | #define BD_ENET_RX_INTR ((ushort)0x1000) | ||
446 | #define BD_ENET_RX_LAST ((ushort)0x0800) | ||
447 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | ||
448 | #define BD_ENET_RX_MISS ((ushort)0x0100) | ||
449 | #define BD_ENET_RX_LG ((ushort)0x0020) | ||
450 | #define BD_ENET_RX_NO ((ushort)0x0010) | ||
451 | #define BD_ENET_RX_SH ((ushort)0x0008) | ||
452 | #define BD_ENET_RX_CR ((ushort)0x0004) | ||
453 | #define BD_ENET_RX_OV ((ushort)0x0002) | ||
454 | #define BD_ENET_RX_CL ((ushort)0x0001) | ||
455 | #define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ | ||
456 | #define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ | ||
457 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | ||
458 | |||
459 | /* Buffer descriptor control/status used by Ethernet transmit. | ||
460 | */ | ||
461 | #define BD_ENET_TX_READY ((ushort)0x8000) | ||
462 | #define BD_ENET_TX_PAD ((ushort)0x4000) | ||
463 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | ||
464 | #define BD_ENET_TX_INTR ((ushort)0x1000) | ||
465 | #define BD_ENET_TX_LAST ((ushort)0x0800) | ||
466 | #define BD_ENET_TX_TC ((ushort)0x0400) | ||
467 | #define BD_ENET_TX_DEF ((ushort)0x0200) | ||
468 | #define BD_ENET_TX_HB ((ushort)0x0100) | ||
469 | #define BD_ENET_TX_LC ((ushort)0x0080) | ||
470 | #define BD_ENET_TX_RL ((ushort)0x0040) | ||
471 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | ||
472 | #define BD_ENET_TX_UN ((ushort)0x0002) | ||
473 | #define BD_ENET_TX_CSL ((ushort)0x0001) | ||
474 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | ||
475 | |||
476 | /* SCC as UART | ||
477 | */ | ||
478 | typedef struct scc_uart { | ||
479 | sccp_t scc_genscc; | ||
480 | char res1[8]; /* Reserved */ | ||
481 | ushort scc_maxidl; /* Maximum idle chars */ | ||
482 | ushort scc_idlc; /* temp idle counter */ | ||
483 | ushort scc_brkcr; /* Break count register */ | ||
484 | ushort scc_parec; /* receive parity error counter */ | ||
485 | ushort scc_frmec; /* receive framing error counter */ | ||
486 | ushort scc_nosec; /* receive noise counter */ | ||
487 | ushort scc_brkec; /* receive break condition counter */ | ||
488 | ushort scc_brkln; /* last received break length */ | ||
489 | ushort scc_uaddr1; /* UART address character 1 */ | ||
490 | ushort scc_uaddr2; /* UART address character 2 */ | ||
491 | ushort scc_rtemp; /* Temp storage */ | ||
492 | ushort scc_toseq; /* Transmit out of sequence char */ | ||
493 | ushort scc_char1; /* control character 1 */ | ||
494 | ushort scc_char2; /* control character 2 */ | ||
495 | ushort scc_char3; /* control character 3 */ | ||
496 | ushort scc_char4; /* control character 4 */ | ||
497 | ushort scc_char5; /* control character 5 */ | ||
498 | ushort scc_char6; /* control character 6 */ | ||
499 | ushort scc_char7; /* control character 7 */ | ||
500 | ushort scc_char8; /* control character 8 */ | ||
501 | ushort scc_rccm; /* receive control character mask */ | ||
502 | ushort scc_rccr; /* receive control character register */ | ||
503 | ushort scc_rlbc; /* receive last break character */ | ||
504 | } scc_uart_t; | ||
505 | |||
506 | /* SCC Event and Mask registers when it is used as a UART. | ||
507 | */ | ||
508 | #define UART_SCCM_GLR ((ushort)0x1000) | ||
509 | #define UART_SCCM_GLT ((ushort)0x0800) | ||
510 | #define UART_SCCM_AB ((ushort)0x0200) | ||
511 | #define UART_SCCM_IDL ((ushort)0x0100) | ||
512 | #define UART_SCCM_GRA ((ushort)0x0080) | ||
513 | #define UART_SCCM_BRKE ((ushort)0x0040) | ||
514 | #define UART_SCCM_BRKS ((ushort)0x0020) | ||
515 | #define UART_SCCM_CCR ((ushort)0x0008) | ||
516 | #define UART_SCCM_BSY ((ushort)0x0004) | ||
517 | #define UART_SCCM_TX ((ushort)0x0002) | ||
518 | #define UART_SCCM_RX ((ushort)0x0001) | ||
519 | |||
520 | /* The SCC PMSR when used as a UART. | ||
521 | */ | ||
522 | #define SCU_PSMR_FLC ((ushort)0x8000) | ||
523 | #define SCU_PSMR_SL ((ushort)0x4000) | ||
524 | #define SCU_PSMR_CL ((ushort)0x3000) | ||
525 | #define SCU_PSMR_UM ((ushort)0x0c00) | ||
526 | #define SCU_PSMR_FRZ ((ushort)0x0200) | ||
527 | #define SCU_PSMR_RZS ((ushort)0x0100) | ||
528 | #define SCU_PSMR_SYN ((ushort)0x0080) | ||
529 | #define SCU_PSMR_DRT ((ushort)0x0040) | ||
530 | #define SCU_PSMR_PEN ((ushort)0x0010) | ||
531 | #define SCU_PSMR_RPM ((ushort)0x000c) | ||
532 | #define SCU_PSMR_REVP ((ushort)0x0008) | ||
533 | #define SCU_PSMR_TPM ((ushort)0x0003) | ||
534 | #define SCU_PSMR_TEVP ((ushort)0x0002) | ||
535 | |||
536 | /* CPM Transparent mode SCC. | ||
537 | */ | ||
538 | typedef struct scc_trans { | ||
539 | sccp_t st_genscc; | ||
540 | uint st_cpres; /* Preset CRC */ | ||
541 | uint st_cmask; /* Constant mask for CRC */ | ||
542 | } scc_trans_t; | ||
543 | |||
544 | #define BD_SCC_TX_LAST ((ushort)0x0800) | ||
545 | |||
546 | /* IIC parameter RAM. | ||
547 | */ | ||
548 | typedef struct iic { | ||
549 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | ||
550 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | ||
551 | u_char iic_rfcr; /* Rx function code */ | ||
552 | u_char iic_tfcr; /* Tx function code */ | ||
553 | ushort iic_mrblr; /* Max receive buffer length */ | ||
554 | uint iic_rstate; /* Internal */ | ||
555 | uint iic_rdp; /* Internal */ | ||
556 | ushort iic_rbptr; /* Internal */ | ||
557 | ushort iic_rbc; /* Internal */ | ||
558 | uint iic_rxtmp; /* Internal */ | ||
559 | uint iic_tstate; /* Internal */ | ||
560 | uint iic_tdp; /* Internal */ | ||
561 | ushort iic_tbptr; /* Internal */ | ||
562 | ushort iic_tbc; /* Internal */ | ||
563 | uint iic_txtmp; /* Internal */ | ||
564 | char res1[4]; /* Reserved */ | ||
565 | ushort iic_rpbase; /* Relocation pointer */ | ||
566 | char res2[2]; /* Reserved */ | ||
567 | } iic_t; | ||
568 | |||
569 | #define BD_IIC_START ((ushort)0x0400) | ||
570 | |||
571 | /* SPI parameter RAM. | ||
572 | */ | ||
573 | typedef struct spi { | ||
574 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | ||
575 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | ||
576 | u_char spi_rfcr; /* Rx function code */ | ||
577 | u_char spi_tfcr; /* Tx function code */ | ||
578 | ushort spi_mrblr; /* Max receive buffer length */ | ||
579 | uint spi_rstate; /* Internal */ | ||
580 | uint spi_rdp; /* Internal */ | ||
581 | ushort spi_rbptr; /* Internal */ | ||
582 | ushort spi_rbc; /* Internal */ | ||
583 | uint spi_rxtmp; /* Internal */ | ||
584 | uint spi_tstate; /* Internal */ | ||
585 | uint spi_tdp; /* Internal */ | ||
586 | ushort spi_tbptr; /* Internal */ | ||
587 | ushort spi_tbc; /* Internal */ | ||
588 | uint spi_txtmp; /* Internal */ | ||
589 | uint spi_res; | ||
590 | ushort spi_rpbase; /* Relocation pointer */ | ||
591 | ushort spi_res2; | ||
592 | } spi_t; | ||
593 | |||
594 | /* SPI Mode register. | ||
595 | */ | ||
596 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | ||
597 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | ||
598 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | ||
599 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | ||
600 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | ||
601 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | ||
602 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | ||
603 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | ||
604 | #define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ | ||
605 | #define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ | ||
606 | #define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ | ||
607 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | ||
608 | |||
609 | /* SPIE fields */ | ||
610 | #define SPIE_MME 0x20 | ||
611 | #define SPIE_TXE 0x10 | ||
612 | #define SPIE_BSY 0x04 | ||
613 | #define SPIE_TXB 0x02 | ||
614 | #define SPIE_RXB 0x01 | ||
615 | |||
616 | /* | ||
617 | * RISC Controller Configuration Register definitons | ||
618 | */ | ||
619 | #define RCCR_TIME 0x8000 /* RISC Timer Enable */ | ||
620 | #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ | ||
621 | #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ | ||
622 | |||
623 | /* RISC Timer Parameter RAM offset */ | ||
624 | #define PROFF_RTMR ((uint)0x01B0) | ||
625 | |||
626 | typedef struct risc_timer_pram { | ||
627 | unsigned short tm_base; /* RISC Timer Table Base Address */ | ||
628 | unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ | ||
629 | unsigned short r_tmr; /* RISC Timer Mode Register */ | ||
630 | unsigned short r_tmv; /* RISC Timer Valid Register */ | ||
631 | unsigned long tm_cmd; /* RISC Timer Command Register */ | ||
632 | unsigned long tm_cnt; /* RISC Timer Internal Count */ | ||
633 | } rt_pram_t; | ||
634 | |||
635 | /* Bits in RISC Timer Command Register */ | ||
636 | #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ | ||
637 | #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ | ||
638 | #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ | ||
639 | #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ | ||
640 | #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ | ||
641 | |||
642 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | ||
643 | * channels or devices. All of these are presented to the PPC core | ||
644 | * as a single interrupt. The CPM interrupt handler dispatches its | ||
645 | * own handlers, in a similar fashion to the PPC core handler. We | ||
646 | * use the table as defined in the manuals (i.e. no special high | ||
647 | * priority and SCC1 == SCCa, etc...). | ||
648 | */ | ||
649 | #define CPMVEC_NR 32 | ||
650 | #define CPMVEC_PIO_PC15 ((ushort)0x1f) | ||
651 | #define CPMVEC_SCC1 ((ushort)0x1e) | ||
652 | #define CPMVEC_SCC2 ((ushort)0x1d) | ||
653 | #define CPMVEC_SCC3 ((ushort)0x1c) | ||
654 | #define CPMVEC_SCC4 ((ushort)0x1b) | ||
655 | #define CPMVEC_PIO_PC14 ((ushort)0x1a) | ||
656 | #define CPMVEC_TIMER1 ((ushort)0x19) | ||
657 | #define CPMVEC_PIO_PC13 ((ushort)0x18) | ||
658 | #define CPMVEC_PIO_PC12 ((ushort)0x17) | ||
659 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) | ||
660 | #define CPMVEC_IDMA1 ((ushort)0x15) | ||
661 | #define CPMVEC_IDMA2 ((ushort)0x14) | ||
662 | #define CPMVEC_TIMER2 ((ushort)0x12) | ||
663 | #define CPMVEC_RISCTIMER ((ushort)0x11) | ||
664 | #define CPMVEC_I2C ((ushort)0x10) | ||
665 | #define CPMVEC_PIO_PC11 ((ushort)0x0f) | ||
666 | #define CPMVEC_PIO_PC10 ((ushort)0x0e) | ||
667 | #define CPMVEC_TIMER3 ((ushort)0x0c) | ||
668 | #define CPMVEC_PIO_PC9 ((ushort)0x0b) | ||
669 | #define CPMVEC_PIO_PC8 ((ushort)0x0a) | ||
670 | #define CPMVEC_PIO_PC7 ((ushort)0x09) | ||
671 | #define CPMVEC_TIMER4 ((ushort)0x07) | ||
672 | #define CPMVEC_PIO_PC6 ((ushort)0x06) | ||
673 | #define CPMVEC_SPI ((ushort)0x05) | ||
674 | #define CPMVEC_SMC1 ((ushort)0x04) | ||
675 | #define CPMVEC_SMC2 ((ushort)0x03) | ||
676 | #define CPMVEC_PIO_PC5 ((ushort)0x02) | ||
677 | #define CPMVEC_PIO_PC4 ((ushort)0x01) | ||
678 | #define CPMVEC_ERROR ((ushort)0x00) | ||
679 | |||
680 | /* CPM interrupt configuration vector. | ||
681 | */ | ||
682 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | ||
683 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | ||
684 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | ||
685 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | ||
686 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ | ||
687 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | ||
688 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | ||
689 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | ||
690 | |||
691 | extern void cpm_install_handler(int vec, | ||
692 | void (*handler)(void *, struct pt_regs *regs), void *dev_id); | ||
693 | extern void cpm_free_handler(int vec); | ||
694 | |||
695 | #endif /* __CPM_8XX__ */ | ||
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h new file mode 100644 index 000000000000..42fd1068cf2a --- /dev/null +++ b/include/asm-ppc/cpm2.h | |||
@@ -0,0 +1,1045 @@ | |||
1 | /* | ||
2 | * Communication Processor Module v2. | ||
3 | * | ||
4 | * This file contains structures and information for the communication | ||
5 | * processor channels found in the dual port RAM or parameter RAM. | ||
6 | * All CPM control and status is available through the CPM2 internal | ||
7 | * memory map. See immap_cpm2.h for details. | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef __CPM2__ | ||
11 | #define __CPM2__ | ||
12 | |||
13 | #include <asm/immap_cpm2.h> | ||
14 | |||
15 | /* CPM Command register. | ||
16 | */ | ||
17 | #define CPM_CR_RST ((uint)0x80000000) | ||
18 | #define CPM_CR_PAGE ((uint)0x7c000000) | ||
19 | #define CPM_CR_SBLOCK ((uint)0x03e00000) | ||
20 | #define CPM_CR_FLG ((uint)0x00010000) | ||
21 | #define CPM_CR_MCN ((uint)0x00003fc0) | ||
22 | #define CPM_CR_OPCODE ((uint)0x0000000f) | ||
23 | |||
24 | /* Device sub-block and page codes. | ||
25 | */ | ||
26 | #define CPM_CR_SCC1_SBLOCK (0x04) | ||
27 | #define CPM_CR_SCC2_SBLOCK (0x05) | ||
28 | #define CPM_CR_SCC3_SBLOCK (0x06) | ||
29 | #define CPM_CR_SCC4_SBLOCK (0x07) | ||
30 | #define CPM_CR_SMC1_SBLOCK (0x08) | ||
31 | #define CPM_CR_SMC2_SBLOCK (0x09) | ||
32 | #define CPM_CR_SPI_SBLOCK (0x0a) | ||
33 | #define CPM_CR_I2C_SBLOCK (0x0b) | ||
34 | #define CPM_CR_TIMER_SBLOCK (0x0f) | ||
35 | #define CPM_CR_RAND_SBLOCK (0x0e) | ||
36 | #define CPM_CR_FCC1_SBLOCK (0x10) | ||
37 | #define CPM_CR_FCC2_SBLOCK (0x11) | ||
38 | #define CPM_CR_FCC3_SBLOCK (0x12) | ||
39 | #define CPM_CR_IDMA1_SBLOCK (0x14) | ||
40 | #define CPM_CR_IDMA2_SBLOCK (0x15) | ||
41 | #define CPM_CR_IDMA3_SBLOCK (0x16) | ||
42 | #define CPM_CR_IDMA4_SBLOCK (0x17) | ||
43 | #define CPM_CR_MCC1_SBLOCK (0x1c) | ||
44 | |||
45 | #define CPM_CR_SCC1_PAGE (0x00) | ||
46 | #define CPM_CR_SCC2_PAGE (0x01) | ||
47 | #define CPM_CR_SCC3_PAGE (0x02) | ||
48 | #define CPM_CR_SCC4_PAGE (0x03) | ||
49 | #define CPM_CR_SMC1_PAGE (0x07) | ||
50 | #define CPM_CR_SMC2_PAGE (0x08) | ||
51 | #define CPM_CR_SPI_PAGE (0x09) | ||
52 | #define CPM_CR_I2C_PAGE (0x0a) | ||
53 | #define CPM_CR_TIMER_PAGE (0x0a) | ||
54 | #define CPM_CR_RAND_PAGE (0x0a) | ||
55 | #define CPM_CR_FCC1_PAGE (0x04) | ||
56 | #define CPM_CR_FCC2_PAGE (0x05) | ||
57 | #define CPM_CR_FCC3_PAGE (0x06) | ||
58 | #define CPM_CR_IDMA1_PAGE (0x07) | ||
59 | #define CPM_CR_IDMA2_PAGE (0x08) | ||
60 | #define CPM_CR_IDMA3_PAGE (0x09) | ||
61 | #define CPM_CR_IDMA4_PAGE (0x0a) | ||
62 | #define CPM_CR_MCC1_PAGE (0x07) | ||
63 | #define CPM_CR_MCC2_PAGE (0x08) | ||
64 | |||
65 | /* Some opcodes (there are more...later) | ||
66 | */ | ||
67 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | ||
68 | #define CPM_CR_INIT_RX ((ushort)0x0001) | ||
69 | #define CPM_CR_INIT_TX ((ushort)0x0002) | ||
70 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | ||
71 | #define CPM_CR_STOP_TX ((ushort)0x0004) | ||
72 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) | ||
73 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | ||
74 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | ||
75 | #define CPM_CR_START_IDMA ((ushort)0x0009) | ||
76 | #define CPM_CR_STOP_IDMA ((ushort)0x000b) | ||
77 | |||
78 | #define mk_cr_cmd(PG, SBC, MCN, OP) \ | ||
79 | ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) | ||
80 | |||
81 | /* Dual Port RAM addresses. The first 16K is available for almost | ||
82 | * any CPM use, so we put the BDs there. The first 128 bytes are | ||
83 | * used for SMC1 and SMC2 parameter RAM, so we start allocating | ||
84 | * BDs above that. All of this must change when we start | ||
85 | * downloading RAM microcode. | ||
86 | */ | ||
87 | #define CPM_DATAONLY_BASE ((uint)128) | ||
88 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | ||
89 | #if defined(CONFIG_8272) || defined(CONFIG_MPC8555) | ||
90 | #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) | ||
91 | #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) | ||
92 | #else | ||
93 | #define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE) | ||
94 | #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) | ||
95 | #endif | ||
96 | |||
97 | /* The number of pages of host memory we allocate for CPM. This is | ||
98 | * done early in kernel initialization to get physically contiguous | ||
99 | * pages. | ||
100 | */ | ||
101 | #define NUM_CPM_HOST_PAGES 2 | ||
102 | |||
103 | static inline long IS_DPERR(const uint offset) | ||
104 | { | ||
105 | return (uint)offset > (uint)-1000L; | ||
106 | } | ||
107 | |||
108 | /* Export the base address of the communication processor registers | ||
109 | * and dual port ram. | ||
110 | */ | ||
111 | extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ | ||
112 | extern uint cpm_dpalloc(uint size, uint align); | ||
113 | extern int cpm_dpfree(uint offset); | ||
114 | extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); | ||
115 | extern void cpm_dpdump(void); | ||
116 | extern void *cpm_dpram_addr(uint offset); | ||
117 | extern void cpm_setbrg(uint brg, uint rate); | ||
118 | extern void cpm2_fastbrg(uint brg, uint rate, int div16); | ||
119 | |||
120 | /* Buffer descriptors used by many of the CPM protocols. | ||
121 | */ | ||
122 | typedef struct cpm_buf_desc { | ||
123 | ushort cbd_sc; /* Status and Control */ | ||
124 | ushort cbd_datlen; /* Data length in buffer */ | ||
125 | uint cbd_bufaddr; /* Buffer address in host memory */ | ||
126 | } cbd_t; | ||
127 | |||
128 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | ||
129 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | ||
130 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | ||
131 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | ||
132 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | ||
133 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | ||
134 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | ||
135 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | ||
136 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | ||
137 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | ||
138 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | ||
139 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | ||
140 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | ||
141 | |||
142 | /* Function code bits, usually generic to devices. | ||
143 | */ | ||
144 | #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ | ||
145 | #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ | ||
146 | #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ | ||
147 | #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ | ||
148 | #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ | ||
149 | |||
150 | /* Parameter RAM offsets from the base. | ||
151 | */ | ||
152 | #define PROFF_SCC1 ((uint)0x8000) | ||
153 | #define PROFF_SCC2 ((uint)0x8100) | ||
154 | #define PROFF_SCC3 ((uint)0x8200) | ||
155 | #define PROFF_SCC4 ((uint)0x8300) | ||
156 | #define PROFF_FCC1 ((uint)0x8400) | ||
157 | #define PROFF_FCC2 ((uint)0x8500) | ||
158 | #define PROFF_FCC3 ((uint)0x8600) | ||
159 | #define PROFF_MCC1 ((uint)0x8700) | ||
160 | #define PROFF_SMC1_BASE ((uint)0x87fc) | ||
161 | #define PROFF_IDMA1_BASE ((uint)0x87fe) | ||
162 | #define PROFF_MCC2 ((uint)0x8800) | ||
163 | #define PROFF_SMC2_BASE ((uint)0x88fc) | ||
164 | #define PROFF_IDMA2_BASE ((uint)0x88fe) | ||
165 | #define PROFF_SPI_BASE ((uint)0x89fc) | ||
166 | #define PROFF_IDMA3_BASE ((uint)0x89fe) | ||
167 | #define PROFF_TIMERS ((uint)0x8ae0) | ||
168 | #define PROFF_REVNUM ((uint)0x8af0) | ||
169 | #define PROFF_RAND ((uint)0x8af8) | ||
170 | #define PROFF_I2C_BASE ((uint)0x8afc) | ||
171 | #define PROFF_IDMA4_BASE ((uint)0x8afe) | ||
172 | |||
173 | /* The SMCs are relocated to any of the first eight DPRAM pages. | ||
174 | * We will fix these at the first locations of DPRAM, until we | ||
175 | * get some microcode patches :-). | ||
176 | * The parameter ram space for the SMCs is fifty-some bytes, and | ||
177 | * they are required to start on a 64 byte boundary. | ||
178 | */ | ||
179 | #define PROFF_SMC1 (0) | ||
180 | #define PROFF_SMC2 (64) | ||
181 | |||
182 | |||
183 | /* Define enough so I can at least use the serial port as a UART. | ||
184 | */ | ||
185 | typedef struct smc_uart { | ||
186 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | ||
187 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | ||
188 | u_char smc_rfcr; /* Rx function code */ | ||
189 | u_char smc_tfcr; /* Tx function code */ | ||
190 | ushort smc_mrblr; /* Max receive buffer length */ | ||
191 | uint smc_rstate; /* Internal */ | ||
192 | uint smc_idp; /* Internal */ | ||
193 | ushort smc_rbptr; /* Internal */ | ||
194 | ushort smc_ibc; /* Internal */ | ||
195 | uint smc_rxtmp; /* Internal */ | ||
196 | uint smc_tstate; /* Internal */ | ||
197 | uint smc_tdp; /* Internal */ | ||
198 | ushort smc_tbptr; /* Internal */ | ||
199 | ushort smc_tbc; /* Internal */ | ||
200 | uint smc_txtmp; /* Internal */ | ||
201 | ushort smc_maxidl; /* Maximum idle characters */ | ||
202 | ushort smc_tmpidl; /* Temporary idle counter */ | ||
203 | ushort smc_brklen; /* Last received break length */ | ||
204 | ushort smc_brkec; /* rcv'd break condition counter */ | ||
205 | ushort smc_brkcr; /* xmt break count register */ | ||
206 | ushort smc_rmask; /* Temporary bit mask */ | ||
207 | uint smc_stmp; /* SDMA Temp */ | ||
208 | } smc_uart_t; | ||
209 | |||
210 | /* SMC uart mode register (Internal memory map). | ||
211 | */ | ||
212 | #define SMCMR_REN ((ushort)0x0001) | ||
213 | #define SMCMR_TEN ((ushort)0x0002) | ||
214 | #define SMCMR_DM ((ushort)0x000c) | ||
215 | #define SMCMR_SM_GCI ((ushort)0x0000) | ||
216 | #define SMCMR_SM_UART ((ushort)0x0020) | ||
217 | #define SMCMR_SM_TRANS ((ushort)0x0030) | ||
218 | #define SMCMR_SM_MASK ((ushort)0x0030) | ||
219 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | ||
220 | #define SMCMR_REVD SMCMR_PM_EVEN | ||
221 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | ||
222 | #define SMCMR_BS SMCMR_PEN | ||
223 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | ||
224 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | ||
225 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | ||
226 | |||
227 | /* SMC Event and Mask register. | ||
228 | */ | ||
229 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | ||
230 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | ||
231 | #define SMCM_TXE ((unsigned char)0x10) | ||
232 | #define SMCM_BSY ((unsigned char)0x04) | ||
233 | #define SMCM_TX ((unsigned char)0x02) | ||
234 | #define SMCM_RX ((unsigned char)0x01) | ||
235 | |||
236 | /* Baud rate generators. | ||
237 | */ | ||
238 | #define CPM_BRG_RST ((uint)0x00020000) | ||
239 | #define CPM_BRG_EN ((uint)0x00010000) | ||
240 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | ||
241 | #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) | ||
242 | #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) | ||
243 | #define CPM_BRG_ATB ((uint)0x00002000) | ||
244 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | ||
245 | #define CPM_BRG_DIV16 ((uint)0x00000001) | ||
246 | |||
247 | /* SCCs. | ||
248 | */ | ||
249 | #define SCC_GSMRH_IRP ((uint)0x00040000) | ||
250 | #define SCC_GSMRH_GDE ((uint)0x00010000) | ||
251 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | ||
252 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | ||
253 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | ||
254 | #define SCC_GSMRH_REVD ((uint)0x00002000) | ||
255 | #define SCC_GSMRH_TRX ((uint)0x00001000) | ||
256 | #define SCC_GSMRH_TTX ((uint)0x00000800) | ||
257 | #define SCC_GSMRH_CDP ((uint)0x00000400) | ||
258 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | ||
259 | #define SCC_GSMRH_CDS ((uint)0x00000100) | ||
260 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | ||
261 | #define SCC_GSMRH_TFL ((uint)0x00000040) | ||
262 | #define SCC_GSMRH_RFW ((uint)0x00000020) | ||
263 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | ||
264 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | ||
265 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | ||
266 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | ||
267 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | ||
268 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | ||
269 | |||
270 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | ||
271 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | ||
272 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | ||
273 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | ||
274 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | ||
275 | #define SCC_GSMRL_TCI ((uint)0x10000000) | ||
276 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | ||
277 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | ||
278 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | ||
279 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | ||
280 | #define SCC_GSMRL_RINV ((uint)0x02000000) | ||
281 | #define SCC_GSMRL_TINV ((uint)0x01000000) | ||
282 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | ||
283 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | ||
284 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | ||
285 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | ||
286 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | ||
287 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | ||
288 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | ||
289 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | ||
290 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | ||
291 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | ||
292 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | ||
293 | #define SCC_GSMRL_TEND ((uint)0x00040000) | ||
294 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | ||
295 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | ||
296 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | ||
297 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | ||
298 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | ||
299 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | ||
300 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | ||
301 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | ||
302 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | ||
303 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | ||
304 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | ||
305 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | ||
306 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | ||
307 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | ||
308 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | ||
309 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | ||
310 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | ||
311 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | ||
312 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | ||
313 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | ||
314 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | ||
315 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | ||
316 | #define SCC_GSMRL_ENR ((uint)0x00000020) | ||
317 | #define SCC_GSMRL_ENT ((uint)0x00000010) | ||
318 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | ||
319 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | ||
320 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | ||
321 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | ||
322 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | ||
323 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | ||
324 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | ||
325 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | ||
326 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | ||
327 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | ||
328 | |||
329 | #define SCC_TODR_TOD ((ushort)0x8000) | ||
330 | |||
331 | /* SCC Event and Mask register. | ||
332 | */ | ||
333 | #define SCCM_TXE ((unsigned char)0x10) | ||
334 | #define SCCM_BSY ((unsigned char)0x04) | ||
335 | #define SCCM_TX ((unsigned char)0x02) | ||
336 | #define SCCM_RX ((unsigned char)0x01) | ||
337 | |||
338 | typedef struct scc_param { | ||
339 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | ||
340 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | ||
341 | u_char scc_rfcr; /* Rx function code */ | ||
342 | u_char scc_tfcr; /* Tx function code */ | ||
343 | ushort scc_mrblr; /* Max receive buffer length */ | ||
344 | uint scc_rstate; /* Internal */ | ||
345 | uint scc_idp; /* Internal */ | ||
346 | ushort scc_rbptr; /* Internal */ | ||
347 | ushort scc_ibc; /* Internal */ | ||
348 | uint scc_rxtmp; /* Internal */ | ||
349 | uint scc_tstate; /* Internal */ | ||
350 | uint scc_tdp; /* Internal */ | ||
351 | ushort scc_tbptr; /* Internal */ | ||
352 | ushort scc_tbc; /* Internal */ | ||
353 | uint scc_txtmp; /* Internal */ | ||
354 | uint scc_rcrc; /* Internal */ | ||
355 | uint scc_tcrc; /* Internal */ | ||
356 | } sccp_t; | ||
357 | |||
358 | /* CPM Ethernet through SCC1. | ||
359 | */ | ||
360 | typedef struct scc_enet { | ||
361 | sccp_t sen_genscc; | ||
362 | uint sen_cpres; /* Preset CRC */ | ||
363 | uint sen_cmask; /* Constant mask for CRC */ | ||
364 | uint sen_crcec; /* CRC Error counter */ | ||
365 | uint sen_alec; /* alignment error counter */ | ||
366 | uint sen_disfc; /* discard frame counter */ | ||
367 | ushort sen_pads; /* Tx short frame pad character */ | ||
368 | ushort sen_retlim; /* Retry limit threshold */ | ||
369 | ushort sen_retcnt; /* Retry limit counter */ | ||
370 | ushort sen_maxflr; /* maximum frame length register */ | ||
371 | ushort sen_minflr; /* minimum frame length register */ | ||
372 | ushort sen_maxd1; /* maximum DMA1 length */ | ||
373 | ushort sen_maxd2; /* maximum DMA2 length */ | ||
374 | ushort sen_maxd; /* Rx max DMA */ | ||
375 | ushort sen_dmacnt; /* Rx DMA counter */ | ||
376 | ushort sen_maxb; /* Max BD byte count */ | ||
377 | ushort sen_gaddr1; /* Group address filter */ | ||
378 | ushort sen_gaddr2; | ||
379 | ushort sen_gaddr3; | ||
380 | ushort sen_gaddr4; | ||
381 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | ||
382 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | ||
383 | uint sen_tbuf0rba; /* Internal */ | ||
384 | uint sen_tbuf0crc; /* Internal */ | ||
385 | ushort sen_tbuf0bcnt; /* Internal */ | ||
386 | ushort sen_paddrh; /* physical address (MSB) */ | ||
387 | ushort sen_paddrm; | ||
388 | ushort sen_paddrl; /* physical address (LSB) */ | ||
389 | ushort sen_pper; /* persistence */ | ||
390 | ushort sen_rfbdptr; /* Rx first BD pointer */ | ||
391 | ushort sen_tfbdptr; /* Tx first BD pointer */ | ||
392 | ushort sen_tlbdptr; /* Tx last BD pointer */ | ||
393 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | ||
394 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | ||
395 | uint sen_tbuf1rba; /* Internal */ | ||
396 | uint sen_tbuf1crc; /* Internal */ | ||
397 | ushort sen_tbuf1bcnt; /* Internal */ | ||
398 | ushort sen_txlen; /* Tx Frame length counter */ | ||
399 | ushort sen_iaddr1; /* Individual address filter */ | ||
400 | ushort sen_iaddr2; | ||
401 | ushort sen_iaddr3; | ||
402 | ushort sen_iaddr4; | ||
403 | ushort sen_boffcnt; /* Backoff counter */ | ||
404 | |||
405 | /* NOTE: Some versions of the manual have the following items | ||
406 | * incorrectly documented. Below is the proper order. | ||
407 | */ | ||
408 | ushort sen_taddrh; /* temp address (MSB) */ | ||
409 | ushort sen_taddrm; | ||
410 | ushort sen_taddrl; /* temp address (LSB) */ | ||
411 | } scc_enet_t; | ||
412 | |||
413 | |||
414 | /* SCC Event register as used by Ethernet. | ||
415 | */ | ||
416 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
417 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
418 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
419 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | ||
420 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
421 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
422 | |||
423 | /* SCC Mode Register (PSMR) as used by Ethernet. | ||
424 | */ | ||
425 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | ||
426 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | ||
427 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | ||
428 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | ||
429 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | ||
430 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | ||
431 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | ||
432 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | ||
433 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | ||
434 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | ||
435 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | ||
436 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | ||
437 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | ||
438 | |||
439 | /* Buffer descriptor control/status used by Ethernet receive. | ||
440 | * Common to SCC and FCC. | ||
441 | */ | ||
442 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | ||
443 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | ||
444 | #define BD_ENET_RX_INTR ((ushort)0x1000) | ||
445 | #define BD_ENET_RX_LAST ((ushort)0x0800) | ||
446 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | ||
447 | #define BD_ENET_RX_MISS ((ushort)0x0100) | ||
448 | #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ | ||
449 | #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ | ||
450 | #define BD_ENET_RX_LG ((ushort)0x0020) | ||
451 | #define BD_ENET_RX_NO ((ushort)0x0010) | ||
452 | #define BD_ENET_RX_SH ((ushort)0x0008) | ||
453 | #define BD_ENET_RX_CR ((ushort)0x0004) | ||
454 | #define BD_ENET_RX_OV ((ushort)0x0002) | ||
455 | #define BD_ENET_RX_CL ((ushort)0x0001) | ||
456 | #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ | ||
457 | |||
458 | /* Buffer descriptor control/status used by Ethernet transmit. | ||
459 | * Common to SCC and FCC. | ||
460 | */ | ||
461 | #define BD_ENET_TX_READY ((ushort)0x8000) | ||
462 | #define BD_ENET_TX_PAD ((ushort)0x4000) | ||
463 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | ||
464 | #define BD_ENET_TX_INTR ((ushort)0x1000) | ||
465 | #define BD_ENET_TX_LAST ((ushort)0x0800) | ||
466 | #define BD_ENET_TX_TC ((ushort)0x0400) | ||
467 | #define BD_ENET_TX_DEF ((ushort)0x0200) | ||
468 | #define BD_ENET_TX_HB ((ushort)0x0100) | ||
469 | #define BD_ENET_TX_LC ((ushort)0x0080) | ||
470 | #define BD_ENET_TX_RL ((ushort)0x0040) | ||
471 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | ||
472 | #define BD_ENET_TX_UN ((ushort)0x0002) | ||
473 | #define BD_ENET_TX_CSL ((ushort)0x0001) | ||
474 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | ||
475 | |||
476 | /* SCC as UART | ||
477 | */ | ||
478 | typedef struct scc_uart { | ||
479 | sccp_t scc_genscc; | ||
480 | uint scc_res1; /* Reserved */ | ||
481 | uint scc_res2; /* Reserved */ | ||
482 | ushort scc_maxidl; /* Maximum idle chars */ | ||
483 | ushort scc_idlc; /* temp idle counter */ | ||
484 | ushort scc_brkcr; /* Break count register */ | ||
485 | ushort scc_parec; /* receive parity error counter */ | ||
486 | ushort scc_frmec; /* receive framing error counter */ | ||
487 | ushort scc_nosec; /* receive noise counter */ | ||
488 | ushort scc_brkec; /* receive break condition counter */ | ||
489 | ushort scc_brkln; /* last received break length */ | ||
490 | ushort scc_uaddr1; /* UART address character 1 */ | ||
491 | ushort scc_uaddr2; /* UART address character 2 */ | ||
492 | ushort scc_rtemp; /* Temp storage */ | ||
493 | ushort scc_toseq; /* Transmit out of sequence char */ | ||
494 | ushort scc_char1; /* control character 1 */ | ||
495 | ushort scc_char2; /* control character 2 */ | ||
496 | ushort scc_char3; /* control character 3 */ | ||
497 | ushort scc_char4; /* control character 4 */ | ||
498 | ushort scc_char5; /* control character 5 */ | ||
499 | ushort scc_char6; /* control character 6 */ | ||
500 | ushort scc_char7; /* control character 7 */ | ||
501 | ushort scc_char8; /* control character 8 */ | ||
502 | ushort scc_rccm; /* receive control character mask */ | ||
503 | ushort scc_rccr; /* receive control character register */ | ||
504 | ushort scc_rlbc; /* receive last break character */ | ||
505 | } scc_uart_t; | ||
506 | |||
507 | /* SCC Event and Mask registers when it is used as a UART. | ||
508 | */ | ||
509 | #define UART_SCCM_GLR ((ushort)0x1000) | ||
510 | #define UART_SCCM_GLT ((ushort)0x0800) | ||
511 | #define UART_SCCM_AB ((ushort)0x0200) | ||
512 | #define UART_SCCM_IDL ((ushort)0x0100) | ||
513 | #define UART_SCCM_GRA ((ushort)0x0080) | ||
514 | #define UART_SCCM_BRKE ((ushort)0x0040) | ||
515 | #define UART_SCCM_BRKS ((ushort)0x0020) | ||
516 | #define UART_SCCM_CCR ((ushort)0x0008) | ||
517 | #define UART_SCCM_BSY ((ushort)0x0004) | ||
518 | #define UART_SCCM_TX ((ushort)0x0002) | ||
519 | #define UART_SCCM_RX ((ushort)0x0001) | ||
520 | |||
521 | /* The SCC PSMR when used as a UART. | ||
522 | */ | ||
523 | #define SCU_PSMR_FLC ((ushort)0x8000) | ||
524 | #define SCU_PSMR_SL ((ushort)0x4000) | ||
525 | #define SCU_PSMR_CL ((ushort)0x3000) | ||
526 | #define SCU_PSMR_UM ((ushort)0x0c00) | ||
527 | #define SCU_PSMR_FRZ ((ushort)0x0200) | ||
528 | #define SCU_PSMR_RZS ((ushort)0x0100) | ||
529 | #define SCU_PSMR_SYN ((ushort)0x0080) | ||
530 | #define SCU_PSMR_DRT ((ushort)0x0040) | ||
531 | #define SCU_PSMR_PEN ((ushort)0x0010) | ||
532 | #define SCU_PSMR_RPM ((ushort)0x000c) | ||
533 | #define SCU_PSMR_REVP ((ushort)0x0008) | ||
534 | #define SCU_PSMR_TPM ((ushort)0x0003) | ||
535 | #define SCU_PSMR_TEVP ((ushort)0x0002) | ||
536 | |||
537 | /* CPM Transparent mode SCC. | ||
538 | */ | ||
539 | typedef struct scc_trans { | ||
540 | sccp_t st_genscc; | ||
541 | uint st_cpres; /* Preset CRC */ | ||
542 | uint st_cmask; /* Constant mask for CRC */ | ||
543 | } scc_trans_t; | ||
544 | |||
545 | #define BD_SCC_TX_LAST ((ushort)0x0800) | ||
546 | |||
547 | /* How about some FCCs..... | ||
548 | */ | ||
549 | #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) | ||
550 | #define FCC_GFMR_DIAG_LE ((uint)0x40000000) | ||
551 | #define FCC_GFMR_DIAG_AE ((uint)0x80000000) | ||
552 | #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) | ||
553 | #define FCC_GFMR_TCI ((uint)0x20000000) | ||
554 | #define FCC_GFMR_TRX ((uint)0x10000000) | ||
555 | #define FCC_GFMR_TTX ((uint)0x08000000) | ||
556 | #define FCC_GFMR_TTX ((uint)0x08000000) | ||
557 | #define FCC_GFMR_CDP ((uint)0x04000000) | ||
558 | #define FCC_GFMR_CTSP ((uint)0x02000000) | ||
559 | #define FCC_GFMR_CDS ((uint)0x01000000) | ||
560 | #define FCC_GFMR_CTSS ((uint)0x00800000) | ||
561 | #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) | ||
562 | #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) | ||
563 | #define FCC_GFMR_SYNL_8 ((uint)0x00008000) | ||
564 | #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) | ||
565 | #define FCC_GFMR_RTSM ((uint)0x00002000) | ||
566 | #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) | ||
567 | #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) | ||
568 | #define FCC_GFMR_REVD ((uint)0x00000400) | ||
569 | #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) | ||
570 | #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) | ||
571 | #define FCC_GFMR_TCRC_16 ((uint)0x00000000) | ||
572 | #define FCC_GFMR_TCRC_32 ((uint)0x00000080) | ||
573 | #define FCC_GFMR_ENR ((uint)0x00000020) | ||
574 | #define FCC_GFMR_ENT ((uint)0x00000010) | ||
575 | #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) | ||
576 | #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) | ||
577 | #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) | ||
578 | |||
579 | /* Generic FCC parameter ram. | ||
580 | */ | ||
581 | typedef struct fcc_param { | ||
582 | ushort fcc_riptr; /* Rx Internal temp pointer */ | ||
583 | ushort fcc_tiptr; /* Tx Internal temp pointer */ | ||
584 | ushort fcc_res1; | ||
585 | ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ | ||
586 | uint fcc_rstate; /* Upper byte is Func code, must be set */ | ||
587 | uint fcc_rbase; /* Receive BD base */ | ||
588 | ushort fcc_rbdstat; /* RxBD status */ | ||
589 | ushort fcc_rbdlen; /* RxBD down counter */ | ||
590 | uint fcc_rdptr; /* RxBD internal data pointer */ | ||
591 | uint fcc_tstate; /* Upper byte is Func code, must be set */ | ||
592 | uint fcc_tbase; /* Transmit BD base */ | ||
593 | ushort fcc_tbdstat; /* TxBD status */ | ||
594 | ushort fcc_tbdlen; /* TxBD down counter */ | ||
595 | uint fcc_tdptr; /* TxBD internal data pointer */ | ||
596 | uint fcc_rbptr; /* Rx BD Internal buf pointer */ | ||
597 | uint fcc_tbptr; /* Tx BD Internal buf pointer */ | ||
598 | uint fcc_rcrc; /* Rx temp CRC */ | ||
599 | uint fcc_res2; | ||
600 | uint fcc_tcrc; /* Tx temp CRC */ | ||
601 | } fccp_t; | ||
602 | |||
603 | |||
604 | /* Ethernet controller through FCC. | ||
605 | */ | ||
606 | typedef struct fcc_enet { | ||
607 | fccp_t fen_genfcc; | ||
608 | uint fen_statbuf; /* Internal status buffer */ | ||
609 | uint fen_camptr; /* CAM address */ | ||
610 | uint fen_cmask; /* Constant mask for CRC */ | ||
611 | uint fen_cpres; /* Preset CRC */ | ||
612 | uint fen_crcec; /* CRC Error counter */ | ||
613 | uint fen_alec; /* alignment error counter */ | ||
614 | uint fen_disfc; /* discard frame counter */ | ||
615 | ushort fen_retlim; /* Retry limit */ | ||
616 | ushort fen_retcnt; /* Retry counter */ | ||
617 | ushort fen_pper; /* Persistence */ | ||
618 | ushort fen_boffcnt; /* backoff counter */ | ||
619 | uint fen_gaddrh; /* Group address filter, high 32-bits */ | ||
620 | uint fen_gaddrl; /* Group address filter, low 32-bits */ | ||
621 | ushort fen_tfcstat; /* out of sequence TxBD */ | ||
622 | ushort fen_tfclen; | ||
623 | uint fen_tfcptr; | ||
624 | ushort fen_mflr; /* Maximum frame length (1518) */ | ||
625 | ushort fen_paddrh; /* MAC address */ | ||
626 | ushort fen_paddrm; | ||
627 | ushort fen_paddrl; | ||
628 | ushort fen_ibdcount; /* Internal BD counter */ | ||
629 | ushort fen_ibdstart; /* Internal BD start pointer */ | ||
630 | ushort fen_ibdend; /* Internal BD end pointer */ | ||
631 | ushort fen_txlen; /* Internal Tx frame length counter */ | ||
632 | uint fen_ibdbase[8]; /* Internal use */ | ||
633 | uint fen_iaddrh; /* Individual address filter */ | ||
634 | uint fen_iaddrl; | ||
635 | ushort fen_minflr; /* Minimum frame length (64) */ | ||
636 | ushort fen_taddrh; /* Filter transfer MAC address */ | ||
637 | ushort fen_taddrm; | ||
638 | ushort fen_taddrl; | ||
639 | ushort fen_padptr; /* Pointer to pad byte buffer */ | ||
640 | ushort fen_cftype; /* control frame type */ | ||
641 | ushort fen_cfrange; /* control frame range */ | ||
642 | ushort fen_maxb; /* maximum BD count */ | ||
643 | ushort fen_maxd1; /* Max DMA1 length (1520) */ | ||
644 | ushort fen_maxd2; /* Max DMA2 length (1520) */ | ||
645 | ushort fen_maxd; /* internal max DMA count */ | ||
646 | ushort fen_dmacnt; /* internal DMA counter */ | ||
647 | uint fen_octc; /* Total octect counter */ | ||
648 | uint fen_colc; /* Total collision counter */ | ||
649 | uint fen_broc; /* Total broadcast packet counter */ | ||
650 | uint fen_mulc; /* Total multicast packet count */ | ||
651 | uint fen_uspc; /* Total packets < 64 bytes */ | ||
652 | uint fen_frgc; /* Total packets < 64 bytes with errors */ | ||
653 | uint fen_ospc; /* Total packets > 1518 */ | ||
654 | uint fen_jbrc; /* Total packets > 1518 with errors */ | ||
655 | uint fen_p64c; /* Total packets == 64 bytes */ | ||
656 | uint fen_p65c; /* Total packets 64 < bytes <= 127 */ | ||
657 | uint fen_p128c; /* Total packets 127 < bytes <= 255 */ | ||
658 | uint fen_p256c; /* Total packets 256 < bytes <= 511 */ | ||
659 | uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ | ||
660 | uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ | ||
661 | uint fen_cambuf; /* Internal CAM buffer poiner */ | ||
662 | ushort fen_rfthr; /* Received frames threshold */ | ||
663 | ushort fen_rfcnt; /* Received frames count */ | ||
664 | } fcc_enet_t; | ||
665 | |||
666 | /* FCC Event/Mask register as used by Ethernet. | ||
667 | */ | ||
668 | #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
669 | #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ | ||
670 | #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ | ||
671 | #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
672 | #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
673 | #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ | ||
674 | #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
675 | #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
676 | |||
677 | /* FCC Mode Register (FPSMR) as used by Ethernet. | ||
678 | */ | ||
679 | #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ | ||
680 | #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ | ||
681 | #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ | ||
682 | #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ | ||
683 | #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ | ||
684 | #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ | ||
685 | #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ | ||
686 | #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ | ||
687 | #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ | ||
688 | #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ | ||
689 | #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ | ||
690 | #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ | ||
691 | #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ | ||
692 | |||
693 | /* IIC parameter RAM. | ||
694 | */ | ||
695 | typedef struct iic { | ||
696 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | ||
697 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | ||
698 | u_char iic_rfcr; /* Rx function code */ | ||
699 | u_char iic_tfcr; /* Tx function code */ | ||
700 | ushort iic_mrblr; /* Max receive buffer length */ | ||
701 | uint iic_rstate; /* Internal */ | ||
702 | uint iic_rdp; /* Internal */ | ||
703 | ushort iic_rbptr; /* Internal */ | ||
704 | ushort iic_rbc; /* Internal */ | ||
705 | uint iic_rxtmp; /* Internal */ | ||
706 | uint iic_tstate; /* Internal */ | ||
707 | uint iic_tdp; /* Internal */ | ||
708 | ushort iic_tbptr; /* Internal */ | ||
709 | ushort iic_tbc; /* Internal */ | ||
710 | uint iic_txtmp; /* Internal */ | ||
711 | } iic_t; | ||
712 | |||
713 | /* SPI parameter RAM. | ||
714 | */ | ||
715 | typedef struct spi { | ||
716 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | ||
717 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | ||
718 | u_char spi_rfcr; /* Rx function code */ | ||
719 | u_char spi_tfcr; /* Tx function code */ | ||
720 | ushort spi_mrblr; /* Max receive buffer length */ | ||
721 | uint spi_rstate; /* Internal */ | ||
722 | uint spi_rdp; /* Internal */ | ||
723 | ushort spi_rbptr; /* Internal */ | ||
724 | ushort spi_rbc; /* Internal */ | ||
725 | uint spi_rxtmp; /* Internal */ | ||
726 | uint spi_tstate; /* Internal */ | ||
727 | uint spi_tdp; /* Internal */ | ||
728 | ushort spi_tbptr; /* Internal */ | ||
729 | ushort spi_tbc; /* Internal */ | ||
730 | uint spi_txtmp; /* Internal */ | ||
731 | uint spi_res; /* Tx temp. */ | ||
732 | uint spi_res1[4]; /* SDMA temp. */ | ||
733 | } spi_t; | ||
734 | |||
735 | /* SPI Mode register. | ||
736 | */ | ||
737 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | ||
738 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | ||
739 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | ||
740 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | ||
741 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | ||
742 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | ||
743 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | ||
744 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | ||
745 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | ||
746 | |||
747 | #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) | ||
748 | #define SPMODE_PM(x) ((x) &0xF) | ||
749 | |||
750 | #define SPI_EB ((u_char)0x10) /* big endian byte order */ | ||
751 | |||
752 | #define BD_IIC_START ((ushort)0x0400) | ||
753 | |||
754 | /* IDMA parameter RAM | ||
755 | */ | ||
756 | typedef struct idma { | ||
757 | ushort ibase; /* IDMA buffer descriptor table base address */ | ||
758 | ushort dcm; /* DMA channel mode */ | ||
759 | ushort ibdptr; /* IDMA current buffer descriptor pointer */ | ||
760 | ushort dpr_buf; /* IDMA transfer buffer base address */ | ||
761 | ushort buf_inv; /* internal buffer inventory */ | ||
762 | ushort ss_max; /* steady-state maximum transfer size */ | ||
763 | ushort dpr_in_ptr; /* write pointer inside the internal buffer */ | ||
764 | ushort sts; /* source transfer size */ | ||
765 | ushort dpr_out_ptr; /* read pointer inside the internal buffer */ | ||
766 | ushort seob; /* source end of burst */ | ||
767 | ushort deob; /* destination end of burst */ | ||
768 | ushort dts; /* destination transfer size */ | ||
769 | ushort ret_add; /* return address when working in ERM=1 mode */ | ||
770 | ushort res0; /* reserved */ | ||
771 | uint bd_cnt; /* internal byte count */ | ||
772 | uint s_ptr; /* source internal data pointer */ | ||
773 | uint d_ptr; /* destination internal data pointer */ | ||
774 | uint istate; /* internal state */ | ||
775 | u_char res1[20]; /* pad to 64-byte length */ | ||
776 | } idma_t; | ||
777 | |||
778 | /* DMA channel mode bit fields | ||
779 | */ | ||
780 | #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ | ||
781 | #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ | ||
782 | #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ | ||
783 | #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ | ||
784 | #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ | ||
785 | #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ | ||
786 | #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ | ||
787 | #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ | ||
788 | #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ | ||
789 | #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ | ||
790 | #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ | ||
791 | #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ | ||
792 | #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ | ||
793 | #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ | ||
794 | #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ | ||
795 | #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ | ||
796 | #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ | ||
797 | #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ | ||
798 | |||
799 | /* IDMA Buffer Descriptors | ||
800 | */ | ||
801 | typedef struct idma_bd { | ||
802 | uint flags; | ||
803 | uint len; /* data length */ | ||
804 | uint src; /* source data buffer pointer */ | ||
805 | uint dst; /* destination data buffer pointer */ | ||
806 | } idma_bd_t; | ||
807 | |||
808 | /* IDMA buffer descriptor flag bit fields | ||
809 | */ | ||
810 | #define IDMA_BD_V ((uint)0x80000000) /* valid */ | ||
811 | #define IDMA_BD_W ((uint)0x20000000) /* wrap */ | ||
812 | #define IDMA_BD_I ((uint)0x10000000) /* interrupt */ | ||
813 | #define IDMA_BD_L ((uint)0x08000000) /* last */ | ||
814 | #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ | ||
815 | #define IDMA_BD_SDN ((uint)0x00400000) /* source done */ | ||
816 | #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ | ||
817 | #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ | ||
818 | #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ | ||
819 | #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ | ||
820 | #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ | ||
821 | #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ | ||
822 | #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ | ||
823 | #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ | ||
824 | #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ | ||
825 | |||
826 | /* per-channel IDMA registers | ||
827 | */ | ||
828 | typedef struct im_idma { | ||
829 | u_char idsr; /* IDMAn event status register */ | ||
830 | u_char res0[3]; | ||
831 | u_char idmr; /* IDMAn event mask register */ | ||
832 | u_char res1[3]; | ||
833 | } im_idma_t; | ||
834 | |||
835 | /* IDMA event register bit fields | ||
836 | */ | ||
837 | #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ | ||
838 | #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ | ||
839 | #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ | ||
840 | #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ | ||
841 | |||
842 | /* RISC Controller Configuration Register (RCCR) bit fields | ||
843 | */ | ||
844 | #define RCCR_TIME ((uint)0x80000000) /* timer enable */ | ||
845 | #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ | ||
846 | #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ | ||
847 | #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ | ||
848 | #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ | ||
849 | #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ | ||
850 | #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ | ||
851 | #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ | ||
852 | #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ | ||
853 | #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ | ||
854 | #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ | ||
855 | #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ | ||
856 | #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ | ||
857 | #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ | ||
858 | #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ | ||
859 | #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ | ||
860 | #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ | ||
861 | #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ | ||
862 | #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ | ||
863 | #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ | ||
864 | #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ | ||
865 | #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ | ||
866 | #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ | ||
867 | #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ | ||
868 | #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ | ||
869 | #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ | ||
870 | #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ | ||
871 | #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ | ||
872 | #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ | ||
873 | #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ | ||
874 | #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ | ||
875 | #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ | ||
876 | #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ | ||
877 | #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ | ||
878 | #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ | ||
879 | #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ | ||
880 | #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ | ||
881 | #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ | ||
882 | |||
883 | /*----------------------------------------------------------------------- | ||
884 | * CMXFCR - CMX FCC Clock Route Register | ||
885 | */ | ||
886 | #define CMXFCR_FC1 0x40000000 /* FCC1 connection */ | ||
887 | #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ | ||
888 | #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ | ||
889 | #define CMXFCR_FC2 0x00400000 /* FCC2 connection */ | ||
890 | #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ | ||
891 | #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ | ||
892 | #define CMXFCR_FC3 0x00004000 /* FCC3 connection */ | ||
893 | #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ | ||
894 | #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ | ||
895 | |||
896 | #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ | ||
897 | #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ | ||
898 | #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ | ||
899 | #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ | ||
900 | #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ | ||
901 | #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ | ||
902 | #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ | ||
903 | #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ | ||
904 | |||
905 | #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ | ||
906 | #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ | ||
907 | #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ | ||
908 | #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ | ||
909 | #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ | ||
910 | #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ | ||
911 | #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ | ||
912 | #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ | ||
913 | |||
914 | #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ | ||
915 | #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ | ||
916 | #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ | ||
917 | #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ | ||
918 | #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ | ||
919 | #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ | ||
920 | #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ | ||
921 | #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ | ||
922 | |||
923 | #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ | ||
924 | #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ | ||
925 | #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ | ||
926 | #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ | ||
927 | #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ | ||
928 | #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ | ||
929 | #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ | ||
930 | #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ | ||
931 | |||
932 | #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ | ||
933 | #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ | ||
934 | #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ | ||
935 | #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ | ||
936 | #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ | ||
937 | #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ | ||
938 | #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ | ||
939 | #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ | ||
940 | |||
941 | #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ | ||
942 | #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ | ||
943 | #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ | ||
944 | #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ | ||
945 | #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ | ||
946 | #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ | ||
947 | #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ | ||
948 | #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ | ||
949 | |||
950 | /*----------------------------------------------------------------------- | ||
951 | * CMXSCR - CMX SCC Clock Route Register | ||
952 | */ | ||
953 | #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ | ||
954 | #define CMXSCR_SC1 0x40000000 /* SCC1 connection */ | ||
955 | #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ | ||
956 | #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ | ||
957 | #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ | ||
958 | #define CMXSCR_SC2 0x00400000 /* SCC2 connection */ | ||
959 | #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ | ||
960 | #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ | ||
961 | #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ | ||
962 | #define CMXSCR_SC3 0x00004000 /* SCC3 connection */ | ||
963 | #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ | ||
964 | #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ | ||
965 | #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ | ||
966 | #define CMXSCR_SC4 0x00000040 /* SCC4 connection */ | ||
967 | #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ | ||
968 | #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ | ||
969 | |||
970 | #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ | ||
971 | #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ | ||
972 | #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ | ||
973 | #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ | ||
974 | #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ | ||
975 | #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ | ||
976 | #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ | ||
977 | #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ | ||
978 | |||
979 | #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ | ||
980 | #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ | ||
981 | #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ | ||
982 | #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ | ||
983 | #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ | ||
984 | #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ | ||
985 | #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ | ||
986 | #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ | ||
987 | |||
988 | #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ | ||
989 | #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ | ||
990 | #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ | ||
991 | #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ | ||
992 | #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ | ||
993 | #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ | ||
994 | #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ | ||
995 | #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ | ||
996 | |||
997 | #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ | ||
998 | #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ | ||
999 | #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ | ||
1000 | #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ | ||
1001 | #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ | ||
1002 | #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ | ||
1003 | #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ | ||
1004 | #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ | ||
1005 | |||
1006 | #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ | ||
1007 | #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ | ||
1008 | #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ | ||
1009 | #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ | ||
1010 | #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ | ||
1011 | #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ | ||
1012 | #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ | ||
1013 | #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ | ||
1014 | |||
1015 | #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ | ||
1016 | #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ | ||
1017 | #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ | ||
1018 | #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ | ||
1019 | #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ | ||
1020 | #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ | ||
1021 | #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ | ||
1022 | #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ | ||
1023 | |||
1024 | #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ | ||
1025 | #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ | ||
1026 | #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ | ||
1027 | #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ | ||
1028 | #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ | ||
1029 | #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ | ||
1030 | #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ | ||
1031 | #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ | ||
1032 | |||
1033 | #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ | ||
1034 | #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ | ||
1035 | #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ | ||
1036 | #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ | ||
1037 | #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ | ||
1038 | #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ | ||
1039 | #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ | ||
1040 | #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ | ||
1041 | |||
1042 | #endif /* __CPM2__ */ | ||
1043 | #endif /* __KERNEL__ */ | ||
1044 | |||
1045 | |||
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h new file mode 100644 index 000000000000..22de04fe1b4c --- /dev/null +++ b/include/asm-ppc/cputable.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/cputable.h | ||
3 | * | ||
4 | * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_PPC_CPUTABLE_H | ||
13 | #define __ASM_PPC_CPUTABLE_H | ||
14 | |||
15 | /* Exposed to userland CPU features */ | ||
16 | #define PPC_FEATURE_32 0x80000000 | ||
17 | #define PPC_FEATURE_64 0x40000000 | ||
18 | #define PPC_FEATURE_601_INSTR 0x20000000 | ||
19 | #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 | ||
20 | #define PPC_FEATURE_HAS_FPU 0x08000000 | ||
21 | #define PPC_FEATURE_HAS_MMU 0x04000000 | ||
22 | #define PPC_FEATURE_HAS_4xxMAC 0x02000000 | ||
23 | #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 | ||
24 | #define PPC_FEATURE_HAS_SPE 0x00800000 | ||
25 | #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 | ||
26 | #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 | ||
27 | |||
28 | #ifdef __KERNEL__ | ||
29 | |||
30 | #ifndef __ASSEMBLY__ | ||
31 | |||
32 | /* This structure can grow, it's real size is used by head.S code | ||
33 | * via the mkdefs mecanism. | ||
34 | */ | ||
35 | struct cpu_spec; | ||
36 | |||
37 | typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec); | ||
38 | |||
39 | struct cpu_spec { | ||
40 | /* CPU is matched via (PVR & pvr_mask) == pvr_value */ | ||
41 | unsigned int pvr_mask; | ||
42 | unsigned int pvr_value; | ||
43 | |||
44 | char *cpu_name; | ||
45 | unsigned int cpu_features; /* Kernel features */ | ||
46 | unsigned int cpu_user_features; /* Userland features */ | ||
47 | |||
48 | /* cache line sizes */ | ||
49 | unsigned int icache_bsize; | ||
50 | unsigned int dcache_bsize; | ||
51 | |||
52 | /* number of performance monitor counters */ | ||
53 | unsigned int num_pmcs; | ||
54 | |||
55 | /* this is called to initialize various CPU bits like L1 cache, | ||
56 | * BHT, SPD, etc... from head.S before branching to identify_machine | ||
57 | */ | ||
58 | cpu_setup_t cpu_setup; | ||
59 | }; | ||
60 | |||
61 | extern struct cpu_spec cpu_specs[]; | ||
62 | extern struct cpu_spec *cur_cpu_spec[]; | ||
63 | |||
64 | static inline unsigned int cpu_has_feature(unsigned int feature) | ||
65 | { | ||
66 | return cur_cpu_spec[0]->cpu_features & feature; | ||
67 | } | ||
68 | |||
69 | #endif /* __ASSEMBLY__ */ | ||
70 | |||
71 | /* CPU kernel features */ | ||
72 | #define CPU_FTR_SPLIT_ID_CACHE 0x00000001 | ||
73 | #define CPU_FTR_L2CR 0x00000002 | ||
74 | #define CPU_FTR_SPEC7450 0x00000004 | ||
75 | #define CPU_FTR_ALTIVEC 0x00000008 | ||
76 | #define CPU_FTR_TAU 0x00000010 | ||
77 | #define CPU_FTR_CAN_DOZE 0x00000020 | ||
78 | #define CPU_FTR_USE_TB 0x00000040 | ||
79 | #define CPU_FTR_604_PERF_MON 0x00000080 | ||
80 | #define CPU_FTR_601 0x00000100 | ||
81 | #define CPU_FTR_HPTE_TABLE 0x00000200 | ||
82 | #define CPU_FTR_CAN_NAP 0x00000400 | ||
83 | #define CPU_FTR_L3CR 0x00000800 | ||
84 | #define CPU_FTR_L3_DISABLE_NAP 0x00001000 | ||
85 | #define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000 | ||
86 | #define CPU_FTR_DUAL_PLL_750FX 0x00004000 | ||
87 | #define CPU_FTR_NO_DPM 0x00008000 | ||
88 | #define CPU_FTR_HAS_HIGH_BATS 0x00010000 | ||
89 | #define CPU_FTR_NEED_COHERENT 0x00020000 | ||
90 | #define CPU_FTR_NO_BTIC 0x00040000 | ||
91 | |||
92 | #ifdef __ASSEMBLY__ | ||
93 | |||
94 | #define BEGIN_FTR_SECTION 98: | ||
95 | |||
96 | #define END_FTR_SECTION(msk, val) \ | ||
97 | 99: \ | ||
98 | .section __ftr_fixup,"a"; \ | ||
99 | .align 2; \ | ||
100 | .long msk; \ | ||
101 | .long val; \ | ||
102 | .long 98b; \ | ||
103 | .long 99b; \ | ||
104 | .previous | ||
105 | |||
106 | #else | ||
107 | |||
108 | #define BEGIN_FTR_SECTION "98:\n" | ||
109 | #define END_FTR_SECTION(msk, val) \ | ||
110 | "99:\n" \ | ||
111 | " .section __ftr_fixup,\"a\";\n" \ | ||
112 | " .align 2;\n" \ | ||
113 | " .long "#msk";\n" \ | ||
114 | " .long "#val";\n" \ | ||
115 | " .long 98b;\n" \ | ||
116 | " .long 99b;\n" \ | ||
117 | " .previous\n" | ||
118 | |||
119 | |||
120 | #endif /* __ASSEMBLY__ */ | ||
121 | |||
122 | #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) | ||
123 | #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) | ||
124 | |||
125 | #endif /* __ASM_PPC_CPUTABLE_H */ | ||
126 | #endif /* __KERNEL__ */ | ||
127 | |||
diff --git a/include/asm-ppc/cputime.h b/include/asm-ppc/cputime.h new file mode 100644 index 000000000000..8e9faf5ce720 --- /dev/null +++ b/include/asm-ppc/cputime.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __PPC_CPUTIME_H | ||
2 | #define __PPC_CPUTIME_H | ||
3 | |||
4 | #include <asm-generic/cputime.h> | ||
5 | |||
6 | #endif /* __PPC_CPUTIME_H */ | ||
diff --git a/include/asm-ppc/current.h b/include/asm-ppc/current.h new file mode 100644 index 000000000000..8d41501ba10d --- /dev/null +++ b/include/asm-ppc/current.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_CURRENT_H | ||
3 | #define _PPC_CURRENT_H | ||
4 | |||
5 | /* | ||
6 | * We keep `current' in r2 for speed. | ||
7 | */ | ||
8 | register struct task_struct *current asm ("r2"); | ||
9 | |||
10 | #endif /* !(_PPC_CURRENT_H) */ | ||
11 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/dbdma.h b/include/asm-ppc/dbdma.h new file mode 100644 index 000000000000..6047f288c70b --- /dev/null +++ b/include/asm-ppc/dbdma.h | |||
@@ -0,0 +1,102 @@ | |||
1 | /* | ||
2 | * Definitions for using the Apple Descriptor-Based DMA controller | ||
3 | * in Power Macintosh computers. | ||
4 | * | ||
5 | * Copyright (C) 1996 Paul Mackerras. | ||
6 | */ | ||
7 | |||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef _ASM_DBDMA_H_ | ||
10 | #define _ASM_DBDMA_H_ | ||
11 | /* | ||
12 | * DBDMA control/status registers. All little-endian. | ||
13 | */ | ||
14 | struct dbdma_regs { | ||
15 | unsigned int control; /* lets you change bits in status */ | ||
16 | unsigned int status; /* DMA and device status bits (see below) */ | ||
17 | unsigned int cmdptr_hi; /* upper 32 bits of command address */ | ||
18 | unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */ | ||
19 | unsigned int intr_sel; /* select interrupt condition bit */ | ||
20 | unsigned int br_sel; /* select branch condition bit */ | ||
21 | unsigned int wait_sel; /* select wait condition bit */ | ||
22 | unsigned int xfer_mode; | ||
23 | unsigned int data2ptr_hi; | ||
24 | unsigned int data2ptr; | ||
25 | unsigned int res1; | ||
26 | unsigned int address_hi; | ||
27 | unsigned int br_addr_hi; | ||
28 | unsigned int res2[3]; | ||
29 | }; | ||
30 | |||
31 | /* Bits in control and status registers */ | ||
32 | #define RUN 0x8000 | ||
33 | #define PAUSE 0x4000 | ||
34 | #define FLUSH 0x2000 | ||
35 | #define WAKE 0x1000 | ||
36 | #define DEAD 0x0800 | ||
37 | #define ACTIVE 0x0400 | ||
38 | #define BT 0x0100 | ||
39 | #define DEVSTAT 0x00ff | ||
40 | |||
41 | /* | ||
42 | * DBDMA command structure. These fields are all little-endian! | ||
43 | */ | ||
44 | struct dbdma_cmd { | ||
45 | unsigned short req_count; /* requested byte transfer count */ | ||
46 | unsigned short command; /* command word (has bit-fields) */ | ||
47 | unsigned int phy_addr; /* physical data address */ | ||
48 | unsigned int cmd_dep; /* command-dependent field */ | ||
49 | unsigned short res_count; /* residual count after completion */ | ||
50 | unsigned short xfer_status; /* transfer status */ | ||
51 | }; | ||
52 | |||
53 | /* DBDMA command values in command field */ | ||
54 | #define OUTPUT_MORE 0 /* transfer memory data to stream */ | ||
55 | #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ | ||
56 | #define INPUT_MORE 0x2000 /* transfer stream data to memory */ | ||
57 | #define INPUT_LAST 0x3000 /* ditto, expect end marker */ | ||
58 | #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ | ||
59 | #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ | ||
60 | #define DBDMA_NOP 0x6000 /* do nothing */ | ||
61 | #define DBDMA_STOP 0x7000 /* suspend processing */ | ||
62 | |||
63 | /* Key values in command field */ | ||
64 | #define KEY_STREAM0 0 /* usual data stream */ | ||
65 | #define KEY_STREAM1 0x100 /* control/status stream */ | ||
66 | #define KEY_STREAM2 0x200 /* device-dependent stream */ | ||
67 | #define KEY_STREAM3 0x300 /* device-dependent stream */ | ||
68 | #define KEY_REGS 0x500 /* device register space */ | ||
69 | #define KEY_SYSTEM 0x600 /* system memory-mapped space */ | ||
70 | #define KEY_DEVICE 0x700 /* device memory-mapped space */ | ||
71 | |||
72 | /* Interrupt control values in command field */ | ||
73 | #define INTR_NEVER 0 /* don't interrupt */ | ||
74 | #define INTR_IFSET 0x10 /* intr if condition bit is 1 */ | ||
75 | #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */ | ||
76 | #define INTR_ALWAYS 0x30 /* always interrupt */ | ||
77 | |||
78 | /* Branch control values in command field */ | ||
79 | #define BR_NEVER 0 /* don't branch */ | ||
80 | #define BR_IFSET 0x4 /* branch if condition bit is 1 */ | ||
81 | #define BR_IFCLR 0x8 /* branch if condition bit is 0 */ | ||
82 | #define BR_ALWAYS 0xc /* always branch */ | ||
83 | |||
84 | /* Wait control values in command field */ | ||
85 | #define WAIT_NEVER 0 /* don't wait */ | ||
86 | #define WAIT_IFSET 1 /* wait if condition bit is 1 */ | ||
87 | #define WAIT_IFCLR 2 /* wait if condition bit is 0 */ | ||
88 | #define WAIT_ALWAYS 3 /* always wait */ | ||
89 | |||
90 | /* Align an address for a DBDMA command structure */ | ||
91 | #define DBDMA_ALIGN(x) (((unsigned)(x) + sizeof(struct dbdma_cmd) - 1) \ | ||
92 | & -sizeof(struct dbdma_cmd)) | ||
93 | |||
94 | /* Useful macros */ | ||
95 | #define DBDMA_DO_STOP(regs) do { \ | ||
96 | out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ | ||
97 | while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \ | ||
98 | ; \ | ||
99 | } while(0) | ||
100 | |||
101 | #endif /* _ASM_DBDMA_H_ */ | ||
102 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h new file mode 100644 index 000000000000..badde6845af2 --- /dev/null +++ b/include/asm-ppc/delay.h | |||
@@ -0,0 +1,66 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_DELAY_H | ||
3 | #define _PPC_DELAY_H | ||
4 | |||
5 | #include <asm/param.h> | ||
6 | |||
7 | /* | ||
8 | * Copyright 1996, Paul Mackerras. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or | ||
11 | * modify it under the terms of the GNU General Public License | ||
12 | * as published by the Free Software Foundation; either version | ||
13 | * 2 of the License, or (at your option) any later version. | ||
14 | */ | ||
15 | |||
16 | extern unsigned long loops_per_jiffy; | ||
17 | |||
18 | extern void __delay(unsigned int loops); | ||
19 | |||
20 | /* | ||
21 | * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so | ||
22 | * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32. | ||
23 | * | ||
24 | * The mulhwu instruction gives us loops = (a * b) / 2^32. | ||
25 | * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226 | ||
26 | * because this lets us support a wide range of HZ and | ||
27 | * loops_per_jiffy values without either a or b overflowing 2^32. | ||
28 | * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and | ||
29 | * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280 | ||
30 | * (which corresponds to ~3800 bogomips at HZ = 100). | ||
31 | * -- paulus | ||
32 | */ | ||
33 | #define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */ | ||
34 | #define __MAX_NDELAY (4294967295UL/HZ) /* maximum ndelay argument */ | ||
35 | |||
36 | extern __inline__ void __udelay(unsigned int x) | ||
37 | { | ||
38 | unsigned int loops; | ||
39 | |||
40 | __asm__("mulhwu %0,%1,%2" : "=r" (loops) : | ||
41 | "r" (x), "r" (loops_per_jiffy * 226)); | ||
42 | __delay(loops); | ||
43 | } | ||
44 | |||
45 | extern __inline__ void __ndelay(unsigned int x) | ||
46 | { | ||
47 | unsigned int loops; | ||
48 | |||
49 | __asm__("mulhwu %0,%1,%2" : "=r" (loops) : | ||
50 | "r" (x), "r" (loops_per_jiffy * 5)); | ||
51 | __delay(loops); | ||
52 | } | ||
53 | |||
54 | extern void __bad_udelay(void); /* deliberately undefined */ | ||
55 | extern void __bad_ndelay(void); /* deliberately undefined */ | ||
56 | |||
57 | #define udelay(n) (__builtin_constant_p(n)? \ | ||
58 | ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \ | ||
59 | __udelay((n) * (19 * HZ))) | ||
60 | |||
61 | #define ndelay(n) (__builtin_constant_p(n)? \ | ||
62 | ((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \ | ||
63 | __ndelay((n) * HZ)) | ||
64 | |||
65 | #endif /* defined(_PPC_DELAY_H) */ | ||
66 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/div64.h b/include/asm-ppc/div64.h new file mode 100644 index 000000000000..6cd978cefb28 --- /dev/null +++ b/include/asm-ppc/div64.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/div64.h> | |||
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h new file mode 100644 index 000000000000..7f0487afebbe --- /dev/null +++ b/include/asm-ppc/dma-mapping.h | |||
@@ -0,0 +1,236 @@ | |||
1 | /* | ||
2 | * This is based on both include/asm-sh/dma-mapping.h and | ||
3 | * include/asm-ppc/pci.h | ||
4 | */ | ||
5 | #ifndef __ASM_PPC_DMA_MAPPING_H | ||
6 | #define __ASM_PPC_DMA_MAPPING_H | ||
7 | |||
8 | #include <linux/config.h> | ||
9 | /* need struct page definitions */ | ||
10 | #include <linux/mm.h> | ||
11 | #include <asm/scatterlist.h> | ||
12 | #include <asm/io.h> | ||
13 | |||
14 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
15 | /* | ||
16 | * DMA-consistent mapping functions for PowerPCs that don't support | ||
17 | * cache snooping. These allocate/free a region of uncached mapped | ||
18 | * memory space for use with DMA devices. Alternatively, you could | ||
19 | * allocate the space "normally" and use the cache management functions | ||
20 | * to ensure it is consistent. | ||
21 | */ | ||
22 | extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp); | ||
23 | extern void __dma_free_coherent(size_t size, void *vaddr); | ||
24 | extern void __dma_sync(void *vaddr, size_t size, int direction); | ||
25 | extern void __dma_sync_page(struct page *page, unsigned long offset, | ||
26 | size_t size, int direction); | ||
27 | #define dma_cache_inv(_start,_size) \ | ||
28 | invalidate_dcache_range(_start, (_start + _size)) | ||
29 | #define dma_cache_wback(_start,_size) \ | ||
30 | clean_dcache_range(_start, (_start + _size)) | ||
31 | #define dma_cache_wback_inv(_start,_size) \ | ||
32 | flush_dcache_range(_start, (_start + _size)) | ||
33 | |||
34 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | ||
35 | /* | ||
36 | * Cache coherent cores. | ||
37 | */ | ||
38 | |||
39 | #define dma_cache_inv(_start,_size) do { } while (0) | ||
40 | #define dma_cache_wback(_start,_size) do { } while (0) | ||
41 | #define dma_cache_wback_inv(_start,_size) do { } while (0) | ||
42 | |||
43 | #define __dma_alloc_coherent(gfp, size, handle) NULL | ||
44 | #define __dma_free_coherent(size, addr) do { } while (0) | ||
45 | #define __dma_sync(addr, size, rw) do { } while (0) | ||
46 | #define __dma_sync_page(pg, off, sz, rw) do { } while (0) | ||
47 | |||
48 | #endif /* ! CONFIG_NOT_COHERENT_CACHE */ | ||
49 | |||
50 | #define dma_supported(dev, mask) (1) | ||
51 | |||
52 | static inline int dma_set_mask(struct device *dev, u64 dma_mask) | ||
53 | { | ||
54 | if (!dev->dma_mask || !dma_supported(dev, mask)) | ||
55 | return -EIO; | ||
56 | |||
57 | *dev->dma_mask = dma_mask; | ||
58 | |||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, | ||
63 | dma_addr_t * dma_handle, int gfp) | ||
64 | { | ||
65 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
66 | return __dma_alloc_coherent(size, dma_handle, gfp); | ||
67 | #else | ||
68 | void *ret; | ||
69 | /* ignore region specifiers */ | ||
70 | gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); | ||
71 | |||
72 | if (dev == NULL || dev->coherent_dma_mask < 0xffffffff) | ||
73 | gfp |= GFP_DMA; | ||
74 | |||
75 | ret = (void *)__get_free_pages(gfp, get_order(size)); | ||
76 | |||
77 | if (ret != NULL) { | ||
78 | memset(ret, 0, size); | ||
79 | *dma_handle = virt_to_bus(ret); | ||
80 | } | ||
81 | |||
82 | return ret; | ||
83 | #endif | ||
84 | } | ||
85 | |||
86 | static inline void | ||
87 | dma_free_coherent(struct device *dev, size_t size, void *vaddr, | ||
88 | dma_addr_t dma_handle) | ||
89 | { | ||
90 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
91 | __dma_free_coherent(size, vaddr); | ||
92 | #else | ||
93 | free_pages((unsigned long)vaddr, get_order(size)); | ||
94 | #endif | ||
95 | } | ||
96 | |||
97 | static inline dma_addr_t | ||
98 | dma_map_single(struct device *dev, void *ptr, size_t size, | ||
99 | enum dma_data_direction direction) | ||
100 | { | ||
101 | BUG_ON(direction == DMA_NONE); | ||
102 | |||
103 | __dma_sync(ptr, size, direction); | ||
104 | |||
105 | return virt_to_bus(ptr); | ||
106 | } | ||
107 | |||
108 | /* We do nothing. */ | ||
109 | #define dma_unmap_single(dev, addr, size, dir) do { } while (0) | ||
110 | |||
111 | static inline dma_addr_t | ||
112 | dma_map_page(struct device *dev, struct page *page, | ||
113 | unsigned long offset, size_t size, | ||
114 | enum dma_data_direction direction) | ||
115 | { | ||
116 | BUG_ON(direction == DMA_NONE); | ||
117 | |||
118 | __dma_sync_page(page, offset, size, direction); | ||
119 | |||
120 | return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; | ||
121 | } | ||
122 | |||
123 | /* We do nothing. */ | ||
124 | #define dma_unmap_page(dev, handle, size, dir) do { } while (0) | ||
125 | |||
126 | static inline int | ||
127 | dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | ||
128 | enum dma_data_direction direction) | ||
129 | { | ||
130 | int i; | ||
131 | |||
132 | BUG_ON(direction == DMA_NONE); | ||
133 | |||
134 | for (i = 0; i < nents; i++, sg++) { | ||
135 | BUG_ON(!sg->page); | ||
136 | __dma_sync_page(sg->page, sg->offset, sg->length, direction); | ||
137 | sg->dma_address = page_to_bus(sg->page) + sg->offset; | ||
138 | } | ||
139 | |||
140 | return nents; | ||
141 | } | ||
142 | |||
143 | /* We don't do anything here. */ | ||
144 | #define dma_unmap_sg(dev, sg, nents, dir) do { } while (0) | ||
145 | |||
146 | static inline void | ||
147 | dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, | ||
148 | size_t size, | ||
149 | enum dma_data_direction direction) | ||
150 | { | ||
151 | BUG_ON(direction == DMA_NONE); | ||
152 | |||
153 | __dma_sync(bus_to_virt(dma_handle), size, direction); | ||
154 | } | ||
155 | |||
156 | static inline void | ||
157 | dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, | ||
158 | size_t size, | ||
159 | enum dma_data_direction direction) | ||
160 | { | ||
161 | BUG_ON(direction == DMA_NONE); | ||
162 | |||
163 | __dma_sync(bus_to_virt(dma_handle), size, direction); | ||
164 | } | ||
165 | |||
166 | static inline void | ||
167 | dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, | ||
168 | enum dma_data_direction direction) | ||
169 | { | ||
170 | int i; | ||
171 | |||
172 | BUG_ON(direction == DMA_NONE); | ||
173 | |||
174 | for (i = 0; i < nents; i++, sg++) | ||
175 | __dma_sync_page(sg->page, sg->offset, sg->length, direction); | ||
176 | } | ||
177 | |||
178 | static inline void | ||
179 | dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, | ||
180 | enum dma_data_direction direction) | ||
181 | { | ||
182 | int i; | ||
183 | |||
184 | BUG_ON(direction == DMA_NONE); | ||
185 | |||
186 | for (i = 0; i < nents; i++, sg++) | ||
187 | __dma_sync_page(sg->page, sg->offset, sg->length, direction); | ||
188 | } | ||
189 | |||
190 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) | ||
191 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | ||
192 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
193 | #define dma_is_consistent(d) (0) | ||
194 | #else | ||
195 | #define dma_is_consistent(d) (1) | ||
196 | #endif | ||
197 | |||
198 | static inline int dma_get_cache_alignment(void) | ||
199 | { | ||
200 | /* | ||
201 | * Each processor family will define its own L1_CACHE_SHIFT, | ||
202 | * L1_CACHE_BYTES wraps to this, so this is always safe. | ||
203 | */ | ||
204 | return L1_CACHE_BYTES; | ||
205 | } | ||
206 | |||
207 | static inline void | ||
208 | dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, | ||
209 | unsigned long offset, size_t size, | ||
210 | enum dma_data_direction direction) | ||
211 | { | ||
212 | /* just sync everything for now */ | ||
213 | dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction); | ||
214 | } | ||
215 | |||
216 | static inline void | ||
217 | dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, | ||
218 | unsigned long offset, size_t size, | ||
219 | enum dma_data_direction direction) | ||
220 | { | ||
221 | /* just sync everything for now */ | ||
222 | dma_sync_single_for_device(dev, dma_handle, offset + size, direction); | ||
223 | } | ||
224 | |||
225 | static inline void dma_cache_sync(void *vaddr, size_t size, | ||
226 | enum dma_data_direction direction) | ||
227 | { | ||
228 | __dma_sync(vaddr, size, (int)direction); | ||
229 | } | ||
230 | |||
231 | static inline int dma_mapping_error(dma_addr_t dma_addr) | ||
232 | { | ||
233 | return 0; | ||
234 | } | ||
235 | |||
236 | #endif /* __ASM_PPC_DMA_MAPPING_H */ | ||
diff --git a/include/asm-ppc/dma.h b/include/asm-ppc/dma.h new file mode 100644 index 000000000000..cc8e5cd8c9d2 --- /dev/null +++ b/include/asm-ppc/dma.h | |||
@@ -0,0 +1,371 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/dma.h: Defines for using and allocating dma channels. | ||
3 | * Written by Hennus Bergman, 1992. | ||
4 | * High DMA channel support & info by Hannu Savolainen | ||
5 | * and John Boyd, Nov. 1992. | ||
6 | * Changes for ppc sound by Christoph Nadig | ||
7 | */ | ||
8 | |||
9 | #ifdef __KERNEL__ | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | #include <asm/io.h> | ||
13 | #include <linux/spinlock.h> | ||
14 | #include <asm/system.h> | ||
15 | |||
16 | /* | ||
17 | * Note: Adapted for PowerPC by Gary Thomas | ||
18 | * Modified by Cort Dougan <cort@cs.nmt.edu> | ||
19 | * | ||
20 | * None of this really applies for Power Macintoshes. There is | ||
21 | * basically just enough here to get kernel/dma.c to compile. | ||
22 | * | ||
23 | * There may be some comments or restrictions made here which are | ||
24 | * not valid for the PReP platform. Take what you read | ||
25 | * with a grain of salt. | ||
26 | */ | ||
27 | |||
28 | #ifndef _ASM_DMA_H | ||
29 | #define _ASM_DMA_H | ||
30 | |||
31 | #ifndef MAX_DMA_CHANNELS | ||
32 | #define MAX_DMA_CHANNELS 8 | ||
33 | #endif | ||
34 | |||
35 | /* The maximum address that we can perform a DMA transfer to on this platform */ | ||
36 | /* Doesn't really apply... */ | ||
37 | #define MAX_DMA_ADDRESS 0xFFFFFFFF | ||
38 | |||
39 | /* in arch/ppc/kernel/setup.c -- Cort */ | ||
40 | extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; | ||
41 | extern unsigned long ISA_DMA_THRESHOLD; | ||
42 | |||
43 | #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER | ||
44 | #define dma_outb outb_p | ||
45 | #else | ||
46 | #define dma_outb outb | ||
47 | #endif | ||
48 | |||
49 | #define dma_inb inb | ||
50 | |||
51 | /* | ||
52 | * NOTES about DMA transfers: | ||
53 | * | ||
54 | * controller 1: channels 0-3, byte operations, ports 00-1F | ||
55 | * controller 2: channels 4-7, word operations, ports C0-DF | ||
56 | * | ||
57 | * - ALL registers are 8 bits only, regardless of transfer size | ||
58 | * - channel 4 is not used - cascades 1 into 2. | ||
59 | * - channels 0-3 are byte - addresses/counts are for physical bytes | ||
60 | * - channels 5-7 are word - addresses/counts are for physical words | ||
61 | * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries | ||
62 | * - transfer count loaded to registers is 1 less than actual count | ||
63 | * - controller 2 offsets are all even (2x offsets for controller 1) | ||
64 | * - page registers for 5-7 don't use data bit 0, represent 128K pages | ||
65 | * - page registers for 0-3 use bit 0, represent 64K pages | ||
66 | * | ||
67 | * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. | ||
68 | * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. | ||
69 | * Note that addresses loaded into registers must be _physical_ addresses, | ||
70 | * not logical addresses (which may differ if paging is active). | ||
71 | * | ||
72 | * Address mapping for channels 0-3: | ||
73 | * | ||
74 | * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) | ||
75 | * | ... | | ... | | ... | | ||
76 | * | ... | | ... | | ... | | ||
77 | * | ... | | ... | | ... | | ||
78 | * P7 ... P0 A7 ... A0 A7 ... A0 | ||
79 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
80 | * | ||
81 | * Address mapping for channels 5-7: | ||
82 | * | ||
83 | * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) | ||
84 | * | ... | \ \ ... \ \ \ ... \ \ | ||
85 | * | ... | \ \ ... \ \ \ ... \ (not used) | ||
86 | * | ... | \ \ ... \ \ \ ... \ | ||
87 | * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 | ||
88 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
89 | * | ||
90 | * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses | ||
91 | * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at | ||
92 | * the hardware level, so odd-byte transfers aren't possible). | ||
93 | * | ||
94 | * Transfer count (_not # bytes_) is limited to 64K, represented as actual | ||
95 | * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, | ||
96 | * and up to 128K bytes may be transferred on channels 5-7 in one operation. | ||
97 | * | ||
98 | */ | ||
99 | |||
100 | /* see prep_setup_arch() for detailed informations */ | ||
101 | #if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP) | ||
102 | extern long ppc_cs4232_dma, ppc_cs4232_dma2; | ||
103 | #define SND_DMA1 ppc_cs4232_dma | ||
104 | #define SND_DMA2 ppc_cs4232_dma2 | ||
105 | #else | ||
106 | #define SND_DMA1 -1 | ||
107 | #define SND_DMA2 -1 | ||
108 | #endif | ||
109 | |||
110 | /* 8237 DMA controllers */ | ||
111 | #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ | ||
112 | #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ | ||
113 | |||
114 | /* DMA controller registers */ | ||
115 | #define DMA1_CMD_REG 0x08 /* command register (w) */ | ||
116 | #define DMA1_STAT_REG 0x08 /* status register (r) */ | ||
117 | #define DMA1_REQ_REG 0x09 /* request register (w) */ | ||
118 | #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ | ||
119 | #define DMA1_MODE_REG 0x0B /* mode register (w) */ | ||
120 | #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ | ||
121 | #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ | ||
122 | #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ | ||
123 | #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ | ||
124 | #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ | ||
125 | |||
126 | #define DMA2_CMD_REG 0xD0 /* command register (w) */ | ||
127 | #define DMA2_STAT_REG 0xD0 /* status register (r) */ | ||
128 | #define DMA2_REQ_REG 0xD2 /* request register (w) */ | ||
129 | #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ | ||
130 | #define DMA2_MODE_REG 0xD6 /* mode register (w) */ | ||
131 | #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ | ||
132 | #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ | ||
133 | #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ | ||
134 | #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ | ||
135 | #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ | ||
136 | |||
137 | #define DMA_ADDR_0 0x00 /* DMA address registers */ | ||
138 | #define DMA_ADDR_1 0x02 | ||
139 | #define DMA_ADDR_2 0x04 | ||
140 | #define DMA_ADDR_3 0x06 | ||
141 | #define DMA_ADDR_4 0xC0 | ||
142 | #define DMA_ADDR_5 0xC4 | ||
143 | #define DMA_ADDR_6 0xC8 | ||
144 | #define DMA_ADDR_7 0xCC | ||
145 | |||
146 | #define DMA_CNT_0 0x01 /* DMA count registers */ | ||
147 | #define DMA_CNT_1 0x03 | ||
148 | #define DMA_CNT_2 0x05 | ||
149 | #define DMA_CNT_3 0x07 | ||
150 | #define DMA_CNT_4 0xC2 | ||
151 | #define DMA_CNT_5 0xC6 | ||
152 | #define DMA_CNT_6 0xCA | ||
153 | #define DMA_CNT_7 0xCE | ||
154 | |||
155 | #define DMA_LO_PAGE_0 0x87 /* DMA page registers */ | ||
156 | #define DMA_LO_PAGE_1 0x83 | ||
157 | #define DMA_LO_PAGE_2 0x81 | ||
158 | #define DMA_LO_PAGE_3 0x82 | ||
159 | #define DMA_LO_PAGE_5 0x8B | ||
160 | #define DMA_LO_PAGE_6 0x89 | ||
161 | #define DMA_LO_PAGE_7 0x8A | ||
162 | |||
163 | #define DMA_HI_PAGE_0 0x487 /* DMA page registers */ | ||
164 | #define DMA_HI_PAGE_1 0x483 | ||
165 | #define DMA_HI_PAGE_2 0x481 | ||
166 | #define DMA_HI_PAGE_3 0x482 | ||
167 | #define DMA_HI_PAGE_5 0x48B | ||
168 | #define DMA_HI_PAGE_6 0x489 | ||
169 | #define DMA_HI_PAGE_7 0x48A | ||
170 | |||
171 | #define DMA1_EXT_REG 0x40B | ||
172 | #define DMA2_EXT_REG 0x4D6 | ||
173 | |||
174 | #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ | ||
175 | #define DMA_AUTOINIT 0x10 | ||
176 | |||
177 | extern spinlock_t dma_spin_lock; | ||
178 | |||
179 | static __inline__ unsigned long claim_dma_lock(void) | ||
180 | { | ||
181 | unsigned long flags; | ||
182 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
183 | return flags; | ||
184 | } | ||
185 | |||
186 | static __inline__ void release_dma_lock(unsigned long flags) | ||
187 | { | ||
188 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
189 | } | ||
190 | |||
191 | /* enable/disable a specific DMA channel */ | ||
192 | static __inline__ void enable_dma(unsigned int dmanr) | ||
193 | { | ||
194 | unsigned char ucDmaCmd = 0x00; | ||
195 | |||
196 | if (dmanr != 4) { | ||
197 | dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ | ||
198 | dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ | ||
199 | } | ||
200 | if (dmanr <= 3) { | ||
201 | dma_outb(dmanr, DMA1_MASK_REG); | ||
202 | dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ | ||
203 | } else | ||
204 | dma_outb(dmanr & 3, DMA2_MASK_REG); | ||
205 | } | ||
206 | |||
207 | static __inline__ void disable_dma(unsigned int dmanr) | ||
208 | { | ||
209 | if (dmanr <= 3) | ||
210 | dma_outb(dmanr | 4, DMA1_MASK_REG); | ||
211 | else | ||
212 | dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); | ||
213 | } | ||
214 | |||
215 | /* Clear the 'DMA Pointer Flip Flop'. | ||
216 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
217 | * Use this once to initialize the FF to a known state. | ||
218 | * After that, keep track of it. :-) | ||
219 | * --- In order to do that, the DMA routines below should --- | ||
220 | * --- only be used while interrupts are disabled! --- | ||
221 | */ | ||
222 | static __inline__ void clear_dma_ff(unsigned int dmanr) | ||
223 | { | ||
224 | if (dmanr <= 3) | ||
225 | dma_outb(0, DMA1_CLEAR_FF_REG); | ||
226 | else | ||
227 | dma_outb(0, DMA2_CLEAR_FF_REG); | ||
228 | } | ||
229 | |||
230 | /* set mode (above) for a specific DMA channel */ | ||
231 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | ||
232 | { | ||
233 | if (dmanr <= 3) | ||
234 | dma_outb(mode | dmanr, DMA1_MODE_REG); | ||
235 | else | ||
236 | dma_outb(mode | (dmanr & 3), DMA2_MODE_REG); | ||
237 | } | ||
238 | |||
239 | /* Set only the page register bits of the transfer address. | ||
240 | * This is used for successive transfers when we know the contents of | ||
241 | * the lower 16 bits of the DMA current address register, but a 64k boundary | ||
242 | * may have been crossed. | ||
243 | */ | ||
244 | static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) | ||
245 | { | ||
246 | switch (dmanr) { | ||
247 | case 0: | ||
248 | dma_outb(pagenr, DMA_LO_PAGE_0); | ||
249 | dma_outb(pagenr >> 8, DMA_HI_PAGE_0); | ||
250 | break; | ||
251 | case 1: | ||
252 | dma_outb(pagenr, DMA_LO_PAGE_1); | ||
253 | dma_outb(pagenr >> 8, DMA_HI_PAGE_1); | ||
254 | break; | ||
255 | case 2: | ||
256 | dma_outb(pagenr, DMA_LO_PAGE_2); | ||
257 | dma_outb(pagenr >> 8, DMA_HI_PAGE_2); | ||
258 | break; | ||
259 | case 3: | ||
260 | dma_outb(pagenr, DMA_LO_PAGE_3); | ||
261 | dma_outb(pagenr >> 8, DMA_HI_PAGE_3); | ||
262 | break; | ||
263 | case 5: | ||
264 | if (SND_DMA1 == 5 || SND_DMA2 == 5) | ||
265 | dma_outb(pagenr, DMA_LO_PAGE_5); | ||
266 | else | ||
267 | dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); | ||
268 | dma_outb(pagenr >> 8, DMA_HI_PAGE_5); | ||
269 | break; | ||
270 | case 6: | ||
271 | if (SND_DMA1 == 6 || SND_DMA2 == 6) | ||
272 | dma_outb(pagenr, DMA_LO_PAGE_6); | ||
273 | else | ||
274 | dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); | ||
275 | dma_outb(pagenr >> 8, DMA_HI_PAGE_6); | ||
276 | break; | ||
277 | case 7: | ||
278 | if (SND_DMA1 == 7 || SND_DMA2 == 7) | ||
279 | dma_outb(pagenr, DMA_LO_PAGE_7); | ||
280 | else | ||
281 | dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); | ||
282 | dma_outb(pagenr >> 8, DMA_HI_PAGE_7); | ||
283 | break; | ||
284 | } | ||
285 | } | ||
286 | |||
287 | /* Set transfer address & page bits for specific DMA channel. | ||
288 | * Assumes dma flipflop is clear. | ||
289 | */ | ||
290 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) | ||
291 | { | ||
292 | if (dmanr <= 3) { | ||
293 | dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE); | ||
294 | dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE); | ||
295 | } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { | ||
296 | dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); | ||
297 | dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); | ||
298 | dma_outb((dmanr & 3), DMA2_EXT_REG); | ||
299 | } else { | ||
300 | dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); | ||
301 | dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); | ||
302 | } | ||
303 | set_dma_page(dmanr, phys >> 16); | ||
304 | } | ||
305 | |||
306 | /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for | ||
307 | * a specific DMA channel. | ||
308 | * You must ensure the parameters are valid. | ||
309 | * NOTE: from a manual: "the number of transfers is one more | ||
310 | * than the initial word count"! This is taken into account. | ||
311 | * Assumes dma flip-flop is clear. | ||
312 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. | ||
313 | */ | ||
314 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | ||
315 | { | ||
316 | count--; | ||
317 | if (dmanr <= 3) { | ||
318 | dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); | ||
319 | dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 + | ||
320 | IO_DMA1_BASE); | ||
321 | } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { | ||
322 | dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); | ||
323 | dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 + | ||
324 | IO_DMA2_BASE); | ||
325 | } else { | ||
326 | dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 + | ||
327 | IO_DMA2_BASE); | ||
328 | dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 + | ||
329 | IO_DMA2_BASE); | ||
330 | } | ||
331 | } | ||
332 | |||
333 | /* Get DMA residue count. After a DMA transfer, this | ||
334 | * should return zero. Reading this while a DMA transfer is | ||
335 | * still in progress will return unpredictable results. | ||
336 | * If called before the channel has been used, it may return 1. | ||
337 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
338 | * | ||
339 | * Assumes DMA flip-flop is clear. | ||
340 | */ | ||
341 | static __inline__ int get_dma_residue(unsigned int dmanr) | ||
342 | { | ||
343 | unsigned int io_port = (dmanr <= 3) ? | ||
344 | ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE | ||
345 | : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE; | ||
346 | |||
347 | /* using short to get 16-bit wrap around */ | ||
348 | unsigned short count; | ||
349 | |||
350 | count = 1 + dma_inb(io_port); | ||
351 | count += dma_inb(io_port) << 8; | ||
352 | |||
353 | return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2) | ||
354 | ? count : (count << 1); | ||
355 | |||
356 | } | ||
357 | |||
358 | /* These are in kernel/dma.c: */ | ||
359 | |||
360 | /* reserve a DMA channel */ | ||
361 | extern int request_dma(unsigned int dmanr, const char *device_id); | ||
362 | /* release it again */ | ||
363 | extern void free_dma(unsigned int dmanr); | ||
364 | |||
365 | #ifdef CONFIG_PCI | ||
366 | extern int isa_dma_bridge_buggy; | ||
367 | #else | ||
368 | #define isa_dma_bridge_buggy (0) | ||
369 | #endif | ||
370 | #endif /* _ASM_DMA_H */ | ||
371 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h new file mode 100644 index 000000000000..2c056966efd3 --- /dev/null +++ b/include/asm-ppc/elf.h | |||
@@ -0,0 +1,160 @@ | |||
1 | #ifndef __PPC_ELF_H | ||
2 | #define __PPC_ELF_H | ||
3 | |||
4 | /* | ||
5 | * ELF register definitions.. | ||
6 | */ | ||
7 | #include <asm/types.h> | ||
8 | #include <asm/ptrace.h> | ||
9 | #include <asm/cputable.h> | ||
10 | |||
11 | /* PowerPC relocations defined by the ABIs */ | ||
12 | #define R_PPC_NONE 0 | ||
13 | #define R_PPC_ADDR32 1 /* 32bit absolute address */ | ||
14 | #define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ | ||
15 | #define R_PPC_ADDR16 3 /* 16bit absolute address */ | ||
16 | #define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ | ||
17 | #define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ | ||
18 | #define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ | ||
19 | #define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ | ||
20 | #define R_PPC_ADDR14_BRTAKEN 8 | ||
21 | #define R_PPC_ADDR14_BRNTAKEN 9 | ||
22 | #define R_PPC_REL24 10 /* PC relative 26 bit */ | ||
23 | #define R_PPC_REL14 11 /* PC relative 16 bit */ | ||
24 | #define R_PPC_REL14_BRTAKEN 12 | ||
25 | #define R_PPC_REL14_BRNTAKEN 13 | ||
26 | #define R_PPC_GOT16 14 | ||
27 | #define R_PPC_GOT16_LO 15 | ||
28 | #define R_PPC_GOT16_HI 16 | ||
29 | #define R_PPC_GOT16_HA 17 | ||
30 | #define R_PPC_PLTREL24 18 | ||
31 | #define R_PPC_COPY 19 | ||
32 | #define R_PPC_GLOB_DAT 20 | ||
33 | #define R_PPC_JMP_SLOT 21 | ||
34 | #define R_PPC_RELATIVE 22 | ||
35 | #define R_PPC_LOCAL24PC 23 | ||
36 | #define R_PPC_UADDR32 24 | ||
37 | #define R_PPC_UADDR16 25 | ||
38 | #define R_PPC_REL32 26 | ||
39 | #define R_PPC_PLT32 27 | ||
40 | #define R_PPC_PLTREL32 28 | ||
41 | #define R_PPC_PLT16_LO 29 | ||
42 | #define R_PPC_PLT16_HI 30 | ||
43 | #define R_PPC_PLT16_HA 31 | ||
44 | #define R_PPC_SDAREL16 32 | ||
45 | #define R_PPC_SECTOFF 33 | ||
46 | #define R_PPC_SECTOFF_LO 34 | ||
47 | #define R_PPC_SECTOFF_HI 35 | ||
48 | #define R_PPC_SECTOFF_HA 36 | ||
49 | /* Keep this the last entry. */ | ||
50 | #define R_PPC_NUM 37 | ||
51 | |||
52 | #define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ | ||
53 | #define ELF_NFPREG 33 /* includes fpscr */ | ||
54 | #define ELF_NVRREG 33 /* includes vscr */ | ||
55 | #define ELF_NEVRREG 34 /* includes acc (as 2) */ | ||
56 | |||
57 | /* | ||
58 | * These are used to set parameters in the core dumps. | ||
59 | */ | ||
60 | #define ELF_ARCH EM_PPC | ||
61 | #define ELF_CLASS ELFCLASS32 | ||
62 | #define ELF_DATA ELFDATA2MSB | ||
63 | |||
64 | /* General registers */ | ||
65 | typedef unsigned long elf_greg_t; | ||
66 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
67 | |||
68 | /* Floating point registers */ | ||
69 | typedef double elf_fpreg_t; | ||
70 | typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | ||
71 | |||
72 | /* Altivec registers */ | ||
73 | typedef __vector128 elf_vrreg_t; | ||
74 | typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG]; | ||
75 | |||
76 | #ifdef __KERNEL__ | ||
77 | |||
78 | struct task_struct; | ||
79 | |||
80 | /* | ||
81 | * This is used to ensure we don't load something for the wrong architecture. | ||
82 | */ | ||
83 | |||
84 | #define elf_check_arch(x) ((x)->e_machine == EM_PPC) | ||
85 | |||
86 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
87 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
88 | the loader. We need to make sure that it is out of the way of the program | ||
89 | that it will "exec", and that there is sufficient room for the brk. */ | ||
90 | |||
91 | #define ELF_ET_DYN_BASE (0x08000000) | ||
92 | |||
93 | #define USE_ELF_CORE_DUMP | ||
94 | #define ELF_EXEC_PAGESIZE 4096 | ||
95 | |||
96 | #define ELF_CORE_COPY_REGS(gregs, regs) \ | ||
97 | memcpy((gregs), (regs), sizeof(struct pt_regs)); \ | ||
98 | memset((char *)(gregs) + sizeof(struct pt_regs), 0, \ | ||
99 | sizeof(elf_gregset_t) - sizeof(struct pt_regs)); | ||
100 | |||
101 | #define ELF_CORE_COPY_TASK_REGS(t, elfregs) \ | ||
102 | ((t)->thread.regs? \ | ||
103 | ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0) | ||
104 | |||
105 | extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu); | ||
106 | #define ELF_CORE_COPY_FPREGS(t, fpu) dump_task_fpu((t), (fpu)) | ||
107 | |||
108 | /* This yields a mask that user programs can use to figure out what | ||
109 | instruction set this cpu supports. This could be done in userspace, | ||
110 | but it's not easy, and we've already done it here. */ | ||
111 | |||
112 | #define ELF_HWCAP (cur_cpu_spec[0]->cpu_user_features) | ||
113 | |||
114 | /* This yields a string that ld.so will use to load implementation | ||
115 | specific libraries for optimization. This is more specific in | ||
116 | intent than poking at uname or /proc/cpuinfo. | ||
117 | |||
118 | For the moment, we have only optimizations for the Intel generations, | ||
119 | but that could change... */ | ||
120 | |||
121 | #define ELF_PLATFORM (NULL) | ||
122 | |||
123 | #define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) | ||
124 | |||
125 | /* | ||
126 | * We need to put in some extra aux table entries to tell glibc what | ||
127 | * the cache block size is, so it can use the dcbz instruction safely. | ||
128 | */ | ||
129 | #define AT_DCACHEBSIZE 19 | ||
130 | #define AT_ICACHEBSIZE 20 | ||
131 | #define AT_UCACHEBSIZE 21 | ||
132 | /* A special ignored type value for PPC, for glibc compatibility. */ | ||
133 | #define AT_IGNOREPPC 22 | ||
134 | |||
135 | extern int dcache_bsize; | ||
136 | extern int icache_bsize; | ||
137 | extern int ucache_bsize; | ||
138 | |||
139 | /* | ||
140 | * The requirements here are: | ||
141 | * - keep the final alignment of sp (sp & 0xf) | ||
142 | * - make sure the 32-bit value at the first 16 byte aligned position of | ||
143 | * AUXV is greater than 16 for glibc compatibility. | ||
144 | * AT_IGNOREPPC is used for that. | ||
145 | * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC, | ||
146 | * even if DLINFO_ARCH_ITEMS goes to zero or is undefined. | ||
147 | */ | ||
148 | #define ARCH_DLINFO \ | ||
149 | do { \ | ||
150 | /* Handle glibc compatibility. */ \ | ||
151 | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ | ||
152 | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ | ||
153 | /* Cache size items */ \ | ||
154 | NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \ | ||
155 | NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \ | ||
156 | NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \ | ||
157 | } while (0) | ||
158 | |||
159 | #endif /* __KERNEL__ */ | ||
160 | #endif | ||
diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h new file mode 100644 index 000000000000..19f20bd41ae6 --- /dev/null +++ b/include/asm-ppc/errno.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef _PPC_ERRNO_H | ||
2 | #define _PPC_ERRNO_H | ||
3 | |||
4 | #include <asm-generic/errno.h> | ||
5 | |||
6 | #undef EDEADLOCK | ||
7 | #define EDEADLOCK 58 /* File locking deadlock error */ | ||
8 | |||
9 | #define _LAST_ERRNO 516 | ||
10 | |||
11 | #endif | ||
diff --git a/include/asm-ppc/fcntl.h b/include/asm-ppc/fcntl.h new file mode 100644 index 000000000000..5e28e41fb29f --- /dev/null +++ b/include/asm-ppc/fcntl.h | |||
@@ -0,0 +1,93 @@ | |||
1 | #ifndef _PPC_FCNTL_H | ||
2 | #define _PPC_FCNTL_H | ||
3 | |||
4 | /* open/fcntl - O_SYNC is only implemented on blocks devices and on files | ||
5 | located on an ext2 file system */ | ||
6 | #define O_ACCMODE 0003 | ||
7 | #define O_RDONLY 00 | ||
8 | #define O_WRONLY 01 | ||
9 | #define O_RDWR 02 | ||
10 | #define O_CREAT 0100 /* not fcntl */ | ||
11 | #define O_EXCL 0200 /* not fcntl */ | ||
12 | #define O_NOCTTY 0400 /* not fcntl */ | ||
13 | #define O_TRUNC 01000 /* not fcntl */ | ||
14 | #define O_APPEND 02000 | ||
15 | #define O_NONBLOCK 04000 | ||
16 | #define O_NDELAY O_NONBLOCK | ||
17 | #define O_SYNC 010000 | ||
18 | #define FASYNC 020000 /* fcntl, for BSD compatibility */ | ||
19 | #define O_DIRECTORY 040000 /* must be a directory */ | ||
20 | #define O_NOFOLLOW 0100000 /* don't follow links */ | ||
21 | #define O_LARGEFILE 0200000 | ||
22 | #define O_DIRECT 0400000 /* direct disk access hint */ | ||
23 | #define O_NOATIME 01000000 | ||
24 | |||
25 | #define F_DUPFD 0 /* dup */ | ||
26 | #define F_GETFD 1 /* get close_on_exec */ | ||
27 | #define F_SETFD 2 /* set/clear close_on_exec */ | ||
28 | #define F_GETFL 3 /* get file->f_flags */ | ||
29 | #define F_SETFL 4 /* set file->f_flags */ | ||
30 | #define F_GETLK 5 | ||
31 | #define F_SETLK 6 | ||
32 | #define F_SETLKW 7 | ||
33 | |||
34 | #define F_SETOWN 8 /* for sockets. */ | ||
35 | #define F_GETOWN 9 /* for sockets. */ | ||
36 | #define F_SETSIG 10 /* for sockets. */ | ||
37 | #define F_GETSIG 11 /* for sockets. */ | ||
38 | |||
39 | #define F_GETLK64 12 /* using 'struct flock64' */ | ||
40 | #define F_SETLK64 13 | ||
41 | #define F_SETLKW64 14 | ||
42 | |||
43 | /* for F_[GET|SET]FL */ | ||
44 | #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ | ||
45 | |||
46 | /* for posix fcntl() and lockf() */ | ||
47 | #define F_RDLCK 0 | ||
48 | #define F_WRLCK 1 | ||
49 | #define F_UNLCK 2 | ||
50 | |||
51 | /* for old implementation of bsd flock () */ | ||
52 | #define F_EXLCK 4 /* or 3 */ | ||
53 | #define F_SHLCK 8 /* or 4 */ | ||
54 | |||
55 | /* for leases */ | ||
56 | #define F_INPROGRESS 16 | ||
57 | |||
58 | /* operations for bsd flock(), also used by the kernel implementation */ | ||
59 | #define LOCK_SH 1 /* shared lock */ | ||
60 | #define LOCK_EX 2 /* exclusive lock */ | ||
61 | #define LOCK_NB 4 /* or'd with one of the above to prevent | ||
62 | blocking */ | ||
63 | #define LOCK_UN 8 /* remove lock */ | ||
64 | |||
65 | #define LOCK_MAND 32 /* This is a mandatory flock */ | ||
66 | #define LOCK_READ 64 /* ... Which allows concurrent read operations */ | ||
67 | #define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ | ||
68 | #define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ | ||
69 | |||
70 | #ifdef __KERNEL__ | ||
71 | #define F_POSIX 1 | ||
72 | #define F_FLOCK 2 | ||
73 | #define F_BROKEN 4 /* broken flock() emulation */ | ||
74 | #endif /* __KERNEL__ */ | ||
75 | |||
76 | struct flock { | ||
77 | short l_type; | ||
78 | short l_whence; | ||
79 | off_t l_start; | ||
80 | off_t l_len; | ||
81 | pid_t l_pid; | ||
82 | }; | ||
83 | |||
84 | struct flock64 { | ||
85 | short l_type; | ||
86 | short l_whence; | ||
87 | loff_t l_start; | ||
88 | loff_t l_len; | ||
89 | pid_t l_pid; | ||
90 | }; | ||
91 | |||
92 | #define F_LINUX_SPECIFIC_BASE 1024 | ||
93 | #endif | ||
diff --git a/include/asm-ppc/floppy.h b/include/asm-ppc/floppy.h new file mode 100644 index 000000000000..8ccd4a276fe9 --- /dev/null +++ b/include/asm-ppc/floppy.h | |||
@@ -0,0 +1,182 @@ | |||
1 | /* | ||
2 | * Architecture specific parts of the Floppy driver | ||
3 | * | ||
4 | * This file is subject to the terms and conditions of the GNU General Public | ||
5 | * License. See the file "COPYING" in the main directory of this archive | ||
6 | * for more details. | ||
7 | * | ||
8 | * Copyright (C) 1995 | ||
9 | */ | ||
10 | #ifdef __KERNEL__ | ||
11 | #ifndef __ASM_PPC_FLOPPY_H | ||
12 | #define __ASM_PPC_FLOPPY_H | ||
13 | |||
14 | #define fd_inb(port) inb_p(port) | ||
15 | #define fd_outb(value,port) outb_p(value,port) | ||
16 | |||
17 | #define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA) | ||
18 | #define fd_free_dma() fd_ops->_free_dma(FLOPPY_DMA) | ||
19 | #define fd_get_dma_residue() fd_ops->_get_dma_residue(FLOPPY_DMA) | ||
20 | #define fd_dma_setup(addr, size, mode, io) fd_ops->_dma_setup(addr, size, mode, io) | ||
21 | #define fd_enable_irq() enable_irq(FLOPPY_IRQ) | ||
22 | #define fd_disable_irq() disable_irq(FLOPPY_IRQ) | ||
23 | #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); | ||
24 | |||
25 | static int fd_request_dma(void); | ||
26 | |||
27 | struct fd_dma_ops { | ||
28 | void (*_disable_dma)(unsigned int dmanr); | ||
29 | void (*_free_dma)(unsigned int dmanr); | ||
30 | int (*_get_dma_residue)(unsigned int dummy); | ||
31 | int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); | ||
32 | }; | ||
33 | |||
34 | static int virtual_dma_count; | ||
35 | static int virtual_dma_residue; | ||
36 | static char *virtual_dma_addr; | ||
37 | static int virtual_dma_mode; | ||
38 | static int doing_vdma; | ||
39 | static struct fd_dma_ops *fd_ops; | ||
40 | |||
41 | static irqreturn_t floppy_hardint(int irq, void *dev_id, struct pt_regs * regs) | ||
42 | { | ||
43 | unsigned char st; | ||
44 | int lcount; | ||
45 | char *lptr; | ||
46 | |||
47 | if (!doing_vdma) | ||
48 | return floppy_interrupt(irq, dev_id, regs); | ||
49 | |||
50 | |||
51 | st = 1; | ||
52 | for (lcount=virtual_dma_count, lptr=virtual_dma_addr; | ||
53 | lcount; lcount--, lptr++) { | ||
54 | st=inb(virtual_dma_port+4) & 0xa0 ; | ||
55 | if (st != 0xa0) | ||
56 | break; | ||
57 | if (virtual_dma_mode) | ||
58 | outb_p(*lptr, virtual_dma_port+5); | ||
59 | else | ||
60 | *lptr = inb_p(virtual_dma_port+5); | ||
61 | } | ||
62 | virtual_dma_count = lcount; | ||
63 | virtual_dma_addr = lptr; | ||
64 | st = inb(virtual_dma_port+4); | ||
65 | |||
66 | if (st == 0x20) | ||
67 | return IRQ_HANDLED; | ||
68 | if (!(st & 0x20)) { | ||
69 | virtual_dma_residue += virtual_dma_count; | ||
70 | virtual_dma_count=0; | ||
71 | doing_vdma = 0; | ||
72 | floppy_interrupt(irq, dev_id, regs); | ||
73 | return IRQ_HANDLED; | ||
74 | } | ||
75 | return IRQ_HANDLED; | ||
76 | } | ||
77 | |||
78 | static void vdma_disable_dma(unsigned int dummy) | ||
79 | { | ||
80 | doing_vdma = 0; | ||
81 | virtual_dma_residue += virtual_dma_count; | ||
82 | virtual_dma_count=0; | ||
83 | } | ||
84 | |||
85 | static void vdma_nop(unsigned int dummy) | ||
86 | { | ||
87 | } | ||
88 | |||
89 | |||
90 | static int vdma_get_dma_residue(unsigned int dummy) | ||
91 | { | ||
92 | return virtual_dma_count + virtual_dma_residue; | ||
93 | } | ||
94 | |||
95 | |||
96 | static int fd_request_irq(void) | ||
97 | { | ||
98 | if (can_use_virtual_dma) | ||
99 | return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT, | ||
100 | "floppy", NULL); | ||
101 | else | ||
102 | return request_irq(FLOPPY_IRQ, floppy_interrupt, | ||
103 | SA_INTERRUPT|SA_SAMPLE_RANDOM, | ||
104 | "floppy", NULL); | ||
105 | |||
106 | } | ||
107 | |||
108 | static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) | ||
109 | { | ||
110 | doing_vdma = 1; | ||
111 | virtual_dma_port = io; | ||
112 | virtual_dma_mode = (mode == DMA_MODE_WRITE); | ||
113 | virtual_dma_addr = addr; | ||
114 | virtual_dma_count = size; | ||
115 | virtual_dma_residue = 0; | ||
116 | return 0; | ||
117 | } | ||
118 | |||
119 | static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) | ||
120 | { | ||
121 | /* actual, physical DMA */ | ||
122 | doing_vdma = 0; | ||
123 | clear_dma_ff(FLOPPY_DMA); | ||
124 | set_dma_mode(FLOPPY_DMA,mode); | ||
125 | set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr)); | ||
126 | set_dma_count(FLOPPY_DMA,size); | ||
127 | enable_dma(FLOPPY_DMA); | ||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static struct fd_dma_ops real_dma_ops = | ||
132 | { | ||
133 | ._disable_dma = disable_dma, | ||
134 | ._free_dma = free_dma, | ||
135 | ._get_dma_residue = get_dma_residue, | ||
136 | ._dma_setup = hard_dma_setup | ||
137 | }; | ||
138 | |||
139 | static struct fd_dma_ops virt_dma_ops = | ||
140 | { | ||
141 | ._disable_dma = vdma_disable_dma, | ||
142 | ._free_dma = vdma_nop, | ||
143 | ._get_dma_residue = vdma_get_dma_residue, | ||
144 | ._dma_setup = vdma_dma_setup | ||
145 | }; | ||
146 | |||
147 | static int fd_request_dma() | ||
148 | { | ||
149 | if (can_use_virtual_dma & 1) { | ||
150 | fd_ops = &virt_dma_ops; | ||
151 | return 0; | ||
152 | } | ||
153 | else { | ||
154 | fd_ops = &real_dma_ops; | ||
155 | return request_dma(FLOPPY_DMA, "floppy"); | ||
156 | } | ||
157 | } | ||
158 | |||
159 | static int FDC1 = 0x3f0; | ||
160 | static int FDC2 = -1; | ||
161 | |||
162 | /* | ||
163 | * Again, the CMOS information not available | ||
164 | */ | ||
165 | #define FLOPPY0_TYPE 6 | ||
166 | #define FLOPPY1_TYPE 0 | ||
167 | |||
168 | #define N_FDC 2 /* Don't change this! */ | ||
169 | #define N_DRIVE 8 | ||
170 | |||
171 | #define FLOPPY_MOTOR_MASK 0xf0 | ||
172 | |||
173 | /* | ||
174 | * The PowerPC has no problems with floppy DMA crossing 64k borders. | ||
175 | */ | ||
176 | #define CROSS_64KB(a,s) (0) | ||
177 | |||
178 | #endif /* __ASM_PPC_FLOPPY_H */ | ||
179 | |||
180 | #define EXTRA_FLOPPY_PARAMS | ||
181 | |||
182 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/fsl_ocp.h b/include/asm-ppc/fsl_ocp.h new file mode 100644 index 000000000000..050fbba8d049 --- /dev/null +++ b/include/asm-ppc/fsl_ocp.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/fsl_ocp.h | ||
3 | * | ||
4 | * Definitions for the on-chip peripherals on Freescale PPC processors | ||
5 | * | ||
6 | * Maintainer: Kumar Gala (kumar.gala@freescale.com) | ||
7 | * | ||
8 | * Copyright 2004 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_FS_OCP_H__ | ||
18 | #define __ASM_FS_OCP_H__ | ||
19 | |||
20 | /* A table of information for supporting the Gianfar Ethernet Controller | ||
21 | * This helps identify which enet controller we are dealing with, | ||
22 | * and what type of enet controller it is | ||
23 | */ | ||
24 | struct ocp_gfar_data { | ||
25 | uint interruptTransmit; | ||
26 | uint interruptError; | ||
27 | uint interruptReceive; | ||
28 | uint interruptPHY; | ||
29 | uint flags; | ||
30 | uint phyid; | ||
31 | uint phyregidx; | ||
32 | unsigned char mac_addr[6]; | ||
33 | }; | ||
34 | |||
35 | /* Flags in the flags field */ | ||
36 | #define GFAR_HAS_COALESCE 0x20 | ||
37 | #define GFAR_HAS_RMON 0x10 | ||
38 | #define GFAR_HAS_MULTI_INTR 0x08 | ||
39 | #define GFAR_FIRM_SET_MACADDR 0x04 | ||
40 | #define GFAR_HAS_PHY_INTR 0x02 /* if not set use a timer */ | ||
41 | #define GFAR_HAS_GIGABIT 0x01 | ||
42 | |||
43 | /* Data structure for I2C support. Just contains a couple flags | ||
44 | * to distinguish various I2C implementations*/ | ||
45 | struct ocp_fs_i2c_data { | ||
46 | uint flags; | ||
47 | }; | ||
48 | |||
49 | /* Flags for I2C */ | ||
50 | #define FS_I2C_SEPARATE_DFSRR 0x02 | ||
51 | #define FS_I2C_CLOCK_5200 0x01 | ||
52 | |||
53 | #endif /* __ASM_FS_OCP_H__ */ | ||
54 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h new file mode 100644 index 000000000000..341ae55b99fb --- /dev/null +++ b/include/asm-ppc/gg2.h | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions | ||
3 | * | ||
4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
5 | * | ||
6 | * This file is based on the following documentation: | ||
7 | * | ||
8 | * The VAS96011/12 Chipset, Data Book, Edition 1.0 | ||
9 | * VLSI Technology, Inc. | ||
10 | * | ||
11 | * This file is subject to the terms and conditions of the GNU General Public | ||
12 | * License. See the file COPYING in the main directory of this archive | ||
13 | * for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _ASMPPC_GG2_H | ||
17 | #define _ASMPPC_GG2_H | ||
18 | |||
19 | /* | ||
20 | * Memory Map (CHRP mode) | ||
21 | */ | ||
22 | |||
23 | #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ | ||
24 | #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ | ||
25 | #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ | ||
26 | #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ | ||
27 | #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ | ||
28 | /* special PCI cycles */ | ||
29 | #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ | ||
30 | #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ | ||
31 | |||
32 | |||
33 | /* | ||
34 | * GG2 specific PCI Registers | ||
35 | */ | ||
36 | |||
37 | extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ | ||
38 | |||
39 | #define GG2_PCI_BUSNO 0x40 /* Bus number */ | ||
40 | #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ | ||
41 | #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ | ||
42 | #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ | ||
43 | #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ | ||
44 | #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ | ||
45 | #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ | ||
46 | #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ | ||
47 | #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ | ||
48 | #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ | ||
49 | #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ | ||
50 | #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ | ||
51 | #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ | ||
52 | #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ | ||
53 | #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ | ||
54 | #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ | ||
55 | #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ | ||
56 | #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ | ||
57 | #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ | ||
58 | #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ | ||
59 | /* Cleared when read */ | ||
60 | |||
61 | #endif /* _ASMPPC_GG2_H */ | ||
diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h new file mode 100644 index 000000000000..cd0ef644943d --- /dev/null +++ b/include/asm-ppc/gt64260.h | |||
@@ -0,0 +1,322 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/gt64260.h | ||
3 | * | ||
4 | * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines. | ||
5 | * | ||
6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
7 | * | ||
8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | #ifndef __ASMPPC_GT64260_H | ||
14 | #define __ASMPPC_GT64260_H | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/pci.h> | ||
19 | #include <linux/slab.h> | ||
20 | |||
21 | #include <asm/byteorder.h> | ||
22 | #include <asm/io.h> | ||
23 | #include <asm/irq.h> | ||
24 | #include <asm/uaccess.h> | ||
25 | #include <asm/machdep.h> | ||
26 | #include <asm/pci-bridge.h> | ||
27 | #include <asm/gt64260_defs.h> | ||
28 | |||
29 | |||
30 | extern u32 gt64260_base; | ||
31 | extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */ | ||
32 | extern u32 gt64260_revision; | ||
33 | extern u8 gt64260_pci_exclude_bridge; | ||
34 | |||
35 | #ifndef TRUE | ||
36 | #define TRUE 1 | ||
37 | #endif | ||
38 | |||
39 | #ifndef FALSE | ||
40 | #define FALSE 0 | ||
41 | #endif | ||
42 | |||
43 | /* IRQs defined by the 64260 */ | ||
44 | #define GT64260_IRQ_MPSC0 40 | ||
45 | #define GT64260_IRQ_MPSC1 42 | ||
46 | #define GT64260_IRQ_SDMA 36 | ||
47 | |||
48 | /* | ||
49 | * Define a default physical memory map to be set up on the bridge. | ||
50 | * Also define a struct to pass that info from board-specific routines to | ||
51 | * GT64260 generic set up routines. By passing this info in, the board | ||
52 | * support developer can modify it at will. | ||
53 | */ | ||
54 | |||
55 | /* | ||
56 | * This is the default memory map: | ||
57 | * CPU PCI | ||
58 | * --- --- | ||
59 | * PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff | ||
60 | * PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff | ||
61 | * PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff | ||
62 | * PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff | ||
63 | */ | ||
64 | |||
65 | /* Default physical memory map for the GT64260 bridge */ | ||
66 | |||
67 | /* | ||
68 | * PCI Bus 0 Definitions | ||
69 | */ | ||
70 | #define GT64260_PCI_0_IO_SIZE 0x01000000U | ||
71 | #define GT64260_PCI_0_MEM_SIZE 0x10000000U | ||
72 | |||
73 | /* Processor Physical addresses */ | ||
74 | #define GT64260_PCI_0_IO_START_PROC 0xfa000000U | ||
75 | #define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \ | ||
76 | GT64260_PCI_0_IO_SIZE - 1) | ||
77 | |||
78 | /* PCI 0 addresses */ | ||
79 | #define GT64260_PCI_0_IO_START 0x00000000U | ||
80 | #define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \ | ||
81 | GT64260_PCI_0_IO_SIZE - 1) | ||
82 | |||
83 | /* Processor Physical addresses */ | ||
84 | #define GT64260_PCI_0_MEM_START_PROC 0x80000000U | ||
85 | #define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \ | ||
86 | GT64260_PCI_0_MEM_SIZE - 1) | ||
87 | |||
88 | /* PCI 0 addresses */ | ||
89 | #define GT64260_PCI_0_MEM_START 0x80000000U | ||
90 | #define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \ | ||
91 | GT64260_PCI_0_MEM_SIZE - 1) | ||
92 | |||
93 | /* | ||
94 | * PCI Bus 1 Definitions | ||
95 | */ | ||
96 | #define GT64260_PCI_1_IO_SIZE 0x01000000U | ||
97 | #define GT64260_PCI_1_MEM_SIZE 0x10000000U | ||
98 | |||
99 | /* PCI 1 addresses */ | ||
100 | #define GT64260_PCI_1_IO_START 0x01000000U | ||
101 | #define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \ | ||
102 | GT64260_PCI_1_IO_SIZE - 1) | ||
103 | |||
104 | /* Processor Physical addresses */ | ||
105 | #define GT64260_PCI_1_IO_START_PROC 0xfb000000U | ||
106 | #define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \ | ||
107 | GT64260_PCI_1_IO_SIZE - 1) | ||
108 | |||
109 | /* PCI 1 addresses */ | ||
110 | #define GT64260_PCI_1_MEM_START 0x90000000U | ||
111 | #define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \ | ||
112 | GT64260_PCI_1_MEM_SIZE - 1) | ||
113 | |||
114 | /* Processor Physical addresses */ | ||
115 | #define GT64260_PCI_1_MEM_START_PROC 0x90000000U | ||
116 | #define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \ | ||
117 | GT64260_PCI_1_MEM_SIZE - 1) | ||
118 | |||
119 | /* Define struct to pass mem-map info into gt64260_common.c code */ | ||
120 | typedef struct { | ||
121 | struct pci_controller *hose_a; | ||
122 | struct pci_controller *hose_b; | ||
123 | |||
124 | u32 mem_size; | ||
125 | |||
126 | u32 pci_0_io_start_proc; | ||
127 | u32 pci_0_io_start_pci; | ||
128 | u32 pci_0_io_size; | ||
129 | u32 pci_0_io_swap; | ||
130 | |||
131 | u32 pci_0_mem_start_proc; | ||
132 | u32 pci_0_mem_start_pci_hi; | ||
133 | u32 pci_0_mem_start_pci_lo; | ||
134 | u32 pci_0_mem_size; | ||
135 | u32 pci_0_mem_swap; | ||
136 | |||
137 | u32 pci_1_io_start_proc; | ||
138 | u32 pci_1_io_start_pci; | ||
139 | u32 pci_1_io_size; | ||
140 | u32 pci_1_io_swap; | ||
141 | |||
142 | u32 pci_1_mem_start_proc; | ||
143 | u32 pci_1_mem_start_pci_hi; | ||
144 | u32 pci_1_mem_start_pci_lo; | ||
145 | u32 pci_1_mem_size; | ||
146 | u32 pci_1_mem_swap; | ||
147 | } gt64260_bridge_info_t; | ||
148 | |||
149 | #define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \ | ||
150 | (ip)->mem_size = (ms); \ | ||
151 | \ | ||
152 | (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \ | ||
153 | (ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \ | ||
154 | (ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \ | ||
155 | (ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
156 | \ | ||
157 | (ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \ | ||
158 | (ip)->pci_0_mem_start_pci_hi = 0x00000000; \ | ||
159 | (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \ | ||
160 | (ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \ | ||
161 | (ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
162 | \ | ||
163 | (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \ | ||
164 | (ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \ | ||
165 | (ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \ | ||
166 | (ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
167 | \ | ||
168 | (ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \ | ||
169 | (ip)->pci_1_mem_start_pci_hi = 0x00000000; \ | ||
170 | (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \ | ||
171 | (ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \ | ||
172 | (ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ | ||
173 | } | ||
174 | |||
175 | /* | ||
176 | ***************************************************************************** | ||
177 | * | ||
178 | * I/O macros to access the 64260's registers | ||
179 | * | ||
180 | ***************************************************************************** | ||
181 | */ | ||
182 | |||
183 | extern inline uint32_t gt_read(uint32_t offs){ | ||
184 | return (in_le32((volatile uint *)(gt64260_base + offs))); | ||
185 | } | ||
186 | extern inline void gt_write(uint32_t offs, uint32_t d){ | ||
187 | out_le32((volatile uint *)(gt64260_base + offs), d); | ||
188 | } | ||
189 | |||
190 | #if 0 /* paranoid SMP version */ | ||
191 | extern inline void gt_modify(u32 offs, u32 data, u32 mask) \ | ||
192 | { | ||
193 | uint32_t reg; | ||
194 | spin_lock(>64260_lock); | ||
195 | reg = gt_read(offs) & (~mask); /* zero any bits we care about*/ | ||
196 | reg |= data & mask; /* set bits from the data */ | ||
197 | gt_write(offs, reg); | ||
198 | spin_unlock(>64260_lock); | ||
199 | } | ||
200 | #else | ||
201 | extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask) | ||
202 | { | ||
203 | uint32_t reg; | ||
204 | reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/ | ||
205 | reg |= (data) & (mask); /* set bits from the data */ | ||
206 | gt_write(offs, reg); | ||
207 | } | ||
208 | #endif | ||
209 | #define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits) | ||
210 | |||
211 | #define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits) | ||
212 | |||
213 | |||
214 | /* | ||
215 | ***************************************************************************** | ||
216 | * | ||
217 | * Function Prototypes | ||
218 | * | ||
219 | ***************************************************************************** | ||
220 | */ | ||
221 | |||
222 | int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info, | ||
223 | int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char))); | ||
224 | int gt64260_bridge_init(gt64260_bridge_info_t *info); | ||
225 | int gt64260_cpu_scs_set_window(u32 window, | ||
226 | u32 base_addr, | ||
227 | u32 size); | ||
228 | int gt64260_cpu_cs_set_window(u32 window, | ||
229 | u32 base_addr, | ||
230 | u32 size); | ||
231 | int gt64260_cpu_boot_set_window(u32 base_addr, | ||
232 | u32 size); | ||
233 | int gt64260_cpu_set_pci_io_window(u32 pci_bus, | ||
234 | u32 cpu_base_addr, | ||
235 | u32 pci_base_addr, | ||
236 | u32 size, | ||
237 | u32 swap); | ||
238 | int gt64260_cpu_set_pci_mem_window(u32 pci_bus, | ||
239 | u32 window, | ||
240 | u32 cpu_base_addr, | ||
241 | u32 pci_base_addr_hi, | ||
242 | u32 pci_base_addr_lo, | ||
243 | u32 size, | ||
244 | u32 swap_64bit); | ||
245 | int gt64260_cpu_prot_set_window(u32 window, | ||
246 | u32 base_addr, | ||
247 | u32 size, | ||
248 | u32 access_bits); | ||
249 | int gt64260_cpu_snoop_set_window(u32 window, | ||
250 | u32 base_addr, | ||
251 | u32 size, | ||
252 | u32 snoop_type); | ||
253 | void gt64260_cpu_disable_all_windows(void); | ||
254 | int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits); | ||
255 | int gt64260_pci_slave_scs_set_window(struct pci_controller *hose, | ||
256 | u32 window, | ||
257 | u32 pci_base_addr, | ||
258 | u32 cpu_base_addr, | ||
259 | u32 size); | ||
260 | int gt64260_pci_slave_cs_set_window(struct pci_controller *hose, | ||
261 | u32 window, | ||
262 | u32 pci_base_addr, | ||
263 | u32 cpu_base_addr, | ||
264 | u32 size); | ||
265 | int gt64260_pci_slave_boot_set_window(struct pci_controller *hose, | ||
266 | u32 pci_base_addr, | ||
267 | u32 cpu_base_addr, | ||
268 | u32 size); | ||
269 | int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose, | ||
270 | u32 window, | ||
271 | u32 pci_base_addr, | ||
272 | u32 other_bus_base_addr, | ||
273 | u32 size); | ||
274 | int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose, | ||
275 | u32 pci_base_addr, | ||
276 | u32 other_bus_base_addr, | ||
277 | u32 size); | ||
278 | int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose, | ||
279 | u32 window, | ||
280 | u32 pci_base_addr_hi, | ||
281 | u32 pci_base_addr_lo, | ||
282 | u32 cpu_base_addr, | ||
283 | u32 size); | ||
284 | int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose, | ||
285 | u32 window, | ||
286 | u32 pci_base_addr_hi, | ||
287 | u32 pci_base_addr_lo, | ||
288 | u32 cpu_base_addr, | ||
289 | u32 size); | ||
290 | int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose, | ||
291 | u32 pci_base_addr_hi, | ||
292 | u32 pci_base_addr_lo, | ||
293 | u32 cpu_base_addr, | ||
294 | u32 size); | ||
295 | int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose, | ||
296 | u32 window, | ||
297 | u32 pci_base_addr_hi, | ||
298 | u32 pci_base_addr_lo, | ||
299 | u32 other_bus_base_addr, | ||
300 | u32 size); | ||
301 | int gt64260_pci_acc_cntl_set_window(u32 pci_bus, | ||
302 | u32 window, | ||
303 | u32 base_addr_hi, | ||
304 | u32 base_addr_lo, | ||
305 | u32 size, | ||
306 | u32 features); | ||
307 | int gt64260_pci_snoop_set_window(u32 pci_bus, | ||
308 | u32 window, | ||
309 | u32 base_addr_hi, | ||
310 | u32 base_addr_lo, | ||
311 | u32 size, | ||
312 | u32 snoop_type); | ||
313 | int gt64260_set_base(u32 new_base); | ||
314 | int gt64260_get_base(u32 *base); | ||
315 | int gt64260_pci_exclude_device(u8 bus, u8 devfn); | ||
316 | |||
317 | void gt64260_init_irq(void); | ||
318 | int gt64260_get_irq(struct pt_regs *regs); | ||
319 | |||
320 | void gt64260_mpsc_progress(char *s, unsigned short hex); | ||
321 | |||
322 | #endif /* __ASMPPC_GT64260_H */ | ||
diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h new file mode 100644 index 000000000000..6ffd01a5373e --- /dev/null +++ b/include/asm-ppc/gt64260_defs.h | |||
@@ -0,0 +1,1010 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/gt64260_defs.h | ||
3 | * | ||
4 | * Register definitions for the Marvell/Galileo GT64260 host bridge. | ||
5 | * | ||
6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
7 | * | ||
8 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | #ifndef __ASMPPC_GT64260_DEFS_H | ||
14 | #define __ASMPPC_GT64260_DEFS_H | ||
15 | |||
16 | /* | ||
17 | * Define a macro to represent the supported version of the 64260. | ||
18 | */ | ||
19 | #define GT64260 0x01 | ||
20 | #define GT64260A 0x10 | ||
21 | |||
22 | /* | ||
23 | ***************************************************************************** | ||
24 | * | ||
25 | * CPU Interface Registers | ||
26 | * | ||
27 | ***************************************************************************** | ||
28 | */ | ||
29 | |||
30 | /* CPU physical address of 64260's registers */ | ||
31 | #define GT64260_INTERNAL_SPACE_DECODE 0x0068 | ||
32 | #define GT64260_INTERNAL_SPACE_SIZE 0x10000 | ||
33 | #define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 | ||
34 | |||
35 | /* CPU Memory Controller Window Registers (4 windows) */ | ||
36 | #define GT64260_CPU_SCS_DECODE_WINDOWS 4 | ||
37 | |||
38 | #define GT64260_CPU_SCS_DECODE_0_BOT 0x0008 | ||
39 | #define GT64260_CPU_SCS_DECODE_0_TOP 0x0010 | ||
40 | #define GT64260_CPU_SCS_DECODE_1_BOT 0x0208 | ||
41 | #define GT64260_CPU_SCS_DECODE_1_TOP 0x0210 | ||
42 | #define GT64260_CPU_SCS_DECODE_2_BOT 0x0018 | ||
43 | #define GT64260_CPU_SCS_DECODE_2_TOP 0x0020 | ||
44 | #define GT64260_CPU_SCS_DECODE_3_BOT 0x0218 | ||
45 | #define GT64260_CPU_SCS_DECODE_3_TOP 0x0220 | ||
46 | |||
47 | /* CPU Device Controller Window Registers (4 windows) */ | ||
48 | #define GT64260_CPU_CS_DECODE_WINDOWS 4 | ||
49 | |||
50 | #define GT64260_CPU_CS_DECODE_0_BOT 0x0028 | ||
51 | #define GT64260_CPU_CS_DECODE_0_TOP 0x0030 | ||
52 | #define GT64260_CPU_CS_DECODE_1_BOT 0x0228 | ||
53 | #define GT64260_CPU_CS_DECODE_1_TOP 0x0230 | ||
54 | #define GT64260_CPU_CS_DECODE_2_BOT 0x0248 | ||
55 | #define GT64260_CPU_CS_DECODE_2_TOP 0x0250 | ||
56 | #define GT64260_CPU_CS_DECODE_3_BOT 0x0038 | ||
57 | #define GT64260_CPU_CS_DECODE_3_TOP 0x0040 | ||
58 | |||
59 | #define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238 | ||
60 | #define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240 | ||
61 | |||
62 | /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ | ||
63 | #define GT64260_PCI_BUSES 2 | ||
64 | #define GT64260_PCI_IO_WINDOWS_PER_BUS 1 | ||
65 | #define GT64260_PCI_MEM_WINDOWS_PER_BUS 4 | ||
66 | |||
67 | #define GT64260_CPU_PCI_SWAP_BYTE 0x00000000 | ||
68 | #define GT64260_CPU_PCI_SWAP_NONE 0x01000000 | ||
69 | #define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000 | ||
70 | #define GT64260_CPU_PCI_SWAP_WORD 0x03000000 | ||
71 | #define GT64260_CPU_PCI_SWAP_MASK 0x07000000 | ||
72 | |||
73 | #define GT64260_CPU_PCI_MEM_REQ64 (1<<27) | ||
74 | |||
75 | #define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048 | ||
76 | #define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050 | ||
77 | #define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058 | ||
78 | #define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060 | ||
79 | #define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080 | ||
80 | #define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088 | ||
81 | #define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258 | ||
82 | #define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260 | ||
83 | #define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280 | ||
84 | #define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288 | ||
85 | |||
86 | #define GT64260_CPU_PCI_0_IO_REMAP 0x00f0 | ||
87 | #define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8 | ||
88 | #define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320 | ||
89 | #define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100 | ||
90 | #define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328 | ||
91 | #define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8 | ||
92 | #define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330 | ||
93 | #define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300 | ||
94 | #define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338 | ||
95 | |||
96 | #define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090 | ||
97 | #define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098 | ||
98 | #define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0 | ||
99 | #define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8 | ||
100 | #define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0 | ||
101 | #define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8 | ||
102 | #define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0 | ||
103 | #define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8 | ||
104 | #define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0 | ||
105 | #define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8 | ||
106 | |||
107 | #define GT64260_CPU_PCI_1_IO_REMAP 0x0108 | ||
108 | #define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110 | ||
109 | #define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340 | ||
110 | #define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118 | ||
111 | #define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348 | ||
112 | #define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310 | ||
113 | #define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350 | ||
114 | #define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318 | ||
115 | #define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358 | ||
116 | |||
117 | /* CPU Control Registers */ | ||
118 | #define GT64260_CPU_CONFIG 0x0000 | ||
119 | #define GT64260_CPU_MODE 0x0120 | ||
120 | #define GT64260_CPU_MASTER_CNTL 0x0160 | ||
121 | #define GT64260_CPU_XBAR_CNTL_LO 0x0150 | ||
122 | #define GT64260_CPU_XBAR_CNTL_HI 0x0158 | ||
123 | #define GT64260_CPU_XBAR_TO 0x0168 | ||
124 | #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 | ||
125 | #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 | ||
126 | |||
127 | /* CPU Sync Barrier Registers */ | ||
128 | #define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0 | ||
129 | #define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8 | ||
130 | |||
131 | /* CPU Access Protection Registers */ | ||
132 | #define GT64260_CPU_PROT_WINDOWS 8 | ||
133 | |||
134 | #define GT64260_CPU_PROT_ACCPROTECT (1<<16) | ||
135 | #define GT64260_CPU_PROT_WRPROTECT (1<<17) | ||
136 | #define GT64260_CPU_PROT_CACHEPROTECT (1<<18) | ||
137 | |||
138 | #define GT64260_CPU_PROT_BASE_0 0x0180 | ||
139 | #define GT64260_CPU_PROT_TOP_0 0x0188 | ||
140 | #define GT64260_CPU_PROT_BASE_1 0x0190 | ||
141 | #define GT64260_CPU_PROT_TOP_1 0x0198 | ||
142 | #define GT64260_CPU_PROT_BASE_2 0x01a0 | ||
143 | #define GT64260_CPU_PROT_TOP_2 0x01a8 | ||
144 | #define GT64260_CPU_PROT_BASE_3 0x01b0 | ||
145 | #define GT64260_CPU_PROT_TOP_3 0x01b8 | ||
146 | #define GT64260_CPU_PROT_BASE_4 0x01c0 | ||
147 | #define GT64260_CPU_PROT_TOP_4 0x01c8 | ||
148 | #define GT64260_CPU_PROT_BASE_5 0x01d0 | ||
149 | #define GT64260_CPU_PROT_TOP_5 0x01d8 | ||
150 | #define GT64260_CPU_PROT_BASE_6 0x01e0 | ||
151 | #define GT64260_CPU_PROT_TOP_6 0x01e8 | ||
152 | #define GT64260_CPU_PROT_BASE_7 0x01f0 | ||
153 | #define GT64260_CPU_PROT_TOP_7 0x01f8 | ||
154 | |||
155 | /* CPU Snoop Control Registers */ | ||
156 | #define GT64260_CPU_SNOOP_WINDOWS 4 | ||
157 | |||
158 | #define GT64260_CPU_SNOOP_NONE 0x00000000 | ||
159 | #define GT64260_CPU_SNOOP_WT 0x00010000 | ||
160 | #define GT64260_CPU_SNOOP_WB 0x00020000 | ||
161 | #define GT64260_CPU_SNOOP_MASK 0x00030000 | ||
162 | #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK | ||
163 | |||
164 | #define GT64260_CPU_SNOOP_BASE_0 0x0380 | ||
165 | #define GT64260_CPU_SNOOP_TOP_0 0x0388 | ||
166 | #define GT64260_CPU_SNOOP_BASE_1 0x0390 | ||
167 | #define GT64260_CPU_SNOOP_TOP_1 0x0398 | ||
168 | #define GT64260_CPU_SNOOP_BASE_2 0x03a0 | ||
169 | #define GT64260_CPU_SNOOP_TOP_2 0x03a8 | ||
170 | #define GT64260_CPU_SNOOP_BASE_3 0x03b0 | ||
171 | #define GT64260_CPU_SNOOP_TOP_3 0x03b8 | ||
172 | |||
173 | /* CPU Error Report Registers */ | ||
174 | #define GT64260_CPU_ERR_ADDR_LO 0x0070 | ||
175 | #define GT64260_CPU_ERR_ADDR_HI 0x0078 | ||
176 | #define GT64260_CPU_ERR_DATA_LO 0x0128 | ||
177 | #define GT64260_CPU_ERR_DATA_HI 0x0130 | ||
178 | #define GT64260_CPU_ERR_PARITY 0x0138 | ||
179 | #define GT64260_CPU_ERR_CAUSE 0x0140 | ||
180 | #define GT64260_CPU_ERR_MASK 0x0148 | ||
181 | |||
182 | |||
183 | /* | ||
184 | ***************************************************************************** | ||
185 | * | ||
186 | * SDRAM Cotnroller Registers | ||
187 | * | ||
188 | ***************************************************************************** | ||
189 | */ | ||
190 | |||
191 | /* SDRAM Config Registers */ | ||
192 | #define GT64260_SDRAM_CONFIG 0x0448 | ||
193 | #define GT64260_SDRAM_OPERATION_MODE 0x0474 | ||
194 | #define GT64260_SDRAM_ADDR_CNTL 0x047c | ||
195 | #define GT64260_SDRAM_TIMING_PARAMS 0x04b4 | ||
196 | #define GT64260_SDRAM_UMA_CNTL 0x04a4 | ||
197 | #define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8 | ||
198 | #define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac | ||
199 | #define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0 | ||
200 | |||
201 | /* SDRAM Banks Parameters Registers */ | ||
202 | #define GT64260_SDRAM_BANK_PARAMS_0 0x044c | ||
203 | #define GT64260_SDRAM_BANK_PARAMS_1 0x0450 | ||
204 | #define GT64260_SDRAM_BANK_PARAMS_2 0x0454 | ||
205 | #define GT64260_SDRAM_BANK_PARAMS_3 0x0458 | ||
206 | |||
207 | /* SDRAM Error Report Registers */ | ||
208 | #define GT64260_SDRAM_ERR_DATA_LO 0x0484 | ||
209 | #define GT64260_SDRAM_ERR_DATA_HI 0x0480 | ||
210 | #define GT64260_SDRAM_ERR_ADDR 0x0490 | ||
211 | #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 | ||
212 | #define GT64260_SDRAM_ERR_ECC_CALC 0x048c | ||
213 | #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 | ||
214 | #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 | ||
215 | |||
216 | |||
217 | /* | ||
218 | ***************************************************************************** | ||
219 | * | ||
220 | * Device/BOOT Cotnroller Registers | ||
221 | * | ||
222 | ***************************************************************************** | ||
223 | */ | ||
224 | |||
225 | /* Device Control Registers */ | ||
226 | #define GT64260_DEV_BANK_PARAMS_0 0x045c | ||
227 | #define GT64260_DEV_BANK_PARAMS_1 0x0460 | ||
228 | #define GT64260_DEV_BANK_PARAMS_2 0x0464 | ||
229 | #define GT64260_DEV_BANK_PARAMS_3 0x0468 | ||
230 | #define GT64260_DEV_BOOT_PARAMS 0x046c | ||
231 | #define GT64260_DEV_IF_CNTL 0x04c0 | ||
232 | #define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8 | ||
233 | #define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc | ||
234 | #define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4 | ||
235 | |||
236 | /* Device Interrupt Registers */ | ||
237 | #define GT64260_DEV_INTR_CAUSE 0x04d0 | ||
238 | #define GT64260_DEV_INTR_MASK 0x04d4 | ||
239 | #define GT64260_DEV_INTR_ERR_ADDR 0x04d8 | ||
240 | |||
241 | |||
242 | /* | ||
243 | ***************************************************************************** | ||
244 | * | ||
245 | * PCI Bridge Interface Registers | ||
246 | * | ||
247 | ***************************************************************************** | ||
248 | */ | ||
249 | |||
250 | /* PCI Configuration Access Registers */ | ||
251 | #define GT64260_PCI_0_CONFIG_ADDR 0x0cf8 | ||
252 | #define GT64260_PCI_0_CONFIG_DATA 0x0cfc | ||
253 | #define GT64260_PCI_0_IACK 0x0c34 | ||
254 | |||
255 | #define GT64260_PCI_1_CONFIG_ADDR 0x0c78 | ||
256 | #define GT64260_PCI_1_CONFIG_DATA 0x0c7c | ||
257 | #define GT64260_PCI_1_IACK 0x0cb4 | ||
258 | |||
259 | /* PCI Control Registers */ | ||
260 | #define GT64260_PCI_0_CMD 0x0c00 | ||
261 | #define GT64260_PCI_0_MODE 0x0d00 | ||
262 | #define GT64260_PCI_0_TO_RETRY 0x0c04 | ||
263 | #define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04 | ||
264 | #define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38 | ||
265 | #define GT64260_PCI_0_ARBITER_CNTL 0x1d00 | ||
266 | #define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08 | ||
267 | #define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c | ||
268 | #define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04 | ||
269 | #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18 | ||
270 | #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c | ||
271 | #define GT64260_PCI_0_SYNC_BARRIER 0x1d10 | ||
272 | #define GT64260_PCI_0_P2P_CONFIG 0x1d14 | ||
273 | #define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54 | ||
274 | |||
275 | #define GT64260_PCI_1_CMD 0x0c80 | ||
276 | #define GT64260_PCI_1_MODE 0x0d80 | ||
277 | #define GT64260_PCI_1_TO_RETRY 0x0c84 | ||
278 | #define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84 | ||
279 | #define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8 | ||
280 | #define GT64260_PCI_1_ARBITER_CNTL 0x1d80 | ||
281 | #define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88 | ||
282 | #define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c | ||
283 | #define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84 | ||
284 | #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98 | ||
285 | #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c | ||
286 | #define GT64260_PCI_1_SYNC_BARRIER 0x1d90 | ||
287 | #define GT64260_PCI_1_P2P_CONFIG 0x1d94 | ||
288 | #define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4 | ||
289 | |||
290 | /* PCI Access Control Regions Registers */ | ||
291 | #define GT64260_PCI_ACC_CNTL_WINDOWS 8 | ||
292 | |||
293 | #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) | ||
294 | #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) | ||
295 | #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) | ||
296 | #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) | ||
297 | #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) | ||
298 | #define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000 | ||
299 | #define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000 | ||
300 | #define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000 | ||
301 | #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 | ||
302 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
303 | #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 | ||
304 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 | ||
305 | #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 | ||
306 | #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 | ||
307 | #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) | ||
308 | #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) | ||
309 | |||
310 | #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ | ||
311 | GT64260_PCI_ACC_CNTL_DREADEN | \ | ||
312 | GT64260_PCI_ACC_CNTL_RDPREFETCH | \ | ||
313 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ | ||
314 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ | ||
315 | GT64260_PCI_ACC_CNTL_MBURST_MASK | \ | ||
316 | GT64260_PCI_ACC_CNTL_SWAP_MASK | \ | ||
317 | GT64260_PCI_ACC_CNTL_ACCPROT| \ | ||
318 | GT64260_PCI_ACC_CNTL_WRPROT) | ||
319 | |||
320 | #define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00 | ||
321 | #define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04 | ||
322 | #define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08 | ||
323 | #define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10 | ||
324 | #define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14 | ||
325 | #define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18 | ||
326 | #define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20 | ||
327 | #define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24 | ||
328 | #define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28 | ||
329 | #define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30 | ||
330 | #define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34 | ||
331 | #define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38 | ||
332 | #define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40 | ||
333 | #define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44 | ||
334 | #define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48 | ||
335 | #define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50 | ||
336 | #define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54 | ||
337 | #define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58 | ||
338 | #define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60 | ||
339 | #define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64 | ||
340 | #define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68 | ||
341 | #define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70 | ||
342 | #define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74 | ||
343 | #define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78 | ||
344 | |||
345 | #define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80 | ||
346 | #define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84 | ||
347 | #define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88 | ||
348 | #define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90 | ||
349 | #define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94 | ||
350 | #define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98 | ||
351 | #define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0 | ||
352 | #define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4 | ||
353 | #define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8 | ||
354 | #define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0 | ||
355 | #define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4 | ||
356 | #define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8 | ||
357 | #define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0 | ||
358 | #define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4 | ||
359 | #define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8 | ||
360 | #define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0 | ||
361 | #define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4 | ||
362 | #define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8 | ||
363 | #define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0 | ||
364 | #define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4 | ||
365 | #define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8 | ||
366 | #define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0 | ||
367 | #define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4 | ||
368 | #define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8 | ||
369 | |||
370 | /* PCI Snoop Control Registers */ | ||
371 | #define GT64260_PCI_SNOOP_WINDOWS 4 | ||
372 | |||
373 | #define GT64260_PCI_SNOOP_NONE 0x00000000 | ||
374 | #define GT64260_PCI_SNOOP_WT 0x00001000 | ||
375 | #define GT64260_PCI_SNOOP_WB 0x00002000 | ||
376 | |||
377 | #define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00 | ||
378 | #define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04 | ||
379 | #define GT64260_PCI_0_SNOOP_0_TOP 0x1f08 | ||
380 | #define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10 | ||
381 | #define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14 | ||
382 | #define GT64260_PCI_0_SNOOP_1_TOP 0x1f18 | ||
383 | #define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20 | ||
384 | #define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24 | ||
385 | #define GT64260_PCI_0_SNOOP_2_TOP 0x1f28 | ||
386 | #define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30 | ||
387 | #define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34 | ||
388 | #define GT64260_PCI_0_SNOOP_3_TOP 0x1f38 | ||
389 | |||
390 | #define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80 | ||
391 | #define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84 | ||
392 | #define GT64260_PCI_1_SNOOP_0_TOP 0x1f88 | ||
393 | #define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90 | ||
394 | #define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94 | ||
395 | #define GT64260_PCI_1_SNOOP_1_TOP 0x1f98 | ||
396 | #define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0 | ||
397 | #define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4 | ||
398 | #define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8 | ||
399 | #define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0 | ||
400 | #define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4 | ||
401 | #define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8 | ||
402 | |||
403 | /* PCI Error Report Registers */ | ||
404 | #define GT64260_PCI_0_ERR_SERR_MASK 0x0c28 | ||
405 | #define GT64260_PCI_0_ERR_ADDR_LO 0x1d40 | ||
406 | #define GT64260_PCI_0_ERR_ADDR_HI 0x1d44 | ||
407 | #define GT64260_PCI_0_ERR_DATA_LO 0x1d48 | ||
408 | #define GT64260_PCI_0_ERR_DATA_HI 0x1d4c | ||
409 | #define GT64260_PCI_0_ERR_CMD 0x1d50 | ||
410 | #define GT64260_PCI_0_ERR_CAUSE 0x1d58 | ||
411 | #define GT64260_PCI_0_ERR_MASK 0x1d5c | ||
412 | |||
413 | #define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8 | ||
414 | #define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0 | ||
415 | #define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4 | ||
416 | #define GT64260_PCI_1_ERR_DATA_LO 0x1dc8 | ||
417 | #define GT64260_PCI_1_ERR_DATA_HI 0x1dcc | ||
418 | #define GT64260_PCI_1_ERR_CMD 0x1dd0 | ||
419 | #define GT64260_PCI_1_ERR_CAUSE 0x1dd8 | ||
420 | #define GT64260_PCI_1_ERR_MASK 0x1ddc | ||
421 | |||
422 | /* PCI Slave Address Decoding Registers */ | ||
423 | #define GT64260_PCI_SCS_WINDOWS 4 | ||
424 | #define GT64260_PCI_CS_WINDOWS 4 | ||
425 | #define GT64260_PCI_BOOT_WINDOWS 1 | ||
426 | #define GT64260_PCI_P2P_MEM_WINDOWS 2 | ||
427 | #define GT64260_PCI_P2P_IO_WINDOWS 1 | ||
428 | #define GT64260_PCI_DAC_SCS_WINDOWS 4 | ||
429 | #define GT64260_PCI_DAC_CS_WINDOWS 4 | ||
430 | #define GT64260_PCI_DAC_BOOT_WINDOWS 1 | ||
431 | #define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2 | ||
432 | |||
433 | #define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08 | ||
434 | #define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08 | ||
435 | #define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c | ||
436 | #define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c | ||
437 | #define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10 | ||
438 | #define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10 | ||
439 | #define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18 | ||
440 | #define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14 | ||
441 | #define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14 | ||
442 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c | ||
443 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20 | ||
444 | #define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24 | ||
445 | #define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28 | ||
446 | |||
447 | #define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00 | ||
448 | #define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04 | ||
449 | #define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08 | ||
450 | #define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c | ||
451 | #define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10 | ||
452 | #define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14 | ||
453 | #define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18 | ||
454 | #define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c | ||
455 | #define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20 | ||
456 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24 | ||
457 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28 | ||
458 | #define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c | ||
459 | |||
460 | #define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c | ||
461 | |||
462 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0) | ||
463 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1) | ||
464 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2) | ||
465 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3) | ||
466 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4) | ||
467 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5) | ||
468 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6) | ||
469 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7) | ||
470 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8) | ||
471 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9) | ||
472 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10) | ||
473 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11) | ||
474 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12) | ||
475 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13) | ||
476 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14) | ||
477 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15) | ||
478 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16) | ||
479 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17) | ||
480 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18) | ||
481 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19) | ||
482 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20) | ||
483 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21) | ||
484 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22) | ||
485 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23) | ||
486 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24) | ||
487 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25) | ||
488 | #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26) | ||
489 | |||
490 | #define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c | ||
491 | #define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48 | ||
492 | #define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48 | ||
493 | #define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c | ||
494 | #define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c | ||
495 | #define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50 | ||
496 | #define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50 | ||
497 | #define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58 | ||
498 | #define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54 | ||
499 | #define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54 | ||
500 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c | ||
501 | #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 | ||
502 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 | ||
503 | #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 | ||
504 | #define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c | ||
505 | #define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70 | ||
506 | |||
507 | #define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00 | ||
508 | #define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04 | ||
509 | #define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08 | ||
510 | #define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c | ||
511 | #define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10 | ||
512 | #define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14 | ||
513 | #define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18 | ||
514 | #define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c | ||
515 | #define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20 | ||
516 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24 | ||
517 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28 | ||
518 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c | ||
519 | #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30 | ||
520 | #define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34 | ||
521 | |||
522 | #define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38 | ||
523 | #define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c | ||
524 | |||
525 | #define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88 | ||
526 | #define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88 | ||
527 | #define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c | ||
528 | #define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c | ||
529 | #define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90 | ||
530 | #define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90 | ||
531 | #define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98 | ||
532 | #define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94 | ||
533 | #define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94 | ||
534 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c | ||
535 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0 | ||
536 | #define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4 | ||
537 | #define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8 | ||
538 | |||
539 | #define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80 | ||
540 | #define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84 | ||
541 | #define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88 | ||
542 | #define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c | ||
543 | #define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90 | ||
544 | #define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94 | ||
545 | #define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98 | ||
546 | #define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c | ||
547 | #define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0 | ||
548 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4 | ||
549 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8 | ||
550 | #define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac | ||
551 | |||
552 | #define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac | ||
553 | |||
554 | #define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc | ||
555 | #define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8 | ||
556 | #define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8 | ||
557 | #define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc | ||
558 | #define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc | ||
559 | #define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0 | ||
560 | #define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0 | ||
561 | #define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8 | ||
562 | #define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4 | ||
563 | #define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4 | ||
564 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc | ||
565 | #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 | ||
566 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 | ||
567 | #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 | ||
568 | #define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec | ||
569 | #define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0 | ||
570 | |||
571 | #define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80 | ||
572 | #define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84 | ||
573 | #define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88 | ||
574 | #define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c | ||
575 | #define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90 | ||
576 | #define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94 | ||
577 | #define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98 | ||
578 | #define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c | ||
579 | #define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0 | ||
580 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4 | ||
581 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8 | ||
582 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac | ||
583 | #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0 | ||
584 | #define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4 | ||
585 | |||
586 | #define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8 | ||
587 | #define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc | ||
588 | |||
589 | |||
590 | /* | ||
591 | ***************************************************************************** | ||
592 | * | ||
593 | * I2O Controller Interface Registers | ||
594 | * | ||
595 | ***************************************************************************** | ||
596 | */ | ||
597 | |||
598 | /* FIXME: fill in */ | ||
599 | |||
600 | |||
601 | |||
602 | /* | ||
603 | ***************************************************************************** | ||
604 | * | ||
605 | * DMA Controller Interface Registers | ||
606 | * | ||
607 | ***************************************************************************** | ||
608 | */ | ||
609 | |||
610 | /* FIXME: fill in */ | ||
611 | |||
612 | |||
613 | /* | ||
614 | ***************************************************************************** | ||
615 | * | ||
616 | * Timer/Counter Interface Registers | ||
617 | * | ||
618 | ***************************************************************************** | ||
619 | */ | ||
620 | |||
621 | /* FIXME: fill in */ | ||
622 | |||
623 | |||
624 | /* | ||
625 | ***************************************************************************** | ||
626 | * | ||
627 | * Communications Controller (Enet, Serial, etc.) Interface Registers | ||
628 | * | ||
629 | ***************************************************************************** | ||
630 | */ | ||
631 | |||
632 | #define GT64260_ENET_0_CNTL_LO 0xf200 | ||
633 | #define GT64260_ENET_0_CNTL_HI 0xf204 | ||
634 | #define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208 | ||
635 | #define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c | ||
636 | #define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210 | ||
637 | #define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214 | ||
638 | #define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218 | ||
639 | #define GT64260_ENET_1_CNTL_LO 0xf220 | ||
640 | #define GT64260_ENET_1_CNTL_HI 0xf224 | ||
641 | #define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228 | ||
642 | #define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c | ||
643 | #define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230 | ||
644 | #define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234 | ||
645 | #define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238 | ||
646 | #define GT64260_ENET_2_CNTL_LO 0xf240 | ||
647 | #define GT64260_ENET_2_CNTL_HI 0xf244 | ||
648 | #define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248 | ||
649 | #define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c | ||
650 | #define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250 | ||
651 | #define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254 | ||
652 | #define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258 | ||
653 | |||
654 | #define GT64260_MPSC_0_CNTL_LO 0xf280 | ||
655 | #define GT64260_MPSC_0_CNTL_HI 0xf284 | ||
656 | #define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288 | ||
657 | #define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c | ||
658 | #define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290 | ||
659 | #define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294 | ||
660 | #define GT64260_MPSC_1_CNTL_LO 0xf2c0 | ||
661 | #define GT64260_MPSC_1_CNTL_HI 0xf2c4 | ||
662 | #define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8 | ||
663 | #define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc | ||
664 | #define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0 | ||
665 | #define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4 | ||
666 | |||
667 | #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 | ||
668 | #define GT64260_SER_INIT_LAST_DATA 0xf324 | ||
669 | #define GT64260_SER_INIT_CONTROL 0xf328 | ||
670 | #define GT64260_SER_INIT_STATUS 0xf32c | ||
671 | |||
672 | #define GT64260_COMM_ARBITER_CNTL 0xf300 | ||
673 | #define GT64260_COMM_CONFIG 0xb40c | ||
674 | #define GT64260_COMM_XBAR_TO 0xf304 | ||
675 | #define GT64260_COMM_INTR_CAUSE 0xf310 | ||
676 | #define GT64260_COMM_INTR_MASK 0xf314 | ||
677 | #define GT64260_COMM_ERR_ADDR 0xf318 | ||
678 | |||
679 | |||
680 | /* | ||
681 | ***************************************************************************** | ||
682 | * | ||
683 | * Fast Ethernet Controller Interface Registers | ||
684 | * | ||
685 | ***************************************************************************** | ||
686 | */ | ||
687 | |||
688 | #define GT64260_ENET_PHY_ADDR 0x2000 | ||
689 | #define GT64260_ENET_ESMIR 0x2010 | ||
690 | |||
691 | #define GT64260_ENET_E0PCR 0x2400 | ||
692 | #define GT64260_ENET_E0PCXR 0x2408 | ||
693 | #define GT64260_ENET_E0PCMR 0x2410 | ||
694 | #define GT64260_ENET_E0PSR 0x2418 | ||
695 | #define GT64260_ENET_E0SPR 0x2420 | ||
696 | #define GT64260_ENET_E0HTPR 0x2428 | ||
697 | #define GT64260_ENET_E0FCSAL 0x2430 | ||
698 | #define GT64260_ENET_E0FCSAH 0x2438 | ||
699 | #define GT64260_ENET_E0SDCR 0x2440 | ||
700 | #define GT64260_ENET_E0SDCMR 0x2448 | ||
701 | #define GT64260_ENET_E0ICR 0x2450 | ||
702 | #define GT64260_ENET_E0IMR 0x2458 | ||
703 | #define GT64260_ENET_E0FRDP0 0x2480 | ||
704 | #define GT64260_ENET_E0FRDP1 0x2484 | ||
705 | #define GT64260_ENET_E0FRDP2 0x2488 | ||
706 | #define GT64260_ENET_E0FRDP3 0x248c | ||
707 | #define GT64260_ENET_E0CRDP0 0x24a0 | ||
708 | #define GT64260_ENET_E0CRDP1 0x24a4 | ||
709 | #define GT64260_ENET_E0CRDP2 0x24a8 | ||
710 | #define GT64260_ENET_E0CRDP3 0x24ac | ||
711 | #define GT64260_ENET_E0CTDP0 0x24e0 | ||
712 | #define GT64260_ENET_E0CTDP1 0x24e4 | ||
713 | #define GT64260_ENET_0_DSCP2P0L 0x2460 | ||
714 | #define GT64260_ENET_0_DSCP2P0H 0x2464 | ||
715 | #define GT64260_ENET_0_DSCP2P1L 0x2468 | ||
716 | #define GT64260_ENET_0_DSCP2P1H 0x246c | ||
717 | #define GT64260_ENET_0_VPT2P 0x2470 | ||
718 | #define GT64260_ENET_0_MIB_CTRS 0x2500 | ||
719 | |||
720 | #define GT64260_ENET_E1PCR 0x2800 | ||
721 | #define GT64260_ENET_E1PCXR 0x2808 | ||
722 | #define GT64260_ENET_E1PCMR 0x2810 | ||
723 | #define GT64260_ENET_E1PSR 0x2818 | ||
724 | #define GT64260_ENET_E1SPR 0x2820 | ||
725 | #define GT64260_ENET_E1HTPR 0x2828 | ||
726 | #define GT64260_ENET_E1FCSAL 0x2830 | ||
727 | #define GT64260_ENET_E1FCSAH 0x2838 | ||
728 | #define GT64260_ENET_E1SDCR 0x2840 | ||
729 | #define GT64260_ENET_E1SDCMR 0x2848 | ||
730 | #define GT64260_ENET_E1ICR 0x2850 | ||
731 | #define GT64260_ENET_E1IMR 0x2858 | ||
732 | #define GT64260_ENET_E1FRDP0 0x2880 | ||
733 | #define GT64260_ENET_E1FRDP1 0x2884 | ||
734 | #define GT64260_ENET_E1FRDP2 0x2888 | ||
735 | #define GT64260_ENET_E1FRDP3 0x288c | ||
736 | #define GT64260_ENET_E1CRDP0 0x28a0 | ||
737 | #define GT64260_ENET_E1CRDP1 0x28a4 | ||
738 | #define GT64260_ENET_E1CRDP2 0x28a8 | ||
739 | #define GT64260_ENET_E1CRDP3 0x28ac | ||
740 | #define GT64260_ENET_E1CTDP0 0x28e0 | ||
741 | #define GT64260_ENET_E1CTDP1 0x28e4 | ||
742 | #define GT64260_ENET_1_DSCP2P0L 0x2860 | ||
743 | #define GT64260_ENET_1_DSCP2P0H 0x2864 | ||
744 | #define GT64260_ENET_1_DSCP2P1L 0x2868 | ||
745 | #define GT64260_ENET_1_DSCP2P1H 0x286c | ||
746 | #define GT64260_ENET_1_VPT2P 0x2870 | ||
747 | #define GT64260_ENET_1_MIB_CTRS 0x2900 | ||
748 | |||
749 | #define GT64260_ENET_E2PCR 0x2c00 | ||
750 | #define GT64260_ENET_E2PCXR 0x2c08 | ||
751 | #define GT64260_ENET_E2PCMR 0x2c10 | ||
752 | #define GT64260_ENET_E2PSR 0x2c18 | ||
753 | #define GT64260_ENET_E2SPR 0x2c20 | ||
754 | #define GT64260_ENET_E2HTPR 0x2c28 | ||
755 | #define GT64260_ENET_E2FCSAL 0x2c30 | ||
756 | #define GT64260_ENET_E2FCSAH 0x2c38 | ||
757 | #define GT64260_ENET_E2SDCR 0x2c40 | ||
758 | #define GT64260_ENET_E2SDCMR 0x2c48 | ||
759 | #define GT64260_ENET_E2ICR 0x2c50 | ||
760 | #define GT64260_ENET_E2IMR 0x2c58 | ||
761 | #define GT64260_ENET_E2FRDP0 0x2c80 | ||
762 | #define GT64260_ENET_E2FRDP1 0x2c84 | ||
763 | #define GT64260_ENET_E2FRDP2 0x2c88 | ||
764 | #define GT64260_ENET_E2FRDP3 0x2c8c | ||
765 | #define GT64260_ENET_E2CRDP0 0x2ca0 | ||
766 | #define GT64260_ENET_E2CRDP1 0x2ca4 | ||
767 | #define GT64260_ENET_E2CRDP2 0x2ca8 | ||
768 | #define GT64260_ENET_E2CRDP3 0x2cac | ||
769 | #define GT64260_ENET_E2CTDP0 0x2ce0 | ||
770 | #define GT64260_ENET_E2CTDP1 0x2ce4 | ||
771 | #define GT64260_ENET_2_DSCP2P0L 0x2c60 | ||
772 | #define GT64260_ENET_2_DSCP2P0H 0x2c64 | ||
773 | #define GT64260_ENET_2_DSCP2P1L 0x2c68 | ||
774 | #define GT64260_ENET_2_DSCP2P1H 0x2c6c | ||
775 | #define GT64260_ENET_2_VPT2P 0x2c70 | ||
776 | #define GT64260_ENET_2_MIB_CTRS 0x2d00 | ||
777 | |||
778 | |||
779 | /* | ||
780 | ***************************************************************************** | ||
781 | * | ||
782 | * Multi-Protocol Serial Controller Interface Registers | ||
783 | * | ||
784 | ***************************************************************************** | ||
785 | */ | ||
786 | |||
787 | /* Signal Routing */ | ||
788 | #define GT64260_MPSC_MRR 0xb400 | ||
789 | #define GT64260_MPSC_RCRR 0xb404 | ||
790 | #define GT64260_MPSC_TCRR 0xb408 | ||
791 | |||
792 | /* Main Configuratino Registers */ | ||
793 | #define GT64260_MPSC_0_MMCRL 0x8000 | ||
794 | #define GT64260_MPSC_0_MMCRH 0x8004 | ||
795 | #define GT64260_MPSC_0_MPCR 0x8008 | ||
796 | #define GT64260_MPSC_0_CHR_1 0x800c | ||
797 | #define GT64260_MPSC_0_CHR_2 0x8010 | ||
798 | #define GT64260_MPSC_0_CHR_3 0x8014 | ||
799 | #define GT64260_MPSC_0_CHR_4 0x8018 | ||
800 | #define GT64260_MPSC_0_CHR_5 0x801c | ||
801 | #define GT64260_MPSC_0_CHR_6 0x8020 | ||
802 | #define GT64260_MPSC_0_CHR_7 0x8024 | ||
803 | #define GT64260_MPSC_0_CHR_8 0x8028 | ||
804 | #define GT64260_MPSC_0_CHR_9 0x802c | ||
805 | #define GT64260_MPSC_0_CHR_10 0x8030 | ||
806 | #define GT64260_MPSC_0_CHR_11 0x8034 | ||
807 | |||
808 | #define GT64260_MPSC_1_MMCRL 0x9000 | ||
809 | #define GT64260_MPSC_1_MMCRH 0x9004 | ||
810 | #define GT64260_MPSC_1_MPCR 0x9008 | ||
811 | #define GT64260_MPSC_1_CHR_1 0x900c | ||
812 | #define GT64260_MPSC_1_CHR_2 0x9010 | ||
813 | #define GT64260_MPSC_1_CHR_3 0x9014 | ||
814 | #define GT64260_MPSC_1_CHR_4 0x9018 | ||
815 | #define GT64260_MPSC_1_CHR_5 0x901c | ||
816 | #define GT64260_MPSC_1_CHR_6 0x9020 | ||
817 | #define GT64260_MPSC_1_CHR_7 0x9024 | ||
818 | #define GT64260_MPSC_1_CHR_8 0x9028 | ||
819 | #define GT64260_MPSC_1_CHR_9 0x902c | ||
820 | #define GT64260_MPSC_1_CHR_10 0x9030 | ||
821 | #define GT64260_MPSC_1_CHR_11 0x9034 | ||
822 | |||
823 | #define GT64260_MPSC_0_INTR_CAUSE 0xb804 | ||
824 | #define GT64260_MPSC_0_INTR_MASK 0xb884 | ||
825 | #define GT64260_MPSC_1_INTR_CAUSE 0xb80c | ||
826 | #define GT64260_MPSC_1_INTR_MASK 0xb88c | ||
827 | |||
828 | #define GT64260_MPSC_UART_CR_TEV (1<<1) | ||
829 | #define GT64260_MPSC_UART_CR_TA (1<<7) | ||
830 | #define GT64260_MPSC_UART_CR_TTCS (1<<9) | ||
831 | #define GT64260_MPSC_UART_CR_REV (1<<17) | ||
832 | #define GT64260_MPSC_UART_CR_RA (1<<23) | ||
833 | #define GT64260_MPSC_UART_CR_CRD (1<<25) | ||
834 | #define GT64260_MPSC_UART_CR_EH (1<<31) | ||
835 | |||
836 | #define GT64260_MPSC_UART_ESR_CTS (1<<0) | ||
837 | #define GT64260_MPSC_UART_ESR_CD (1<<1) | ||
838 | #define GT64260_MPSC_UART_ESR_TIDLE (1<<3) | ||
839 | #define GT64260_MPSC_UART_ESR_RHS (1<<5) | ||
840 | #define GT64260_MPSC_UART_ESR_RLS (1<<7) | ||
841 | #define GT64260_MPSC_UART_ESR_RLIDL (1<<11) | ||
842 | |||
843 | |||
844 | /* | ||
845 | ***************************************************************************** | ||
846 | * | ||
847 | * Serial DMA Controller Interface Registers | ||
848 | * | ||
849 | ***************************************************************************** | ||
850 | */ | ||
851 | |||
852 | #define GT64260_SDMA_0_SDC 0x4000 | ||
853 | #define GT64260_SDMA_0_SDCM 0x4008 | ||
854 | #define GT64260_SDMA_0_RX_DESC 0x4800 | ||
855 | #define GT64260_SDMA_0_RX_BUF_PTR 0x4808 | ||
856 | #define GT64260_SDMA_0_SCRDP 0x4810 | ||
857 | #define GT64260_SDMA_0_TX_DESC 0x4c00 | ||
858 | #define GT64260_SDMA_0_SCTDP 0x4c10 | ||
859 | #define GT64260_SDMA_0_SFTDP 0x4c14 | ||
860 | |||
861 | #define GT64260_SDMA_1_SDC 0x6000 | ||
862 | #define GT64260_SDMA_1_SDCM 0x6008 | ||
863 | #define GT64260_SDMA_1_RX_DESC 0x6800 | ||
864 | #define GT64260_SDMA_1_RX_BUF_PTR 0x6808 | ||
865 | #define GT64260_SDMA_1_SCRDP 0x6810 | ||
866 | #define GT64260_SDMA_1_TX_DESC 0x6c00 | ||
867 | #define GT64260_SDMA_1_SCTDP 0x6c10 | ||
868 | #define GT64260_SDMA_1_SFTDP 0x6c14 | ||
869 | |||
870 | #define GT64260_SDMA_INTR_CAUSE 0xb800 | ||
871 | #define GT64260_SDMA_INTR_MASK 0xb880 | ||
872 | |||
873 | #define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0) | ||
874 | #define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1) | ||
875 | #define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3) | ||
876 | #define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6) | ||
877 | #define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9) | ||
878 | #define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10) | ||
879 | #define GT64260_SDMA_DESC_CMDSTAT_A (1<<11) | ||
880 | #define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12) | ||
881 | #define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13) | ||
882 | #define GT64260_SDMA_DESC_CMDSTAT_C (1<<14) | ||
883 | #define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15) | ||
884 | #define GT64260_SDMA_DESC_CMDSTAT_L (1<<16) | ||
885 | #define GT64260_SDMA_DESC_CMDSTAT_F (1<<17) | ||
886 | #define GT64260_SDMA_DESC_CMDSTAT_P (1<<18) | ||
887 | #define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23) | ||
888 | #define GT64260_SDMA_DESC_CMDSTAT_O (1<<31) | ||
889 | |||
890 | #define GT64260_SDMA_SDC_RFT (1<<0) | ||
891 | #define GT64260_SDMA_SDC_SFM (1<<1) | ||
892 | #define GT64260_SDMA_SDC_BLMR (1<<6) | ||
893 | #define GT64260_SDMA_SDC_BLMT (1<<7) | ||
894 | #define GT64260_SDMA_SDC_POVR (1<<8) | ||
895 | #define GT64260_SDMA_SDC_RIFB (1<<9) | ||
896 | |||
897 | #define GT64260_SDMA_SDCM_ERD (1<<7) | ||
898 | #define GT64260_SDMA_SDCM_AR (1<<15) | ||
899 | #define GT64260_SDMA_SDCM_STD (1<<16) | ||
900 | #define GT64260_SDMA_SDCM_TXD (1<<23) | ||
901 | #define GT64260_SDMA_SDCM_AT (1<<31) | ||
902 | |||
903 | #define GT64260_SDMA_0_CAUSE_RXBUF (1<<0) | ||
904 | #define GT64260_SDMA_0_CAUSE_RXERR (1<<1) | ||
905 | #define GT64260_SDMA_0_CAUSE_TXBUF (1<<2) | ||
906 | #define GT64260_SDMA_0_CAUSE_TXEND (1<<3) | ||
907 | #define GT64260_SDMA_1_CAUSE_RXBUF (1<<8) | ||
908 | #define GT64260_SDMA_1_CAUSE_RXERR (1<<9) | ||
909 | #define GT64260_SDMA_1_CAUSE_TXBUF (1<<10) | ||
910 | #define GT64260_SDMA_1_CAUSE_TXEND (1<<11) | ||
911 | |||
912 | |||
913 | /* | ||
914 | ***************************************************************************** | ||
915 | * | ||
916 | * Baud Rate Generator Interface Registers | ||
917 | * | ||
918 | ***************************************************************************** | ||
919 | */ | ||
920 | |||
921 | #define GT64260_BRG_0_BCR 0xb200 | ||
922 | #define GT64260_BRG_0_BTR 0xb204 | ||
923 | #define GT64260_BRG_1_BCR 0xb208 | ||
924 | #define GT64260_BRG_1_BTR 0xb20c | ||
925 | #define GT64260_BRG_2_BCR 0xb210 | ||
926 | #define GT64260_BRG_2_BTR 0xb214 | ||
927 | |||
928 | #define GT64260_BRG_INTR_CAUSE 0xb834 | ||
929 | #define GT64260_BRG_INTR_MASK 0xb8b4 | ||
930 | |||
931 | |||
932 | /* | ||
933 | ***************************************************************************** | ||
934 | * | ||
935 | * Watchdog Timer Interface Registers | ||
936 | * | ||
937 | ***************************************************************************** | ||
938 | */ | ||
939 | |||
940 | #define GT64260_WDT_WDC 0xb410 | ||
941 | #define GT64260_WDT_WDV 0xb414 | ||
942 | |||
943 | |||
944 | /* | ||
945 | ***************************************************************************** | ||
946 | * | ||
947 | * General Purpose Pins Controller Interface Registers | ||
948 | * | ||
949 | ***************************************************************************** | ||
950 | */ | ||
951 | |||
952 | #define GT64260_GPP_IO_CNTL 0xf100 | ||
953 | #define GT64260_GPP_LEVEL_CNTL 0xf110 | ||
954 | #define GT64260_GPP_VALUE 0xf104 | ||
955 | #define GT64260_GPP_INTR_CAUSE 0xf108 | ||
956 | #define GT64260_GPP_INTR_MASK 0xf10c | ||
957 | |||
958 | |||
959 | /* | ||
960 | ***************************************************************************** | ||
961 | * | ||
962 | * Multi-Purpose Pins Controller Interface Registers | ||
963 | * | ||
964 | ***************************************************************************** | ||
965 | */ | ||
966 | |||
967 | #define GT64260_MPP_CNTL_0 0xf000 | ||
968 | #define GT64260_MPP_CNTL_1 0xf004 | ||
969 | #define GT64260_MPP_CNTL_2 0xf008 | ||
970 | #define GT64260_MPP_CNTL_3 0xf00c | ||
971 | #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 | ||
972 | |||
973 | |||
974 | /* | ||
975 | ***************************************************************************** | ||
976 | * | ||
977 | * I2C Controller Interface Registers | ||
978 | * | ||
979 | ***************************************************************************** | ||
980 | */ | ||
981 | |||
982 | /* FIXME: fill in */ | ||
983 | |||
984 | |||
985 | /* | ||
986 | ***************************************************************************** | ||
987 | * | ||
988 | * Interrupt Controller Interface Registers | ||
989 | * | ||
990 | ***************************************************************************** | ||
991 | */ | ||
992 | |||
993 | #define GT64260_IC_MAIN_CAUSE_LO 0x0c18 | ||
994 | #define GT64260_IC_MAIN_CAUSE_HI 0x0c68 | ||
995 | #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c | ||
996 | #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c | ||
997 | #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 | ||
998 | #define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24 | ||
999 | #define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64 | ||
1000 | #define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74 | ||
1001 | #define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4 | ||
1002 | #define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4 | ||
1003 | #define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4 | ||
1004 | #define GT64260_IC_CPU_INT_0_MASK 0x0e60 | ||
1005 | #define GT64260_IC_CPU_INT_1_MASK 0x0e64 | ||
1006 | #define GT64260_IC_CPU_INT_2_MASK 0x0e68 | ||
1007 | #define GT64260_IC_CPU_INT_3_MASK 0x0e6c | ||
1008 | |||
1009 | |||
1010 | #endif /* __ASMPPC_GT64260_DEFS_H */ | ||
diff --git a/include/asm-ppc/hardirq.h b/include/asm-ppc/hardirq.h new file mode 100644 index 000000000000..94f1411b1a93 --- /dev/null +++ b/include/asm-ppc/hardirq.h | |||
@@ -0,0 +1,31 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef __ASM_HARDIRQ_H | ||
3 | #define __ASM_HARDIRQ_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <linux/cache.h> | ||
7 | #include <linux/smp_lock.h> | ||
8 | #include <asm/irq.h> | ||
9 | |||
10 | /* The __last_jiffy_stamp field is needed to ensure that no decrementer | ||
11 | * interrupt is lost on SMP machines. Since on most CPUs it is in the same | ||
12 | * cache line as local_irq_count, it is cheap to access and is also used on UP | ||
13 | * for uniformity. | ||
14 | */ | ||
15 | typedef struct { | ||
16 | unsigned long __softirq_pending; /* set_bit is used on this */ | ||
17 | unsigned int __last_jiffy_stamp; | ||
18 | } ____cacheline_aligned irq_cpustat_t; | ||
19 | |||
20 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
21 | |||
22 | #define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp) | ||
23 | |||
24 | static inline void ack_bad_irq(int irq) | ||
25 | { | ||
26 | printk(KERN_CRIT "illegal vector %d received!\n", irq); | ||
27 | BUG(); | ||
28 | } | ||
29 | |||
30 | #endif /* __ASM_HARDIRQ_H */ | ||
31 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h new file mode 100644 index 000000000000..36c73ab7e43e --- /dev/null +++ b/include/asm-ppc/harrier.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * arch/ppc/kernel/harrier.h | ||
3 | * | ||
4 | * Definitions for Motorola MCG Harrier North Bridge & Memory controller | ||
5 | * | ||
6 | * Author: Dale Farnsworth | ||
7 | * dale.farnsworth@mvista.com | ||
8 | * | ||
9 | * Modified by: Randy Vinson | ||
10 | * rvinson@mvista.com | ||
11 | * | ||
12 | * Copyright 2001-2002 MontaVista Software Inc. | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify it | ||
15 | * under the terms of the GNU General Public License as published by the | ||
16 | * Free Software Foundation; either version 2 of the License, or (at your | ||
17 | * option) any later version. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASMPPC_HARRIER_H | ||
21 | #define __ASMPPC_HARRIER_H | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | #include <asm/pci-bridge.h> | ||
25 | |||
26 | struct pci_controller; | ||
27 | int harrier_init(struct pci_controller *hose, | ||
28 | uint ppc_reg_base, | ||
29 | ulong processor_pci_mem_start, | ||
30 | ulong processor_pci_mem_end, | ||
31 | ulong processor_pci_io_start, | ||
32 | ulong processor_pci_io_end, | ||
33 | ulong processor_mpic_base); | ||
34 | |||
35 | unsigned long harrier_get_mem_size(uint smc_base); | ||
36 | |||
37 | int harrier_mpic_init(unsigned int pci_mem_offset); | ||
38 | |||
39 | void harrier_setup_nonmonarch(uint ppc_reg_base, | ||
40 | uint in0_size); | ||
41 | void harrier_release_eready(uint ppc_reg_base); | ||
42 | |||
43 | void harrier_wait_eready(uint ppc_reg_base); | ||
44 | |||
45 | #endif /* __ASMPPC_HARRIER_H */ | ||
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h new file mode 100644 index 000000000000..f347007d22af --- /dev/null +++ b/include/asm-ppc/hawk.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/hawk.h | ||
3 | * | ||
4 | * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. | ||
5 | * | ||
6 | * Author: Mark A. Greer | ||
7 | * mgreer@mvista.com | ||
8 | * | ||
9 | * Modified by Randy Vinson (rvinson@mvista.com) | ||
10 | * | ||
11 | * 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
12 | * the terms of the GNU General Public License version 2. This program | ||
13 | * is licensed "as is" without any warranty of any kind, whether express | ||
14 | * or implied. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ASMPPC_HAWK_H | ||
18 | #define __ASMPPC_HAWK_H | ||
19 | |||
20 | #include <asm/pci-bridge.h> | ||
21 | #include <asm/hawk_defs.h> | ||
22 | |||
23 | extern int hawk_init(struct pci_controller *hose, | ||
24 | unsigned int ppc_reg_base, unsigned long processor_pci_mem_start, | ||
25 | unsigned long processor_pci_mem_end, | ||
26 | unsigned long processor_pci_io_start, | ||
27 | unsigned long processor_pci_io_end, | ||
28 | unsigned long processor_mpic_base); | ||
29 | extern unsigned long hawk_get_mem_size(unsigned int smc_base); | ||
30 | extern int hawk_mpic_init(unsigned int pci_mem_offset); | ||
31 | |||
32 | #endif /* __ASMPPC_HAWK_H */ | ||
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h new file mode 100644 index 000000000000..6d1d2baf648c --- /dev/null +++ b/include/asm-ppc/hawk_defs.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/hawk_defs.h | ||
3 | * | ||
4 | * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. | ||
5 | * | ||
6 | * Author: Mark A. Greer | ||
7 | * mgreer@mvista.com | ||
8 | * | ||
9 | * Modified by Randy Vinson (rvinson@mvista.com) | ||
10 | * | ||
11 | * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under | ||
12 | * the terms of the GNU General Public License version 2. This program | ||
13 | * is licensed "as is" without any warranty of any kind, whether express | ||
14 | * or implied. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ASMPPC_HAWK_DEFS_H | ||
18 | #define __ASMPPC_HAWK_DEFS_H | ||
19 | |||
20 | #include <asm/pci-bridge.h> | ||
21 | |||
22 | /* | ||
23 | * The Falcon/Raven and HAWK have 4 sets of registers: | ||
24 | * 1) PPC Registers which define the mappings from PPC bus to PCI bus, | ||
25 | * etc. | ||
26 | * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the | ||
27 | * MPIC base address. | ||
28 | * 3) MPIC registers | ||
29 | * 4) System Memory Controller (SMC) registers. | ||
30 | */ | ||
31 | |||
32 | #define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8 | ||
33 | #define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc | ||
34 | |||
35 | #define HAWK_MPIC_SIZE 0x00040000U | ||
36 | #define HAWK_SMC_SIZE 0x00001000U | ||
37 | |||
38 | /* | ||
39 | * Define PPC register offsets. | ||
40 | */ | ||
41 | #define HAWK_PPC_XSADD0_OFF 0x40 | ||
42 | #define HAWK_PPC_XSOFF0_OFF 0x44 | ||
43 | #define HAWK_PPC_XSADD1_OFF 0x48 | ||
44 | #define HAWK_PPC_XSOFF1_OFF 0x4c | ||
45 | #define HAWK_PPC_XSADD2_OFF 0x50 | ||
46 | #define HAWK_PPC_XSOFF2_OFF 0x54 | ||
47 | #define HAWK_PPC_XSADD3_OFF 0x58 | ||
48 | #define HAWK_PPC_XSOFF3_OFF 0x5c | ||
49 | |||
50 | /* | ||
51 | * Define PCI register offsets. | ||
52 | */ | ||
53 | #define HAWK_PCI_PSADD0_OFF 0x80 | ||
54 | #define HAWK_PCI_PSOFF0_OFF 0x84 | ||
55 | #define HAWK_PCI_PSADD1_OFF 0x88 | ||
56 | #define HAWK_PCI_PSOFF1_OFF 0x8c | ||
57 | #define HAWK_PCI_PSADD2_OFF 0x90 | ||
58 | #define HAWK_PCI_PSOFF2_OFF 0x94 | ||
59 | #define HAWK_PCI_PSADD3_OFF 0x98 | ||
60 | #define HAWK_PCI_PSOFF3_OFF 0x9c | ||
61 | |||
62 | /* | ||
63 | * Define the System Memory Controller (SMC) register offsets. | ||
64 | */ | ||
65 | #define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10 | ||
66 | #define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11 | ||
67 | #define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12 | ||
68 | #define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13 | ||
69 | #define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ | ||
70 | #define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ | ||
71 | #define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ | ||
72 | #define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ | ||
73 | |||
74 | #define FALCON_SMC_REG_COUNT 4 | ||
75 | #define HAWK_SMC_REG_COUNT 8 | ||
76 | #endif /* __ASMPPC_HAWK_DEFS_H */ | ||
diff --git a/include/asm-ppc/hdreg.h b/include/asm-ppc/hdreg.h new file mode 100644 index 000000000000..7f7fd1af0af3 --- /dev/null +++ b/include/asm-ppc/hdreg.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/hdreg.h> | |||
diff --git a/include/asm-ppc/heathrow.h b/include/asm-ppc/heathrow.h new file mode 100644 index 000000000000..22ac179856b9 --- /dev/null +++ b/include/asm-ppc/heathrow.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * heathrow.h: definitions for using the "Heathrow" I/O controller chip. | ||
3 | * | ||
4 | * Grabbed from Open Firmware definitions on a PowerBook G3 Series | ||
5 | * | ||
6 | * Copyright (C) 1997 Paul Mackerras. | ||
7 | */ | ||
8 | |||
9 | /* Front light color on Yikes/B&W G3. 32 bits */ | ||
10 | #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */ | ||
11 | |||
12 | /* Brightness/contrast (gossamer iMac ?). 8 bits */ | ||
13 | #define HEATHROW_BRIGHTNESS_CNTL 0x32 | ||
14 | #define HEATHROW_CONTRAST_CNTL 0x33 | ||
15 | |||
16 | /* offset from ohare base for feature control register */ | ||
17 | #define HEATHROW_MBCR 0x34 /* Media bay control */ | ||
18 | #define HEATHROW_FCR 0x38 /* Feature control */ | ||
19 | #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ | ||
20 | |||
21 | /* | ||
22 | * Bits in feature control register. | ||
23 | * Bits postfixed with a _N are in inverse logic | ||
24 | */ | ||
25 | #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */ | ||
26 | #define HRW_BAY_POWER_N 0x00000002 | ||
27 | #define HRW_BAY_PCI_ENABLE 0x00000004 | ||
28 | #define HRW_BAY_IDE_ENABLE 0x00000008 | ||
29 | #define HRW_BAY_FLOPPY_ENABLE 0x00000010 | ||
30 | #define HRW_IDE0_ENABLE 0x00000020 | ||
31 | #define HRW_IDE0_RESET_N 0x00000040 | ||
32 | #define HRW_BAY_DEV_MASK 0x0000001c | ||
33 | #define HRW_BAY_RESET_N 0x00000080 | ||
34 | #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ | ||
35 | #define HRW_SCC_ENABLE 0x00000200 | ||
36 | #define HRW_MESH_ENABLE 0x00000400 | ||
37 | #define HRW_SWIM_ENABLE 0x00000800 | ||
38 | #define HRW_SOUND_POWER_N 0x00001000 | ||
39 | #define HRW_SOUND_CLK_ENABLE 0x00002000 | ||
40 | #define HRW_SCCA_IO 0x00004000 | ||
41 | #define HRW_SCCB_IO 0x00008000 | ||
42 | #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */ | ||
43 | #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */ | ||
44 | #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */ | ||
45 | #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ | ||
46 | #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ | ||
47 | #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ | ||
48 | #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ | ||
49 | #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ | ||
50 | #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ | ||
51 | #define HRW_RESET_SCC 0x02000000 | ||
52 | #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */ | ||
53 | #define HRW_USE_MFDC 0x08000000 /* ??? (0) */ | ||
54 | #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */ | ||
55 | #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */ | ||
56 | |||
57 | /* We OR those features at boot on desktop G3s */ | ||
58 | #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE) | ||
59 | |||
60 | /* Looks like Heathrow has some sort of GPIOs as well... */ | ||
61 | #define HRW_GPIO_MODEM_RESET 0x6d | ||
62 | |||
diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h new file mode 100644 index 000000000000..1d2c4ef81c22 --- /dev/null +++ b/include/asm-ppc/highmem.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * highmem.h: virtual kernel memory mappings for high memory | ||
3 | * | ||
4 | * PowerPC version, stolen from the i386 version. | ||
5 | * | ||
6 | * Used in CONFIG_HIGHMEM systems for memory pages which | ||
7 | * are not addressable by direct kernel virtual addresses. | ||
8 | * | ||
9 | * Copyright (C) 1999 Gerhard Wichert, Siemens AG | ||
10 | * Gerhard.Wichert@pdb.siemens.de | ||
11 | * | ||
12 | * | ||
13 | * Redesigned the x86 32-bit VM architecture to deal with | ||
14 | * up to 16 Terrabyte physical memory. With current x86 CPUs | ||
15 | * we now support up to 64 Gigabytes physical RAM. | ||
16 | * | ||
17 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> | ||
18 | */ | ||
19 | |||
20 | #ifndef _ASM_HIGHMEM_H | ||
21 | #define _ASM_HIGHMEM_H | ||
22 | |||
23 | #ifdef __KERNEL__ | ||
24 | |||
25 | #include <linux/init.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <asm/kmap_types.h> | ||
28 | #include <asm/tlbflush.h> | ||
29 | #include <asm/page.h> | ||
30 | |||
31 | /* undef for production */ | ||
32 | #define HIGHMEM_DEBUG 1 | ||
33 | |||
34 | extern pte_t *kmap_pte; | ||
35 | extern pgprot_t kmap_prot; | ||
36 | extern pte_t *pkmap_page_table; | ||
37 | |||
38 | /* | ||
39 | * Right now we initialize only a single pte table. It can be extended | ||
40 | * easily, subsequent pte tables have to be allocated in one physical | ||
41 | * chunk of RAM. | ||
42 | */ | ||
43 | #define PKMAP_BASE CONFIG_HIGHMEM_START | ||
44 | #define LAST_PKMAP (1 << PTE_SHIFT) | ||
45 | #define LAST_PKMAP_MASK (LAST_PKMAP-1) | ||
46 | #define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) | ||
47 | #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) | ||
48 | |||
49 | #define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) | ||
50 | |||
51 | extern void *kmap_high(struct page *page); | ||
52 | extern void kunmap_high(struct page *page); | ||
53 | |||
54 | static inline void *kmap(struct page *page) | ||
55 | { | ||
56 | might_sleep(); | ||
57 | if (!PageHighMem(page)) | ||
58 | return page_address(page); | ||
59 | return kmap_high(page); | ||
60 | } | ||
61 | |||
62 | static inline void kunmap(struct page *page) | ||
63 | { | ||
64 | BUG_ON(in_interrupt()); | ||
65 | if (!PageHighMem(page)) | ||
66 | return; | ||
67 | kunmap_high(page); | ||
68 | } | ||
69 | |||
70 | /* | ||
71 | * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap | ||
72 | * gives a more generic (and caching) interface. But kmap_atomic can | ||
73 | * be used in IRQ contexts, so in some (very limited) cases we need | ||
74 | * it. | ||
75 | */ | ||
76 | static inline void *kmap_atomic(struct page *page, enum km_type type) | ||
77 | { | ||
78 | unsigned int idx; | ||
79 | unsigned long vaddr; | ||
80 | |||
81 | /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ | ||
82 | inc_preempt_count(); | ||
83 | if (!PageHighMem(page)) | ||
84 | return page_address(page); | ||
85 | |||
86 | idx = type + KM_TYPE_NR*smp_processor_id(); | ||
87 | vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE; | ||
88 | #ifdef HIGHMEM_DEBUG | ||
89 | BUG_ON(!pte_none(*(kmap_pte+idx))); | ||
90 | #endif | ||
91 | set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot)); | ||
92 | flush_tlb_page(NULL, vaddr); | ||
93 | |||
94 | return (void*) vaddr; | ||
95 | } | ||
96 | |||
97 | static inline void kunmap_atomic(void *kvaddr, enum km_type type) | ||
98 | { | ||
99 | #ifdef HIGHMEM_DEBUG | ||
100 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
101 | unsigned int idx = type + KM_TYPE_NR*smp_processor_id(); | ||
102 | |||
103 | if (vaddr < KMAP_FIX_BEGIN) { // FIXME | ||
104 | dec_preempt_count(); | ||
105 | preempt_check_resched(); | ||
106 | return; | ||
107 | } | ||
108 | |||
109 | BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE); | ||
110 | |||
111 | /* | ||
112 | * force other mappings to Oops if they'll try to access | ||
113 | * this pte without first remap it | ||
114 | */ | ||
115 | pte_clear(&init_mm, vaddr, kmap_pte+idx); | ||
116 | flush_tlb_page(NULL, vaddr); | ||
117 | #endif | ||
118 | dec_preempt_count(); | ||
119 | preempt_check_resched(); | ||
120 | } | ||
121 | |||
122 | static inline struct page *kmap_atomic_to_page(void *ptr) | ||
123 | { | ||
124 | unsigned long idx, vaddr = (unsigned long) ptr; | ||
125 | |||
126 | if (vaddr < KMAP_FIX_BEGIN) | ||
127 | return virt_to_page(ptr); | ||
128 | |||
129 | idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT; | ||
130 | return pte_page(kmap_pte[idx]); | ||
131 | } | ||
132 | |||
133 | #define flush_cache_kmaps() flush_cache_all() | ||
134 | |||
135 | #endif /* __KERNEL__ */ | ||
136 | |||
137 | #endif /* _ASM_HIGHMEM_H */ | ||
diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h new file mode 100644 index 000000000000..47dc7990fb26 --- /dev/null +++ b/include/asm-ppc/hw_irq.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | ||
3 | */ | ||
4 | #ifdef __KERNEL__ | ||
5 | #ifndef _PPC_HW_IRQ_H | ||
6 | #define _PPC_HW_IRQ_H | ||
7 | |||
8 | #include <asm/ptrace.h> | ||
9 | #include <asm/reg.h> | ||
10 | |||
11 | extern void timer_interrupt(struct pt_regs *); | ||
12 | |||
13 | #define INLINE_IRQS | ||
14 | |||
15 | #define irqs_disabled() ((mfmsr() & MSR_EE) == 0) | ||
16 | |||
17 | #ifdef INLINE_IRQS | ||
18 | |||
19 | static inline void local_irq_disable(void) | ||
20 | { | ||
21 | unsigned long msr; | ||
22 | msr = mfmsr(); | ||
23 | mtmsr(msr & ~MSR_EE); | ||
24 | __asm__ __volatile__("": : :"memory"); | ||
25 | } | ||
26 | |||
27 | static inline void local_irq_enable(void) | ||
28 | { | ||
29 | unsigned long msr; | ||
30 | __asm__ __volatile__("": : :"memory"); | ||
31 | msr = mfmsr(); | ||
32 | mtmsr(msr | MSR_EE); | ||
33 | } | ||
34 | |||
35 | static inline void local_irq_save_ptr(unsigned long *flags) | ||
36 | { | ||
37 | unsigned long msr; | ||
38 | msr = mfmsr(); | ||
39 | *flags = msr; | ||
40 | mtmsr(msr & ~MSR_EE); | ||
41 | __asm__ __volatile__("": : :"memory"); | ||
42 | } | ||
43 | |||
44 | #define local_save_flags(flags) ((flags) = mfmsr()) | ||
45 | #define local_irq_save(flags) local_irq_save_ptr(&flags) | ||
46 | #define local_irq_restore(flags) mtmsr(flags) | ||
47 | |||
48 | #else | ||
49 | |||
50 | extern void local_irq_enable(void); | ||
51 | extern void local_irq_disable(void); | ||
52 | extern void local_irq_restore(unsigned long); | ||
53 | extern void local_save_flags_ptr(unsigned long *); | ||
54 | |||
55 | #define local_save_flags(flags) local_save_flags_ptr(&flags) | ||
56 | #define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();}) | ||
57 | |||
58 | #endif | ||
59 | |||
60 | extern void do_lost_interrupts(unsigned long); | ||
61 | |||
62 | #define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);}) | ||
63 | #define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);}) | ||
64 | #define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);}) | ||
65 | |||
66 | /* Should we handle this via lost interrupts and IPIs or should we don't care like | ||
67 | * we do now ? --BenH. | ||
68 | */ | ||
69 | struct hw_interrupt_type; | ||
70 | static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {} | ||
71 | |||
72 | |||
73 | #endif /* _PPC_HW_IRQ_H */ | ||
74 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/hydra.h b/include/asm-ppc/hydra.h new file mode 100644 index 000000000000..1134431431da --- /dev/null +++ b/include/asm-ppc/hydra.h | |||
@@ -0,0 +1,102 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions | ||
3 | * | ||
4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
5 | * | ||
6 | * This file is based on the following documentation: | ||
7 | * | ||
8 | * Macintosh Technology in the Common Hardware Reference Platform | ||
9 | * Apple Computer, Inc. | ||
10 | * | ||
11 | * � Copyright 1995 Apple Computer, Inc. All rights reserved. | ||
12 | * | ||
13 | * It's available online from http://chrp.apple.com/MacTech.pdf. | ||
14 | * You can obtain paper copies of this book from computer bookstores or by | ||
15 | * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San | ||
16 | * Francisco, CA 94104. Reference ISBN 1-55860-393-X. | ||
17 | * | ||
18 | * This file is subject to the terms and conditions of the GNU General Public | ||
19 | * License. See the file COPYING in the main directory of this archive | ||
20 | * for more details. | ||
21 | */ | ||
22 | |||
23 | #ifndef _ASMPPC_HYDRA_H | ||
24 | #define _ASMPPC_HYDRA_H | ||
25 | |||
26 | #ifdef __KERNEL__ | ||
27 | |||
28 | struct Hydra { | ||
29 | /* DBDMA Controller Register Space */ | ||
30 | char Pad1[0x30]; | ||
31 | u_int CachePD; | ||
32 | u_int IDs; | ||
33 | u_int Feature_Control; | ||
34 | char Pad2[0x7fc4]; | ||
35 | /* DBDMA Channel Register Space */ | ||
36 | char SCSI_DMA[0x100]; | ||
37 | char Pad3[0x300]; | ||
38 | char SCCA_Tx_DMA[0x100]; | ||
39 | char SCCA_Rx_DMA[0x100]; | ||
40 | char SCCB_Tx_DMA[0x100]; | ||
41 | char SCCB_Rx_DMA[0x100]; | ||
42 | char Pad4[0x7800]; | ||
43 | /* Device Register Space */ | ||
44 | char SCSI[0x1000]; | ||
45 | char ADB[0x1000]; | ||
46 | char SCC_Legacy[0x1000]; | ||
47 | char SCC[0x1000]; | ||
48 | char Pad9[0x2000]; | ||
49 | char VIA[0x2000]; | ||
50 | char Pad10[0x28000]; | ||
51 | char OpenPIC[0x40000]; | ||
52 | }; | ||
53 | |||
54 | extern volatile struct Hydra *Hydra; | ||
55 | |||
56 | |||
57 | /* | ||
58 | * Feature Control Register | ||
59 | */ | ||
60 | |||
61 | #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ | ||
62 | #define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ | ||
63 | #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ | ||
64 | #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ | ||
65 | #define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ | ||
66 | #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ | ||
67 | #define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ | ||
68 | #define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ | ||
69 | #define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ | ||
70 | |||
71 | |||
72 | /* | ||
73 | * OpenPIC Interrupt Sources | ||
74 | */ | ||
75 | |||
76 | #define HYDRA_INT_SIO 0 | ||
77 | #define HYDRA_INT_SCSI_DMA 1 | ||
78 | #define HYDRA_INT_SCCA_TX_DMA 2 | ||
79 | #define HYDRA_INT_SCCA_RX_DMA 3 | ||
80 | #define HYDRA_INT_SCCB_TX_DMA 4 | ||
81 | #define HYDRA_INT_SCCB_RX_DMA 5 | ||
82 | #define HYDRA_INT_SCSI 6 | ||
83 | #define HYDRA_INT_SCCA 7 | ||
84 | #define HYDRA_INT_SCCB 8 | ||
85 | #define HYDRA_INT_VIA 9 | ||
86 | #define HYDRA_INT_ADB 10 | ||
87 | #define HYDRA_INT_ADB_NMI 11 | ||
88 | #define HYDRA_INT_EXT1 12 /* PCI IRQW */ | ||
89 | #define HYDRA_INT_EXT2 13 /* PCI IRQX */ | ||
90 | #define HYDRA_INT_EXT3 14 /* PCI IRQY */ | ||
91 | #define HYDRA_INT_EXT4 15 /* PCI IRQZ */ | ||
92 | #define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */ | ||
93 | #define HYDRA_INT_EXT6 17 /* IDE Secondary */ | ||
94 | #define HYDRA_INT_EXT7 18 /* Power Off Request */ | ||
95 | #define HYDRA_INT_SPARE 19 | ||
96 | |||
97 | extern int hydra_init(void); | ||
98 | extern void macio_adb_init(void); | ||
99 | |||
100 | #endif /* __KERNEL__ */ | ||
101 | |||
102 | #endif /* _ASMPPC_HYDRA_H */ | ||
diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h new file mode 100644 index 000000000000..091b71295de4 --- /dev/null +++ b/include/asm-ppc/i8259.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef _PPC_KERNEL_i8259_H | ||
2 | #define _PPC_KERNEL_i8259_H | ||
3 | |||
4 | #include <linux/irq.h> | ||
5 | |||
6 | extern struct hw_interrupt_type i8259_pic; | ||
7 | |||
8 | extern void i8259_init(long intack_addr); | ||
9 | extern int i8259_irq(struct pt_regs *regs); | ||
10 | |||
11 | #endif /* _PPC_KERNEL_i8259_H */ | ||
diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h new file mode 100644 index 000000000000..bf6efa0417ab --- /dev/null +++ b/include/asm-ppc/ibm403.h | |||
@@ -0,0 +1,479 @@ | |||
1 | /* | ||
2 | * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com> | ||
3 | * | ||
4 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
5 | * the terms of the GNU General Public License version 2. This program | ||
6 | * is licensed "as is" without any warranty of any kind, whether express | ||
7 | * or implied. | ||
8 | */ | ||
9 | |||
10 | |||
11 | #ifdef __KERNEL__ | ||
12 | #ifndef __ASM_IBM403_H__ | ||
13 | #define __ASM_IBM403_H__ | ||
14 | |||
15 | #include <linux/config.h> | ||
16 | |||
17 | #if defined(CONFIG_403GCX) | ||
18 | |||
19 | #define DCRN_BE_BASE 0x090 | ||
20 | #define DCRN_DMA0_BASE 0x0C0 | ||
21 | #define DCRN_DMA1_BASE 0x0C8 | ||
22 | #define DCRN_DMA2_BASE 0x0D0 | ||
23 | #define DCRN_DMA3_BASE 0x0D8 | ||
24 | #define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ | ||
25 | #define DCRN_DMASR_BASE 0x0E0 | ||
26 | |||
27 | #define DCRN_EXIER_BASE 0x042 | ||
28 | #define DCRN_EXISR_BASE 0x040 | ||
29 | #define DCRN_IOCR_BASE 0x0A0 | ||
30 | |||
31 | |||
32 | /* ------------------------------------------------------------------------- */ | ||
33 | #endif | ||
34 | |||
35 | |||
36 | |||
37 | #ifdef DCRN_BE_BASE | ||
38 | #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ | ||
39 | #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ | ||
40 | #endif | ||
41 | /* DCRN_BESR */ | ||
42 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ | ||
43 | #define BESR_DMES 0x40000000 /* DMA Error Status */ | ||
44 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | ||
45 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | ||
46 | #define ET_PROT 0 | ||
47 | #define ET_PARITY 1 | ||
48 | #define ET_NCFG 2 | ||
49 | #define ET_BUSERR 4 | ||
50 | #define ET_BUSTO 6 | ||
51 | |||
52 | #ifdef DCRN_CHCR_BASE | ||
53 | #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ | ||
54 | #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ | ||
55 | #endif | ||
56 | #define CHR1_CETE 0x00800000 /* CPU external timer enable */ | ||
57 | #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ | ||
58 | |||
59 | #ifdef DCRN_CHPSR_BASE | ||
60 | #define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ | ||
61 | #endif | ||
62 | |||
63 | #ifdef DCRN_CIC_BASE | ||
64 | #define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ | ||
65 | #define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ | ||
66 | #define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ | ||
67 | #define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ | ||
68 | #define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ | ||
69 | #define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ | ||
70 | #define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ | ||
71 | #define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ | ||
72 | #define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ | ||
73 | #endif | ||
74 | |||
75 | #ifdef DCRN_CPMFR_BASE | ||
76 | #define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ | ||
77 | #endif | ||
78 | |||
79 | #ifndef CPM_AUD | ||
80 | #define CPM_AUD 0x00000000 | ||
81 | #endif | ||
82 | #ifndef CPM_BRG | ||
83 | #define CPM_BRG 0x00000000 | ||
84 | #endif | ||
85 | #ifndef CPM_CBS | ||
86 | #define CPM_CBS 0x00000000 | ||
87 | #endif | ||
88 | #ifndef CPM_CPU | ||
89 | #define CPM_CPU 0x00000000 | ||
90 | #endif | ||
91 | #ifndef CPM_DCP | ||
92 | #define CPM_DCP 0x00000000 | ||
93 | #endif | ||
94 | #ifndef CPM_DCRX | ||
95 | #define CPM_DCRX 0x00000000 | ||
96 | #endif | ||
97 | #ifndef CPM_DENC | ||
98 | #define CPM_DENC 0x00000000 | ||
99 | #endif | ||
100 | #ifndef CPM_DMA | ||
101 | #define CPM_DMA 0x00000000 | ||
102 | #endif | ||
103 | #ifndef CPM_DSCR | ||
104 | #define CPM_DSCR 0x00000000 | ||
105 | #endif | ||
106 | #ifndef CPM_EBC | ||
107 | #define CPM_EBC 0x00000000 | ||
108 | #endif | ||
109 | #ifndef CPM_EBIU | ||
110 | #define CPM_EBIU 0x00000000 | ||
111 | #endif | ||
112 | #ifndef CPM_EMAC_MM | ||
113 | #define CPM_EMAC_MM 0x00000000 | ||
114 | #endif | ||
115 | #ifndef CPM_EMAC_RM | ||
116 | #define CPM_EMAC_RM 0x00000000 | ||
117 | #endif | ||
118 | #ifndef CPM_EMAC_TM | ||
119 | #define CPM_EMAC_TM 0x00000000 | ||
120 | #endif | ||
121 | #ifndef CPM_GPIO0 | ||
122 | #define CPM_GPIO0 0x00000000 | ||
123 | #endif | ||
124 | #ifndef CPM_GPT | ||
125 | #define CPM_GPT 0x00000000 | ||
126 | #endif | ||
127 | #ifndef CPM_I1284 | ||
128 | #define CPM_I1284 0x00000000 | ||
129 | #endif | ||
130 | #ifndef CPM_IIC0 | ||
131 | #define CPM_IIC0 0x00000000 | ||
132 | #endif | ||
133 | #ifndef CPM_IIC1 | ||
134 | #define CPM_IIC1 0x00000000 | ||
135 | #endif | ||
136 | #ifndef CPM_MSI | ||
137 | #define CPM_MSI 0x00000000 | ||
138 | #endif | ||
139 | #ifndef CPM_PCI | ||
140 | #define CPM_PCI 0x00000000 | ||
141 | #endif | ||
142 | #ifndef CPM_PLB | ||
143 | #define CPM_PLB 0x00000000 | ||
144 | #endif | ||
145 | #ifndef CPM_SC0 | ||
146 | #define CPM_SC0 0x00000000 | ||
147 | #endif | ||
148 | #ifndef CPM_SC1 | ||
149 | #define CPM_SC1 0x00000000 | ||
150 | #endif | ||
151 | #ifndef CPM_SDRAM0 | ||
152 | #define CPM_SDRAM0 0x00000000 | ||
153 | #endif | ||
154 | #ifndef CPM_SDRAM1 | ||
155 | #define CPM_SDRAM1 0x00000000 | ||
156 | #endif | ||
157 | #ifndef CPM_TMRCLK | ||
158 | #define CPM_TMRCLK 0x00000000 | ||
159 | #endif | ||
160 | #ifndef CPM_UART0 | ||
161 | #define CPM_UART0 0x00000000 | ||
162 | #endif | ||
163 | #ifndef CPM_UART1 | ||
164 | #define CPM_UART1 0x00000000 | ||
165 | #endif | ||
166 | #ifndef CPM_UART2 | ||
167 | #define CPM_UART2 0x00000000 | ||
168 | #endif | ||
169 | #ifndef CPM_UIC | ||
170 | #define CPM_UIC 0x00000000 | ||
171 | #endif | ||
172 | #ifndef CPM_VID2 | ||
173 | #define CPM_VID2 0x00000000 | ||
174 | #endif | ||
175 | #ifndef CPM_XPT27 | ||
176 | #define CPM_XPT27 0x00000000 | ||
177 | #endif | ||
178 | #ifndef CPM_XPT54 | ||
179 | #define CPM_XPT54 0x00000000 | ||
180 | #endif | ||
181 | |||
182 | #ifdef DCRN_CPMSR_BASE | ||
183 | #define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ | ||
184 | #define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ | ||
185 | #endif | ||
186 | |||
187 | #ifdef DCRN_DCP0_BASE | ||
188 | #define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ | ||
189 | #define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ | ||
190 | #endif | ||
191 | |||
192 | #ifdef DCRN_DCRX_BASE | ||
193 | #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ | ||
194 | #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ | ||
195 | #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ | ||
196 | #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ | ||
197 | #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ | ||
198 | #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ | ||
199 | #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ | ||
200 | #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ | ||
201 | #endif | ||
202 | |||
203 | #ifdef DCRN_DMA0_BASE | ||
204 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ | ||
205 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ | ||
206 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ | ||
207 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ | ||
208 | #ifdef DCRNCAP_DMA_CC | ||
209 | #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ | ||
210 | #endif | ||
211 | |||
212 | #ifdef DCRNCAP_DMA_SG | ||
213 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ | ||
214 | #endif | ||
215 | #endif | ||
216 | |||
217 | #ifdef DCRN_DMA1_BASE | ||
218 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ | ||
219 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ | ||
220 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ | ||
221 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ | ||
222 | |||
223 | #ifdef DCRNCAP_DMA_CC | ||
224 | #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ | ||
225 | #endif | ||
226 | #ifdef DCRNCAP_DMA_SG | ||
227 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ | ||
228 | #endif | ||
229 | #endif | ||
230 | |||
231 | #ifdef DCRN_DMA2_BASE | ||
232 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ | ||
233 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ | ||
234 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ | ||
235 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ | ||
236 | #ifdef DCRNCAP_DMA_CC | ||
237 | #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ | ||
238 | #endif | ||
239 | #ifdef DCRNCAP_DMA_SG | ||
240 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ | ||
241 | #endif | ||
242 | #endif | ||
243 | |||
244 | #ifdef DCRN_DMA3_BASE | ||
245 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ | ||
246 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ | ||
247 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ | ||
248 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ | ||
249 | #ifdef DCRNCAP_DMA_CC | ||
250 | #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ | ||
251 | #endif | ||
252 | #ifdef DCRNCAP_DMA_SG | ||
253 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ | ||
254 | #endif | ||
255 | #endif | ||
256 | |||
257 | #ifdef DCRN_DMASR_BASE | ||
258 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
259 | #ifdef DCRNCAP_DMA_SG | ||
260 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
261 | /* don't know if these two registers always exist if scatter/gather exists */ | ||
262 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
263 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
264 | #endif | ||
265 | #endif | ||
266 | |||
267 | #ifdef DCRN_EBC_BASE | ||
268 | #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ | ||
269 | #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ | ||
270 | #endif | ||
271 | |||
272 | #ifdef DCRN_EXIER_BASE | ||
273 | #define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ | ||
274 | #endif | ||
275 | |||
276 | #ifdef DCRN_EBIMC_BASE | ||
277 | #define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ | ||
278 | #define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ | ||
279 | #define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ | ||
280 | #define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ | ||
281 | #define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ | ||
282 | #define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ | ||
283 | #define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ | ||
284 | #define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ | ||
285 | #define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ | ||
286 | #define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ | ||
287 | #define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ | ||
288 | #define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ | ||
289 | #define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ | ||
290 | #define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ | ||
291 | #define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ | ||
292 | #define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ | ||
293 | #define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ | ||
294 | #define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ | ||
295 | #define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ | ||
296 | #endif | ||
297 | |||
298 | #ifdef DCRN_EXISR_BASE | ||
299 | #define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ | ||
300 | #endif | ||
301 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ | ||
302 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | ||
303 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | ||
304 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | ||
305 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | ||
306 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | ||
307 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | ||
308 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | ||
309 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | ||
310 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | ||
311 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | ||
312 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | ||
313 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | ||
314 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | ||
315 | |||
316 | #ifdef DCRN_IOCR_BASE | ||
317 | #define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ | ||
318 | #endif | ||
319 | #define IOCR_E0TE 0x80000000 | ||
320 | #define IOCR_E0LP 0x40000000 | ||
321 | #define IOCR_E1TE 0x20000000 | ||
322 | #define IOCR_E1LP 0x10000000 | ||
323 | #define IOCR_E2TE 0x08000000 | ||
324 | #define IOCR_E2LP 0x04000000 | ||
325 | #define IOCR_E3TE 0x02000000 | ||
326 | #define IOCR_E3LP 0x01000000 | ||
327 | #define IOCR_E4TE 0x00800000 | ||
328 | #define IOCR_E4LP 0x00400000 | ||
329 | #define IOCR_EDT 0x00080000 | ||
330 | #define IOCR_SOR 0x00040000 | ||
331 | #define IOCR_EDO 0x00008000 | ||
332 | #define IOCR_2XC 0x00004000 | ||
333 | #define IOCR_ATC 0x00002000 | ||
334 | #define IOCR_SPD 0x00001000 | ||
335 | #define IOCR_BEM 0x00000800 | ||
336 | #define IOCR_PTD 0x00000400 | ||
337 | #define IOCR_ARE 0x00000080 | ||
338 | #define IOCR_DRC 0x00000020 | ||
339 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | ||
340 | #define IOCR_TCS 0x00000004 | ||
341 | #define IOCR_SCS 0x00000002 | ||
342 | #define IOCR_SPC 0x00000001 | ||
343 | |||
344 | #ifdef DCRN_MAL_BASE | ||
345 | #define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ | ||
346 | #define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ | ||
347 | #define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ | ||
348 | #define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ | ||
349 | #define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ | ||
350 | #define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ | ||
351 | #define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ | ||
352 | #define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
353 | #define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ | ||
354 | #define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ | ||
355 | #define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ | ||
356 | #define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
357 | #define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
358 | #define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
359 | #define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
360 | #define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
361 | #endif | ||
362 | /* DCRN_MALCR */ | ||
363 | #define MALCR_MMSR 0x80000000/* MAL Software reset */ | ||
364 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
365 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
366 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
367 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
368 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
369 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
370 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
371 | #define MALCR_PLBLT_2 0x00020000 | ||
372 | #define MALCR_PLBLT_3 0x00010000 | ||
373 | #define MALCR_PLBLT_4 0x00008000 | ||
374 | #define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ | ||
375 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
376 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
377 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
378 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
379 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
380 | /* DCRN_MALESR */ | ||
381 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
382 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
383 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
384 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
385 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
386 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
387 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
388 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
389 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
390 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
391 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
392 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
393 | /* DCRN_MALIER */ | ||
394 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
395 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
396 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
397 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
398 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
399 | /* DCRN_MALTXEOBISR */ | ||
400 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
401 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
402 | |||
403 | #ifdef DCRN_OCM0_BASE | ||
404 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
405 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
406 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
407 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
408 | #endif | ||
409 | |||
410 | #ifdef DCRN_PLB0_BASE | ||
411 | #define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) | ||
412 | #define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) | ||
413 | /* doesn't exist on stb03xxx? */ | ||
414 | #define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) | ||
415 | #endif | ||
416 | |||
417 | #ifdef DCRN_PLB1_BASE | ||
418 | #define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) | ||
419 | #define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) | ||
420 | /* doesn't exist on stb03xxx? */ | ||
421 | #define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) | ||
422 | #endif | ||
423 | |||
424 | #ifdef DCRN_PLLMR_BASE | ||
425 | #define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ | ||
426 | #endif | ||
427 | |||
428 | #ifdef DCRN_POB0_BASE | ||
429 | #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) | ||
430 | #define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) | ||
431 | #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) | ||
432 | #endif | ||
433 | |||
434 | #ifdef DCRN_SCCR_BASE | ||
435 | #define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) | ||
436 | #endif | ||
437 | |||
438 | #ifdef DCRN_SDRAM0_BASE | ||
439 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ | ||
440 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ | ||
441 | #endif | ||
442 | |||
443 | #ifdef DCRN_UIC0_BASE | ||
444 | #define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) | ||
445 | #define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) | ||
446 | #define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) | ||
447 | #define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) | ||
448 | #define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) | ||
449 | #define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) | ||
450 | #define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) | ||
451 | #define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) | ||
452 | #endif | ||
453 | |||
454 | #ifdef DCRN_UIC1_BASE | ||
455 | #define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) | ||
456 | #define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) | ||
457 | #define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) | ||
458 | #define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) | ||
459 | #define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) | ||
460 | #define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) | ||
461 | #define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) | ||
462 | #define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) | ||
463 | #define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) | ||
464 | #endif | ||
465 | |||
466 | #ifdef DCRN_SDRAM0_BASE | ||
467 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ | ||
468 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ | ||
469 | #endif | ||
470 | |||
471 | #ifdef DCRN_OCM0_BASE | ||
472 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
473 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
474 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
475 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
476 | #endif | ||
477 | |||
478 | #endif /* __ASM_IBM403_H__ */ | ||
479 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm405.h b/include/asm-ppc/ibm405.h new file mode 100644 index 000000000000..4e5be9e2c153 --- /dev/null +++ b/include/asm-ppc/ibm405.h | |||
@@ -0,0 +1,299 @@ | |||
1 | /* | ||
2 | * Author: Armin Kuster <akuster@mvista.com> | ||
3 | * | ||
4 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
5 | * the terms of the GNU General Public License version 2. This program | ||
6 | * is licensed "as is" without any warranty of any kind, whether express | ||
7 | * or implied. | ||
8 | */ | ||
9 | |||
10 | #ifdef __KERNEL__ | ||
11 | #ifndef __ASM_IBM405_H__ | ||
12 | #define __ASM_IBM405_H__ | ||
13 | |||
14 | #ifdef DCRN_BE_BASE | ||
15 | #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ | ||
16 | #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ | ||
17 | #endif | ||
18 | /* DCRN_BESR */ | ||
19 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ | ||
20 | #define BESR_DMES 0x40000000 /* DMA Error Status */ | ||
21 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | ||
22 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | ||
23 | #define ET_PROT 0 | ||
24 | #define ET_PARITY 1 | ||
25 | #define ET_NCFG 2 | ||
26 | #define ET_BUSERR 4 | ||
27 | #define ET_BUSTO 6 | ||
28 | |||
29 | /* Clock and power management shifts for emacs */ | ||
30 | #define IBM_CPM_EMMII 0 /* Shift value for MII */ | ||
31 | #define IBM_CPM_EMRX 1 /* Shift value for recv */ | ||
32 | #define IBM_CPM_EMTX 2 /* Shift value for MAC */ | ||
33 | |||
34 | #ifdef DCRN_CHCR_BASE | ||
35 | #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ | ||
36 | #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ | ||
37 | #endif | ||
38 | #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ | ||
39 | |||
40 | #ifdef DCRN_CHPSR_BASE | ||
41 | #define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ | ||
42 | #endif | ||
43 | |||
44 | #ifdef DCRN_CPMFR_BASE | ||
45 | #define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ | ||
46 | #endif | ||
47 | |||
48 | #ifdef DCRN_CPMSR_BASE | ||
49 | #define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ | ||
50 | #define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ | ||
51 | #endif | ||
52 | |||
53 | #ifdef DCRN_DCP0_BASE | ||
54 | /* Decompression Controller Address */ | ||
55 | #define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) | ||
56 | /* Decompression Controller Data */ | ||
57 | #define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) | ||
58 | #else | ||
59 | #define DCRN_DCP0_CFGADDR 0x0 | ||
60 | #define DCRN_DCP0_CFGDATA 0x0 | ||
61 | #endif | ||
62 | |||
63 | #ifdef DCRN_DMA0_BASE | ||
64 | /* DMA Channel Control Register 0 */ | ||
65 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) | ||
66 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ | ||
67 | /* DMA Destination Address Register 0 */ | ||
68 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) | ||
69 | /* DMA Source Address Register 0 */ | ||
70 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) | ||
71 | #ifdef DCRNCAP_DMA_CC | ||
72 | /* DMA Chained Count Register 0 */ | ||
73 | #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) | ||
74 | #endif | ||
75 | #ifdef DCRNCAP_DMA_SG | ||
76 | /* DMA Scatter/Gather Descriptor Addr 0 */ | ||
77 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) | ||
78 | #endif | ||
79 | #endif | ||
80 | |||
81 | #ifdef DCRN_DMA1_BASE | ||
82 | /* DMA Channel Control Register 1 */ | ||
83 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) | ||
84 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ | ||
85 | /* DMA Destination Address Register 1 */ | ||
86 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) | ||
87 | /* DMA Source Address Register 1 */ | ||
88 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ | ||
89 | #ifdef DCRNCAP_DMA_CC | ||
90 | /* DMA Chained Count Register 1 */ | ||
91 | #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) | ||
92 | #endif | ||
93 | #ifdef DCRNCAP_DMA_SG | ||
94 | /* DMA Scatter/Gather Descriptor Addr 1 */ | ||
95 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) | ||
96 | #endif | ||
97 | #endif | ||
98 | |||
99 | #ifdef DCRN_DMA2_BASE | ||
100 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ | ||
101 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ | ||
102 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ | ||
103 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ | ||
104 | #ifdef DCRNCAP_DMA_CC | ||
105 | #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ | ||
106 | #endif | ||
107 | #ifdef DCRNCAP_DMA_SG | ||
108 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ | ||
109 | #endif | ||
110 | #endif | ||
111 | |||
112 | #ifdef DCRN_DMA3_BASE | ||
113 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ | ||
114 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ | ||
115 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ | ||
116 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ | ||
117 | #ifdef DCRNCAP_DMA_CC | ||
118 | #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ | ||
119 | #endif | ||
120 | #ifdef DCRNCAP_DMA_SG | ||
121 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ | ||
122 | #endif | ||
123 | #endif | ||
124 | |||
125 | #ifdef DCRN_DMASR_BASE | ||
126 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
127 | #ifdef DCRNCAP_DMA_SG | ||
128 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
129 | /* don't know if these two registers always exist if scatter/gather exists */ | ||
130 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
131 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
132 | #endif | ||
133 | #endif | ||
134 | |||
135 | #ifdef DCRN_EBC_BASE | ||
136 | #define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ | ||
137 | #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ | ||
138 | #endif | ||
139 | |||
140 | #ifdef DCRN_EXIER_BASE | ||
141 | #define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ | ||
142 | #endif | ||
143 | |||
144 | #ifdef DCRN_EXISR_BASE | ||
145 | #define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ | ||
146 | #endif | ||
147 | |||
148 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ | ||
149 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | ||
150 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | ||
151 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | ||
152 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | ||
153 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | ||
154 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | ||
155 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | ||
156 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | ||
157 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | ||
158 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | ||
159 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | ||
160 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | ||
161 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | ||
162 | |||
163 | #ifdef DCRN_IOCR_BASE | ||
164 | #define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ | ||
165 | #endif | ||
166 | #define IOCR_E0TE 0x80000000 | ||
167 | #define IOCR_E0LP 0x40000000 | ||
168 | #define IOCR_E1TE 0x20000000 | ||
169 | #define IOCR_E1LP 0x10000000 | ||
170 | #define IOCR_E2TE 0x08000000 | ||
171 | #define IOCR_E2LP 0x04000000 | ||
172 | #define IOCR_E3TE 0x02000000 | ||
173 | #define IOCR_E3LP 0x01000000 | ||
174 | #define IOCR_E4TE 0x00800000 | ||
175 | #define IOCR_E4LP 0x00400000 | ||
176 | #define IOCR_EDT 0x00080000 | ||
177 | #define IOCR_SOR 0x00040000 | ||
178 | #define IOCR_EDO 0x00008000 | ||
179 | #define IOCR_2XC 0x00004000 | ||
180 | #define IOCR_ATC 0x00002000 | ||
181 | #define IOCR_SPD 0x00001000 | ||
182 | #define IOCR_BEM 0x00000800 | ||
183 | #define IOCR_PTD 0x00000400 | ||
184 | #define IOCR_ARE 0x00000080 | ||
185 | #define IOCR_DRC 0x00000020 | ||
186 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | ||
187 | #define IOCR_TCS 0x00000004 | ||
188 | #define IOCR_SCS 0x00000002 | ||
189 | #define IOCR_SPC 0x00000001 | ||
190 | |||
191 | #define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */ | ||
192 | #define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */ | ||
193 | #define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */ | ||
194 | #define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */ | ||
195 | #define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */ | ||
196 | #define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */ | ||
197 | #define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */ | ||
198 | #define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
199 | #define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */ | ||
200 | #define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */ | ||
201 | #define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */ | ||
202 | #define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
203 | #define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
204 | #define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */ | ||
205 | #define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
206 | #define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
207 | #define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */ | ||
208 | #define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */ | ||
209 | #define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
210 | #define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */ | ||
211 | |||
212 | /* DCRN_MALCR */ | ||
213 | #define MALCR_MMSR 0x80000000 /* MAL Software reset */ | ||
214 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
215 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
216 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
217 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
218 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
219 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
220 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
221 | #define MALCR_PLBLT_2 0x00020000 | ||
222 | #define MALCR_PLBLT_3 0x00010000 | ||
223 | #define MALCR_PLBLT_4 0x00008000 | ||
224 | #define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ | ||
225 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
226 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
227 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
228 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
229 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
230 | /* DCRN_MALESR */ | ||
231 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
232 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
233 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
234 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
235 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
236 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
237 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
238 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
239 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
240 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
241 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
242 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
243 | /* DCRN_MALIER */ | ||
244 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
245 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
246 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
247 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
248 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
249 | /* DCRN_MALTXEOBISR */ | ||
250 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
251 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
252 | |||
253 | #ifdef DCRN_PLB0_BASE | ||
254 | #define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) | ||
255 | #define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) | ||
256 | /* doesn't exist on stb03xxx? */ | ||
257 | #define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) | ||
258 | #endif | ||
259 | |||
260 | #ifdef DCRN_PLB1_BASE | ||
261 | #define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) | ||
262 | #define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) | ||
263 | /* doesn't exist on stb03xxx? */ | ||
264 | #define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) | ||
265 | #endif | ||
266 | |||
267 | #ifdef DCRN_PLLMR_BASE | ||
268 | #define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ | ||
269 | #endif | ||
270 | |||
271 | #ifdef DCRN_POB0_BASE | ||
272 | #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) | ||
273 | #define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) | ||
274 | #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) | ||
275 | #endif | ||
276 | |||
277 | #define DCRN_UIC_SR(base) (base + 0x0) | ||
278 | #define DCRN_UIC_ER(base) (base + 0x2) | ||
279 | #define DCRN_UIC_CR(base) (base + 0x3) | ||
280 | #define DCRN_UIC_PR(base) (base + 0x4) | ||
281 | #define DCRN_UIC_TR(base) (base + 0x5) | ||
282 | #define DCRN_UIC_MSR(base) (base + 0x6) | ||
283 | #define DCRN_UIC_VR(base) (base + 0x7) | ||
284 | #define DCRN_UIC_VCR(base) (base + 0x8) | ||
285 | |||
286 | #ifdef DCRN_SDRAM0_BASE | ||
287 | #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ | ||
288 | #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ | ||
289 | #endif | ||
290 | |||
291 | #ifdef DCRN_OCM0_BASE | ||
292 | #define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ | ||
293 | #define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ | ||
294 | #define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ | ||
295 | #define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ | ||
296 | #endif | ||
297 | |||
298 | #endif /* __ASM_IBM405_H__ */ | ||
299 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h new file mode 100644 index 000000000000..87f051138b9d --- /dev/null +++ b/include/asm-ppc/ibm44x.h | |||
@@ -0,0 +1,599 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ibm44x.h | ||
3 | * | ||
4 | * PPC44x definitions | ||
5 | * | ||
6 | * Matt Porter <mporter@kernel.crashing.org> | ||
7 | * | ||
8 | * Copyright 2002-2005 MontaVista Software Inc. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_IBM44x_H__ | ||
18 | #define __ASM_IBM44x_H__ | ||
19 | |||
20 | #include <linux/config.h> | ||
21 | |||
22 | #ifndef NR_BOARD_IRQS | ||
23 | #define NR_BOARD_IRQS 0 | ||
24 | #endif | ||
25 | |||
26 | #define _IO_BASE isa_io_base | ||
27 | #define _ISA_MEM_BASE isa_mem_base | ||
28 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
29 | |||
30 | /* TLB entry offset/size used for pinning kernel lowmem */ | ||
31 | #define PPC44x_PIN_SHIFT 28 | ||
32 | #define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT) | ||
33 | |||
34 | /* Lowest TLB slot consumed by the default pinned TLBs */ | ||
35 | #define PPC44x_LOW_SLOT 63 | ||
36 | |||
37 | /* LS 32-bits of UART0 physical address location for early serial text debug */ | ||
38 | #ifdef CONFIG_440SP | ||
39 | #define UART0_PHYS_IO_BASE 0xf0000200 | ||
40 | #else | ||
41 | #define UART0_PHYS_IO_BASE 0x40000200 | ||
42 | #endif | ||
43 | |||
44 | /* | ||
45 | * XXX This 36-bit trap stuff will move somewhere in syslib/ | ||
46 | * when we rework/abstract the PPC44x PCI-X handling -mdp | ||
47 | */ | ||
48 | |||
49 | /* | ||
50 | * Standard 4GB "page" definitions | ||
51 | */ | ||
52 | #ifdef CONFIG_440SP | ||
53 | #define PPC44x_IO_PAGE 0x0000000100000000ULL | ||
54 | #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL | ||
55 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
56 | #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL | ||
57 | #else | ||
58 | #define PPC44x_IO_PAGE 0x0000000100000000ULL | ||
59 | #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL | ||
60 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
61 | #define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL | ||
62 | #endif | ||
63 | |||
64 | /* | ||
65 | * 36-bit trap ranges | ||
66 | */ | ||
67 | #ifdef CONFIG_440SP | ||
68 | #define PPC44x_IO_LO 0xf0000000UL | ||
69 | #define PPC44x_IO_HI 0xf0000fffUL | ||
70 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL | ||
71 | #define PPC44x_PCI0CFG_HI 0x0ec00007UL | ||
72 | #define PPC44x_PCI1CFG_LO 0x1ec00000UL | ||
73 | #define PPC44x_PCI1CFG_HI 0x1ec00007UL | ||
74 | #define PPC44x_PCI2CFG_LO 0x2ec00000UL | ||
75 | #define PPC44x_PCI2CFG_HI 0x2ec00007UL | ||
76 | #define PPC44x_PCIMEM_LO 0x80000000UL | ||
77 | #define PPC44x_PCIMEM_HI 0xdfffffffUL | ||
78 | #else | ||
79 | #define PPC44x_IO_LO 0x40000000UL | ||
80 | #define PPC44x_IO_HI 0x40000fffUL | ||
81 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL | ||
82 | #define PPC44x_PCI0CFG_HI 0x0ec00007UL | ||
83 | #define PPC44x_PCIMEM_LO 0x80002000UL | ||
84 | #define PPC44x_PCIMEM_HI 0xffffffffUL | ||
85 | #endif | ||
86 | |||
87 | /* | ||
88 | * The "residual" board information structure the boot loader passes | ||
89 | * into the kernel. | ||
90 | */ | ||
91 | #ifndef __ASSEMBLY__ | ||
92 | |||
93 | /* | ||
94 | * DCRN definitions | ||
95 | */ | ||
96 | |||
97 | |||
98 | /* CPRs (440GX and 440SP) */ | ||
99 | #define DCRN_CPR_CONFIG_ADDR 0xc | ||
100 | #define DCRN_CPR_CONFIG_DATA 0xd | ||
101 | |||
102 | #define DCRN_CPR_CLKUPD 0x0020 | ||
103 | #define DCRN_CPR_PLLC 0x0040 | ||
104 | #define DCRN_CPR_PLLD 0x0060 | ||
105 | #define DCRN_CPR_PRIMAD 0x0080 | ||
106 | #define DCRN_CPR_PRIMBD 0x00a0 | ||
107 | #define DCRN_CPR_OPBD 0x00c0 | ||
108 | #define DCRN_CPR_PERD 0x00e0 | ||
109 | #define DCRN_CPR_MALD 0x0100 | ||
110 | |||
111 | /* CPRs read/write helper macros */ | ||
112 | #define CPR_READ(offset) ({\ | ||
113 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ | ||
114 | mfdcr(DCRN_CPR_CONFIG_DATA);}) | ||
115 | #define CPR_WRITE(offset, data) ({\ | ||
116 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ | ||
117 | mtdcr(DCRN_CPR_CONFIG_DATA, data);}) | ||
118 | |||
119 | /* SDRs (440GX and 440SP) */ | ||
120 | #define DCRN_SDR_CONFIG_ADDR 0xe | ||
121 | #define DCRN_SDR_CONFIG_DATA 0xf | ||
122 | #define DCRN_SDR_PFC0 0x4100 | ||
123 | #define DCRN_SDR_PFC1 0x4101 | ||
124 | #define DCRN_SDR_PFC1_EPS 0x1c00000 | ||
125 | #define DCRN_SDR_PFC1_EPS_SHIFT 22 | ||
126 | #define DCRN_SDR_PFC1_RMII 0x02000000 | ||
127 | #define DCRN_SDR_MFR 0x4300 | ||
128 | #define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ | ||
129 | #define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ | ||
130 | #define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ | ||
131 | #define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ | ||
132 | #define DCRN_SDR_MFR_T0TXFL 0x00080000 | ||
133 | #define DCRN_SDR_MFR_T0TXFH 0x00040000 | ||
134 | #define DCRN_SDR_MFR_T1TXFL 0x00020000 | ||
135 | #define DCRN_SDR_MFR_T1TXFH 0x00010000 | ||
136 | #define DCRN_SDR_MFR_E0TXFL 0x00008000 | ||
137 | #define DCRN_SDR_MFR_E0TXFH 0x00004000 | ||
138 | #define DCRN_SDR_MFR_E0RXFL 0x00002000 | ||
139 | #define DCRN_SDR_MFR_E0RXFH 0x00001000 | ||
140 | #define DCRN_SDR_MFR_E1TXFL 0x00000800 | ||
141 | #define DCRN_SDR_MFR_E1TXFH 0x00000400 | ||
142 | #define DCRN_SDR_MFR_E1RXFL 0x00000200 | ||
143 | #define DCRN_SDR_MFR_E1RXFH 0x00000100 | ||
144 | #define DCRN_SDR_MFR_E2TXFL 0x00000080 | ||
145 | #define DCRN_SDR_MFR_E2TXFH 0x00000040 | ||
146 | #define DCRN_SDR_MFR_E2RXFL 0x00000020 | ||
147 | #define DCRN_SDR_MFR_E2RXFH 0x00000010 | ||
148 | #define DCRN_SDR_MFR_E3TXFL 0x00000008 | ||
149 | #define DCRN_SDR_MFR_E3TXFH 0x00000004 | ||
150 | #define DCRN_SDR_MFR_E3RXFL 0x00000002 | ||
151 | #define DCRN_SDR_MFR_E3RXFH 0x00000001 | ||
152 | #define DCRN_SDR_UART0 0x0120 | ||
153 | #define DCRN_SDR_UART1 0x0121 | ||
154 | |||
155 | /* SDR read/write helper macros */ | ||
156 | #define SDR_READ(offset) ({\ | ||
157 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ | ||
158 | mfdcr(DCRN_SDR_CONFIG_DATA);}) | ||
159 | #define SDR_WRITE(offset, data) ({\ | ||
160 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ | ||
161 | mtdcr(DCRN_SDR_CONFIG_DATA,data);}) | ||
162 | |||
163 | /* DMA (excluding 440SP) */ | ||
164 | #define DCRN_DMA0_BASE 0x100 | ||
165 | #define DCRN_DMA1_BASE 0x108 | ||
166 | #define DCRN_DMA2_BASE 0x110 | ||
167 | #define DCRN_DMA3_BASE 0x118 | ||
168 | #define DCRN_DMASR_BASE 0x120 | ||
169 | #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ | ||
170 | #define DCRN_MAL_BASE 0x180 | ||
171 | |||
172 | /* UIC */ | ||
173 | #define DCRN_UIC0_BASE 0xc0 | ||
174 | #define DCRN_UIC1_BASE 0xd0 | ||
175 | #define DCRN_UIC2_BASE 0x210 | ||
176 | #define DCRN_UICB_BASE 0x200 | ||
177 | #define UIC0 DCRN_UIC0_BASE | ||
178 | #define UIC1 DCRN_UIC1_BASE | ||
179 | #define UIC2 DCRN_UIC2_BASE | ||
180 | #define UICB DCRN_UICB_BASE | ||
181 | |||
182 | #define DCRN_UIC_SR(base) (base + 0x0) | ||
183 | #define DCRN_UIC_ER(base) (base + 0x2) | ||
184 | #define DCRN_UIC_CR(base) (base + 0x3) | ||
185 | #define DCRN_UIC_PR(base) (base + 0x4) | ||
186 | #define DCRN_UIC_TR(base) (base + 0x5) | ||
187 | #define DCRN_UIC_MSR(base) (base + 0x6) | ||
188 | #define DCRN_UIC_VR(base) (base + 0x7) | ||
189 | #define DCRN_UIC_VCR(base) (base + 0x8) | ||
190 | |||
191 | #define UIC0_UIC1NC 0x00000002 | ||
192 | |||
193 | #define UICB_UIC0NC 0x40000000 | ||
194 | #define UICB_UIC1NC 0x10000000 | ||
195 | #define UICB_UIC2NC 0x04000000 | ||
196 | |||
197 | /* 440 MAL DCRs */ | ||
198 | #define DCRN_MALCR(base) (base + 0x0) /* Configuration */ | ||
199 | #define DCRN_MALESR(base) (base + 0x1) /* Error Status */ | ||
200 | #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ | ||
201 | #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ | ||
202 | #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ | ||
203 | #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ | ||
204 | #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ | ||
205 | #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ | ||
206 | #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ | ||
207 | #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ | ||
208 | #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ | ||
209 | #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ | ||
210 | #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ | ||
211 | #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ | ||
212 | #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ | ||
213 | #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ | ||
214 | #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ | ||
215 | #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ | ||
216 | #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ | ||
217 | |||
218 | /* Compatibility DCRN's */ | ||
219 | #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ | ||
220 | #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ | ||
221 | #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ | ||
222 | #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ | ||
223 | #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ | ||
224 | #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ | ||
225 | #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ | ||
226 | #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ | ||
227 | |||
228 | #define MALCR_MMSR 0x80000000 /* MAL Software reset */ | ||
229 | #define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ | ||
230 | #define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ | ||
231 | #define MALCR_PLBP_3 0x00C00000 /* highest */ | ||
232 | #define MALCR_GA 0x00200000 /* Guarded Active Bit */ | ||
233 | #define MALCR_OA 0x00100000 /* Ordered Active Bit */ | ||
234 | #define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ | ||
235 | #define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ | ||
236 | #define MALCR_PLBLT_2 0x00020000 | ||
237 | #define MALCR_PLBLT_3 0x00010000 | ||
238 | #define MALCR_PLBLT_4 0x00008000 | ||
239 | #ifdef CONFIG_440GP | ||
240 | #define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ | ||
241 | #else | ||
242 | #define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ | ||
243 | #endif | ||
244 | #define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ | ||
245 | #define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ | ||
246 | #define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ | ||
247 | #define MALCR_LEA 0x00000002 /* Locked Error Active */ | ||
248 | #define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ | ||
249 | /* DCRN_MALESR */ | ||
250 | #define MALESR_EVB 0x80000000 /* Error Valid Bit */ | ||
251 | #define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ | ||
252 | #define MALESR_DE 0x00100000 /* Descriptor Error */ | ||
253 | #define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ | ||
254 | #define MALESR_OTE 0x00040000 /* OPB Timeout Error */ | ||
255 | #define MALESR_OSE 0x00020000 /* OPB Slave Error */ | ||
256 | #define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ | ||
257 | #define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ | ||
258 | #define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ | ||
259 | #define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ | ||
260 | #define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ | ||
261 | #define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ | ||
262 | /* DCRN_MALIER */ | ||
263 | #define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ | ||
264 | #define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ | ||
265 | #define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ | ||
266 | #define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ | ||
267 | #define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ | ||
268 | /* DCRN_MALTXEOBISR */ | ||
269 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | ||
270 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | ||
271 | |||
272 | /* 440GP/GX PLB Arbiter DCRs */ | ||
273 | #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ | ||
274 | #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ | ||
275 | #define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ | ||
276 | #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ | ||
277 | #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ | ||
278 | #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ | ||
279 | |||
280 | /* 440GP/GX PLB to OPB bridge DCRs */ | ||
281 | #define DCRN_POB0_BESR0 0x090 | ||
282 | #define DCRN_POB0_BESR1 0x094 | ||
283 | #define DCRN_POB0_BEARL 0x092 | ||
284 | #define DCRN_POB0_BEARH 0x093 | ||
285 | |||
286 | /* 440GP/GX OPB to PLB bridge DCRs */ | ||
287 | #define DCRN_OPB0_BSTAT 0x0a9 | ||
288 | #define DCRN_OPB0_BEARL 0x0aa | ||
289 | #define DCRN_OPB0_BEARH 0x0ab | ||
290 | |||
291 | /* 440GP Clock, PM, chip control */ | ||
292 | #define DCRN_CPC0_SR 0x0b0 | ||
293 | #define DCRN_CPC0_ER 0x0b1 | ||
294 | #define DCRN_CPC0_FR 0x0b2 | ||
295 | #define DCRN_CPC0_SYS0 0x0e0 | ||
296 | #define DCRN_CPC0_SYS1 0x0e1 | ||
297 | #define DCRN_CPC0_CUST0 0x0e2 | ||
298 | #define DCRN_CPC0_CUST1 0x0e3 | ||
299 | #define DCRN_CPC0_STRP0 0x0e4 | ||
300 | #define DCRN_CPC0_STRP1 0x0e5 | ||
301 | #define DCRN_CPC0_STRP2 0x0e6 | ||
302 | #define DCRN_CPC0_STRP3 0x0e7 | ||
303 | #define DCRN_CPC0_GPIO 0x0e8 | ||
304 | #define DCRN_CPC0_PLB 0x0e9 | ||
305 | #define DCRN_CPC0_CR1 0x0ea | ||
306 | #define DCRN_CPC0_CR0 0x0eb | ||
307 | #define DCRN_CPC0_MIRQ0 0x0ec | ||
308 | #define DCRN_CPC0_MIRQ1 0x0ed | ||
309 | #define DCRN_CPC0_JTAGID 0x0ef | ||
310 | |||
311 | /* 440GP DMA controller DCRs */ | ||
312 | #define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ | ||
313 | #define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ | ||
314 | #define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ | ||
315 | #define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ | ||
316 | #define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ | ||
317 | #define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ | ||
318 | #define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ | ||
319 | #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ | ||
320 | |||
321 | #define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ | ||
322 | #define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ | ||
323 | #define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ | ||
324 | #define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ | ||
325 | #define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ | ||
326 | #define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ | ||
327 | #define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ | ||
328 | #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ | ||
329 | |||
330 | #define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ | ||
331 | #define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ | ||
332 | #define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ | ||
333 | #define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ | ||
334 | #define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ | ||
335 | #define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ | ||
336 | #define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ | ||
337 | #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ | ||
338 | |||
339 | #define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ | ||
340 | #define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ | ||
341 | #define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ | ||
342 | #define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ | ||
343 | #define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ | ||
344 | #define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ | ||
345 | #define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ | ||
346 | #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ | ||
347 | |||
348 | #define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ | ||
349 | #define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ | ||
350 | #define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ | ||
351 | #define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ | ||
352 | |||
353 | /* 440GP/440GX SDRAM controller DCRs */ | ||
354 | #define DCRN_SDRAM0_CFGADDR 0x010 | ||
355 | #define DCRN_SDRAM0_CFGDATA 0x011 | ||
356 | |||
357 | #define SDRAM0_B0CR 0x40 | ||
358 | #define SDRAM0_B1CR 0x44 | ||
359 | #define SDRAM0_B2CR 0x48 | ||
360 | #define SDRAM0_B3CR 0x4c | ||
361 | |||
362 | #define SDRAM_CONFIG_BANK_ENABLE 0x00000001 | ||
363 | #define SDRAM_CONFIG_SIZE_MASK 0x000e0000 | ||
364 | #define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) | ||
365 | #define SDRAM_CONFIG_SIZE_8M 0x00000001 | ||
366 | #define SDRAM_CONFIG_SIZE_16M 0x00000002 | ||
367 | #define SDRAM_CONFIG_SIZE_32M 0x00000003 | ||
368 | #define SDRAM_CONFIG_SIZE_64M 0x00000004 | ||
369 | #define SDRAM_CONFIG_SIZE_128M 0x00000005 | ||
370 | #define SDRAM_CONFIG_SIZE_256M 0x00000006 | ||
371 | #define SDRAM_CONFIG_SIZE_512M 0x00000007 | ||
372 | #define PPC44x_MEM_SIZE_8M 0x00800000 | ||
373 | #define PPC44x_MEM_SIZE_16M 0x01000000 | ||
374 | #define PPC44x_MEM_SIZE_32M 0x02000000 | ||
375 | #define PPC44x_MEM_SIZE_64M 0x04000000 | ||
376 | #define PPC44x_MEM_SIZE_128M 0x08000000 | ||
377 | #define PPC44x_MEM_SIZE_256M 0x10000000 | ||
378 | #define PPC44x_MEM_SIZE_512M 0x20000000 | ||
379 | #define PPC44x_MEM_SIZE_1G 0x40000000 | ||
380 | #define PPC44x_MEM_SIZE_2G 0x80000000 | ||
381 | |||
382 | /* 440SP memory controller DCRs */ | ||
383 | #define DCRN_MQ0_BS0BAS 0x40 | ||
384 | #define DCRN_MQ0_BS1BAS 0x41 | ||
385 | |||
386 | #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 | ||
387 | #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 | ||
388 | #define MQ0_CONFIG_SIZE_16M 0x0000ff80 | ||
389 | #define MQ0_CONFIG_SIZE_32M 0x0000ff00 | ||
390 | #define MQ0_CONFIG_SIZE_64M 0x0000fe00 | ||
391 | #define MQ0_CONFIG_SIZE_128M 0x0000fc00 | ||
392 | #define MQ0_CONFIG_SIZE_256M 0x0000f800 | ||
393 | #define MQ0_CONFIG_SIZE_512M 0x0000f000 | ||
394 | #define MQ0_CONFIG_SIZE_1G 0x0000e000 | ||
395 | #define MQ0_CONFIG_SIZE_2G 0x0000c000 | ||
396 | |||
397 | /* Internal SRAM Controller 440GX/440SP */ | ||
398 | #ifdef CONFIG_440SP | ||
399 | #define DCRN_SRAM0_BASE 0x100 | ||
400 | #else /* 440GX */ | ||
401 | #define DCRN_SRAM0_BASE 0x000 | ||
402 | #endif | ||
403 | |||
404 | #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) | ||
405 | #define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) | ||
406 | #define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022) | ||
407 | #define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023) | ||
408 | #define SRAM_SBCR_BAS0 0x80000000 | ||
409 | #define SRAM_SBCR_BAS1 0x80010000 | ||
410 | #define SRAM_SBCR_BAS2 0x80020000 | ||
411 | #define SRAM_SBCR_BAS3 0x80030000 | ||
412 | #define SRAM_SBCR_BU_MASK 0x00000180 | ||
413 | #define SRAM_SBCR_BS_64KB 0x00000800 | ||
414 | #define SRAM_SBCR_BU_RO 0x00000080 | ||
415 | #define SRAM_SBCR_BU_RW 0x00000180 | ||
416 | #define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024) | ||
417 | #define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025) | ||
418 | #define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026) | ||
419 | #define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027) | ||
420 | #define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028) | ||
421 | #define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029) | ||
422 | #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) | ||
423 | #define SRAM_DPC_ENABLE 0x80000000 | ||
424 | |||
425 | /* L2 Cache Controller 440GX/440SP */ | ||
426 | #define DCRN_L2C0_CFG 0x030 | ||
427 | #define L2C_CFG_L2M 0x80000000 | ||
428 | #define L2C_CFG_ICU 0x40000000 | ||
429 | #define L2C_CFG_DCU 0x20000000 | ||
430 | #define L2C_CFG_DCW_MASK 0x1e000000 | ||
431 | #define L2C_CFG_TPC 0x01000000 | ||
432 | #define L2C_CFG_CPC 0x00800000 | ||
433 | #define L2C_CFG_FRAN 0x00200000 | ||
434 | #define L2C_CFG_SS_MASK 0x00180000 | ||
435 | #define L2C_CFG_SS_256 0x00000000 | ||
436 | #define L2C_CFG_CPIM 0x00040000 | ||
437 | #define L2C_CFG_TPIM 0x00020000 | ||
438 | #define L2C_CFG_LIM 0x00010000 | ||
439 | #define L2C_CFG_PMUX_MASK 0x00007000 | ||
440 | #define L2C_CFG_PMUX_SNP 0x00000000 | ||
441 | #define L2C_CFG_PMUX_IF 0x00001000 | ||
442 | #define L2C_CFG_PMUX_DF 0x00002000 | ||
443 | #define L2C_CFG_PMUX_DS 0x00003000 | ||
444 | #define L2C_CFG_PMIM 0x00000800 | ||
445 | #define L2C_CFG_TPEI 0x00000400 | ||
446 | #define L2C_CFG_CPEI 0x00000200 | ||
447 | #define L2C_CFG_NAM 0x00000100 | ||
448 | #define L2C_CFG_SMCM 0x00000080 | ||
449 | #define L2C_CFG_NBRM 0x00000040 | ||
450 | #define DCRN_L2C0_CMD 0x031 | ||
451 | #define L2C_CMD_CLR 0x80000000 | ||
452 | #define L2C_CMD_DIAG 0x40000000 | ||
453 | #define L2C_CMD_INV 0x20000000 | ||
454 | #define L2C_CMD_CCP 0x10000000 | ||
455 | #define L2C_CMD_CTE 0x08000000 | ||
456 | #define L2C_CMD_STRC 0x04000000 | ||
457 | #define L2C_CMD_STPC 0x02000000 | ||
458 | #define L2C_CMD_RPMC 0x01000000 | ||
459 | #define L2C_CMD_HCC 0x00800000 | ||
460 | #define DCRN_L2C0_ADDR 0x032 | ||
461 | #define DCRN_L2C0_DATA 0x033 | ||
462 | #define DCRN_L2C0_SR 0x034 | ||
463 | #define L2C_SR_CC 0x80000000 | ||
464 | #define L2C_SR_CPE 0x40000000 | ||
465 | #define L2C_SR_TPE 0x20000000 | ||
466 | #define L2C_SR_LRU 0x10000000 | ||
467 | #define L2C_SR_PCS 0x08000000 | ||
468 | #define DCRN_L2C0_REVID 0x035 | ||
469 | #define DCRN_L2C0_SNP0 0x036 | ||
470 | #define DCRN_L2C0_SNP1 0x037 | ||
471 | #define L2C_SNP_BA_MASK 0xffff0000 | ||
472 | #define L2C_SNP_SSR_MASK 0x0000f000 | ||
473 | #define L2C_SNP_SSR_32G 0x0000f000 | ||
474 | #define L2C_SNP_ESR 0x00000800 | ||
475 | |||
476 | /* | ||
477 | * PCI-X definitions | ||
478 | */ | ||
479 | #define PCIX0_CFGA 0x0ec00000UL | ||
480 | #define PCIX1_CFGA 0x1ec00000UL | ||
481 | #define PCIX2_CFGA 0x2ec00000UL | ||
482 | #define PCIX0_CFGD 0x0ec00004UL | ||
483 | #define PCIX1_CFGD 0x1ec00004UL | ||
484 | #define PCIX2_CFGD 0x2ec00004UL | ||
485 | |||
486 | #define PCIX0_IO_BASE 0x0000000908000000ULL | ||
487 | #define PCIX1_IO_BASE 0x0000000908000000ULL | ||
488 | #define PCIX2_IO_BASE 0x0000000908000000ULL | ||
489 | #define PCIX_IO_SIZE 0x00010000 | ||
490 | |||
491 | #ifdef CONFIG_440SP | ||
492 | #define PCIX0_REG_BASE 0x000000090ec80000ULL | ||
493 | #else | ||
494 | #define PCIX0_REG_BASE 0x000000020ec80000ULL | ||
495 | #endif | ||
496 | #define PCIX_REG_OFFSET 0x10000000 | ||
497 | #define PCIX_REG_SIZE 0x200 | ||
498 | |||
499 | #define PCIX0_VENDID 0x000 | ||
500 | #define PCIX0_DEVID 0x002 | ||
501 | #define PCIX0_COMMAND 0x004 | ||
502 | #define PCIX0_STATUS 0x006 | ||
503 | #define PCIX0_REVID 0x008 | ||
504 | #define PCIX0_CLS 0x009 | ||
505 | #define PCIX0_CACHELS 0x00c | ||
506 | #define PCIX0_LATTIM 0x00d | ||
507 | #define PCIX0_HDTYPE 0x00e | ||
508 | #define PCIX0_BIST 0x00f | ||
509 | #define PCIX0_BAR0L 0x010 | ||
510 | #define PCIX0_BAR0H 0x014 | ||
511 | #define PCIX0_BAR1 0x018 | ||
512 | #define PCIX0_BAR2L 0x01c | ||
513 | #define PCIX0_BAR2H 0x020 | ||
514 | #define PCIX0_BAR3 0x024 | ||
515 | #define PCIX0_CISPTR 0x028 | ||
516 | #define PCIX0_SBSYSVID 0x02c | ||
517 | #define PCIX0_SBSYSID 0x02e | ||
518 | #define PCIX0_EROMBA 0x030 | ||
519 | #define PCIX0_CAP 0x034 | ||
520 | #define PCIX0_RES0 0x035 | ||
521 | #define PCIX0_RES1 0x036 | ||
522 | #define PCIX0_RES2 0x038 | ||
523 | #define PCIX0_INTLN 0x03c | ||
524 | #define PCIX0_INTPN 0x03d | ||
525 | #define PCIX0_MINGNT 0x03e | ||
526 | #define PCIX0_MAXLTNCY 0x03f | ||
527 | #define PCIX0_BRDGOPT1 0x040 | ||
528 | #define PCIX0_BRDGOPT2 0x044 | ||
529 | #define PCIX0_ERREN 0x050 | ||
530 | #define PCIX0_ERRSTS 0x054 | ||
531 | #define PCIX0_PLBBESR 0x058 | ||
532 | #define PCIX0_PLBBEARL 0x05c | ||
533 | #define PCIX0_PLBBEARH 0x060 | ||
534 | #define PCIX0_POM0LAL 0x068 | ||
535 | #define PCIX0_POM0LAH 0x06c | ||
536 | #define PCIX0_POM0SA 0x070 | ||
537 | #define PCIX0_POM0PCIAL 0x074 | ||
538 | #define PCIX0_POM0PCIAH 0x078 | ||
539 | #define PCIX0_POM1LAL 0x07c | ||
540 | #define PCIX0_POM1LAH 0x080 | ||
541 | #define PCIX0_POM1SA 0x084 | ||
542 | #define PCIX0_POM1PCIAL 0x088 | ||
543 | #define PCIX0_POM1PCIAH 0x08c | ||
544 | #define PCIX0_POM2SA 0x090 | ||
545 | #define PCIX0_PIM0SAL 0x098 | ||
546 | #define PCIX0_PIM0SA PCIX0_PIM0SAL | ||
547 | #define PCIX0_PIM0LAL 0x09c | ||
548 | #define PCIX0_PIM0LAH 0x0a0 | ||
549 | #define PCIX0_PIM1SA 0x0a4 | ||
550 | #define PCIX0_PIM1LAL 0x0a8 | ||
551 | #define PCIX0_PIM1LAH 0x0ac | ||
552 | #define PCIX0_PIM2SAL 0x0b0 | ||
553 | #define PCIX0_PIM2SA PCIX0_PIM2SAL | ||
554 | #define PCIX0_PIM2LAL 0x0b4 | ||
555 | #define PCIX0_PIM2LAH 0x0b8 | ||
556 | #define PCIX0_OMCAPID 0x0c0 | ||
557 | #define PCIX0_OMNIPTR 0x0c1 | ||
558 | #define PCIX0_OMMC 0x0c2 | ||
559 | #define PCIX0_OMMA 0x0c4 | ||
560 | #define PCIX0_OMMUA 0x0c8 | ||
561 | #define PCIX0_OMMDATA 0x0cc | ||
562 | #define PCIX0_OMMEOI 0x0ce | ||
563 | #define PCIX0_PMCAPID 0x0d0 | ||
564 | #define PCIX0_PMNIPTR 0x0d1 | ||
565 | #define PCIX0_PMC 0x0d2 | ||
566 | #define PCIX0_PMCSR 0x0d4 | ||
567 | #define PCIX0_PMCSRBSE 0x0d6 | ||
568 | #define PCIX0_PMDATA 0x0d7 | ||
569 | #define PCIX0_PMSCRR 0x0d8 | ||
570 | #define PCIX0_CAPID 0x0dc | ||
571 | #define PCIX0_NIPTR 0x0dd | ||
572 | #define PCIX0_CMD 0x0de | ||
573 | #define PCIX0_STS 0x0e0 | ||
574 | #define PCIX0_IDR 0x0e4 | ||
575 | #define PCIX0_CID 0x0e8 | ||
576 | #define PCIX0_RID 0x0ec | ||
577 | #define PCIX0_PIM0SAH 0x0f8 | ||
578 | #define PCIX0_PIM2SAH 0x0fc | ||
579 | #define PCIX0_MSGIL 0x100 | ||
580 | #define PCIX0_MSGIH 0x104 | ||
581 | #define PCIX0_MSGOL 0x108 | ||
582 | #define PCIX0_MSGOH 0x10c | ||
583 | #define PCIX0_IM 0x1f8 | ||
584 | |||
585 | #define IIC_OWN 0x55 | ||
586 | #define IIC_CLOCK 50 | ||
587 | |||
588 | #undef NR_UICS | ||
589 | #ifdef CONFIG_440GX | ||
590 | #define NR_UICS 3 | ||
591 | #else | ||
592 | #define NR_UICS 2 | ||
593 | #endif | ||
594 | |||
595 | #include <asm/ibm4xx.h> | ||
596 | |||
597 | #endif /* __ASSEMBLY__ */ | ||
598 | #endif /* __ASM_IBM44x_H__ */ | ||
599 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h new file mode 100644 index 000000000000..35260afa33a9 --- /dev/null +++ b/include/asm-ppc/ibm4xx.h | |||
@@ -0,0 +1,124 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | ||
4 | * | ||
5 | * Module name: ibm4xx.h | ||
6 | * | ||
7 | * Description: | ||
8 | * A generic include file which pulls in appropriate include files | ||
9 | * for specific board types based on configuration settings. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | #ifndef __ASM_IBM4XX_H__ | ||
15 | #define __ASM_IBM4XX_H__ | ||
16 | |||
17 | #include <linux/config.h> | ||
18 | #include <asm/types.h> | ||
19 | |||
20 | #ifdef CONFIG_40x | ||
21 | |||
22 | #if defined(CONFIG_ASH) | ||
23 | #include <platforms/4xx/ash.h> | ||
24 | #endif | ||
25 | |||
26 | #if defined(CONFIG_BUBINGA) | ||
27 | #include <platforms/4xx/bubinga.h> | ||
28 | #endif | ||
29 | |||
30 | #if defined(CONFIG_CPCI405) | ||
31 | #include <platforms/4xx/cpci405.h> | ||
32 | #endif | ||
33 | |||
34 | #if defined(CONFIG_EP405) | ||
35 | #include <platforms/4xx/ep405.h> | ||
36 | #endif | ||
37 | |||
38 | #if defined(CONFIG_OAK) | ||
39 | #include <platforms/4xx/oak.h> | ||
40 | #endif | ||
41 | |||
42 | #if defined(CONFIG_REDWOOD_4) | ||
43 | #include <platforms/4xx/redwood.h> | ||
44 | #endif | ||
45 | |||
46 | #if defined(CONFIG_REDWOOD_5) | ||
47 | #include <platforms/4xx/redwood5.h> | ||
48 | #endif | ||
49 | |||
50 | #if defined(CONFIG_REDWOOD_6) | ||
51 | #include <platforms/4xx/redwood6.h> | ||
52 | #endif | ||
53 | |||
54 | #if defined(CONFIG_SYCAMORE) | ||
55 | #include <platforms/4xx/sycamore.h> | ||
56 | #endif | ||
57 | |||
58 | #if defined(CONFIG_WALNUT) | ||
59 | #include <platforms/4xx/walnut.h> | ||
60 | #endif | ||
61 | |||
62 | #if defined(CONFIG_XILINX_ML300) | ||
63 | #include <platforms/4xx/xilinx_ml300.h> | ||
64 | #endif | ||
65 | |||
66 | #ifndef __ASSEMBLY__ | ||
67 | |||
68 | #ifdef CONFIG_40x | ||
69 | /* | ||
70 | * The "residual" board information structure the boot loader passes | ||
71 | * into the kernel. | ||
72 | */ | ||
73 | extern bd_t __res; | ||
74 | #endif | ||
75 | |||
76 | void ppc4xx_setup_arch(void); | ||
77 | void ppc4xx_map_io(void); | ||
78 | void ppc4xx_init_IRQ(void); | ||
79 | void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, | ||
80 | unsigned long r6, unsigned long r7); | ||
81 | #endif | ||
82 | |||
83 | #ifndef PPC4xx_MACHINE_NAME | ||
84 | #define PPC4xx_MACHINE_NAME "Unidentified 4xx class" | ||
85 | #endif | ||
86 | |||
87 | |||
88 | /* IO_BASE is for PCI I/O. | ||
89 | * ISA not supported, just here to resolve copilation. | ||
90 | */ | ||
91 | |||
92 | #ifndef _IO_BASE | ||
93 | #define _IO_BASE 0xe8000000 /* The PCI address window */ | ||
94 | #define _ISA_MEM_BASE 0 | ||
95 | #define PCI_DRAM_OFFSET 0 | ||
96 | #endif | ||
97 | |||
98 | #elif CONFIG_44x | ||
99 | |||
100 | #if defined(CONFIG_EBONY) | ||
101 | #include <platforms/4xx/ebony.h> | ||
102 | #endif | ||
103 | |||
104 | #if defined(CONFIG_LUAN) | ||
105 | #include <platforms/4xx/luan.h> | ||
106 | #endif | ||
107 | |||
108 | #if defined(CONFIG_OCOTEA) | ||
109 | #include <platforms/4xx/ocotea.h> | ||
110 | #endif | ||
111 | |||
112 | #ifndef __ASSEMBLY__ | ||
113 | #ifdef CONFIG_40x | ||
114 | /* | ||
115 | * The "residual" board information structure the boot loader passes | ||
116 | * into the kernel. | ||
117 | */ | ||
118 | extern bd_t __res; | ||
119 | #endif | ||
120 | #endif | ||
121 | #endif /* CONFIG_40x */ | ||
122 | |||
123 | #endif /* __ASM_IBM4XX_H__ */ | ||
124 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h new file mode 100644 index 000000000000..8c61d93043af --- /dev/null +++ b/include/asm-ppc/ibm_ocp.h | |||
@@ -0,0 +1,163 @@ | |||
1 | /* | ||
2 | * ibm_ocp.h | ||
3 | * | ||
4 | * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) | ||
5 | * Mipsys - France | ||
6 | * | ||
7 | * Derived from work (c) Armin Kuster akuster@pacbell.net | ||
8 | * | ||
9 | * Additional support and port to 2.6 LDM/sysfs by | ||
10 | * Matt Porter <mporter@kernel.crashing.org> | ||
11 | * Copyright 2003-2004 MontaVista Software, Inc. | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify it | ||
14 | * under the terms of the GNU General Public License as published by the | ||
15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
16 | * option) any later version. | ||
17 | * | ||
18 | */ | ||
19 | #ifdef __KERNEL__ | ||
20 | #ifndef __IBM_OCP_H__ | ||
21 | #define __IBM_OCP_H__ | ||
22 | |||
23 | #include <asm/types.h> | ||
24 | |||
25 | /* | ||
26 | * IBM 4xx OCP system information | ||
27 | */ | ||
28 | struct ocp_sys_info_data { | ||
29 | int opb_bus_freq; /* OPB Bus Frequency (Hz) */ | ||
30 | int ebc_bus_freq; /* EBC Bus Frequency (Hz) */ | ||
31 | }; | ||
32 | |||
33 | extern struct ocp_sys_info_data ocp_sys_info; | ||
34 | |||
35 | /* | ||
36 | * EMAC additional data and sysfs support | ||
37 | * | ||
38 | * Note about mdio_idx: When you have a zmii, it's usually | ||
39 | * not necessary, it covers the case of the 405EP which has | ||
40 | * the MDIO lines on EMAC0 only | ||
41 | * | ||
42 | * Note about phy_map: Per EMAC map of PHY ids which should | ||
43 | * be probed by emac_probe. Different EMACs can have | ||
44 | * overlapping maps. | ||
45 | * | ||
46 | * Note, this map uses inverse logic for bits: | ||
47 | * 0 - id should be probed | ||
48 | * 1 - id should be ignored | ||
49 | * | ||
50 | * Default value of 0x00000000 - will result in usual | ||
51 | * auto-detection logic. | ||
52 | * | ||
53 | */ | ||
54 | |||
55 | struct ocp_func_emac_data { | ||
56 | int rgmii_idx; /* RGMII device index or -1 */ | ||
57 | int rgmii_mux; /* RGMII input of this EMAC */ | ||
58 | int zmii_idx; /* ZMII device index or -1 */ | ||
59 | int zmii_mux; /* ZMII input of this EMAC */ | ||
60 | int mal_idx; /* MAL device index */ | ||
61 | int mal_rx_chan; /* MAL rx channel number */ | ||
62 | int mal_tx_chan; /* MAL tx channel number */ | ||
63 | int wol_irq; /* WOL interrupt */ | ||
64 | int mdio_idx; /* EMAC idx of MDIO master or -1 */ | ||
65 | int tah_idx; /* TAH device index or -1 */ | ||
66 | int jumbo; /* Jumbo frames capable flag */ | ||
67 | int phy_mode; /* PHY type or configurable mode */ | ||
68 | u8 mac_addr[6]; /* EMAC mac address */ | ||
69 | u32 phy_map; /* EMAC phy map */ | ||
70 | }; | ||
71 | |||
72 | /* Sysfs support */ | ||
73 | #define OCP_SYSFS_EMAC_DATA() \ | ||
74 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ | ||
75 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ | ||
76 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ | ||
77 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ | ||
78 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ | ||
79 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ | ||
80 | OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ | ||
81 | \ | ||
82 | void ocp_show_emac_data(struct device *dev) \ | ||
83 | { \ | ||
84 | device_create_file(dev, &dev_attr_emac_zmii_idx); \ | ||
85 | device_create_file(dev, &dev_attr_emac_zmii_mux); \ | ||
86 | device_create_file(dev, &dev_attr_emac_mal_idx); \ | ||
87 | device_create_file(dev, &dev_attr_emac_mal_rx_chan); \ | ||
88 | device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ | ||
89 | device_create_file(dev, &dev_attr_emac_wol_irq); \ | ||
90 | device_create_file(dev, &dev_attr_emac_mdio_idx); \ | ||
91 | } | ||
92 | |||
93 | #ifdef CONFIG_40x | ||
94 | /* | ||
95 | * Helper function to copy MAC addresses from the bd_t to OCP EMAC | ||
96 | * additions. | ||
97 | * | ||
98 | * The range of EMAC indices (inclusive) to be copied are the arguments. | ||
99 | */ | ||
100 | static inline void ibm_ocp_set_emac(int start, int end) | ||
101 | { | ||
102 | int i; | ||
103 | struct ocp_def *def; | ||
104 | |||
105 | /* Copy MAC addresses to EMAC additions */ | ||
106 | for (i=start; i<=end; i++) { | ||
107 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); | ||
108 | memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, | ||
109 | &__res.bi_enetaddr[i], | ||
110 | 6); | ||
111 | } | ||
112 | } | ||
113 | #endif | ||
114 | |||
115 | /* | ||
116 | * MAL additional data and sysfs support | ||
117 | */ | ||
118 | struct ocp_func_mal_data { | ||
119 | int num_tx_chans; /* Number of TX channels */ | ||
120 | int num_rx_chans; /* Number of RX channels */ | ||
121 | int txeob_irq; /* TX End Of Buffer IRQ */ | ||
122 | int rxeob_irq; /* RX End Of Buffer IRQ */ | ||
123 | int txde_irq; /* TX Descriptor Error IRQ */ | ||
124 | int rxde_irq; /* RX Descriptor Error IRQ */ | ||
125 | int serr_irq; /* MAL System Error IRQ */ | ||
126 | }; | ||
127 | |||
128 | #define OCP_SYSFS_MAL_DATA() \ | ||
129 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \ | ||
130 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \ | ||
131 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \ | ||
132 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ | ||
133 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ | ||
134 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ | ||
135 | OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ | ||
136 | \ | ||
137 | void ocp_show_mal_data(struct device *dev) \ | ||
138 | { \ | ||
139 | device_create_file(dev, &dev_attr_mal_num_tx_chans); \ | ||
140 | device_create_file(dev, &dev_attr_mal_num_rx_chans); \ | ||
141 | device_create_file(dev, &dev_attr_mal_txeob_irq); \ | ||
142 | device_create_file(dev, &dev_attr_mal_rxeob_irq); \ | ||
143 | device_create_file(dev, &dev_attr_mal_txde_irq); \ | ||
144 | device_create_file(dev, &dev_attr_mal_rxde_irq); \ | ||
145 | device_create_file(dev, &dev_attr_mal_serr_irq); \ | ||
146 | } | ||
147 | |||
148 | /* | ||
149 | * IIC additional data and sysfs support | ||
150 | */ | ||
151 | struct ocp_func_iic_data { | ||
152 | int fast_mode; /* IIC fast mode enabled */ | ||
153 | }; | ||
154 | |||
155 | #define OCP_SYSFS_IIC_DATA() \ | ||
156 | OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ | ||
157 | \ | ||
158 | void ocp_show_iic_data(struct device *dev) \ | ||
159 | { \ | ||
160 | device_create_file(dev, &dev_attr_iic_fast_mode); \ | ||
161 | } | ||
162 | #endif /* __IBM_OCP_H__ */ | ||
163 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ibm_ocp_pci.h b/include/asm-ppc/ibm_ocp_pci.h new file mode 100644 index 000000000000..a81ab6144358 --- /dev/null +++ b/include/asm-ppc/ibm_ocp_pci.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Author: Armin Kuster <akuster@mvista.com> | ||
3 | * | ||
4 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
5 | * the terms of the GNU General Public License version 2. This program | ||
6 | * is licensed "as is" without any warranty of any kind, whether express | ||
7 | * or implied. | ||
8 | */ | ||
9 | |||
10 | #ifdef __KERNEL__ | ||
11 | #ifndef __ASM_IBM_OCP_PCI_H__ | ||
12 | #define __ASM_IBM_OCP_PCI_H__ | ||
13 | |||
14 | /* PCI 32 */ | ||
15 | |||
16 | struct pmm_regs { | ||
17 | u32 la; | ||
18 | u32 ma; | ||
19 | u32 pcila; | ||
20 | u32 pciha; | ||
21 | }; | ||
22 | |||
23 | typedef struct pcil0_regs { | ||
24 | struct pmm_regs pmm[3]; | ||
25 | u32 ptm1ms; | ||
26 | u32 ptm1la; | ||
27 | u32 ptm2ms; | ||
28 | u32 ptm2la; | ||
29 | } pci0_t; | ||
30 | |||
31 | #endif /* __ASM_IBM_OCP_PCI_H__ */ | ||
32 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ide.h b/include/asm-ppc/ide.h new file mode 100644 index 000000000000..7d6e6599fac4 --- /dev/null +++ b/include/asm-ppc/ide.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * linux/include/asm-ppc/ide.h | ||
3 | * | ||
4 | * Copyright (C) 1994-1996 Linus Torvalds & authors */ | ||
5 | |||
6 | /* | ||
7 | * This file contains the ppc architecture specific IDE code. | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASMPPC_IDE_H | ||
11 | #define __ASMPPC_IDE_H | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | |||
15 | #include <linux/sched.h> | ||
16 | #include <asm/mpc8xx.h> | ||
17 | |||
18 | #ifndef MAX_HWIFS | ||
19 | #define MAX_HWIFS 8 | ||
20 | #endif | ||
21 | |||
22 | #include <linux/config.h> | ||
23 | #include <linux/hdreg.h> | ||
24 | #include <linux/ioport.h> | ||
25 | #include <asm/io.h> | ||
26 | |||
27 | extern void __ide_mm_insw(void __iomem *port, void *addr, u32 count); | ||
28 | extern void __ide_mm_outsw(void __iomem *port, void *addr, u32 count); | ||
29 | extern void __ide_mm_insl(void __iomem *port, void *addr, u32 count); | ||
30 | extern void __ide_mm_outsl(void __iomem *port, void *addr, u32 count); | ||
31 | |||
32 | struct ide_machdep_calls { | ||
33 | int (*default_irq)(unsigned long base); | ||
34 | unsigned long (*default_io_base)(int index); | ||
35 | void (*ide_init_hwif)(hw_regs_t *hw, | ||
36 | unsigned long data_port, | ||
37 | unsigned long ctrl_port, | ||
38 | int *irq); | ||
39 | }; | ||
40 | |||
41 | extern struct ide_machdep_calls ppc_ide_md; | ||
42 | |||
43 | #undef SUPPORT_SLOW_DATA_PORTS | ||
44 | #define SUPPORT_SLOW_DATA_PORTS 0 | ||
45 | |||
46 | #define IDE_ARCH_OBSOLETE_DEFAULTS | ||
47 | |||
48 | static __inline__ int ide_default_irq(unsigned long base) | ||
49 | { | ||
50 | if (ppc_ide_md.default_irq) | ||
51 | return ppc_ide_md.default_irq(base); | ||
52 | return 0; | ||
53 | } | ||
54 | |||
55 | static __inline__ unsigned long ide_default_io_base(int index) | ||
56 | { | ||
57 | if (ppc_ide_md.default_io_base) | ||
58 | return ppc_ide_md.default_io_base(index); | ||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | #define IDE_ARCH_OBSOLETE_INIT | ||
63 | #define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */ | ||
64 | |||
65 | #ifdef CONFIG_PCI | ||
66 | #define ide_init_default_irq(base) (0) | ||
67 | #else | ||
68 | #define ide_init_default_irq(base) ide_default_irq(base) | ||
69 | #endif | ||
70 | |||
71 | #if (defined CONFIG_APUS || defined CONFIG_BLK_DEV_MPC8xx_IDE ) | ||
72 | #define IDE_ARCH_ACK_INTR 1 | ||
73 | #define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1) | ||
74 | #endif | ||
75 | |||
76 | #endif /* __KERNEL__ */ | ||
77 | |||
78 | #endif /* __ASMPPC_IDE_H */ | ||
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h new file mode 100644 index 000000000000..50fb5e47094a --- /dev/null +++ b/include/asm-ppc/immap_85xx.h | |||
@@ -0,0 +1,126 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/immap_85xx.h | ||
3 | * | ||
4 | * MPC85xx Internal Memory Map | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | ||
7 | * | ||
8 | * Copyright 2004 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | * | ||
15 | */ | ||
16 | |||
17 | #ifdef __KERNEL__ | ||
18 | #ifndef __ASM_IMMAP_85XX_H__ | ||
19 | #define __ASM_IMMAP_85XX_H__ | ||
20 | |||
21 | /* Eventually this should define all the IO block registers in 85xx */ | ||
22 | |||
23 | /* PCI Registers */ | ||
24 | typedef struct ccsr_pci { | ||
25 | uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ | ||
26 | uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ | ||
27 | uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | ||
28 | char res1[3060]; | ||
29 | uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ | ||
30 | uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ | ||
31 | uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ | ||
32 | char res2[4]; | ||
33 | uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ | ||
34 | char res3[12]; | ||
35 | uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ | ||
36 | uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ | ||
37 | uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ | ||
38 | char res4[4]; | ||
39 | uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ | ||
40 | char res5[12]; | ||
41 | uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ | ||
42 | uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ | ||
43 | uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ | ||
44 | char res6[4]; | ||
45 | uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ | ||
46 | char res7[12]; | ||
47 | uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ | ||
48 | uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ | ||
49 | uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ | ||
50 | char res8[4]; | ||
51 | uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ | ||
52 | char res9[12]; | ||
53 | uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ | ||
54 | uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ | ||
55 | uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ | ||
56 | char res10[4]; | ||
57 | uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ | ||
58 | char res11[268]; | ||
59 | uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ | ||
60 | char res12[4]; | ||
61 | uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ | ||
62 | uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ | ||
63 | uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ | ||
64 | char res13[12]; | ||
65 | uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ | ||
66 | char res14[4]; | ||
67 | uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ | ||
68 | uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ | ||
69 | uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ | ||
70 | char res15[12]; | ||
71 | uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ | ||
72 | char res16[4]; | ||
73 | uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ | ||
74 | char res17[4]; | ||
75 | uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ | ||
76 | char res18[12]; | ||
77 | uint err_dr; /* 0x.e00 - PCI Error Detect Register */ | ||
78 | uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ | ||
79 | uint err_en; /* 0x.e08 - PCI Error Enable Register */ | ||
80 | uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ | ||
81 | uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ | ||
82 | uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ | ||
83 | uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ | ||
84 | uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ | ||
85 | uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ | ||
86 | uint pci_timr; /* 0x.e24 - PCI Timer Register */ | ||
87 | char res19[472]; | ||
88 | } ccsr_pci_t; | ||
89 | |||
90 | /* Global Utility Registers */ | ||
91 | typedef struct ccsr_guts { | ||
92 | uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | ||
93 | uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | ||
94 | uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ | ||
95 | uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ | ||
96 | uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | ||
97 | char res1[12]; | ||
98 | uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ | ||
99 | char res2[12]; | ||
100 | uint gpiocr; /* 0x.0030 - GPIO Control Register */ | ||
101 | char res3[12]; | ||
102 | uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ | ||
103 | char res4[12]; | ||
104 | uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ | ||
105 | char res5[12]; | ||
106 | uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ | ||
107 | char res6[12]; | ||
108 | uint devdisr; /* 0x.0070 - Device Disable Control */ | ||
109 | char res7[12]; | ||
110 | uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ | ||
111 | char res8[12]; | ||
112 | uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | ||
113 | char res9[12]; | ||
114 | uint pvr; /* 0x.00a0 - Processor Version Register */ | ||
115 | uint svr; /* 0x.00a4 - System Version Register */ | ||
116 | char res10[3416]; | ||
117 | uint clkocr; /* 0x.0e00 - Clock Out Select Register */ | ||
118 | char res11[12]; | ||
119 | uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | ||
120 | char res12[12]; | ||
121 | uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | ||
122 | char res13[61916]; | ||
123 | } ccsr_guts_t; | ||
124 | |||
125 | #endif /* __ASM_IMMAP_85XX_H__ */ | ||
126 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/immap_cpm2.h b/include/asm-ppc/immap_cpm2.h new file mode 100644 index 000000000000..3c23d9cb47a6 --- /dev/null +++ b/include/asm-ppc/immap_cpm2.h | |||
@@ -0,0 +1,648 @@ | |||
1 | /* | ||
2 | * CPM2 Internal Memory Map | ||
3 | * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) | ||
4 | * | ||
5 | * The Internal Memory Map for devices with CPM2 on them. This | ||
6 | * is the superset of all CPM2 devices (8260, 8266, 8280, 8272, | ||
7 | * 8560). | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef __IMMAP_CPM2__ | ||
11 | #define __IMMAP_CPM2__ | ||
12 | |||
13 | /* System configuration registers. | ||
14 | */ | ||
15 | typedef struct sys_82xx_conf { | ||
16 | u32 sc_siumcr; | ||
17 | u32 sc_sypcr; | ||
18 | u8 res1[6]; | ||
19 | u16 sc_swsr; | ||
20 | u8 res2[20]; | ||
21 | u32 sc_bcr; | ||
22 | u8 sc_ppc_acr; | ||
23 | u8 res3[3]; | ||
24 | u32 sc_ppc_alrh; | ||
25 | u32 sc_ppc_alrl; | ||
26 | u8 sc_lcl_acr; | ||
27 | u8 res4[3]; | ||
28 | u32 sc_lcl_alrh; | ||
29 | u32 sc_lcl_alrl; | ||
30 | u32 sc_tescr1; | ||
31 | u32 sc_tescr2; | ||
32 | u32 sc_ltescr1; | ||
33 | u32 sc_ltescr2; | ||
34 | u32 sc_pdtea; | ||
35 | u8 sc_pdtem; | ||
36 | u8 res5[3]; | ||
37 | u32 sc_ldtea; | ||
38 | u8 sc_ldtem; | ||
39 | u8 res6[163]; | ||
40 | } sysconf_82xx_cpm2_t; | ||
41 | |||
42 | typedef struct sys_85xx_conf { | ||
43 | u32 sc_cear; | ||
44 | u16 sc_ceer; | ||
45 | u16 sc_cemr; | ||
46 | u8 res1[70]; | ||
47 | u32 sc_smaer; | ||
48 | u8 res2[4]; | ||
49 | u32 sc_smevr; | ||
50 | u32 sc_smctr; | ||
51 | u32 sc_lmaer; | ||
52 | u8 res3[4]; | ||
53 | u32 sc_lmevr; | ||
54 | u32 sc_lmctr; | ||
55 | u8 res4[144]; | ||
56 | } sysconf_85xx_cpm2_t; | ||
57 | |||
58 | typedef union sys_conf { | ||
59 | sysconf_82xx_cpm2_t siu_82xx; | ||
60 | sysconf_85xx_cpm2_t siu_85xx; | ||
61 | } sysconf_cpm2_t; | ||
62 | |||
63 | |||
64 | |||
65 | /* Memory controller registers. | ||
66 | */ | ||
67 | typedef struct mem_ctlr { | ||
68 | u32 memc_br0; | ||
69 | u32 memc_or0; | ||
70 | u32 memc_br1; | ||
71 | u32 memc_or1; | ||
72 | u32 memc_br2; | ||
73 | u32 memc_or2; | ||
74 | u32 memc_br3; | ||
75 | u32 memc_or3; | ||
76 | u32 memc_br4; | ||
77 | u32 memc_or4; | ||
78 | u32 memc_br5; | ||
79 | u32 memc_or5; | ||
80 | u32 memc_br6; | ||
81 | u32 memc_or6; | ||
82 | u32 memc_br7; | ||
83 | u32 memc_or7; | ||
84 | u32 memc_br8; | ||
85 | u32 memc_or8; | ||
86 | u32 memc_br9; | ||
87 | u32 memc_or9; | ||
88 | u32 memc_br10; | ||
89 | u32 memc_or10; | ||
90 | u32 memc_br11; | ||
91 | u32 memc_or11; | ||
92 | u8 res1[8]; | ||
93 | u32 memc_mar; | ||
94 | u8 res2[4]; | ||
95 | u32 memc_mamr; | ||
96 | u32 memc_mbmr; | ||
97 | u32 memc_mcmr; | ||
98 | u8 res3[8]; | ||
99 | u16 memc_mptpr; | ||
100 | u8 res4[2]; | ||
101 | u32 memc_mdr; | ||
102 | u8 res5[4]; | ||
103 | u32 memc_psdmr; | ||
104 | u32 memc_lsdmr; | ||
105 | u8 memc_purt; | ||
106 | u8 res6[3]; | ||
107 | u8 memc_psrt; | ||
108 | u8 res7[3]; | ||
109 | u8 memc_lurt; | ||
110 | u8 res8[3]; | ||
111 | u8 memc_lsrt; | ||
112 | u8 res9[3]; | ||
113 | u32 memc_immr; | ||
114 | u32 memc_pcibr0; | ||
115 | u32 memc_pcibr1; | ||
116 | u8 res10[16]; | ||
117 | u32 memc_pcimsk0; | ||
118 | u32 memc_pcimsk1; | ||
119 | u8 res11[52]; | ||
120 | } memctl_cpm2_t; | ||
121 | |||
122 | /* System Integration Timers. | ||
123 | */ | ||
124 | typedef struct sys_int_timers { | ||
125 | u8 res1[32]; | ||
126 | u16 sit_tmcntsc; | ||
127 | u8 res2[2]; | ||
128 | u32 sit_tmcnt; | ||
129 | u8 res3[4]; | ||
130 | u32 sit_tmcntal; | ||
131 | u8 res4[16]; | ||
132 | u16 sit_piscr; | ||
133 | u8 res5[2]; | ||
134 | u32 sit_pitc; | ||
135 | u32 sit_pitr; | ||
136 | u8 res6[94]; | ||
137 | u8 res7[390]; | ||
138 | } sit_cpm2_t; | ||
139 | |||
140 | #define PISCR_PIRQ_MASK ((u16)0xff00) | ||
141 | #define PISCR_PS ((u16)0x0080) | ||
142 | #define PISCR_PIE ((u16)0x0004) | ||
143 | #define PISCR_PTF ((u16)0x0002) | ||
144 | #define PISCR_PTE ((u16)0x0001) | ||
145 | |||
146 | /* PCI Controller. | ||
147 | */ | ||
148 | typedef struct pci_ctlr { | ||
149 | u32 pci_omisr; | ||
150 | u32 pci_omimr; | ||
151 | u8 res1[8]; | ||
152 | u32 pci_ifqpr; | ||
153 | u32 pci_ofqpr; | ||
154 | u8 res2[8]; | ||
155 | u32 pci_imr0; | ||
156 | u32 pci_imr1; | ||
157 | u32 pci_omr0; | ||
158 | u32 pci_omr1; | ||
159 | u32 pci_odr; | ||
160 | u8 res3[4]; | ||
161 | u32 pci_idr; | ||
162 | u8 res4[20]; | ||
163 | u32 pci_imisr; | ||
164 | u32 pci_imimr; | ||
165 | u8 res5[24]; | ||
166 | u32 pci_ifhpr; | ||
167 | u8 res6[4]; | ||
168 | u32 pci_iftpr; | ||
169 | u8 res7[4]; | ||
170 | u32 pci_iphpr; | ||
171 | u8 res8[4]; | ||
172 | u32 pci_iptpr; | ||
173 | u8 res9[4]; | ||
174 | u32 pci_ofhpr; | ||
175 | u8 res10[4]; | ||
176 | u32 pci_oftpr; | ||
177 | u8 res11[4]; | ||
178 | u32 pci_ophpr; | ||
179 | u8 res12[4]; | ||
180 | u32 pci_optpr; | ||
181 | u8 res13[8]; | ||
182 | u32 pci_mucr; | ||
183 | u8 res14[8]; | ||
184 | u32 pci_qbar; | ||
185 | u8 res15[12]; | ||
186 | u32 pci_dmamr0; | ||
187 | u32 pci_dmasr0; | ||
188 | u32 pci_dmacdar0; | ||
189 | u8 res16[4]; | ||
190 | u32 pci_dmasar0; | ||
191 | u8 res17[4]; | ||
192 | u32 pci_dmadar0; | ||
193 | u8 res18[4]; | ||
194 | u32 pci_dmabcr0; | ||
195 | u32 pci_dmandar0; | ||
196 | u8 res19[86]; | ||
197 | u32 pci_dmamr1; | ||
198 | u32 pci_dmasr1; | ||
199 | u32 pci_dmacdar1; | ||
200 | u8 res20[4]; | ||
201 | u32 pci_dmasar1; | ||
202 | u8 res21[4]; | ||
203 | u32 pci_dmadar1; | ||
204 | u8 res22[4]; | ||
205 | u32 pci_dmabcr1; | ||
206 | u32 pci_dmandar1; | ||
207 | u8 res23[88]; | ||
208 | u32 pci_dmamr2; | ||
209 | u32 pci_dmasr2; | ||
210 | u32 pci_dmacdar2; | ||
211 | u8 res24[4]; | ||
212 | u32 pci_dmasar2; | ||
213 | u8 res25[4]; | ||
214 | u32 pci_dmadar2; | ||
215 | u8 res26[4]; | ||
216 | u32 pci_dmabcr2; | ||
217 | u32 pci_dmandar2; | ||
218 | u8 res27[88]; | ||
219 | u32 pci_dmamr3; | ||
220 | u32 pci_dmasr3; | ||
221 | u32 pci_dmacdar3; | ||
222 | u8 res28[4]; | ||
223 | u32 pci_dmasar3; | ||
224 | u8 res29[4]; | ||
225 | u32 pci_dmadar3; | ||
226 | u8 res30[4]; | ||
227 | u32 pci_dmabcr3; | ||
228 | u32 pci_dmandar3; | ||
229 | u8 res31[344]; | ||
230 | u32 pci_potar0; | ||
231 | u8 res32[4]; | ||
232 | u32 pci_pobar0; | ||
233 | u8 res33[4]; | ||
234 | u32 pci_pocmr0; | ||
235 | u8 res34[4]; | ||
236 | u32 pci_potar1; | ||
237 | u8 res35[4]; | ||
238 | u32 pci_pobar1; | ||
239 | u8 res36[4]; | ||
240 | u32 pci_pocmr1; | ||
241 | u8 res37[4]; | ||
242 | u32 pci_potar2; | ||
243 | u8 res38[4]; | ||
244 | u32 pci_pobar2; | ||
245 | u8 res39[4]; | ||
246 | u32 pci_pocmr2; | ||
247 | u8 res40[50]; | ||
248 | u32 pci_ptcr; | ||
249 | u32 pci_gpcr; | ||
250 | u32 pci_gcr; | ||
251 | u32 pci_esr; | ||
252 | u32 pci_emr; | ||
253 | u32 pci_ecr; | ||
254 | u32 pci_eacr; | ||
255 | u8 res41[4]; | ||
256 | u32 pci_edcr; | ||
257 | u8 res42[4]; | ||
258 | u32 pci_eccr; | ||
259 | u8 res43[44]; | ||
260 | u32 pci_pitar1; | ||
261 | u8 res44[4]; | ||
262 | u32 pci_pibar1; | ||
263 | u8 res45[4]; | ||
264 | u32 pci_picmr1; | ||
265 | u8 res46[4]; | ||
266 | u32 pci_pitar0; | ||
267 | u8 res47[4]; | ||
268 | u32 pci_pibar0; | ||
269 | u8 res48[4]; | ||
270 | u32 pci_picmr0; | ||
271 | u8 res49[4]; | ||
272 | u32 pci_cfg_addr; | ||
273 | u32 pci_cfg_data; | ||
274 | u32 pci_int_ack; | ||
275 | u8 res50[756]; | ||
276 | } pci_cpm2_t; | ||
277 | |||
278 | /* Interrupt Controller. | ||
279 | */ | ||
280 | typedef struct interrupt_controller { | ||
281 | u16 ic_sicr; | ||
282 | u8 res1[2]; | ||
283 | u32 ic_sivec; | ||
284 | u32 ic_sipnrh; | ||
285 | u32 ic_sipnrl; | ||
286 | u32 ic_siprr; | ||
287 | u32 ic_scprrh; | ||
288 | u32 ic_scprrl; | ||
289 | u32 ic_simrh; | ||
290 | u32 ic_simrl; | ||
291 | u32 ic_siexr; | ||
292 | u8 res2[88]; | ||
293 | } intctl_cpm2_t; | ||
294 | |||
295 | /* Clocks and Reset. | ||
296 | */ | ||
297 | typedef struct clk_and_reset { | ||
298 | u32 car_sccr; | ||
299 | u8 res1[4]; | ||
300 | u32 car_scmr; | ||
301 | u8 res2[4]; | ||
302 | u32 car_rsr; | ||
303 | u32 car_rmr; | ||
304 | u8 res[104]; | ||
305 | } car_cpm2_t; | ||
306 | |||
307 | /* Input/Output Port control/status registers. | ||
308 | * Names consistent with processor manual, although they are different | ||
309 | * from the original 8xx names....... | ||
310 | */ | ||
311 | typedef struct io_port { | ||
312 | u32 iop_pdira; | ||
313 | u32 iop_ppara; | ||
314 | u32 iop_psora; | ||
315 | u32 iop_podra; | ||
316 | u32 iop_pdata; | ||
317 | u8 res1[12]; | ||
318 | u32 iop_pdirb; | ||
319 | u32 iop_pparb; | ||
320 | u32 iop_psorb; | ||
321 | u32 iop_podrb; | ||
322 | u32 iop_pdatb; | ||
323 | u8 res2[12]; | ||
324 | u32 iop_pdirc; | ||
325 | u32 iop_pparc; | ||
326 | u32 iop_psorc; | ||
327 | u32 iop_podrc; | ||
328 | u32 iop_pdatc; | ||
329 | u8 res3[12]; | ||
330 | u32 iop_pdird; | ||
331 | u32 iop_ppard; | ||
332 | u32 iop_psord; | ||
333 | u32 iop_podrd; | ||
334 | u32 iop_pdatd; | ||
335 | u8 res4[12]; | ||
336 | } iop_cpm2_t; | ||
337 | |||
338 | /* Communication Processor Module Timers | ||
339 | */ | ||
340 | typedef struct cpm_timers { | ||
341 | u8 cpmt_tgcr1; | ||
342 | u8 res1[3]; | ||
343 | u8 cpmt_tgcr2; | ||
344 | u8 res2[11]; | ||
345 | u16 cpmt_tmr1; | ||
346 | u16 cpmt_tmr2; | ||
347 | u16 cpmt_trr1; | ||
348 | u16 cpmt_trr2; | ||
349 | u16 cpmt_tcr1; | ||
350 | u16 cpmt_tcr2; | ||
351 | u16 cpmt_tcn1; | ||
352 | u16 cpmt_tcn2; | ||
353 | u16 cpmt_tmr3; | ||
354 | u16 cpmt_tmr4; | ||
355 | u16 cpmt_trr3; | ||
356 | u16 cpmt_trr4; | ||
357 | u16 cpmt_tcr3; | ||
358 | u16 cpmt_tcr4; | ||
359 | u16 cpmt_tcn3; | ||
360 | u16 cpmt_tcn4; | ||
361 | u16 cpmt_ter1; | ||
362 | u16 cpmt_ter2; | ||
363 | u16 cpmt_ter3; | ||
364 | u16 cpmt_ter4; | ||
365 | u8 res3[584]; | ||
366 | } cpmtimer_cpm2_t; | ||
367 | |||
368 | /* DMA control/status registers. | ||
369 | */ | ||
370 | typedef struct sdma_csr { | ||
371 | u8 res0[24]; | ||
372 | u8 sdma_sdsr; | ||
373 | u8 res1[3]; | ||
374 | u8 sdma_sdmr; | ||
375 | u8 res2[3]; | ||
376 | u8 sdma_idsr1; | ||
377 | u8 res3[3]; | ||
378 | u8 sdma_idmr1; | ||
379 | u8 res4[3]; | ||
380 | u8 sdma_idsr2; | ||
381 | u8 res5[3]; | ||
382 | u8 sdma_idmr2; | ||
383 | u8 res6[3]; | ||
384 | u8 sdma_idsr3; | ||
385 | u8 res7[3]; | ||
386 | u8 sdma_idmr3; | ||
387 | u8 res8[3]; | ||
388 | u8 sdma_idsr4; | ||
389 | u8 res9[3]; | ||
390 | u8 sdma_idmr4; | ||
391 | u8 res10[707]; | ||
392 | } sdma_cpm2_t; | ||
393 | |||
394 | /* Fast controllers | ||
395 | */ | ||
396 | typedef struct fcc { | ||
397 | u32 fcc_gfmr; | ||
398 | u32 fcc_fpsmr; | ||
399 | u16 fcc_ftodr; | ||
400 | u8 res1[2]; | ||
401 | u16 fcc_fdsr; | ||
402 | u8 res2[2]; | ||
403 | u16 fcc_fcce; | ||
404 | u8 res3[2]; | ||
405 | u16 fcc_fccm; | ||
406 | u8 res4[2]; | ||
407 | u8 fcc_fccs; | ||
408 | u8 res5[3]; | ||
409 | u8 fcc_ftirr_phy[4]; | ||
410 | } fcc_t; | ||
411 | |||
412 | /* Fast controllers continued | ||
413 | */ | ||
414 | typedef struct fcc_c { | ||
415 | u32 fcc_firper; | ||
416 | u32 fcc_firer; | ||
417 | u32 fcc_firsr_hi; | ||
418 | u32 fcc_firsr_lo; | ||
419 | u8 fcc_gfemr; | ||
420 | u8 res1[15]; | ||
421 | } fcc_c_t; | ||
422 | |||
423 | /* TC Layer | ||
424 | */ | ||
425 | typedef struct tclayer { | ||
426 | u16 tc_tcmode; | ||
427 | u16 tc_cdsmr; | ||
428 | u16 tc_tcer; | ||
429 | u16 tc_rcc; | ||
430 | u16 tc_tcmr; | ||
431 | u16 tc_fcc; | ||
432 | u16 tc_ccc; | ||
433 | u16 tc_icc; | ||
434 | u16 tc_tcc; | ||
435 | u16 tc_ecc; | ||
436 | u8 res1[12]; | ||
437 | } tclayer_t; | ||
438 | |||
439 | |||
440 | /* I2C | ||
441 | */ | ||
442 | typedef struct i2c { | ||
443 | u8 i2c_i2mod; | ||
444 | u8 res1[3]; | ||
445 | u8 i2c_i2add; | ||
446 | u8 res2[3]; | ||
447 | u8 i2c_i2brg; | ||
448 | u8 res3[3]; | ||
449 | u8 i2c_i2com; | ||
450 | u8 res4[3]; | ||
451 | u8 i2c_i2cer; | ||
452 | u8 res5[3]; | ||
453 | u8 i2c_i2cmr; | ||
454 | u8 res6[331]; | ||
455 | } i2c_cpm2_t; | ||
456 | |||
457 | typedef struct scc { /* Serial communication channels */ | ||
458 | u32 scc_gsmrl; | ||
459 | u32 scc_gsmrh; | ||
460 | u16 scc_psmr; | ||
461 | u8 res1[2]; | ||
462 | u16 scc_todr; | ||
463 | u16 scc_dsr; | ||
464 | u16 scc_scce; | ||
465 | u8 res2[2]; | ||
466 | u16 scc_sccm; | ||
467 | u8 res3; | ||
468 | u8 scc_sccs; | ||
469 | u8 res4[8]; | ||
470 | } scc_t; | ||
471 | |||
472 | typedef struct smc { /* Serial management channels */ | ||
473 | u8 res1[2]; | ||
474 | u16 smc_smcmr; | ||
475 | u8 res2[2]; | ||
476 | u8 smc_smce; | ||
477 | u8 res3[3]; | ||
478 | u8 smc_smcm; | ||
479 | u8 res4[5]; | ||
480 | } smc_t; | ||
481 | |||
482 | /* Serial Peripheral Interface. | ||
483 | */ | ||
484 | typedef struct spi_ctrl { | ||
485 | u16 spi_spmode; | ||
486 | u8 res1[4]; | ||
487 | u8 spi_spie; | ||
488 | u8 res2[3]; | ||
489 | u8 spi_spim; | ||
490 | u8 res3[2]; | ||
491 | u8 spi_spcom; | ||
492 | u8 res4[82]; | ||
493 | } spictl_cpm2_t; | ||
494 | |||
495 | /* CPM Mux. | ||
496 | */ | ||
497 | typedef struct cpmux { | ||
498 | u8 cmx_si1cr; | ||
499 | u8 res1; | ||
500 | u8 cmx_si2cr; | ||
501 | u8 res2; | ||
502 | u32 cmx_fcr; | ||
503 | u32 cmx_scr; | ||
504 | u8 cmx_smr; | ||
505 | u8 res3; | ||
506 | u16 cmx_uar; | ||
507 | u8 res4[16]; | ||
508 | } cpmux_t; | ||
509 | |||
510 | /* SIRAM control | ||
511 | */ | ||
512 | typedef struct siram { | ||
513 | u16 si_amr; | ||
514 | u16 si_bmr; | ||
515 | u16 si_cmr; | ||
516 | u16 si_dmr; | ||
517 | u8 si_gmr; | ||
518 | u8 res1; | ||
519 | u8 si_cmdr; | ||
520 | u8 res2; | ||
521 | u8 si_str; | ||
522 | u8 res3; | ||
523 | u16 si_rsr; | ||
524 | } siramctl_t; | ||
525 | |||
526 | typedef struct mcc { | ||
527 | u16 mcc_mcce; | ||
528 | u8 res1[2]; | ||
529 | u16 mcc_mccm; | ||
530 | u8 res2[2]; | ||
531 | u8 mcc_mccf; | ||
532 | u8 res3[7]; | ||
533 | } mcc_t; | ||
534 | |||
535 | typedef struct comm_proc { | ||
536 | u32 cp_cpcr; | ||
537 | u32 cp_rccr; | ||
538 | u8 res1[14]; | ||
539 | u16 cp_rter; | ||
540 | u8 res2[2]; | ||
541 | u16 cp_rtmr; | ||
542 | u16 cp_rtscr; | ||
543 | u8 res3[2]; | ||
544 | u32 cp_rtsr; | ||
545 | u8 res4[12]; | ||
546 | } cpm_cpm2_t; | ||
547 | |||
548 | /* USB Controller. | ||
549 | */ | ||
550 | typedef struct usb_ctlr { | ||
551 | u8 usb_usmod; | ||
552 | u8 usb_usadr; | ||
553 | u8 usb_uscom; | ||
554 | u8 res1[1]; | ||
555 | u16 usb_usep1; | ||
556 | u16 usb_usep2; | ||
557 | u16 usb_usep3; | ||
558 | u16 usb_usep4; | ||
559 | u8 res2[4]; | ||
560 | u16 usb_usber; | ||
561 | u8 res3[2]; | ||
562 | u16 usb_usbmr; | ||
563 | u8 usb_usbs; | ||
564 | u8 res4[7]; | ||
565 | } usb_cpm2_t; | ||
566 | |||
567 | /* ...and the whole thing wrapped up.... | ||
568 | */ | ||
569 | |||
570 | typedef struct immap { | ||
571 | /* Some references are into the unique and known dpram spaces, | ||
572 | * others are from the generic base. | ||
573 | */ | ||
574 | #define im_dprambase im_dpram1 | ||
575 | u8 im_dpram1[16*1024]; | ||
576 | u8 res1[16*1024]; | ||
577 | u8 im_dpram2[4*1024]; | ||
578 | u8 res2[8*1024]; | ||
579 | u8 im_dpram3[4*1024]; | ||
580 | u8 res3[16*1024]; | ||
581 | |||
582 | sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ | ||
583 | memctl_cpm2_t im_memctl; /* Memory Controller */ | ||
584 | sit_cpm2_t im_sit; /* System Integration Timers */ | ||
585 | pci_cpm2_t im_pci; /* PCI Controller */ | ||
586 | intctl_cpm2_t im_intctl; /* Interrupt Controller */ | ||
587 | car_cpm2_t im_clkrst; /* Clocks and reset */ | ||
588 | iop_cpm2_t im_ioport; /* IO Port control/status */ | ||
589 | cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ | ||
590 | sdma_cpm2_t im_sdma; /* SDMA control/status */ | ||
591 | |||
592 | fcc_t im_fcc[3]; /* Three FCCs */ | ||
593 | u8 res4z[32]; | ||
594 | fcc_c_t im_fcc_c[3]; /* Continued FCCs */ | ||
595 | |||
596 | u8 res4[32]; | ||
597 | |||
598 | tclayer_t im_tclayer[8]; /* Eight TCLayers */ | ||
599 | u16 tc_tcgsr; | ||
600 | u16 tc_tcger; | ||
601 | |||
602 | /* First set of baud rate generators. | ||
603 | */ | ||
604 | u8 res[236]; | ||
605 | u32 im_brgc5; | ||
606 | u32 im_brgc6; | ||
607 | u32 im_brgc7; | ||
608 | u32 im_brgc8; | ||
609 | |||
610 | u8 res5[608]; | ||
611 | |||
612 | i2c_cpm2_t im_i2c; /* I2C control/status */ | ||
613 | cpm_cpm2_t im_cpm; /* Communication processor */ | ||
614 | |||
615 | /* Second set of baud rate generators. | ||
616 | */ | ||
617 | u32 im_brgc1; | ||
618 | u32 im_brgc2; | ||
619 | u32 im_brgc3; | ||
620 | u32 im_brgc4; | ||
621 | |||
622 | scc_t im_scc[4]; /* Four SCCs */ | ||
623 | smc_t im_smc[2]; /* Couple of SMCs */ | ||
624 | spictl_cpm2_t im_spi; /* A SPI */ | ||
625 | cpmux_t im_cpmux; /* CPM clock route mux */ | ||
626 | siramctl_t im_siramctl1; /* First SI RAM Control */ | ||
627 | mcc_t im_mcc1; /* First MCC */ | ||
628 | siramctl_t im_siramctl2; /* Second SI RAM Control */ | ||
629 | mcc_t im_mcc2; /* Second MCC */ | ||
630 | usb_cpm2_t im_usb; /* USB Controller */ | ||
631 | |||
632 | u8 res6[1153]; | ||
633 | |||
634 | u16 im_si1txram[256]; | ||
635 | u8 res7[512]; | ||
636 | u16 im_si1rxram[256]; | ||
637 | u8 res8[512]; | ||
638 | u16 im_si2txram[256]; | ||
639 | u8 res9[512]; | ||
640 | u16 im_si2rxram[256]; | ||
641 | u8 res10[512]; | ||
642 | u8 res11[4096]; | ||
643 | } cpm2_map_t; | ||
644 | |||
645 | extern cpm2_map_t *cpm2_immr; | ||
646 | |||
647 | #endif /* __IMMAP_CPM2__ */ | ||
648 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h new file mode 100644 index 000000000000..7eb7cf6360bd --- /dev/null +++ b/include/asm-ppc/io.h | |||
@@ -0,0 +1,566 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_IO_H | ||
3 | #define _PPC_IO_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <linux/string.h> | ||
7 | #include <linux/types.h> | ||
8 | |||
9 | #include <asm/page.h> | ||
10 | #include <asm/byteorder.h> | ||
11 | #include <asm/mmu.h> | ||
12 | |||
13 | #define SIO_CONFIG_RA 0x398 | ||
14 | #define SIO_CONFIG_RD 0x399 | ||
15 | |||
16 | #define SLOW_DOWN_IO | ||
17 | |||
18 | #define PMAC_ISA_MEM_BASE 0 | ||
19 | #define PMAC_PCI_DRAM_OFFSET 0 | ||
20 | #define CHRP_ISA_IO_BASE 0xf8000000 | ||
21 | #define CHRP_ISA_MEM_BASE 0xf7000000 | ||
22 | #define CHRP_PCI_DRAM_OFFSET 0 | ||
23 | #define PREP_ISA_IO_BASE 0x80000000 | ||
24 | #define PREP_ISA_MEM_BASE 0xc0000000 | ||
25 | #define PREP_PCI_DRAM_OFFSET 0x80000000 | ||
26 | |||
27 | #if defined(CONFIG_4xx) | ||
28 | #include <asm/ibm4xx.h> | ||
29 | #elif defined(CONFIG_8xx) | ||
30 | #include <asm/mpc8xx.h> | ||
31 | #elif defined(CONFIG_8260) | ||
32 | #include <asm/mpc8260.h> | ||
33 | #elif defined(CONFIG_83xx) | ||
34 | #include <asm/mpc83xx.h> | ||
35 | #elif defined(CONFIG_85xx) | ||
36 | #include <asm/mpc85xx.h> | ||
37 | #elif defined(CONFIG_APUS) | ||
38 | #define _IO_BASE 0 | ||
39 | #define _ISA_MEM_BASE 0 | ||
40 | #define PCI_DRAM_OFFSET 0 | ||
41 | #else /* Everyone else */ | ||
42 | #define _IO_BASE isa_io_base | ||
43 | #define _ISA_MEM_BASE isa_mem_base | ||
44 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
45 | #endif /* Platform-dependent I/O */ | ||
46 | |||
47 | #define ___IO_BASE ((void __iomem *)_IO_BASE) | ||
48 | extern unsigned long isa_io_base; | ||
49 | extern unsigned long isa_mem_base; | ||
50 | extern unsigned long pci_dram_offset; | ||
51 | |||
52 | /* | ||
53 | * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. | ||
54 | * | ||
55 | * Read operations have additional twi & isync to make sure the read | ||
56 | * is actually performed (i.e. the data has come back) before we start | ||
57 | * executing any following instructions. | ||
58 | */ | ||
59 | extern inline int in_8(volatile unsigned char __iomem *addr) | ||
60 | { | ||
61 | int ret; | ||
62 | |||
63 | __asm__ __volatile__( | ||
64 | "lbz%U1%X1 %0,%1;\n" | ||
65 | "twi 0,%0,0;\n" | ||
66 | "isync" : "=r" (ret) : "m" (*addr)); | ||
67 | return ret; | ||
68 | } | ||
69 | |||
70 | extern inline void out_8(volatile unsigned char __iomem *addr, int val) | ||
71 | { | ||
72 | __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); | ||
73 | } | ||
74 | |||
75 | extern inline int in_le16(volatile unsigned short __iomem *addr) | ||
76 | { | ||
77 | int ret; | ||
78 | |||
79 | __asm__ __volatile__("lhbrx %0,0,%1;\n" | ||
80 | "twi 0,%0,0;\n" | ||
81 | "isync" : "=r" (ret) : | ||
82 | "r" (addr), "m" (*addr)); | ||
83 | return ret; | ||
84 | } | ||
85 | |||
86 | extern inline int in_be16(volatile unsigned short __iomem *addr) | ||
87 | { | ||
88 | int ret; | ||
89 | |||
90 | __asm__ __volatile__("lhz%U1%X1 %0,%1;\n" | ||
91 | "twi 0,%0,0;\n" | ||
92 | "isync" : "=r" (ret) : "m" (*addr)); | ||
93 | return ret; | ||
94 | } | ||
95 | |||
96 | extern inline void out_le16(volatile unsigned short __iomem *addr, int val) | ||
97 | { | ||
98 | __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : | ||
99 | "r" (val), "r" (addr)); | ||
100 | } | ||
101 | |||
102 | extern inline void out_be16(volatile unsigned short __iomem *addr, int val) | ||
103 | { | ||
104 | __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); | ||
105 | } | ||
106 | |||
107 | extern inline unsigned in_le32(volatile unsigned __iomem *addr) | ||
108 | { | ||
109 | unsigned ret; | ||
110 | |||
111 | __asm__ __volatile__("lwbrx %0,0,%1;\n" | ||
112 | "twi 0,%0,0;\n" | ||
113 | "isync" : "=r" (ret) : | ||
114 | "r" (addr), "m" (*addr)); | ||
115 | return ret; | ||
116 | } | ||
117 | |||
118 | extern inline unsigned in_be32(volatile unsigned __iomem *addr) | ||
119 | { | ||
120 | unsigned ret; | ||
121 | |||
122 | __asm__ __volatile__("lwz%U1%X1 %0,%1;\n" | ||
123 | "twi 0,%0,0;\n" | ||
124 | "isync" : "=r" (ret) : "m" (*addr)); | ||
125 | return ret; | ||
126 | } | ||
127 | |||
128 | extern inline void out_le32(volatile unsigned __iomem *addr, int val) | ||
129 | { | ||
130 | __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : | ||
131 | "r" (val), "r" (addr)); | ||
132 | } | ||
133 | |||
134 | extern inline void out_be32(volatile unsigned __iomem *addr, int val) | ||
135 | { | ||
136 | __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); | ||
137 | } | ||
138 | #if defined (CONFIG_8260_PCI9) | ||
139 | #define readb(addr) in_8((volatile u8 *)(addr)) | ||
140 | #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) | ||
141 | #else | ||
142 | static inline __u8 readb(volatile void __iomem *addr) | ||
143 | { | ||
144 | return in_8(addr); | ||
145 | } | ||
146 | static inline void writeb(__u8 b, volatile void __iomem *addr) | ||
147 | { | ||
148 | out_8(addr, b); | ||
149 | } | ||
150 | #endif | ||
151 | |||
152 | #if defined(CONFIG_APUS) | ||
153 | static inline __u16 readw(volatile void __iomem *addr) | ||
154 | { | ||
155 | return *(__force volatile __u16 *)(addr); | ||
156 | } | ||
157 | static inline __u32 readl(volatile void __iomem *addr) | ||
158 | { | ||
159 | return *(__force volatile __u32 *)(addr); | ||
160 | } | ||
161 | static inline void writew(__u16 b, volatile void __iomem *addr) | ||
162 | { | ||
163 | *(__force volatile __u16 *)(addr) = b; | ||
164 | } | ||
165 | static inline void writel(__u32 b, volatile void __iomem *addr) | ||
166 | { | ||
167 | *(__force volatile __u32 *)(addr) = b; | ||
168 | } | ||
169 | #elif defined (CONFIG_8260_PCI9) | ||
170 | /* Use macros if PCI9 workaround enabled */ | ||
171 | #define readw(addr) in_le16((volatile u16 *)(addr)) | ||
172 | #define readl(addr) in_le32((volatile u32 *)(addr)) | ||
173 | #define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) | ||
174 | #define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) | ||
175 | #else | ||
176 | static inline __u16 readw(volatile void __iomem *addr) | ||
177 | { | ||
178 | return in_le16(addr); | ||
179 | } | ||
180 | static inline __u32 readl(volatile void __iomem *addr) | ||
181 | { | ||
182 | return in_le32(addr); | ||
183 | } | ||
184 | static inline void writew(__u16 b, volatile void __iomem *addr) | ||
185 | { | ||
186 | out_le16(addr, b); | ||
187 | } | ||
188 | static inline void writel(__u32 b, volatile void __iomem *addr) | ||
189 | { | ||
190 | out_le32(addr, b); | ||
191 | } | ||
192 | #endif /* CONFIG_APUS */ | ||
193 | |||
194 | #define readb_relaxed(addr) readb(addr) | ||
195 | #define readw_relaxed(addr) readw(addr) | ||
196 | #define readl_relaxed(addr) readl(addr) | ||
197 | |||
198 | static inline __u8 __raw_readb(const volatile void __iomem *addr) | ||
199 | { | ||
200 | return *(__force volatile __u8 *)(addr); | ||
201 | } | ||
202 | static inline __u16 __raw_readw(const volatile void __iomem *addr) | ||
203 | { | ||
204 | return *(__force volatile __u16 *)(addr); | ||
205 | } | ||
206 | static inline __u32 __raw_readl(const volatile void __iomem *addr) | ||
207 | { | ||
208 | return *(__force volatile __u32 *)(addr); | ||
209 | } | ||
210 | static inline void __raw_writeb(__u8 b, volatile void __iomem *addr) | ||
211 | { | ||
212 | *(__force volatile __u8 *)(addr) = b; | ||
213 | } | ||
214 | static inline void __raw_writew(__u16 b, volatile void __iomem *addr) | ||
215 | { | ||
216 | *(__force volatile __u16 *)(addr) = b; | ||
217 | } | ||
218 | static inline void __raw_writel(__u32 b, volatile void __iomem *addr) | ||
219 | { | ||
220 | *(__force volatile __u32 *)(addr) = b; | ||
221 | } | ||
222 | |||
223 | #define mmiowb() | ||
224 | |||
225 | /* | ||
226 | * The insw/outsw/insl/outsl macros don't do byte-swapping. | ||
227 | * They are only used in practice for transferring buffers which | ||
228 | * are arrays of bytes, and byte-swapping is not appropriate in | ||
229 | * that case. - paulus | ||
230 | */ | ||
231 | #define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns)) | ||
232 | #define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns)) | ||
233 | #define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) | ||
234 | #define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) | ||
235 | #define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) | ||
236 | #define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) | ||
237 | |||
238 | /* | ||
239 | * On powermacs, we will get a machine check exception if we | ||
240 | * try to read data from a non-existent I/O port. Because the | ||
241 | * machine check is an asynchronous exception, it isn't | ||
242 | * well-defined which instruction SRR0 will point to when the | ||
243 | * exception occurs. | ||
244 | * With the sequence below (twi; isync; nop), we have found that | ||
245 | * the machine check occurs on one of the three instructions on | ||
246 | * all PPC implementations tested so far. The twi and isync are | ||
247 | * needed on the 601 (in fact twi; sync works too), the isync and | ||
248 | * nop are needed on 604[e|r], and any of twi, sync or isync will | ||
249 | * work on 603[e], 750, 74xx. | ||
250 | * The twi creates an explicit data dependency on the returned | ||
251 | * value which seems to be needed to make the 601 wait for the | ||
252 | * load to finish. | ||
253 | */ | ||
254 | |||
255 | #define __do_in_asm(name, op) \ | ||
256 | extern __inline__ unsigned int name(unsigned int port) \ | ||
257 | { \ | ||
258 | unsigned int x; \ | ||
259 | __asm__ __volatile__( \ | ||
260 | op " %0,0,%1\n" \ | ||
261 | "1: twi 0,%0,0\n" \ | ||
262 | "2: isync\n" \ | ||
263 | "3: nop\n" \ | ||
264 | "4:\n" \ | ||
265 | ".section .fixup,\"ax\"\n" \ | ||
266 | "5: li %0,-1\n" \ | ||
267 | " b 4b\n" \ | ||
268 | ".previous\n" \ | ||
269 | ".section __ex_table,\"a\"\n" \ | ||
270 | " .align 2\n" \ | ||
271 | " .long 1b,5b\n" \ | ||
272 | " .long 2b,5b\n" \ | ||
273 | " .long 3b,5b\n" \ | ||
274 | ".previous" \ | ||
275 | : "=&r" (x) \ | ||
276 | : "r" (port + ___IO_BASE)); \ | ||
277 | return x; \ | ||
278 | } | ||
279 | |||
280 | #define __do_out_asm(name, op) \ | ||
281 | extern __inline__ void name(unsigned int val, unsigned int port) \ | ||
282 | { \ | ||
283 | __asm__ __volatile__( \ | ||
284 | op " %0,0,%1\n" \ | ||
285 | "1: sync\n" \ | ||
286 | "2:\n" \ | ||
287 | ".section __ex_table,\"a\"\n" \ | ||
288 | " .align 2\n" \ | ||
289 | " .long 1b,2b\n" \ | ||
290 | ".previous" \ | ||
291 | : : "r" (val), "r" (port + ___IO_BASE)); \ | ||
292 | } | ||
293 | |||
294 | __do_out_asm(outb, "stbx") | ||
295 | #ifdef CONFIG_APUS | ||
296 | __do_in_asm(inb, "lbzx") | ||
297 | __do_in_asm(inw, "lhz%U1%X1") | ||
298 | __do_in_asm(inl, "lwz%U1%X1") | ||
299 | __do_out_asm(outl,"stw%U0%X0") | ||
300 | __do_out_asm(outw, "sth%U0%X0") | ||
301 | #elif defined (CONFIG_8260_PCI9) | ||
302 | /* in asm cannot be defined if PCI9 workaround is used */ | ||
303 | #define inb(port) in_8((port)+___IO_BASE) | ||
304 | #define inw(port) in_le16((port)+___IO_BASE) | ||
305 | #define inl(port) in_le32((port)+___IO_BASE) | ||
306 | __do_out_asm(outw, "sthbrx") | ||
307 | __do_out_asm(outl, "stwbrx") | ||
308 | #else | ||
309 | __do_in_asm(inb, "lbzx") | ||
310 | __do_in_asm(inw, "lhbrx") | ||
311 | __do_in_asm(inl, "lwbrx") | ||
312 | __do_out_asm(outw, "sthbrx") | ||
313 | __do_out_asm(outl, "stwbrx") | ||
314 | |||
315 | #endif | ||
316 | |||
317 | #define inb_p(port) inb((port)) | ||
318 | #define outb_p(val, port) outb((val), (port)) | ||
319 | #define inw_p(port) inw((port)) | ||
320 | #define outw_p(val, port) outw((val), (port)) | ||
321 | #define inl_p(port) inl((port)) | ||
322 | #define outl_p(val, port) outl((val), (port)) | ||
323 | |||
324 | extern void _insb(volatile u8 __iomem *port, void *buf, int ns); | ||
325 | extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns); | ||
326 | extern void _insw(volatile u16 __iomem *port, void *buf, int ns); | ||
327 | extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns); | ||
328 | extern void _insl(volatile u32 __iomem *port, void *buf, int nl); | ||
329 | extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl); | ||
330 | extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns); | ||
331 | extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns); | ||
332 | extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl); | ||
333 | extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl); | ||
334 | |||
335 | /* | ||
336 | * The *_ns versions below don't do byte-swapping. | ||
337 | * Neither do the standard versions now, these are just here | ||
338 | * for older code. | ||
339 | */ | ||
340 | #define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns)) | ||
341 | #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns)) | ||
342 | #define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl)) | ||
343 | #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl)) | ||
344 | |||
345 | |||
346 | #define IO_SPACE_LIMIT ~0 | ||
347 | |||
348 | #if defined (CONFIG_8260_PCI9) | ||
349 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
350 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
351 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
352 | #else | ||
353 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) | ||
354 | { | ||
355 | memset((void __force *)addr, val, count); | ||
356 | } | ||
357 | static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count) | ||
358 | { | ||
359 | memcpy(dst, (void __force *) src, count); | ||
360 | } | ||
361 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) | ||
362 | { | ||
363 | memcpy((void __force *) dst, src, count); | ||
364 | } | ||
365 | #endif | ||
366 | |||
367 | #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d)) | ||
368 | |||
369 | /* | ||
370 | * Map in an area of physical address space, for accessing | ||
371 | * I/O devices etc. | ||
372 | */ | ||
373 | extern void __iomem *__ioremap(phys_addr_t address, unsigned long size, | ||
374 | unsigned long flags); | ||
375 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); | ||
376 | #ifdef CONFIG_44x | ||
377 | extern void __iomem *ioremap64(unsigned long long address, unsigned long size); | ||
378 | #endif | ||
379 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) | ||
380 | extern void iounmap(volatile void __iomem *addr); | ||
381 | extern unsigned long iopa(unsigned long addr); | ||
382 | extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; | ||
383 | extern void io_block_mapping(unsigned long virt, phys_addr_t phys, | ||
384 | unsigned int size, int flags); | ||
385 | |||
386 | /* | ||
387 | * The PCI bus is inherently Little-Endian. The PowerPC is being | ||
388 | * run Big-Endian. Thus all values which cross the [PCI] barrier | ||
389 | * must be endian-adjusted. Also, the local DRAM has a different | ||
390 | * address from the PCI point of view, thus buffer addresses also | ||
391 | * have to be modified [mapped] appropriately. | ||
392 | */ | ||
393 | extern inline unsigned long virt_to_bus(volatile void * address) | ||
394 | { | ||
395 | #ifndef CONFIG_APUS | ||
396 | if (address == (void *)0) | ||
397 | return 0; | ||
398 | return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET; | ||
399 | #else | ||
400 | return iopa ((unsigned long) address); | ||
401 | #endif | ||
402 | } | ||
403 | |||
404 | extern inline void * bus_to_virt(unsigned long address) | ||
405 | { | ||
406 | #ifndef CONFIG_APUS | ||
407 | if (address == 0) | ||
408 | return NULL; | ||
409 | return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE); | ||
410 | #else | ||
411 | return (void*) mm_ptov (address); | ||
412 | #endif | ||
413 | } | ||
414 | |||
415 | /* | ||
416 | * Change virtual addresses to physical addresses and vv, for | ||
417 | * addresses in the area where the kernel has the RAM mapped. | ||
418 | */ | ||
419 | extern inline unsigned long virt_to_phys(volatile void * address) | ||
420 | { | ||
421 | #ifndef CONFIG_APUS | ||
422 | return (unsigned long) address - KERNELBASE; | ||
423 | #else | ||
424 | return iopa ((unsigned long) address); | ||
425 | #endif | ||
426 | } | ||
427 | |||
428 | extern inline void * phys_to_virt(unsigned long address) | ||
429 | { | ||
430 | #ifndef CONFIG_APUS | ||
431 | return (void *) (address + KERNELBASE); | ||
432 | #else | ||
433 | return (void*) mm_ptov (address); | ||
434 | #endif | ||
435 | } | ||
436 | |||
437 | /* | ||
438 | * Change "struct page" to physical address. | ||
439 | */ | ||
440 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | ||
441 | #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) | ||
442 | |||
443 | /* | ||
444 | * Enforce In-order Execution of I/O: | ||
445 | * Acts as a barrier to ensure all previous I/O accesses have | ||
446 | * completed before any further ones are issued. | ||
447 | */ | ||
448 | extern inline void eieio(void) | ||
449 | { | ||
450 | __asm__ __volatile__ ("eieio" : : : "memory"); | ||
451 | } | ||
452 | |||
453 | /* Enforce in-order execution of data I/O. | ||
454 | * No distinction between read/write on PPC; use eieio for all three. | ||
455 | */ | ||
456 | #define iobarrier_rw() eieio() | ||
457 | #define iobarrier_r() eieio() | ||
458 | #define iobarrier_w() eieio() | ||
459 | |||
460 | static inline int check_signature(volatile void __iomem * io_addr, | ||
461 | const unsigned char *signature, int length) | ||
462 | { | ||
463 | int retval = 0; | ||
464 | do { | ||
465 | if (readb(io_addr) != *signature) | ||
466 | goto out; | ||
467 | io_addr++; | ||
468 | signature++; | ||
469 | length--; | ||
470 | } while (length); | ||
471 | retval = 1; | ||
472 | out: | ||
473 | return retval; | ||
474 | } | ||
475 | |||
476 | /* | ||
477 | * Here comes the ppc implementation of the IOMAP | ||
478 | * interfaces. | ||
479 | */ | ||
480 | static inline unsigned int ioread8(void __iomem *addr) | ||
481 | { | ||
482 | return readb(addr); | ||
483 | } | ||
484 | |||
485 | static inline unsigned int ioread16(void __iomem *addr) | ||
486 | { | ||
487 | return readw(addr); | ||
488 | } | ||
489 | |||
490 | static inline unsigned int ioread32(void __iomem *addr) | ||
491 | { | ||
492 | return readl(addr); | ||
493 | } | ||
494 | |||
495 | static inline void iowrite8(u8 val, void __iomem *addr) | ||
496 | { | ||
497 | writeb(val, addr); | ||
498 | } | ||
499 | |||
500 | static inline void iowrite16(u16 val, void __iomem *addr) | ||
501 | { | ||
502 | writew(val, addr); | ||
503 | } | ||
504 | |||
505 | static inline void iowrite32(u32 val, void __iomem *addr) | ||
506 | { | ||
507 | writel(val, addr); | ||
508 | } | ||
509 | |||
510 | static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count) | ||
511 | { | ||
512 | _insb(addr, dst, count); | ||
513 | } | ||
514 | |||
515 | static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count) | ||
516 | { | ||
517 | _insw_ns(addr, dst, count); | ||
518 | } | ||
519 | |||
520 | static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count) | ||
521 | { | ||
522 | _insl_ns(addr, dst, count); | ||
523 | } | ||
524 | |||
525 | static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count) | ||
526 | { | ||
527 | _outsb(addr, src, count); | ||
528 | } | ||
529 | |||
530 | static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count) | ||
531 | { | ||
532 | _outsw_ns(addr, src, count); | ||
533 | } | ||
534 | |||
535 | static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count) | ||
536 | { | ||
537 | _outsl_ns(addr, src, count); | ||
538 | } | ||
539 | |||
540 | /* Create a virtual mapping cookie for an IO port range */ | ||
541 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | ||
542 | extern void ioport_unmap(void __iomem *); | ||
543 | |||
544 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | ||
545 | struct pci_dev; | ||
546 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | ||
547 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | ||
548 | |||
549 | #endif /* _PPC_IO_H */ | ||
550 | |||
551 | #ifdef CONFIG_8260_PCI9 | ||
552 | #include <asm/mpc8260_pci9.h> | ||
553 | #endif | ||
554 | |||
555 | /* | ||
556 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
557 | * access | ||
558 | */ | ||
559 | #define xlate_dev_mem_ptr(p) __va(p) | ||
560 | |||
561 | /* | ||
562 | * Convert a virtual cached pointer to an uncached pointer | ||
563 | */ | ||
564 | #define xlate_dev_kmem_ptr(p) p | ||
565 | |||
566 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ioctl.h b/include/asm-ppc/ioctl.h new file mode 100644 index 000000000000..93c6acfdd0fd --- /dev/null +++ b/include/asm-ppc/ioctl.h | |||
@@ -0,0 +1,69 @@ | |||
1 | #ifndef _PPC_IOCTL_H | ||
2 | #define _PPC_IOCTL_H | ||
3 | |||
4 | |||
5 | /* | ||
6 | * this was copied from the alpha as it's a bit cleaner there. | ||
7 | * -- Cort | ||
8 | */ | ||
9 | |||
10 | #define _IOC_NRBITS 8 | ||
11 | #define _IOC_TYPEBITS 8 | ||
12 | #define _IOC_SIZEBITS 13 | ||
13 | #define _IOC_DIRBITS 3 | ||
14 | |||
15 | #define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) | ||
16 | #define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) | ||
17 | #define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) | ||
18 | #define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) | ||
19 | |||
20 | #define _IOC_NRSHIFT 0 | ||
21 | #define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) | ||
22 | #define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) | ||
23 | #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) | ||
24 | |||
25 | /* | ||
26 | * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. | ||
27 | * And this turns out useful to catch old ioctl numbers in header | ||
28 | * files for us. | ||
29 | */ | ||
30 | #define _IOC_NONE 1U | ||
31 | #define _IOC_READ 2U | ||
32 | #define _IOC_WRITE 4U | ||
33 | |||
34 | #define _IOC(dir,type,nr,size) \ | ||
35 | (((dir) << _IOC_DIRSHIFT) | \ | ||
36 | ((type) << _IOC_TYPESHIFT) | \ | ||
37 | ((nr) << _IOC_NRSHIFT) | \ | ||
38 | ((size) << _IOC_SIZESHIFT)) | ||
39 | |||
40 | /* provoke compile error for invalid uses of size argument */ | ||
41 | extern unsigned int __invalid_size_argument_for_IOC; | ||
42 | #define _IOC_TYPECHECK(t) \ | ||
43 | ((sizeof(t) == sizeof(t[1]) && \ | ||
44 | sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ | ||
45 | sizeof(t) : __invalid_size_argument_for_IOC) | ||
46 | |||
47 | /* used to create numbers */ | ||
48 | #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) | ||
49 | #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) | ||
50 | #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) | ||
51 | #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) | ||
52 | #define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) | ||
53 | #define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) | ||
54 | #define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) | ||
55 | |||
56 | /* used to decode them.. */ | ||
57 | #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) | ||
58 | #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) | ||
59 | #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) | ||
60 | #define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) | ||
61 | |||
62 | /* various drivers, such as the pcmcia stuff, need these... */ | ||
63 | #define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) | ||
64 | #define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) | ||
65 | #define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) | ||
66 | #define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) | ||
67 | #define IOCSIZE_SHIFT (_IOC_SIZESHIFT) | ||
68 | |||
69 | #endif | ||
diff --git a/include/asm-ppc/ioctls.h b/include/asm-ppc/ioctls.h new file mode 100644 index 000000000000..f5b7f2b055e7 --- /dev/null +++ b/include/asm-ppc/ioctls.h | |||
@@ -0,0 +1,107 @@ | |||
1 | #ifndef _ASM_PPC_IOCTLS_H | ||
2 | #define _ASM_PPC_IOCTLS_H | ||
3 | |||
4 | #include <asm/ioctl.h> | ||
5 | |||
6 | #define FIOCLEX _IO('f', 1) | ||
7 | #define FIONCLEX _IO('f', 2) | ||
8 | #define FIOASYNC _IOW('f', 125, int) | ||
9 | #define FIONBIO _IOW('f', 126, int) | ||
10 | #define FIONREAD _IOR('f', 127, int) | ||
11 | #define TIOCINQ FIONREAD | ||
12 | #define FIOQSIZE _IOR('f', 128, loff_t) | ||
13 | |||
14 | #define TIOCGETP _IOR('t', 8, struct sgttyb) | ||
15 | #define TIOCSETP _IOW('t', 9, struct sgttyb) | ||
16 | #define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */ | ||
17 | |||
18 | #define TIOCSETC _IOW('t', 17, struct tchars) | ||
19 | #define TIOCGETC _IOR('t', 18, struct tchars) | ||
20 | #define TCGETS _IOR('t', 19, struct termios) | ||
21 | #define TCSETS _IOW('t', 20, struct termios) | ||
22 | #define TCSETSW _IOW('t', 21, struct termios) | ||
23 | #define TCSETSF _IOW('t', 22, struct termios) | ||
24 | |||
25 | #define TCGETA _IOR('t', 23, struct termio) | ||
26 | #define TCSETA _IOW('t', 24, struct termio) | ||
27 | #define TCSETAW _IOW('t', 25, struct termio) | ||
28 | #define TCSETAF _IOW('t', 28, struct termio) | ||
29 | |||
30 | #define TCSBRK _IO('t', 29) | ||
31 | #define TCXONC _IO('t', 30) | ||
32 | #define TCFLSH _IO('t', 31) | ||
33 | |||
34 | #define TIOCSWINSZ _IOW('t', 103, struct winsize) | ||
35 | #define TIOCGWINSZ _IOR('t', 104, struct winsize) | ||
36 | #define TIOCSTART _IO('t', 110) /* start output, like ^Q */ | ||
37 | #define TIOCSTOP _IO('t', 111) /* stop output, like ^S */ | ||
38 | #define TIOCOUTQ _IOR('t', 115, int) /* output queue size */ | ||
39 | |||
40 | #define TIOCGLTC _IOR('t', 116, struct ltchars) | ||
41 | #define TIOCSLTC _IOW('t', 117, struct ltchars) | ||
42 | #define TIOCSPGRP _IOW('t', 118, int) | ||
43 | #define TIOCGPGRP _IOR('t', 119, int) | ||
44 | |||
45 | #define TIOCEXCL 0x540C | ||
46 | #define TIOCNXCL 0x540D | ||
47 | #define TIOCSCTTY 0x540E | ||
48 | |||
49 | #define TIOCSTI 0x5412 | ||
50 | #define TIOCMGET 0x5415 | ||
51 | #define TIOCMBIS 0x5416 | ||
52 | #define TIOCMBIC 0x5417 | ||
53 | #define TIOCMSET 0x5418 | ||
54 | # define TIOCM_LE 0x001 | ||
55 | # define TIOCM_DTR 0x002 | ||
56 | # define TIOCM_RTS 0x004 | ||
57 | # define TIOCM_ST 0x008 | ||
58 | # define TIOCM_SR 0x010 | ||
59 | # define TIOCM_CTS 0x020 | ||
60 | # define TIOCM_CAR 0x040 | ||
61 | # define TIOCM_RNG 0x080 | ||
62 | # define TIOCM_DSR 0x100 | ||
63 | # define TIOCM_CD TIOCM_CAR | ||
64 | # define TIOCM_RI TIOCM_RNG | ||
65 | |||
66 | #define TIOCGSOFTCAR 0x5419 | ||
67 | #define TIOCSSOFTCAR 0x541A | ||
68 | #define TIOCLINUX 0x541C | ||
69 | #define TIOCCONS 0x541D | ||
70 | #define TIOCGSERIAL 0x541E | ||
71 | #define TIOCSSERIAL 0x541F | ||
72 | #define TIOCPKT 0x5420 | ||
73 | # define TIOCPKT_DATA 0 | ||
74 | # define TIOCPKT_FLUSHREAD 1 | ||
75 | # define TIOCPKT_FLUSHWRITE 2 | ||
76 | # define TIOCPKT_STOP 4 | ||
77 | # define TIOCPKT_START 8 | ||
78 | # define TIOCPKT_NOSTOP 16 | ||
79 | # define TIOCPKT_DOSTOP 32 | ||
80 | |||
81 | |||
82 | #define TIOCNOTTY 0x5422 | ||
83 | #define TIOCSETD 0x5423 | ||
84 | #define TIOCGETD 0x5424 | ||
85 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
86 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
87 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
88 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
89 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | ||
90 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | ||
91 | |||
92 | #define TIOCSERCONFIG 0x5453 | ||
93 | #define TIOCSERGWILD 0x5454 | ||
94 | #define TIOCSERSWILD 0x5455 | ||
95 | #define TIOCGLCKTRMIOS 0x5456 | ||
96 | #define TIOCSLCKTRMIOS 0x5457 | ||
97 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
98 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
99 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
100 | # define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
101 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
102 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
103 | |||
104 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
105 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
106 | |||
107 | #endif /* _ASM_PPC_IOCTLS_H */ | ||
diff --git a/include/asm-ppc/ipc.h b/include/asm-ppc/ipc.h new file mode 100644 index 000000000000..a46e3d9c2a3f --- /dev/null +++ b/include/asm-ppc/ipc.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/ipc.h> | |||
diff --git a/include/asm-ppc/ipcbuf.h b/include/asm-ppc/ipcbuf.h new file mode 100644 index 000000000000..fab6752c7480 --- /dev/null +++ b/include/asm-ppc/ipcbuf.h | |||
@@ -0,0 +1,29 @@ | |||
1 | #ifndef __PPC_IPCBUF_H__ | ||
2 | #define __PPC_IPCBUF_H__ | ||
3 | |||
4 | /* | ||
5 | * The ipc64_perm structure for PPC architecture. | ||
6 | * Note extra padding because this structure is passed back and forth | ||
7 | * between kernel and user space. | ||
8 | * | ||
9 | * Pad space is left for: | ||
10 | * - 1 32-bit value to fill up for 8-byte alignment | ||
11 | * - 2 miscellaneous 64-bit values (so that this structure matches | ||
12 | * PPC64 ipc64_perm) | ||
13 | */ | ||
14 | |||
15 | struct ipc64_perm | ||
16 | { | ||
17 | __kernel_key_t key; | ||
18 | __kernel_uid_t uid; | ||
19 | __kernel_gid_t gid; | ||
20 | __kernel_uid_t cuid; | ||
21 | __kernel_gid_t cgid; | ||
22 | __kernel_mode_t mode; | ||
23 | unsigned long seq; | ||
24 | unsigned int __pad2; | ||
25 | unsigned long long __unused1; | ||
26 | unsigned long long __unused2; | ||
27 | }; | ||
28 | |||
29 | #endif /* __PPC_IPCBUF_H__ */ | ||
diff --git a/include/asm-ppc/ipic.h b/include/asm-ppc/ipic.h new file mode 100644 index 000000000000..9092b920997a --- /dev/null +++ b/include/asm-ppc/ipic.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ipic.h | ||
3 | * | ||
4 | * IPIC external definitions and structure. | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | ||
7 | * | ||
8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | #ifdef __KERNEL__ | ||
16 | #ifndef __ASM_IPIC_H__ | ||
17 | #define __ASM_IPIC_H__ | ||
18 | |||
19 | #include <linux/irq.h> | ||
20 | |||
21 | /* Flags when we init the IPIC */ | ||
22 | #define IPIC_SPREADMODE_GRP_A 0x00000001 | ||
23 | #define IPIC_SPREADMODE_GRP_D 0x00000002 | ||
24 | #define IPIC_SPREADMODE_MIX_A 0x00000004 | ||
25 | #define IPIC_SPREADMODE_MIX_B 0x00000008 | ||
26 | #define IPIC_DISABLE_MCP_OUT 0x00000010 | ||
27 | #define IPIC_IRQ0_MCP 0x00000020 | ||
28 | |||
29 | /* IPIC registers offsets */ | ||
30 | #define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ | ||
31 | #define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */ | ||
32 | #define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */ | ||
33 | #define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */ | ||
34 | #define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */ | ||
35 | #define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */ | ||
36 | #define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */ | ||
37 | #define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */ | ||
38 | #define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */ | ||
39 | #define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */ | ||
40 | #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */ | ||
41 | #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */ | ||
42 | #define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */ | ||
43 | #define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */ | ||
44 | #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */ | ||
45 | #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */ | ||
46 | #define IPIC_SERSR 0x40 /* System Error Status Register */ | ||
47 | #define IPIC_SERMR 0x44 /* System Error Mask Register */ | ||
48 | #define IPIC_SERCR 0x48 /* System Error Control Register */ | ||
49 | #define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */ | ||
50 | #define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */ | ||
51 | #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */ | ||
52 | #define IPIC_SERFR 0x5C /* System Error Force Register */ | ||
53 | #define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */ | ||
54 | #define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */ | ||
55 | |||
56 | enum ipic_prio_grp { | ||
57 | IPIC_INT_GRP_A = IPIC_SIPRR_A, | ||
58 | IPIC_INT_GRP_D = IPIC_SIPRR_D, | ||
59 | IPIC_MIX_GRP_A = IPIC_SMPRR_A, | ||
60 | IPIC_MIX_GRP_B = IPIC_SMPRR_B, | ||
61 | }; | ||
62 | |||
63 | enum ipic_mcp_irq { | ||
64 | IPIC_MCP_IRQ0 = 0, | ||
65 | IPIC_MCP_WDT = 1, | ||
66 | IPIC_MCP_SBA = 2, | ||
67 | IPIC_MCP_PCI1 = 5, | ||
68 | IPIC_MCP_PCI2 = 6, | ||
69 | IPIC_MCP_MU = 7, | ||
70 | }; | ||
71 | |||
72 | extern void ipic_init(phys_addr_t phys_addr, unsigned int flags, | ||
73 | unsigned int irq_offset, | ||
74 | unsigned char *senses, unsigned int senses_count); | ||
75 | extern int ipic_set_priority(unsigned int irq, unsigned int priority); | ||
76 | extern void ipic_set_highest_priority(unsigned int irq); | ||
77 | extern void ipic_set_default_priority(void); | ||
78 | extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq); | ||
79 | extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq); | ||
80 | extern u32 ipic_get_mcp_status(void); | ||
81 | extern void ipic_clear_mcp_status(u32 mask); | ||
82 | extern int ipic_get_irq(struct pt_regs *regs); | ||
83 | |||
84 | #endif /* __ASM_IPIC_H__ */ | ||
85 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h new file mode 100644 index 000000000000..06b86be61ed1 --- /dev/null +++ b/include/asm-ppc/irq.h | |||
@@ -0,0 +1,400 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _ASM_IRQ_H | ||
3 | #define _ASM_IRQ_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <asm/machdep.h> /* ppc_md */ | ||
7 | #include <asm/atomic.h> | ||
8 | |||
9 | /* | ||
10 | * These constants are used for passing information about interrupt | ||
11 | * signal polarity and level/edge sensing to the low-level PIC chip | ||
12 | * drivers. | ||
13 | */ | ||
14 | #define IRQ_SENSE_MASK 0x1 | ||
15 | #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ | ||
16 | #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ | ||
17 | |||
18 | #define IRQ_POLARITY_MASK 0x2 | ||
19 | #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ | ||
20 | #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ | ||
21 | |||
22 | #if defined(CONFIG_40x) | ||
23 | #include <asm/ibm4xx.h> | ||
24 | |||
25 | #ifndef NR_BOARD_IRQS | ||
26 | #define NR_BOARD_IRQS 0 | ||
27 | #endif | ||
28 | |||
29 | #ifndef UIC_WIDTH /* Number of interrupts per device */ | ||
30 | #define UIC_WIDTH 32 | ||
31 | #endif | ||
32 | |||
33 | #ifndef NR_UICS /* number of UIC devices */ | ||
34 | #define NR_UICS 1 | ||
35 | #endif | ||
36 | |||
37 | #if defined (CONFIG_403) | ||
38 | /* | ||
39 | * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has | ||
40 | * 32 possible interrupts, a majority of which are not implemented on | ||
41 | * all cores. There are six configurable, external interrupt pins and | ||
42 | * there are eight internal interrupts for the on-chip serial port | ||
43 | * (SPU), DMA controller, and JTAG controller. | ||
44 | * | ||
45 | */ | ||
46 | |||
47 | #define NR_AIC_IRQS 32 | ||
48 | #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) | ||
49 | |||
50 | #elif !defined (CONFIG_403) | ||
51 | |||
52 | /* | ||
53 | * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 | ||
54 | * possible interrupts as well. There are seven, configurable external | ||
55 | * interrupt pins and there are 17 internal interrupts for the on-chip | ||
56 | * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. | ||
57 | * | ||
58 | */ | ||
59 | |||
60 | |||
61 | #define NR_UIC_IRQS UIC_WIDTH | ||
62 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | ||
63 | #endif | ||
64 | static __inline__ int | ||
65 | irq_canonicalize(int irq) | ||
66 | { | ||
67 | return (irq); | ||
68 | } | ||
69 | |||
70 | #elif defined(CONFIG_44x) | ||
71 | #include <asm/ibm44x.h> | ||
72 | |||
73 | #define NR_UIC_IRQS 32 | ||
74 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | ||
75 | |||
76 | static __inline__ int | ||
77 | irq_canonicalize(int irq) | ||
78 | { | ||
79 | return (irq); | ||
80 | } | ||
81 | |||
82 | #elif defined(CONFIG_8xx) | ||
83 | |||
84 | /* Now include the board configuration specific associations. | ||
85 | */ | ||
86 | #include <asm/mpc8xx.h> | ||
87 | |||
88 | /* The MPC8xx cores have 16 possible interrupts. There are eight | ||
89 | * possible level sensitive interrupts assigned and generated internally | ||
90 | * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. | ||
91 | * There are eight external interrupts (IRQs) that can be configured | ||
92 | * as either level or edge sensitive. | ||
93 | * | ||
94 | * On some implementations, there is also the possibility of an 8259 | ||
95 | * through the PCI and PCI-ISA bridges. | ||
96 | * | ||
97 | * We are "flattening" the interrupt vectors of the cascaded CPM | ||
98 | * and 8259 interrupt controllers so that we can uniquely identify | ||
99 | * any interrupt source with a single integer. | ||
100 | */ | ||
101 | #define NR_SIU_INTS 16 | ||
102 | #define NR_CPM_INTS 32 | ||
103 | #ifndef NR_8259_INTS | ||
104 | #define NR_8259_INTS 0 | ||
105 | #endif | ||
106 | |||
107 | #define SIU_IRQ_OFFSET 0 | ||
108 | #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS) | ||
109 | #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | ||
110 | |||
111 | #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS) | ||
112 | |||
113 | /* These values must be zero-based and map 1:1 with the SIU configuration. | ||
114 | * They are used throughout the 8xx I/O subsystem to generate | ||
115 | * interrupt masks, flags, and other control patterns. This is why the | ||
116 | * current kernel assumption of the 8259 as the base controller is such | ||
117 | * a pain in the butt. | ||
118 | */ | ||
119 | #define SIU_IRQ0 (0) /* Highest priority */ | ||
120 | #define SIU_LEVEL0 (1) | ||
121 | #define SIU_IRQ1 (2) | ||
122 | #define SIU_LEVEL1 (3) | ||
123 | #define SIU_IRQ2 (4) | ||
124 | #define SIU_LEVEL2 (5) | ||
125 | #define SIU_IRQ3 (6) | ||
126 | #define SIU_LEVEL3 (7) | ||
127 | #define SIU_IRQ4 (8) | ||
128 | #define SIU_LEVEL4 (9) | ||
129 | #define SIU_IRQ5 (10) | ||
130 | #define SIU_LEVEL5 (11) | ||
131 | #define SIU_IRQ6 (12) | ||
132 | #define SIU_LEVEL6 (13) | ||
133 | #define SIU_IRQ7 (14) | ||
134 | #define SIU_LEVEL7 (15) | ||
135 | |||
136 | /* The internal interrupts we can configure as we see fit. | ||
137 | * My personal preference is CPM at level 2, which puts it above the | ||
138 | * MBX PCI/ISA/IDE interrupts. | ||
139 | */ | ||
140 | #ifndef PIT_INTERRUPT | ||
141 | #define PIT_INTERRUPT SIU_LEVEL0 | ||
142 | #endif | ||
143 | #ifndef CPM_INTERRUPT | ||
144 | #define CPM_INTERRUPT SIU_LEVEL2 | ||
145 | #endif | ||
146 | #ifndef PCMCIA_INTERRUPT | ||
147 | #define PCMCIA_INTERRUPT SIU_LEVEL6 | ||
148 | #endif | ||
149 | #ifndef DEC_INTERRUPT | ||
150 | #define DEC_INTERRUPT SIU_LEVEL7 | ||
151 | #endif | ||
152 | |||
153 | /* Some internal interrupt registers use an 8-bit mask for the interrupt | ||
154 | * level instead of a number. | ||
155 | */ | ||
156 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | ||
157 | |||
158 | /* always the same on 8xx -- Cort */ | ||
159 | static __inline__ int irq_canonicalize(int irq) | ||
160 | { | ||
161 | return irq; | ||
162 | } | ||
163 | |||
164 | #elif defined(CONFIG_83xx) | ||
165 | #include <asm/mpc83xx.h> | ||
166 | |||
167 | static __inline__ int irq_canonicalize(int irq) | ||
168 | { | ||
169 | return irq; | ||
170 | } | ||
171 | |||
172 | #define NR_IRQS (NR_IPIC_INTS) | ||
173 | |||
174 | #elif defined(CONFIG_85xx) | ||
175 | /* Now include the board configuration specific associations. | ||
176 | */ | ||
177 | #include <asm/mpc85xx.h> | ||
178 | |||
179 | /* The MPC8560 openpic has 32 internal interrupts and 12 external | ||
180 | * interrupts. | ||
181 | * | ||
182 | * We are "flattening" the interrupt vectors of the cascaded CPM | ||
183 | * so that we can uniquely identify any interrupt source with a | ||
184 | * single integer. | ||
185 | */ | ||
186 | #define NR_CPM_INTS 64 | ||
187 | #define NR_EPIC_INTS 44 | ||
188 | #ifndef NR_8259_INTS | ||
189 | #define NR_8259_INTS 0 | ||
190 | #endif | ||
191 | #define NUM_8259_INTERRUPTS NR_8259_INTS | ||
192 | |||
193 | #ifndef CPM_IRQ_OFFSET | ||
194 | #define CPM_IRQ_OFFSET 0 | ||
195 | #endif | ||
196 | |||
197 | #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) | ||
198 | |||
199 | /* Internal IRQs on MPC85xx OpenPIC */ | ||
200 | |||
201 | #ifndef MPC85xx_OPENPIC_IRQ_OFFSET | ||
202 | #ifdef CONFIG_CPM2 | ||
203 | #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | ||
204 | #else | ||
205 | #define MPC85xx_OPENPIC_IRQ_OFFSET 0 | ||
206 | #endif | ||
207 | #endif | ||
208 | |||
209 | /* Not all of these exist on all MPC85xx implementations */ | ||
210 | #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
211 | #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
212 | #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
213 | #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
214 | #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
215 | #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
216 | #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
217 | #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
218 | #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
219 | #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
220 | #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
221 | #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
222 | #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
223 | #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
224 | #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
225 | #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
226 | #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
227 | #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
228 | #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
229 | #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
230 | #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
231 | #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
232 | #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
233 | #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
234 | #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
235 | #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
236 | |||
237 | /* The 12 external interrupt lines */ | ||
238 | #define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
239 | #define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
240 | #define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
241 | #define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
242 | #define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
243 | #define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
244 | #define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
245 | #define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
246 | #define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
247 | #define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
248 | #define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
249 | #define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
250 | |||
251 | /* CPM related interrupts */ | ||
252 | #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) | ||
253 | #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) | ||
254 | #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) | ||
255 | #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) | ||
256 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) | ||
257 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) | ||
258 | #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) | ||
259 | #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) | ||
260 | #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) | ||
261 | #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) | ||
262 | #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) | ||
263 | #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) | ||
264 | #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) | ||
265 | #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) | ||
266 | #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) | ||
267 | #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) | ||
268 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) | ||
269 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) | ||
270 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) | ||
271 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) | ||
272 | #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) | ||
273 | #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) | ||
274 | #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) | ||
275 | #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) | ||
276 | #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) | ||
277 | #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) | ||
278 | #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) | ||
279 | #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) | ||
280 | #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) | ||
281 | #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) | ||
282 | #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) | ||
283 | #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) | ||
284 | #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) | ||
285 | #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) | ||
286 | #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) | ||
287 | #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) | ||
288 | |||
289 | static __inline__ int irq_canonicalize(int irq) | ||
290 | { | ||
291 | return irq; | ||
292 | } | ||
293 | |||
294 | #else /* CONFIG_40x + CONFIG_8xx */ | ||
295 | /* | ||
296 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) | ||
297 | * so it is the max of them all | ||
298 | */ | ||
299 | #define NR_IRQS 256 | ||
300 | |||
301 | #ifndef CONFIG_8260 | ||
302 | |||
303 | #define NUM_8259_INTERRUPTS 16 | ||
304 | |||
305 | #else /* CONFIG_8260 */ | ||
306 | |||
307 | /* The 8260 has an internal interrupt controller with a maximum of | ||
308 | * 64 IRQs. We will use NR_IRQs from above since it is large enough. | ||
309 | * Don't be confused by the 8260 documentation where they list an | ||
310 | * "interrupt number" and "interrupt vector". We are only interested | ||
311 | * in the interrupt vector. There are "reserved" holes where the | ||
312 | * vector number increases, but the interrupt number in the table does not. | ||
313 | * (Document errata updates have fixed this...make sure you have up to | ||
314 | * date processor documentation -- Dan). | ||
315 | */ | ||
316 | |||
317 | #ifndef CPM_IRQ_OFFSET | ||
318 | #define CPM_IRQ_OFFSET 0 | ||
319 | #endif | ||
320 | |||
321 | #define NR_CPM_INTS 64 | ||
322 | |||
323 | #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET) | ||
324 | #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET) | ||
325 | #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET) | ||
326 | #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET) | ||
327 | #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET) | ||
328 | #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET) | ||
329 | #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET) | ||
330 | #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET) | ||
331 | #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET) | ||
332 | #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET) | ||
333 | #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET) | ||
334 | #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET) | ||
335 | #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET) | ||
336 | #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET) | ||
337 | #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET) | ||
338 | #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET) | ||
339 | #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET) | ||
340 | #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET) | ||
341 | #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET) | ||
342 | #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET) | ||
343 | #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET) | ||
344 | #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET) | ||
345 | #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET) | ||
346 | #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET) | ||
347 | #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET) | ||
348 | #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET) | ||
349 | #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET) | ||
350 | #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET) | ||
351 | #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET) | ||
352 | #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET) | ||
353 | #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET) | ||
354 | #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET) | ||
355 | #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET) | ||
356 | #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET) | ||
357 | #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET) | ||
358 | #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET) | ||
359 | #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET) | ||
360 | #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET) | ||
361 | #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET) | ||
362 | #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET) | ||
363 | #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET) | ||
364 | #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET) | ||
365 | #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET) | ||
366 | #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET) | ||
367 | #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET) | ||
368 | #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET) | ||
369 | #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET) | ||
370 | #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET) | ||
371 | #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET) | ||
372 | |||
373 | #endif /* CONFIG_8260 */ | ||
374 | |||
375 | /* | ||
376 | * This gets called from serial.c, which is now used on | ||
377 | * powermacs as well as prep/chrp boxes. | ||
378 | * Prep and chrp both have cascaded 8259 PICs. | ||
379 | */ | ||
380 | static __inline__ int irq_canonicalize(int irq) | ||
381 | { | ||
382 | if (ppc_md.irq_canonicalize) | ||
383 | return ppc_md.irq_canonicalize(irq); | ||
384 | return irq; | ||
385 | } | ||
386 | |||
387 | #endif | ||
388 | |||
389 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) | ||
390 | /* pedantic: these are long because they are used with set_bit --RR */ | ||
391 | extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; | ||
392 | extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | ||
393 | extern atomic_t ppc_n_lost_interrupts; | ||
394 | |||
395 | struct irqaction; | ||
396 | struct pt_regs; | ||
397 | int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); | ||
398 | |||
399 | #endif /* _ASM_IRQ_H */ | ||
400 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h new file mode 100644 index 000000000000..457c75a4622f --- /dev/null +++ b/include/asm-ppc/keylargo.h | |||
@@ -0,0 +1,243 @@ | |||
1 | /* | ||
2 | * keylargo.h: definitions for using the "KeyLargo" I/O controller chip. | ||
3 | * | ||
4 | */ | ||
5 | |||
6 | /* "Pangea" chipset has keylargo device-id 0x25 while core99 | ||
7 | * has device-id 0x22. The rev. of the pangea one is 0, so we | ||
8 | * fake an artificial rev. in keylargo_rev by oring 0x100 | ||
9 | */ | ||
10 | #define KL_PANGEA_REV 0x100 | ||
11 | |||
12 | /* offset from base for feature control registers */ | ||
13 | #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */ | ||
14 | #define KEYLARGO_FCR0 0x38 | ||
15 | #define KEYLARGO_FCR1 0x3c | ||
16 | #define KEYLARGO_FCR2 0x40 | ||
17 | #define KEYLARGO_FCR3 0x44 | ||
18 | #define KEYLARGO_FCR4 0x48 | ||
19 | #define KEYLARGO_FCR5 0x4c /* Pangea only */ | ||
20 | |||
21 | /* K2 aditional FCRs */ | ||
22 | #define K2_FCR6 0x34 | ||
23 | #define K2_FCR7 0x30 | ||
24 | #define K2_FCR8 0x2c | ||
25 | #define K2_FCR9 0x28 | ||
26 | #define K2_FCR10 0x24 | ||
27 | |||
28 | /* GPIO registers */ | ||
29 | #define KEYLARGO_GPIO_LEVELS0 0x50 | ||
30 | #define KEYLARGO_GPIO_LEVELS1 0x54 | ||
31 | #define KEYLARGO_GPIO_EXTINT_0 0x58 | ||
32 | #define KEYLARGO_GPIO_EXTINT_CNT 18 | ||
33 | #define KEYLARGO_GPIO_0 0x6A | ||
34 | #define KEYLARGO_GPIO_CNT 17 | ||
35 | #define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80 | ||
36 | #define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04 | ||
37 | #define KEYLARGO_GPIO_OUTOUT_DATA 0x01 | ||
38 | #define KEYLARGO_GPIO_INPUT_DATA 0x02 | ||
39 | |||
40 | /* K2 does only extint GPIOs and does 51 of them */ | ||
41 | #define K2_GPIO_EXTINT_0 0x58 | ||
42 | #define K2_GPIO_EXTINT_CNT 51 | ||
43 | |||
44 | /* Specific GPIO regs */ | ||
45 | |||
46 | #define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03) | ||
47 | #define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */ | ||
48 | |||
49 | #define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05) | ||
50 | |||
51 | /* Hrm... this one is only to be used on Pismo. It seeem to also | ||
52 | * control the timebase enable on other machines. Still to be | ||
53 | * experimented... --BenH. | ||
54 | */ | ||
55 | #define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09) | ||
56 | #define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09) | ||
57 | |||
58 | #define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10) | ||
59 | |||
60 | #define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a) | ||
61 | #define KL_GPIO_EXTINT_CPU1_ASSERT 0x04 | ||
62 | #define KL_GPIO_EXTINT_CPU1_RELEASE 0x38 | ||
63 | |||
64 | #define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03) | ||
65 | #define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04) | ||
66 | #define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f) | ||
67 | #define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10) | ||
68 | |||
69 | #define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09) | ||
70 | #define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA | ||
71 | |||
72 | #define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e) | ||
73 | |||
74 | #define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a) | ||
75 | #define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d) | ||
76 | #define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d) | ||
77 | #define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e) | ||
78 | #define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f) | ||
79 | |||
80 | /* | ||
81 | * Bits in feature control register. Those bits different for K2 are | ||
82 | * listed separately | ||
83 | */ | ||
84 | #define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */ | ||
85 | #define KL_MBCR_MB0_IDE_ENABLE 0x00001000 | ||
86 | #define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */ | ||
87 | #define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */ | ||
88 | #define KL_MBCR_MB0_DEV_MASK 0x00007800 | ||
89 | #define KL_MBCR_MB0_DEV_POWER 0x00000400 | ||
90 | #define KL_MBCR_MB0_DEV_RESET 0x00000200 | ||
91 | #define KL_MBCR_MB0_ENABLE 0x00000100 | ||
92 | #define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */ | ||
93 | #define KL_MBCR_MB1_IDE_ENABLE 0x10000000 | ||
94 | #define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */ | ||
95 | #define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */ | ||
96 | #define KL_MBCR_MB1_DEV_MASK 0x78000000 | ||
97 | #define KL_MBCR_MB1_DEV_POWER 0x04000000 | ||
98 | #define KL_MBCR_MB1_DEV_RESET 0x02000000 | ||
99 | #define KL_MBCR_MB1_ENABLE 0x01000000 | ||
100 | |||
101 | #define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */ | ||
102 | #define KL0_SCC_A_INTF_ENABLE 0x00000002 | ||
103 | #define KL0_SCC_SLOWPCLK 0x00000004 | ||
104 | #define KL0_SCC_RESET 0x00000008 | ||
105 | #define KL0_SCCA_ENABLE 0x00000010 | ||
106 | #define KL0_SCCB_ENABLE 0x00000020 | ||
107 | #define KL0_SCC_CELL_ENABLE 0x00000040 | ||
108 | #define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */ | ||
109 | #define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */ | ||
110 | #define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */ | ||
111 | #define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */ | ||
112 | #define KL0_IRDA_RESET 0x00000800 /* (KL Only) */ | ||
113 | #define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */ | ||
114 | #define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */ | ||
115 | #define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */ | ||
116 | #define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */ | ||
117 | #define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */ | ||
118 | #define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */ | ||
119 | #define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */ | ||
120 | #define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */ | ||
121 | #define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */ | ||
122 | #define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */ | ||
123 | #define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */ | ||
124 | #define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */ | ||
125 | #define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */ | ||
126 | #define KL0_USB0_PAD_SUSPEND0 0x00040000 | ||
127 | #define KL0_USB0_PAD_SUSPEND1 0x00080000 | ||
128 | #define KL0_USB0_CELL_ENABLE 0x00100000 | ||
129 | #define KL0_USB1_PAD_SUSPEND0 0x00400000 | ||
130 | #define KL0_USB1_PAD_SUSPEND1 0x00800000 | ||
131 | #define KL0_USB1_CELL_ENABLE 0x01000000 | ||
132 | #define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */ | ||
133 | |||
134 | #define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \ | ||
135 | KL0_SCC_SLOWPCLK | \ | ||
136 | KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE) | ||
137 | |||
138 | #define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */ | ||
139 | #define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */ | ||
140 | #define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */ | ||
141 | #define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */ | ||
142 | #define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */ | ||
143 | #define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */ | ||
144 | #define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */ | ||
145 | #define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */ | ||
146 | #define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */ | ||
147 | #define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */ | ||
148 | #define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */ | ||
149 | #define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */ | ||
150 | #define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */ | ||
151 | #define KL1_I2S0_CELL_ENABLE 0x00000400 | ||
152 | #define KL1_I2S0_CLK_ENABLE_BIT 0x00001000 | ||
153 | #define KL1_I2S0_ENABLE 0x00002000 | ||
154 | #define KL1_I2S1_CELL_ENABLE 0x00020000 | ||
155 | #define KL1_I2S1_CLK_ENABLE_BIT 0x00080000 | ||
156 | #define KL1_I2S1_ENABLE 0x00100000 | ||
157 | #define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */ | ||
158 | #define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */ | ||
159 | #define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */ | ||
160 | #define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */ | ||
161 | #define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */ | ||
162 | #define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */ | ||
163 | |||
164 | #define KL2_IOBUS_ENABLE 0x00000002 | ||
165 | #define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */ | ||
166 | #define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */ | ||
167 | #define KL2_MPIC_ENABLE 0x00020000 | ||
168 | #define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */ | ||
169 | #define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */ | ||
170 | #define KL2_MEM_IS_BIG 0x04000000 | ||
171 | #define KL2_CARDSEL_16 0x08000000 | ||
172 | |||
173 | #define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */ | ||
174 | #define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */ | ||
175 | #define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */ | ||
176 | #define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */ | ||
177 | #define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */ | ||
178 | #define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */ | ||
179 | #define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */ | ||
180 | #define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */ | ||
181 | #define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */ | ||
182 | #define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */ | ||
183 | #define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */ | ||
184 | #define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */ | ||
185 | #define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */ | ||
186 | #define KL3_CLK66_ENABLE 0x00000100 /* KL Only */ | ||
187 | #define KL3_CLK49_ENABLE 0x00000200 | ||
188 | #define KL3_CLK45_ENABLE 0x00000400 | ||
189 | #define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */ | ||
190 | #define KL3_TIMER_CLK18_ENABLE 0x00001000 | ||
191 | #define KL3_I2S1_CLK18_ENABLE 0x00002000 | ||
192 | #define KL3_I2S0_CLK18_ENABLE 0x00004000 | ||
193 | #define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */ | ||
194 | #define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */ | ||
195 | #define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */ | ||
196 | #define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */ | ||
197 | |||
198 | /* Intrepid USB bus 2, port 0,1 */ | ||
199 | #define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3)) | ||
200 | #define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3)) | ||
201 | #define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3)) | ||
202 | #define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3)) | ||
203 | #define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3)) | ||
204 | #define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3)) | ||
205 | #define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3)) | ||
206 | |||
207 | /* Port 0,1 : bus 0, port 2,3 : bus 1 */ | ||
208 | #define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3)) | ||
209 | #define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3)) | ||
210 | #define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3)) | ||
211 | #define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3)) | ||
212 | #define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3)) | ||
213 | #define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3)) | ||
214 | #define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3)) | ||
215 | |||
216 | /* Pangea and Intrepid only */ | ||
217 | #define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */ | ||
218 | #define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */ | ||
219 | #define KL5_PWM_CLK32_EN 0x00000004 | ||
220 | #define KL5_CLK3_68_EN 0x00000010 | ||
221 | #define KL5_CLK32_EN 0x00000020 | ||
222 | |||
223 | |||
224 | /* K2 definitions */ | ||
225 | #define K2_FCR0_USB0_SWRESET 0x00200000 | ||
226 | #define K2_FCR0_USB1_SWRESET 0x02000000 | ||
227 | #define K2_FCR0_RING_PME_DISABLE 0x08000000 | ||
228 | |||
229 | #define K2_FCR1_PCI1_BUS_RESET_N 0x00000010 | ||
230 | #define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020 | ||
231 | #define K2_FCR1_PCI1_CLK_ENABLE 0x00004000 | ||
232 | #define K2_FCR1_FW_CLK_ENABLE 0x00008000 | ||
233 | #define K2_FCR1_FW_RESET_N 0x00010000 | ||
234 | #define K2_FCR1_GMAC_CLK_ENABLE 0x00400000 | ||
235 | #define K2_FCR1_GMAC_POWER_DOWN 0x00800000 | ||
236 | #define K2_FCR1_GMAC_RESET_N 0x01000000 | ||
237 | #define K2_FCR1_SATA_CLK_ENABLE 0x02000000 | ||
238 | #define K2_FCR1_SATA_POWER_DOWN 0x04000000 | ||
239 | #define K2_FCR1_SATA_RESET_N 0x08000000 | ||
240 | #define K2_FCR1_UATA_CLK_ENABLE 0x10000000 | ||
241 | #define K2_FCR1_UATA_RESET_N 0x40000000 | ||
242 | #define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000 | ||
243 | |||
diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h new file mode 100644 index 000000000000..1d3c927ce626 --- /dev/null +++ b/include/asm-ppc/kgdb.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * kgdb.h: Defines and declarations for serial line source level | ||
3 | * remote debugging of the Linux kernel using gdb. | ||
4 | * | ||
5 | * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu) | ||
6 | * | ||
7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef _PPC_KGDB_H | ||
11 | #define _PPC_KGDB_H | ||
12 | |||
13 | #ifndef __ASSEMBLY__ | ||
14 | |||
15 | /* Things specific to the gen550 backend. */ | ||
16 | struct uart_port; | ||
17 | |||
18 | extern void gen550_progress(char *, unsigned short); | ||
19 | extern void gen550_kgdb_map_scc(void); | ||
20 | extern void gen550_init(int, struct uart_port *); | ||
21 | |||
22 | /* Things specific to the pmac backend. */ | ||
23 | extern void zs_kgdb_hook(int tty_num); | ||
24 | |||
25 | /* To init the kgdb engine. (called by serial hook)*/ | ||
26 | extern void set_debug_traps(void); | ||
27 | |||
28 | /* To enter the debugger explicitly. */ | ||
29 | extern void breakpoint(void); | ||
30 | |||
31 | /* For taking exceptions | ||
32 | * these are defined in traps.c | ||
33 | */ | ||
34 | extern void (*debugger)(struct pt_regs *regs); | ||
35 | extern int (*debugger_bpt)(struct pt_regs *regs); | ||
36 | extern int (*debugger_sstep)(struct pt_regs *regs); | ||
37 | extern int (*debugger_iabr_match)(struct pt_regs *regs); | ||
38 | extern int (*debugger_dabr_match)(struct pt_regs *regs); | ||
39 | extern void (*debugger_fault_handler)(struct pt_regs *regs); | ||
40 | |||
41 | /* What we bring to the party */ | ||
42 | int kgdb_bpt(struct pt_regs *regs); | ||
43 | int kgdb_sstep(struct pt_regs *regs); | ||
44 | void kgdb(struct pt_regs *regs); | ||
45 | int kgdb_iabr_match(struct pt_regs *regs); | ||
46 | int kgdb_dabr_match(struct pt_regs *regs); | ||
47 | |||
48 | /* | ||
49 | * external low-level support routines (ie macserial.c) | ||
50 | */ | ||
51 | extern void kgdb_interruptible(int); /* control interrupts from serial */ | ||
52 | extern void putDebugChar(char); /* write a single character */ | ||
53 | extern char getDebugChar(void); /* read and return a single char */ | ||
54 | |||
55 | #endif /* !(__ASSEMBLY__) */ | ||
56 | #endif /* !(_PPC_KGDB_H) */ | ||
57 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h new file mode 100644 index 000000000000..2589f182a6ad --- /dev/null +++ b/include/asm-ppc/kmap_types.h | |||
@@ -0,0 +1,24 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _ASM_KMAP_TYPES_H | ||
3 | #define _ASM_KMAP_TYPES_H | ||
4 | |||
5 | enum km_type { | ||
6 | KM_BOUNCE_READ, | ||
7 | KM_SKB_SUNRPC_DATA, | ||
8 | KM_SKB_DATA_SOFTIRQ, | ||
9 | KM_USER0, | ||
10 | KM_USER1, | ||
11 | KM_BIO_SRC_IRQ, | ||
12 | KM_BIO_DST_IRQ, | ||
13 | KM_PTE0, | ||
14 | KM_PTE1, | ||
15 | KM_IRQ0, | ||
16 | KM_IRQ1, | ||
17 | KM_SOFTIRQ0, | ||
18 | KM_SOFTIRQ1, | ||
19 | KM_PPC_SYNC_PAGE, | ||
20 | KM_TYPE_NR | ||
21 | }; | ||
22 | |||
23 | #endif | ||
24 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/linkage.h b/include/asm-ppc/linkage.h new file mode 100644 index 000000000000..291c2d01c44f --- /dev/null +++ b/include/asm-ppc/linkage.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __ASM_LINKAGE_H | ||
2 | #define __ASM_LINKAGE_H | ||
3 | |||
4 | /* Nothing to see here... */ | ||
5 | |||
6 | #endif | ||
diff --git a/include/asm-ppc/local.h b/include/asm-ppc/local.h new file mode 100644 index 000000000000..b08e3eced10e --- /dev/null +++ b/include/asm-ppc/local.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __PPC_LOCAL_H | ||
2 | #define __PPC_LOCAL_H | ||
3 | |||
4 | #include <asm-generic/local.h> | ||
5 | |||
6 | #endif /* __PPC_LOCAL_H */ | ||
diff --git a/include/asm-ppc/m48t35.h b/include/asm-ppc/m48t35.h new file mode 100644 index 000000000000..f3c5e5dfa986 --- /dev/null +++ b/include/asm-ppc/m48t35.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* | ||
2 | * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip | ||
3 | * and | ||
4 | * Registers for the SGS-Thomson M48T37 Timekeeper RAM chip | ||
5 | * The 37 is the 35 plus alarm and century thus the offsets | ||
6 | * are shifted by the extra registers. | ||
7 | */ | ||
8 | |||
9 | #ifndef __PPC_M48T35_H | ||
10 | #define __PPC_M48T35_H | ||
11 | |||
12 | /* RTC offsets */ | ||
13 | #define M48T35_RTC_FLAGS (-8) /* the negative regs are really T37 only */ | ||
14 | #define M48T35_RTC_CENTURY (-7) | ||
15 | #define M48T35_RTC_AL_SEC (-6) | ||
16 | #define M48T35_RTC_AL_MIN (-5) | ||
17 | #define M48T35_RTC_AL_HRS (-4) | ||
18 | #define M48T35_RTC_AL_DOM (-3) | ||
19 | #define M48T35_RTC_INTERRUPT (-2) | ||
20 | #define M48T35_RTC_WATCHDOG (-1) | ||
21 | #define M48T35_RTC_CONTROL 0 /* T35 starts here */ | ||
22 | #define M48T35_RTC_SECONDS 1 | ||
23 | #define M48T35_RTC_MINUTES 2 | ||
24 | #define M48T35_RTC_HOURS 3 | ||
25 | #define M48T35_RTC_DAY 4 | ||
26 | #define M48T35_RTC_DOM 5 | ||
27 | #define M48T35_RTC_MONTH 6 | ||
28 | #define M48T35_RTC_YEAR 7 | ||
29 | |||
30 | /* this way help us know which bits go with which regs */ | ||
31 | #define M48T35_RTC_FLAGS_BL 0x10 | ||
32 | #define M48T35_RTC_FLAGS_AF 0x40 | ||
33 | #define M48T35_RTC_FLAGS_WDF 0x80 | ||
34 | |||
35 | #define M48T35_RTC_INTERRUPT_AFE 0x80 | ||
36 | #define M48T35_RTC_INTERRUPT_ABE 0x20 | ||
37 | #define M48T35_RTC_INTERRUPT_ALL (M48T35_RTC_INTERRUPT_AFE|M48T35_RTC_INTERRUPT_ABE) | ||
38 | |||
39 | #define M48T35_RTC_WATCHDOG_RB 0x03 | ||
40 | #define M48T35_RTC_WATCHDOG_BMB 0x7c | ||
41 | #define M48T35_RTC_WATCHDOG_WDS 0x80 | ||
42 | #define M48T35_RTC_WATCHDOG_ALL (M48T35_RTC_WATCHDOG_RB|M48T35_RTC_WATCHDOG_BMB|M48T35_RTC_W | ||
43 | |||
44 | #define M48T35_RTC_CONTROL_WRITE 0x80 | ||
45 | #define M48T35_RTC_CONTROL_READ 0x40 | ||
46 | #define M48T35_RTC_CONTROL_CAL_SIGN 0x20 | ||
47 | #define M48T35_RTC_CONTROL_CAL_VALUE 0x1f | ||
48 | #define M48T35_RTC_CONTROL_LOCKED (M48T35_RTC_WRITE|M48T35_RTC_READ) | ||
49 | #define M48T35_RTC_CONTROL_CALIBRATION (M48T35_RTC_CONTROL_CAL_SIGN|M48T35_RTC_CONTROL_CAL_VALUE) | ||
50 | |||
51 | #define M48T35_RTC_SECONDS_SEC_1 0x0f | ||
52 | #define M48T35_RTC_SECONDS_SEC_10 0x70 | ||
53 | #define M48T35_RTC_SECONDS_ST 0x80 | ||
54 | #define M48T35_RTC_SECONDS_SEC_ALL (M48T35_RTC_SECONDS_SEC_1|M48T35_RTC_SECONDS_SEC_10) | ||
55 | |||
56 | #define M48T35_RTC_MINUTES_MIN_1 0x0f | ||
57 | #define M48T35_RTC_MINUTES_MIN_10 0x70 | ||
58 | #define M48T35_RTC_MINUTES_MIN_ALL (M48T35_RTC_MINUTES_MIN_1|M48T35_RTC_MINUTES_MIN_10) | ||
59 | |||
60 | #define M48T35_RTC_HOURS_HRS_1 0x0f | ||
61 | #define M48T35_RTC_HOURS_HRS_10 0x30 | ||
62 | #define M48T35_RTC_HOURS_HRS_ALL (M48T35_RTC_HOURS_HRS_1|M48T35_RTC_HOURS_HRS_10) | ||
63 | |||
64 | #define M48T35_RTC_DAY_DAY_1 0x03 | ||
65 | #define M48T35_RTC_DAY_FT 0x40 | ||
66 | |||
67 | #define M48T35_RTC_ALARM_OFF 0x00 | ||
68 | #define M48T35_RTC_WATCHDOG_OFF 0x00 | ||
69 | |||
70 | |||
71 | /* legacy */ | ||
72 | #define M48T35_RTC_SET 0x80 | ||
73 | #define M48T35_RTC_STOPPED 0x80 | ||
74 | #define M48T35_RTC_READ 0x40 | ||
75 | |||
76 | |||
77 | #endif | ||
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h new file mode 100644 index 000000000000..163a6b91d5b2 --- /dev/null +++ b/include/asm-ppc/m8260_pci.h | |||
@@ -0,0 +1,186 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/m8260_pci.h | ||
3 | * | ||
4 | * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifdef __KERNEL__ | ||
13 | #ifndef __M8260_PCI_H | ||
14 | #define __M8260_PCI_H | ||
15 | |||
16 | #include <linux/pci_ids.h> | ||
17 | |||
18 | /* | ||
19 | * Define the vendor/device ID for the MPC8265. | ||
20 | */ | ||
21 | #define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
22 | |||
23 | #define M8265_PCIBR0 0x101ac | ||
24 | #define M8265_PCIBR1 0x101b0 | ||
25 | #define M8265_PCIMSK0 0x101c4 | ||
26 | #define M8265_PCIMSK1 0x101c8 | ||
27 | |||
28 | /* Bit definitions for PCIBR registers */ | ||
29 | |||
30 | #define PCIBR_ENABLE 0x00000001 | ||
31 | |||
32 | /* Bit definitions for PCIMSK registers */ | ||
33 | |||
34 | #define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */ | ||
35 | #define PCIMSK_64KiB 0xFFFF0000 | ||
36 | #define PCIMSK_128KiB 0xFFFE0000 | ||
37 | #define PCIMSK_256KiB 0xFFFC0000 | ||
38 | #define PCIMSK_512KiB 0xFFF80000 | ||
39 | #define PCIMSK_1MiB 0xFFF00000 | ||
40 | #define PCIMSK_2MiB 0xFFE00000 | ||
41 | #define PCIMSK_4MiB 0xFFC00000 | ||
42 | #define PCIMSK_8MiB 0xFF800000 | ||
43 | #define PCIMSK_16MiB 0xFF000000 | ||
44 | #define PCIMSK_32MiB 0xFE000000 | ||
45 | #define PCIMSK_64MiB 0xFC000000 | ||
46 | #define PCIMSK_128MiB 0xF8000000 | ||
47 | #define PCIMSK_256MiB 0xF0000000 | ||
48 | #define PCIMSK_512MiB 0xE0000000 | ||
49 | #define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */ | ||
50 | |||
51 | |||
52 | #define M826X_SCCR_PCI_MODE_EN 0x100 | ||
53 | |||
54 | |||
55 | /* | ||
56 | * Outbound ATU registers (3 sets). These registers control how 60x bus (local) | ||
57 | * addresses are translated to PCI addresses when the MPC826x is a PCI bus | ||
58 | * master (initiator). | ||
59 | */ | ||
60 | |||
61 | #define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ | ||
62 | #define POTAR_REG1 0x10818 | ||
63 | #define POTAR_REG2 0x10830 | ||
64 | |||
65 | #define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ | ||
66 | #define POBAR_REG1 0x10820 | ||
67 | #define POBAR_REG2 0x10838 | ||
68 | |||
69 | #define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ | ||
70 | #define POCMR_REG1 0x10828 | ||
71 | #define POCMR_REG2 0x10840 | ||
72 | |||
73 | /* Bit definitions for POMCR registers */ | ||
74 | |||
75 | #define POCMR_MASK_4KiB 0x000FFFFF | ||
76 | #define POCMR_MASK_8KiB 0x000FFFFE | ||
77 | #define POCMR_MASK_16KiB 0x000FFFFC | ||
78 | #define POCMR_MASK_32KiB 0x000FFFF8 | ||
79 | #define POCMR_MASK_64KiB 0x000FFFF0 | ||
80 | #define POCMR_MASK_128KiB 0x000FFFE0 | ||
81 | #define POCMR_MASK_256KiB 0x000FFFC0 | ||
82 | #define POCMR_MASK_512KiB 0x000FFF80 | ||
83 | #define POCMR_MASK_1MiB 0x000FFF00 | ||
84 | #define POCMR_MASK_2MiB 0x000FFE00 | ||
85 | #define POCMR_MASK_4MiB 0x000FFC00 | ||
86 | #define POCMR_MASK_8MiB 0x000FF800 | ||
87 | #define POCMR_MASK_16MiB 0x000FF000 | ||
88 | #define POCMR_MASK_32MiB 0x000FE000 | ||
89 | #define POCMR_MASK_64MiB 0x000FC000 | ||
90 | #define POCMR_MASK_128MiB 0x000F8000 | ||
91 | #define POCMR_MASK_256MiB 0x000F0000 | ||
92 | #define POCMR_MASK_512MiB 0x000E0000 | ||
93 | #define POCMR_MASK_1GiB 0x000C0000 | ||
94 | |||
95 | #define POCMR_ENABLE 0x80000000 | ||
96 | #define POCMR_PCI_IO 0x40000000 | ||
97 | #define POCMR_PREFETCH_EN 0x20000000 | ||
98 | |||
99 | /* Soft PCI reset */ | ||
100 | |||
101 | #define PCI_GCR_REG 0x10880 | ||
102 | |||
103 | /* Bit definitions for PCI_GCR registers */ | ||
104 | |||
105 | #define PCIGCR_PCI_BUS_EN 0x1 | ||
106 | |||
107 | #define PCI_EMR_REG 0x10888 | ||
108 | /* | ||
109 | * Inbound ATU registers (2 sets). These registers control how PCI addresses | ||
110 | * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. | ||
111 | */ | ||
112 | |||
113 | #define PITAR_REG1 0x108D0 | ||
114 | #define PIBAR_REG1 0x108D8 | ||
115 | #define PICMR_REG1 0x108E0 | ||
116 | #define PITAR_REG0 0x108E8 | ||
117 | #define PIBAR_REG0 0x108F0 | ||
118 | #define PICMR_REG0 0x108F8 | ||
119 | |||
120 | /* Bit definitions for PCI Inbound Comparison Mask registers */ | ||
121 | |||
122 | #define PICMR_MASK_4KiB 0x000FFFFF | ||
123 | #define PICMR_MASK_8KiB 0x000FFFFE | ||
124 | #define PICMR_MASK_16KiB 0x000FFFFC | ||
125 | #define PICMR_MASK_32KiB 0x000FFFF8 | ||
126 | #define PICMR_MASK_64KiB 0x000FFFF0 | ||
127 | #define PICMR_MASK_128KiB 0x000FFFE0 | ||
128 | #define PICMR_MASK_256KiB 0x000FFFC0 | ||
129 | #define PICMR_MASK_512KiB 0x000FFF80 | ||
130 | #define PICMR_MASK_1MiB 0x000FFF00 | ||
131 | #define PICMR_MASK_2MiB 0x000FFE00 | ||
132 | #define PICMR_MASK_4MiB 0x000FFC00 | ||
133 | #define PICMR_MASK_8MiB 0x000FF800 | ||
134 | #define PICMR_MASK_16MiB 0x000FF000 | ||
135 | #define PICMR_MASK_32MiB 0x000FE000 | ||
136 | #define PICMR_MASK_64MiB 0x000FC000 | ||
137 | #define PICMR_MASK_128MiB 0x000F8000 | ||
138 | #define PICMR_MASK_256MiB 0x000F0000 | ||
139 | #define PICMR_MASK_512MiB 0x000E0000 | ||
140 | #define PICMR_MASK_1GiB 0x000C0000 | ||
141 | |||
142 | #define PICMR_ENABLE 0x80000000 | ||
143 | #define PICMR_NO_SNOOP_EN 0x40000000 | ||
144 | #define PICMR_PREFETCH_EN 0x20000000 | ||
145 | |||
146 | /* PCI error Registers */ | ||
147 | |||
148 | #define PCI_ERROR_STATUS_REG 0x10884 | ||
149 | #define PCI_ERROR_MASK_REG 0x10888 | ||
150 | #define PCI_ERROR_CONTROL_REG 0x1088C | ||
151 | #define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 | ||
152 | #define PCI_ERROR_DATA_CAPTURE_REG 0x10898 | ||
153 | #define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 | ||
154 | |||
155 | /* PCI error Register bit defines */ | ||
156 | |||
157 | #define PCI_ERROR_PCI_ADDR_PAR 0x00000001 | ||
158 | #define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 | ||
159 | #define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 | ||
160 | #define PCI_ERROR_PCI_NO_RSP 0x00000008 | ||
161 | #define PCI_ERROR_PCI_TAR_ABT 0x00000010 | ||
162 | #define PCI_ERROR_PCI_SERR 0x00000020 | ||
163 | #define PCI_ERROR_PCI_PERR_RD 0x00000040 | ||
164 | #define PCI_ERROR_PCI_PERR_WR 0x00000080 | ||
165 | #define PCI_ERROR_I2O_OFQO 0x00000100 | ||
166 | #define PCI_ERROR_I2O_IPQO 0x00000200 | ||
167 | #define PCI_ERROR_IRA 0x00000400 | ||
168 | #define PCI_ERROR_NMI 0x00000800 | ||
169 | #define PCI_ERROR_I2O_DBMC 0x00001000 | ||
170 | |||
171 | /* | ||
172 | * Register pair used to generate configuration cycles on the PCI bus | ||
173 | * and access the MPC826x's own PCI configuration registers. | ||
174 | */ | ||
175 | |||
176 | #define PCI_CFG_ADDR_REG 0x10900 | ||
177 | #define PCI_CFG_DATA_REG 0x10904 | ||
178 | |||
179 | /* Bus parking decides where the bus control sits when idle */ | ||
180 | /* If modifying memory controllers for PCI park on the core */ | ||
181 | |||
182 | #define PPC_ACR_BUS_PARK_CORE 0x6 | ||
183 | #define PPC_ACR_BUS_PARK_PCI 0x3 | ||
184 | |||
185 | #endif /* __M8260_PCI_H */ | ||
186 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h new file mode 100644 index 000000000000..b78d40870c95 --- /dev/null +++ b/include/asm-ppc/machdep.h | |||
@@ -0,0 +1,154 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_MACHDEP_H | ||
3 | #define _PPC_MACHDEP_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <linux/init.h> | ||
7 | |||
8 | #include <asm/setup.h> | ||
9 | #include <asm/page.h> | ||
10 | |||
11 | #ifdef CONFIG_APUS | ||
12 | #include <asm-m68k/machdep.h> | ||
13 | #endif | ||
14 | |||
15 | struct pt_regs; | ||
16 | struct pci_bus; | ||
17 | struct pci_dev; | ||
18 | struct seq_file; | ||
19 | struct file; | ||
20 | |||
21 | /* We export this macro for external modules like Alsa to know if | ||
22 | * ppc_md.feature_call is implemented or not | ||
23 | */ | ||
24 | #define CONFIG_PPC_HAS_FEATURE_CALLS | ||
25 | |||
26 | struct machdep_calls { | ||
27 | void (*setup_arch)(void); | ||
28 | /* Optional, may be NULL. */ | ||
29 | int (*show_cpuinfo)(struct seq_file *m); | ||
30 | int (*show_percpuinfo)(struct seq_file *m, int i); | ||
31 | /* Optional, may be NULL. */ | ||
32 | unsigned int (*irq_canonicalize)(unsigned int irq); | ||
33 | void (*init_IRQ)(void); | ||
34 | int (*get_irq)(struct pt_regs *); | ||
35 | |||
36 | /* A general init function, called by ppc_init in init/main.c. | ||
37 | May be NULL. */ | ||
38 | void (*init)(void); | ||
39 | |||
40 | void (*restart)(char *cmd); | ||
41 | void (*power_off)(void); | ||
42 | void (*halt)(void); | ||
43 | |||
44 | void (*idle)(void); | ||
45 | void (*power_save)(void); | ||
46 | |||
47 | long (*time_init)(void); /* Optional, may be NULL */ | ||
48 | int (*set_rtc_time)(unsigned long nowtime); | ||
49 | unsigned long (*get_rtc_time)(void); | ||
50 | unsigned char (*rtc_read_val)(int addr); | ||
51 | void (*rtc_write_val)(int addr, unsigned char val); | ||
52 | void (*calibrate_decr)(void); | ||
53 | |||
54 | void (*heartbeat)(void); | ||
55 | unsigned long heartbeat_reset; | ||
56 | unsigned long heartbeat_count; | ||
57 | |||
58 | unsigned long (*find_end_of_memory)(void); | ||
59 | void (*setup_io_mappings)(void); | ||
60 | |||
61 | void (*early_serial_map)(void); | ||
62 | void (*progress)(char *, unsigned short); | ||
63 | void (*kgdb_map_scc)(void); | ||
64 | |||
65 | unsigned char (*nvram_read_val)(int addr); | ||
66 | void (*nvram_write_val)(int addr, unsigned char val); | ||
67 | void (*nvram_sync)(void); | ||
68 | |||
69 | /* | ||
70 | * optional PCI "hooks" | ||
71 | */ | ||
72 | |||
73 | /* Called after scanning the bus, before allocating resources */ | ||
74 | void (*pcibios_fixup)(void); | ||
75 | |||
76 | /* Called after PPC generic resource fixup to perform | ||
77 | machine specific fixups */ | ||
78 | void (*pcibios_fixup_resources)(struct pci_dev *); | ||
79 | |||
80 | /* Called for each PCI bus in the system when it's probed */ | ||
81 | void (*pcibios_fixup_bus)(struct pci_bus *); | ||
82 | |||
83 | /* Called when pci_enable_device() is called (initial=0) or | ||
84 | * when a device with no assigned resource is found (initial=1). | ||
85 | * Returns 0 to allow assignment/enabling of the device. */ | ||
86 | int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); | ||
87 | |||
88 | /* For interrupt routing */ | ||
89 | unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *); | ||
90 | int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char); | ||
91 | |||
92 | /* Called in indirect_* to avoid touching devices */ | ||
93 | int (*pci_exclude_device)(unsigned char, unsigned char); | ||
94 | |||
95 | /* Called at then very end of pcibios_init() */ | ||
96 | void (*pcibios_after_init)(void); | ||
97 | |||
98 | /* Get access protection for /dev/mem */ | ||
99 | pgprot_t (*phys_mem_access_prot)(struct file *file, | ||
100 | unsigned long offset, | ||
101 | unsigned long size, | ||
102 | pgprot_t vma_prot); | ||
103 | |||
104 | /* this is for modules, since _machine can be a define -- Cort */ | ||
105 | int ppc_machine; | ||
106 | |||
107 | /* Motherboard/chipset features. This is a kind of general purpose | ||
108 | * hook used to control some machine specific features (like reset | ||
109 | * lines, chip power control, etc...). | ||
110 | */ | ||
111 | long (*feature_call)(unsigned int feature, ...); | ||
112 | |||
113 | #ifdef CONFIG_SMP | ||
114 | /* functions for dealing with other cpus */ | ||
115 | struct smp_ops_t *smp_ops; | ||
116 | #endif /* CONFIG_SMP */ | ||
117 | }; | ||
118 | |||
119 | extern struct machdep_calls ppc_md; | ||
120 | extern char cmd_line[COMMAND_LINE_SIZE]; | ||
121 | |||
122 | extern void setup_pci_ptrs(void); | ||
123 | |||
124 | /* | ||
125 | * Power macintoshes have either a CUDA or a PMU controlling | ||
126 | * system reset, power, NVRAM, RTC. | ||
127 | */ | ||
128 | typedef enum sys_ctrler_kind { | ||
129 | SYS_CTRLER_UNKNOWN = 0, | ||
130 | SYS_CTRLER_CUDA = 1, | ||
131 | SYS_CTRLER_PMU = 2, | ||
132 | SYS_CTRLER_SMU = 3, | ||
133 | } sys_ctrler_t; | ||
134 | |||
135 | extern sys_ctrler_t sys_ctrler; | ||
136 | |||
137 | #ifdef CONFIG_SMP | ||
138 | struct smp_ops_t { | ||
139 | void (*message_pass)(int target, int msg, unsigned long data, int wait); | ||
140 | int (*probe)(void); | ||
141 | void (*kick_cpu)(int nr); | ||
142 | void (*setup_cpu)(int nr); | ||
143 | void (*space_timers)(int nr); | ||
144 | void (*take_timebase)(void); | ||
145 | void (*give_timebase)(void); | ||
146 | }; | ||
147 | |||
148 | /* Poor default implementations */ | ||
149 | extern void __devinit smp_generic_give_timebase(void); | ||
150 | extern void __devinit smp_generic_take_timebase(void); | ||
151 | #endif /* CONFIG_SMP */ | ||
152 | |||
153 | #endif /* _PPC_MACHDEP_H */ | ||
154 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/macio.h b/include/asm-ppc/macio.h new file mode 100644 index 000000000000..00605bb88b2a --- /dev/null +++ b/include/asm-ppc/macio.h | |||
@@ -0,0 +1,140 @@ | |||
1 | #ifndef __MACIO_ASIC_H__ | ||
2 | #define __MACIO_ASIC_H__ | ||
3 | |||
4 | #include <asm/of_device.h> | ||
5 | |||
6 | extern struct bus_type macio_bus_type; | ||
7 | |||
8 | /* MacIO device driver is defined later */ | ||
9 | struct macio_driver; | ||
10 | struct macio_chip; | ||
11 | |||
12 | #define MACIO_DEV_COUNT_RESOURCES 8 | ||
13 | #define MACIO_DEV_COUNT_IRQS 8 | ||
14 | |||
15 | /* | ||
16 | * the macio_bus structure is used to describe a "virtual" bus | ||
17 | * within a MacIO ASIC. It's typically provided by a macio_pci_asic | ||
18 | * PCI device, but could be provided differently as well (nubus | ||
19 | * machines using a fake OF tree). | ||
20 | * | ||
21 | * The pdev field can be NULL on non-PCI machines | ||
22 | */ | ||
23 | struct macio_bus | ||
24 | { | ||
25 | struct macio_chip *chip; /* macio_chip (private use) */ | ||
26 | int index; /* macio chip index in system */ | ||
27 | #ifdef CONFIG_PCI | ||
28 | struct pci_dev *pdev; /* PCI device hosting this bus */ | ||
29 | #endif | ||
30 | }; | ||
31 | |||
32 | /* | ||
33 | * the macio_dev structure is used to describe a device | ||
34 | * within an Apple MacIO ASIC. | ||
35 | */ | ||
36 | struct macio_dev | ||
37 | { | ||
38 | struct macio_bus *bus; /* macio bus this device is on */ | ||
39 | struct macio_dev *media_bay; /* Device is part of a media bay */ | ||
40 | struct of_device ofdev; | ||
41 | int n_resources; | ||
42 | struct resource resource[MACIO_DEV_COUNT_RESOURCES]; | ||
43 | int n_interrupts; | ||
44 | struct resource interrupt[MACIO_DEV_COUNT_IRQS]; | ||
45 | }; | ||
46 | #define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev) | ||
47 | #define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev) | ||
48 | |||
49 | extern struct macio_dev *macio_dev_get(struct macio_dev *dev); | ||
50 | extern void macio_dev_put(struct macio_dev *dev); | ||
51 | |||
52 | /* | ||
53 | * Accessors to resources & interrupts and other device | ||
54 | * fields | ||
55 | */ | ||
56 | |||
57 | static inline int macio_resource_count(struct macio_dev *dev) | ||
58 | { | ||
59 | return dev->n_resources; | ||
60 | } | ||
61 | |||
62 | static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no) | ||
63 | { | ||
64 | return dev->resource[resource_no].start; | ||
65 | } | ||
66 | |||
67 | static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no) | ||
68 | { | ||
69 | return dev->resource[resource_no].end; | ||
70 | } | ||
71 | |||
72 | static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no) | ||
73 | { | ||
74 | struct resource *res = &dev->resource[resource_no]; | ||
75 | if (res->start == 0 || res->end == 0 || res->end < res->start) | ||
76 | return 0; | ||
77 | return res->end - res->start + 1; | ||
78 | } | ||
79 | |||
80 | extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name); | ||
81 | extern void macio_release_resource(struct macio_dev *dev, int resource_no); | ||
82 | extern int macio_request_resources(struct macio_dev *dev, const char *name); | ||
83 | extern void macio_release_resources(struct macio_dev *dev); | ||
84 | |||
85 | static inline int macio_irq_count(struct macio_dev *dev) | ||
86 | { | ||
87 | return dev->n_interrupts; | ||
88 | } | ||
89 | |||
90 | static inline int macio_irq(struct macio_dev *dev, int irq_no) | ||
91 | { | ||
92 | return dev->interrupt[irq_no].start; | ||
93 | } | ||
94 | |||
95 | static inline void macio_set_drvdata(struct macio_dev *dev, void *data) | ||
96 | { | ||
97 | dev_set_drvdata(&dev->ofdev.dev, data); | ||
98 | } | ||
99 | |||
100 | static inline void* macio_get_drvdata(struct macio_dev *dev) | ||
101 | { | ||
102 | return dev_get_drvdata(&dev->ofdev.dev); | ||
103 | } | ||
104 | |||
105 | static inline struct device_node *macio_get_of_node(struct macio_dev *mdev) | ||
106 | { | ||
107 | return mdev->ofdev.node; | ||
108 | } | ||
109 | |||
110 | #ifdef CONFIG_PCI | ||
111 | static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev) | ||
112 | { | ||
113 | return mdev->bus->pdev; | ||
114 | } | ||
115 | #endif | ||
116 | |||
117 | /* | ||
118 | * A driver for a mac-io chip based device | ||
119 | */ | ||
120 | struct macio_driver | ||
121 | { | ||
122 | char *name; | ||
123 | struct of_match *match_table; | ||
124 | struct module *owner; | ||
125 | |||
126 | int (*probe)(struct macio_dev* dev, const struct of_match *match); | ||
127 | int (*remove)(struct macio_dev* dev); | ||
128 | |||
129 | int (*suspend)(struct macio_dev* dev, u32 state); | ||
130 | int (*resume)(struct macio_dev* dev); | ||
131 | int (*shutdown)(struct macio_dev* dev); | ||
132 | |||
133 | struct device_driver driver; | ||
134 | }; | ||
135 | #define to_macio_driver(drv) container_of(drv,struct macio_driver, driver) | ||
136 | |||
137 | extern int macio_register_driver(struct macio_driver *); | ||
138 | extern void macio_unregister_driver(struct macio_driver *); | ||
139 | |||
140 | #endif /* __MACIO_ASIC_H__ */ | ||
diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h new file mode 100644 index 000000000000..227018b2fef8 --- /dev/null +++ b/include/asm-ppc/mc146818rtc.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * Machine dependent access functions for RTC registers. | ||
3 | */ | ||
4 | #ifdef __KERNEL__ | ||
5 | #ifndef __ASM_PPC_MC146818RTC_H | ||
6 | #define __ASM_PPC_MC146818RTC_H | ||
7 | |||
8 | #include <asm/io.h> | ||
9 | |||
10 | #ifndef RTC_PORT | ||
11 | #define RTC_PORT(x) (0x70 + (x)) | ||
12 | #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ | ||
13 | #endif | ||
14 | |||
15 | /* | ||
16 | * The yet supported machines all access the RTC index register via | ||
17 | * an ISA port access but the way to access the date register differs ... | ||
18 | */ | ||
19 | #define CMOS_READ(addr) ({ \ | ||
20 | outb_p((addr),RTC_PORT(0)); \ | ||
21 | inb_p(RTC_PORT(1)); \ | ||
22 | }) | ||
23 | #define CMOS_WRITE(val, addr) ({ \ | ||
24 | outb_p((addr),RTC_PORT(0)); \ | ||
25 | outb_p((val),RTC_PORT(1)); \ | ||
26 | }) | ||
27 | |||
28 | #define RTC_IRQ 8 | ||
29 | |||
30 | #endif /* __ASM_PPC_MC146818RTC_H */ | ||
31 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/md.h b/include/asm-ppc/md.h new file mode 100644 index 000000000000..9a9b6b42b4b4 --- /dev/null +++ b/include/asm-ppc/md.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * md.h: High speed xor_block operation for RAID4/5 | ||
3 | * | ||
4 | */ | ||
5 | |||
6 | #ifdef __KERNEL__ | ||
7 | #ifndef __ASM_MD_H | ||
8 | #define __ASM_MD_H | ||
9 | |||
10 | /* #define HAVE_ARCH_XORBLOCK */ | ||
11 | |||
12 | #define MD_XORBLOCK_ALIGNMENT sizeof(long) | ||
13 | |||
14 | #endif /* __ASM_MD_H */ | ||
15 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mediabay.h b/include/asm-ppc/mediabay.h new file mode 100644 index 000000000000..9daa3252d7b6 --- /dev/null +++ b/include/asm-ppc/mediabay.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * mediabay.h: definitions for using the media bay | ||
3 | * on PowerBook 3400 and similar computers. | ||
4 | * | ||
5 | * Copyright (C) 1997 Paul Mackerras. | ||
6 | */ | ||
7 | #ifndef _PPC_MEDIABAY_H | ||
8 | #define _PPC_MEDIABAY_H | ||
9 | |||
10 | #ifdef __KERNEL__ | ||
11 | |||
12 | #define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */ | ||
13 | #define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */ | ||
14 | #define MB_SOUND 2 /* sound device ? */ | ||
15 | #define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */ | ||
16 | #define MB_PCI 5 /* media bay contains a PCI device */ | ||
17 | #define MB_POWER 6 /* media bay contains a Power device (???) */ | ||
18 | #define MB_NO 7 /* media bay contains nothing */ | ||
19 | |||
20 | int check_media_bay(struct device_node *which_bay, int what); | ||
21 | int check_media_bay_by_base(unsigned long base, int what); | ||
22 | |||
23 | /* Number of bays in the machine or 0 */ | ||
24 | extern int media_bay_count; | ||
25 | |||
26 | /* called by pmac-ide.c to register IDE controller for media bay */ | ||
27 | extern int media_bay_set_ide_infos(struct device_node* which_bay, | ||
28 | unsigned long base, int irq, int index); | ||
29 | |||
30 | #endif /* __KERNEL__ */ | ||
31 | #endif /* _PPC_MEDIABAY_H */ | ||
diff --git a/include/asm-ppc/mk48t59.h b/include/asm-ppc/mk48t59.h new file mode 100644 index 000000000000..6a0ed6fc2d56 --- /dev/null +++ b/include/asm-ppc/mk48t59.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Registers for the mk48t59 real-time-clock | ||
3 | */ | ||
4 | |||
5 | #ifndef _PPC_MK48T59_H | ||
6 | #define _PPC_MK48T59_H | ||
7 | |||
8 | /* RTC Offsets */ | ||
9 | |||
10 | #define MK48T59_RTC_SECONDS 0x1FF9 | ||
11 | #define MK48T59_RTC_MINUTES 0x1FFA | ||
12 | #define MK48T59_RTC_HOURS 0x1FFB | ||
13 | #define MK48T59_RTC_DAY_OF_WEEK 0x1FFC | ||
14 | #define MK48T59_RTC_DAY_OF_MONTH 0x1FFD | ||
15 | #define MK48T59_RTC_MONTH 0x1FFE | ||
16 | #define MK48T59_RTC_YEAR 0x1FFF | ||
17 | |||
18 | #define MK48T59_RTC_CONTROLA 0x1FF8 | ||
19 | #define MK48T59_RTC_CA_WRITE 0x80 | ||
20 | #define MK48T59_RTC_CA_READ 0x40 | ||
21 | #define MK48T59_RTC_CA_CALIB_SIGN 0x20 | ||
22 | #define MK48T59_RTC_CA_CALIB_MASK 0x1f | ||
23 | |||
24 | #define MK48T59_RTC_CONTROLB 0x1FF9 | ||
25 | #define MK48T59_RTC_CB_STOP 0x80 | ||
26 | |||
27 | #endif /* _PPC_MK48T59_H */ | ||
diff --git a/include/asm-ppc/mman.h b/include/asm-ppc/mman.h new file mode 100644 index 000000000000..5fd19fd4936c --- /dev/null +++ b/include/asm-ppc/mman.h | |||
@@ -0,0 +1,44 @@ | |||
1 | #ifndef __PPC_MMAN_H__ | ||
2 | #define __PPC_MMAN_H__ | ||
3 | |||
4 | #define PROT_READ 0x1 /* page can be read */ | ||
5 | #define PROT_WRITE 0x2 /* page can be written */ | ||
6 | #define PROT_EXEC 0x4 /* page can be executed */ | ||
7 | #define PROT_SEM 0x8 /* page may be used for atomic ops */ | ||
8 | #define PROT_NONE 0x0 /* page can not be accessed */ | ||
9 | #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ | ||
10 | #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ | ||
11 | |||
12 | #define MAP_SHARED 0x01 /* Share changes */ | ||
13 | #define MAP_PRIVATE 0x02 /* Changes are private */ | ||
14 | #define MAP_TYPE 0x0f /* Mask for type of mapping */ | ||
15 | #define MAP_FIXED 0x10 /* Interpret addr exactly */ | ||
16 | #define MAP_ANONYMOUS 0x20 /* don't use a file */ | ||
17 | #define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */ | ||
18 | #define MAP_NORESERVE 0x40 /* don't reserve swap pages */ | ||
19 | #define MAP_LOCKED 0x80 | ||
20 | |||
21 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
22 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
23 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
24 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
25 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
26 | |||
27 | #define MS_ASYNC 1 /* sync memory asynchronously */ | ||
28 | #define MS_INVALIDATE 2 /* invalidate the caches */ | ||
29 | #define MS_SYNC 4 /* synchronous memory sync */ | ||
30 | |||
31 | #define MCL_CURRENT 0x2000 /* lock all currently mapped pages */ | ||
32 | #define MCL_FUTURE 0x4000 /* lock all additions to address space */ | ||
33 | |||
34 | #define MADV_NORMAL 0x0 /* default page-in behavior */ | ||
35 | #define MADV_RANDOM 0x1 /* page-in minimum required */ | ||
36 | #define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ | ||
37 | #define MADV_WILLNEED 0x3 /* pre-fault pages */ | ||
38 | #define MADV_DONTNEED 0x4 /* discard these pages */ | ||
39 | |||
40 | /* compatibility flags */ | ||
41 | #define MAP_ANON MAP_ANONYMOUS | ||
42 | #define MAP_FILE 0 | ||
43 | |||
44 | #endif /* __PPC_MMAN_H__ */ | ||
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h new file mode 100644 index 000000000000..4a0c67f672c2 --- /dev/null +++ b/include/asm-ppc/mmu.h | |||
@@ -0,0 +1,454 @@ | |||
1 | /* | ||
2 | * PowerPC memory management structures | ||
3 | */ | ||
4 | |||
5 | #ifdef __KERNEL__ | ||
6 | #ifndef _PPC_MMU_H_ | ||
7 | #define _PPC_MMU_H_ | ||
8 | |||
9 | #include <linux/config.h> | ||
10 | |||
11 | #ifndef __ASSEMBLY__ | ||
12 | |||
13 | /* | ||
14 | * Define physical address type. Machines using split size | ||
15 | * virtual/physical addressing like 32-bit virtual / 36-bit | ||
16 | * physical need a larger than native word size type. -Matt | ||
17 | */ | ||
18 | #ifndef CONFIG_PTE_64BIT | ||
19 | typedef unsigned long phys_addr_t; | ||
20 | #else | ||
21 | typedef unsigned long long phys_addr_t; | ||
22 | extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); | ||
23 | #endif | ||
24 | |||
25 | /* Default "unsigned long" context */ | ||
26 | typedef unsigned long mm_context_t; | ||
27 | |||
28 | /* Hardware Page Table Entry */ | ||
29 | typedef struct _PTE { | ||
30 | #ifdef CONFIG_PPC64BRIDGE | ||
31 | unsigned long long vsid:52; | ||
32 | unsigned long api:5; | ||
33 | unsigned long :5; | ||
34 | unsigned long h:1; | ||
35 | unsigned long v:1; | ||
36 | unsigned long long rpn:52; | ||
37 | #else /* CONFIG_PPC64BRIDGE */ | ||
38 | unsigned long v:1; /* Entry is valid */ | ||
39 | unsigned long vsid:24; /* Virtual segment identifier */ | ||
40 | unsigned long h:1; /* Hash algorithm indicator */ | ||
41 | unsigned long api:6; /* Abbreviated page index */ | ||
42 | unsigned long rpn:20; /* Real (physical) page number */ | ||
43 | #endif /* CONFIG_PPC64BRIDGE */ | ||
44 | unsigned long :3; /* Unused */ | ||
45 | unsigned long r:1; /* Referenced */ | ||
46 | unsigned long c:1; /* Changed */ | ||
47 | unsigned long w:1; /* Write-thru cache mode */ | ||
48 | unsigned long i:1; /* Cache inhibited */ | ||
49 | unsigned long m:1; /* Memory coherence */ | ||
50 | unsigned long g:1; /* Guarded */ | ||
51 | unsigned long :1; /* Unused */ | ||
52 | unsigned long pp:2; /* Page protection */ | ||
53 | } PTE; | ||
54 | |||
55 | /* Values for PP (assumes Ks=0, Kp=1) */ | ||
56 | #define PP_RWXX 0 /* Supervisor read/write, User none */ | ||
57 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | ||
58 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | ||
59 | #define PP_RXRX 3 /* Supervisor read, User read */ | ||
60 | |||
61 | /* Segment Register */ | ||
62 | typedef struct _SEGREG { | ||
63 | unsigned long t:1; /* Normal or I/O type */ | ||
64 | unsigned long ks:1; /* Supervisor 'key' (normally 0) */ | ||
65 | unsigned long kp:1; /* User 'key' (normally 1) */ | ||
66 | unsigned long n:1; /* No-execute */ | ||
67 | unsigned long :4; /* Unused */ | ||
68 | unsigned long vsid:24; /* Virtual Segment Identifier */ | ||
69 | } SEGREG; | ||
70 | |||
71 | /* Block Address Translation (BAT) Registers */ | ||
72 | typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ | ||
73 | unsigned long bepi:15; /* Effective page index (virtual address) */ | ||
74 | unsigned long :8; /* unused */ | ||
75 | unsigned long w:1; | ||
76 | unsigned long i:1; /* Cache inhibit */ | ||
77 | unsigned long m:1; /* Memory coherence */ | ||
78 | unsigned long ks:1; /* Supervisor key (normally 0) */ | ||
79 | unsigned long kp:1; /* User key (normally 1) */ | ||
80 | unsigned long pp:2; /* Page access protections */ | ||
81 | } P601_BATU; | ||
82 | |||
83 | typedef struct _BATU { /* Upper part of BAT (all except 601) */ | ||
84 | #ifdef CONFIG_PPC64BRIDGE | ||
85 | unsigned long long bepi:47; | ||
86 | #else /* CONFIG_PPC64BRIDGE */ | ||
87 | unsigned long bepi:15; /* Effective page index (virtual address) */ | ||
88 | #endif /* CONFIG_PPC64BRIDGE */ | ||
89 | unsigned long :4; /* Unused */ | ||
90 | unsigned long bl:11; /* Block size mask */ | ||
91 | unsigned long vs:1; /* Supervisor valid */ | ||
92 | unsigned long vp:1; /* User valid */ | ||
93 | } BATU; | ||
94 | |||
95 | typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ | ||
96 | unsigned long brpn:15; /* Real page index (physical address) */ | ||
97 | unsigned long :10; /* Unused */ | ||
98 | unsigned long v:1; /* Valid bit */ | ||
99 | unsigned long bl:6; /* Block size mask */ | ||
100 | } P601_BATL; | ||
101 | |||
102 | typedef struct _BATL { /* Lower part of BAT (all except 601) */ | ||
103 | #ifdef CONFIG_PPC64BRIDGE | ||
104 | unsigned long long brpn:47; | ||
105 | #else /* CONFIG_PPC64BRIDGE */ | ||
106 | unsigned long brpn:15; /* Real page index (physical address) */ | ||
107 | #endif /* CONFIG_PPC64BRIDGE */ | ||
108 | unsigned long :10; /* Unused */ | ||
109 | unsigned long w:1; /* Write-thru cache */ | ||
110 | unsigned long i:1; /* Cache inhibit */ | ||
111 | unsigned long m:1; /* Memory coherence */ | ||
112 | unsigned long g:1; /* Guarded (MBZ in IBAT) */ | ||
113 | unsigned long :1; /* Unused */ | ||
114 | unsigned long pp:2; /* Page access protections */ | ||
115 | } BATL; | ||
116 | |||
117 | typedef struct _BAT { | ||
118 | BATU batu; /* Upper register */ | ||
119 | BATL batl; /* Lower register */ | ||
120 | } BAT; | ||
121 | |||
122 | typedef struct _P601_BAT { | ||
123 | P601_BATU batu; /* Upper register */ | ||
124 | P601_BATL batl; /* Lower register */ | ||
125 | } P601_BAT; | ||
126 | |||
127 | #endif /* __ASSEMBLY__ */ | ||
128 | |||
129 | /* Block size masks */ | ||
130 | #define BL_128K 0x000 | ||
131 | #define BL_256K 0x001 | ||
132 | #define BL_512K 0x003 | ||
133 | #define BL_1M 0x007 | ||
134 | #define BL_2M 0x00F | ||
135 | #define BL_4M 0x01F | ||
136 | #define BL_8M 0x03F | ||
137 | #define BL_16M 0x07F | ||
138 | #define BL_32M 0x0FF | ||
139 | #define BL_64M 0x1FF | ||
140 | #define BL_128M 0x3FF | ||
141 | #define BL_256M 0x7FF | ||
142 | |||
143 | /* BAT Access Protection */ | ||
144 | #define BPP_XX 0x00 /* No access */ | ||
145 | #define BPP_RX 0x01 /* Read only */ | ||
146 | #define BPP_RW 0x02 /* Read/write */ | ||
147 | |||
148 | /* Control/status registers for the MPC8xx. | ||
149 | * A write operation to these registers causes serialized access. | ||
150 | * During software tablewalk, the registers used perform mask/shift-add | ||
151 | * operations when written/read. A TLB entry is created when the Mx_RPN | ||
152 | * is written, and the contents of several registers are used to | ||
153 | * create the entry. | ||
154 | */ | ||
155 | #define SPRN_MI_CTR 784 /* Instruction TLB control register */ | ||
156 | #define MI_GPM 0x80000000 /* Set domain manager mode */ | ||
157 | #define MI_PPM 0x40000000 /* Set subpage protection */ | ||
158 | #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | ||
159 | #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | ||
160 | #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | ||
161 | #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ | ||
162 | #define MI_RESETVAL 0x00000000 /* Value of register at reset */ | ||
163 | |||
164 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | ||
165 | * Ks = 0, Kp = 1. | ||
166 | */ | ||
167 | #define SPRN_MI_AP 786 | ||
168 | #define MI_Ks 0x80000000 /* Should not be set */ | ||
169 | #define MI_Kp 0x40000000 /* Should always be set */ | ||
170 | |||
171 | /* The effective page number register. When read, contains the information | ||
172 | * about the last instruction TLB miss. When MI_RPN is written, bits in | ||
173 | * this register are used to create the TLB entry. | ||
174 | */ | ||
175 | #define SPRN_MI_EPN 787 | ||
176 | #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ | ||
177 | #define MI_EVALID 0x00000200 /* Entry is valid */ | ||
178 | #define MI_ASIDMASK 0x0000000f /* ASID match value */ | ||
179 | /* Reset value is undefined */ | ||
180 | |||
181 | /* A "level 1" or "segment" or whatever you want to call it register. | ||
182 | * For the instruction TLB, it contains bits that get loaded into the | ||
183 | * TLB entry when the MI_RPN is written. | ||
184 | */ | ||
185 | #define SPRN_MI_TWC 789 | ||
186 | #define MI_APG 0x000001e0 /* Access protection group (0) */ | ||
187 | #define MI_GUARDED 0x00000010 /* Guarded storage */ | ||
188 | #define MI_PSMASK 0x0000000c /* Mask of page size bits */ | ||
189 | #define MI_PS8MEG 0x0000000c /* 8M page size */ | ||
190 | #define MI_PS512K 0x00000004 /* 512K page size */ | ||
191 | #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ | ||
192 | #define MI_SVALID 0x00000001 /* Segment entry is valid */ | ||
193 | /* Reset value is undefined */ | ||
194 | |||
195 | /* Real page number. Defined by the pte. Writing this register | ||
196 | * causes a TLB entry to be created for the instruction TLB, using | ||
197 | * additional information from the MI_EPN, and MI_TWC registers. | ||
198 | */ | ||
199 | #define SPRN_MI_RPN 790 | ||
200 | |||
201 | /* Define an RPN value for mapping kernel memory to large virtual | ||
202 | * pages for boot initialization. This has real page number of 0, | ||
203 | * large page size, shared page, cache enabled, and valid. | ||
204 | * Also mark all subpages valid and write access. | ||
205 | */ | ||
206 | #define MI_BOOTINIT 0x000001fd | ||
207 | |||
208 | #define SPRN_MD_CTR 792 /* Data TLB control register */ | ||
209 | #define MD_GPM 0x80000000 /* Set domain manager mode */ | ||
210 | #define MD_PPM 0x40000000 /* Set subpage protection */ | ||
211 | #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ | ||
212 | #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ | ||
213 | #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ | ||
214 | #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ | ||
215 | #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ | ||
216 | #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ | ||
217 | #define MD_RESETVAL 0x04000000 /* Value of register at reset */ | ||
218 | |||
219 | #define SPRN_M_CASID 793 /* Address space ID (context) to match */ | ||
220 | #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ | ||
221 | |||
222 | |||
223 | /* These are the Ks and Kp from the PowerPC books. For proper operation, | ||
224 | * Ks = 0, Kp = 1. | ||
225 | */ | ||
226 | #define SPRN_MD_AP 794 | ||
227 | #define MD_Ks 0x80000000 /* Should not be set */ | ||
228 | #define MD_Kp 0x40000000 /* Should always be set */ | ||
229 | |||
230 | /* The effective page number register. When read, contains the information | ||
231 | * about the last instruction TLB miss. When MD_RPN is written, bits in | ||
232 | * this register are used to create the TLB entry. | ||
233 | */ | ||
234 | #define SPRN_MD_EPN 795 | ||
235 | #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ | ||
236 | #define MD_EVALID 0x00000200 /* Entry is valid */ | ||
237 | #define MD_ASIDMASK 0x0000000f /* ASID match value */ | ||
238 | /* Reset value is undefined */ | ||
239 | |||
240 | /* The pointer to the base address of the first level page table. | ||
241 | * During a software tablewalk, reading this register provides the address | ||
242 | * of the entry associated with MD_EPN. | ||
243 | */ | ||
244 | #define SPRN_M_TWB 796 | ||
245 | #define M_L1TB 0xfffff000 /* Level 1 table base address */ | ||
246 | #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ | ||
247 | /* Reset value is undefined */ | ||
248 | |||
249 | /* A "level 1" or "segment" or whatever you want to call it register. | ||
250 | * For the data TLB, it contains bits that get loaded into the TLB entry | ||
251 | * when the MD_RPN is written. It is also provides the hardware assist | ||
252 | * for finding the PTE address during software tablewalk. | ||
253 | */ | ||
254 | #define SPRN_MD_TWC 797 | ||
255 | #define MD_L2TB 0xfffff000 /* Level 2 table base address */ | ||
256 | #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ | ||
257 | #define MD_APG 0x000001e0 /* Access protection group (0) */ | ||
258 | #define MD_GUARDED 0x00000010 /* Guarded storage */ | ||
259 | #define MD_PSMASK 0x0000000c /* Mask of page size bits */ | ||
260 | #define MD_PS8MEG 0x0000000c /* 8M page size */ | ||
261 | #define MD_PS512K 0x00000004 /* 512K page size */ | ||
262 | #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ | ||
263 | #define MD_WT 0x00000002 /* Use writethrough page attribute */ | ||
264 | #define MD_SVALID 0x00000001 /* Segment entry is valid */ | ||
265 | /* Reset value is undefined */ | ||
266 | |||
267 | |||
268 | /* Real page number. Defined by the pte. Writing this register | ||
269 | * causes a TLB entry to be created for the data TLB, using | ||
270 | * additional information from the MD_EPN, and MD_TWC registers. | ||
271 | */ | ||
272 | #define SPRN_MD_RPN 798 | ||
273 | |||
274 | /* This is a temporary storage register that could be used to save | ||
275 | * a processor working register during a tablewalk. | ||
276 | */ | ||
277 | #define SPRN_M_TW 799 | ||
278 | |||
279 | /* | ||
280 | * At present, all PowerPC 400-class processors share a similar TLB | ||
281 | * architecture. The instruction and data sides share a unified, | ||
282 | * 64-entry, fully-associative TLB which is maintained totally under | ||
283 | * software control. In addition, the instruction side has a | ||
284 | * hardware-managed, 4-entry, fully- associative TLB which serves as a | ||
285 | * first level to the shared TLB. These two TLBs are known as the UTLB | ||
286 | * and ITLB, respectively. | ||
287 | */ | ||
288 | |||
289 | #define PPC4XX_TLB_SIZE 64 | ||
290 | |||
291 | /* | ||
292 | * TLB entries are defined by a "high" tag portion and a "low" data | ||
293 | * portion. On all architectures, the data portion is 32-bits. | ||
294 | * | ||
295 | * TLB entries are managed entirely under software control by reading, | ||
296 | * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx | ||
297 | * instructions. | ||
298 | */ | ||
299 | |||
300 | #define TLB_LO 1 | ||
301 | #define TLB_HI 0 | ||
302 | |||
303 | #define TLB_DATA TLB_LO | ||
304 | #define TLB_TAG TLB_HI | ||
305 | |||
306 | /* Tag portion */ | ||
307 | |||
308 | #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ | ||
309 | #define TLB_PAGESZ_MASK 0x00000380 | ||
310 | #define TLB_PAGESZ(x) (((x) & 0x7) << 7) | ||
311 | #define PAGESZ_1K 0 | ||
312 | #define PAGESZ_4K 1 | ||
313 | #define PAGESZ_16K 2 | ||
314 | #define PAGESZ_64K 3 | ||
315 | #define PAGESZ_256K 4 | ||
316 | #define PAGESZ_1M 5 | ||
317 | #define PAGESZ_4M 6 | ||
318 | #define PAGESZ_16M 7 | ||
319 | #define TLB_VALID 0x00000040 /* Entry is valid */ | ||
320 | |||
321 | /* Data portion */ | ||
322 | |||
323 | #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ | ||
324 | #define TLB_PERM_MASK 0x00000300 | ||
325 | #define TLB_EX 0x00000200 /* Instruction execution allowed */ | ||
326 | #define TLB_WR 0x00000100 /* Writes permitted */ | ||
327 | #define TLB_ZSEL_MASK 0x000000F0 | ||
328 | #define TLB_ZSEL(x) (((x) & 0xF) << 4) | ||
329 | #define TLB_ATTR_MASK 0x0000000F | ||
330 | #define TLB_W 0x00000008 /* Caching is write-through */ | ||
331 | #define TLB_I 0x00000004 /* Caching is inhibited */ | ||
332 | #define TLB_M 0x00000002 /* Memory is coherent */ | ||
333 | #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ | ||
334 | |||
335 | /* | ||
336 | * PPC440 support | ||
337 | */ | ||
338 | #define PPC44x_MMUCR_TID 0x000000ff | ||
339 | #define PPC44x_MMUCR_STS 0x00010000 | ||
340 | |||
341 | #define PPC44x_TLB_PAGEID 0 | ||
342 | #define PPC44x_TLB_XLAT 1 | ||
343 | #define PPC44x_TLB_ATTRIB 2 | ||
344 | |||
345 | /* Page identification fields */ | ||
346 | #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ | ||
347 | #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ | ||
348 | #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ | ||
349 | #define PPC44x_TLB_1K 0x00000000 /* Page sizes */ | ||
350 | #define PPC44x_TLB_4K 0x00000010 | ||
351 | #define PPC44x_TLB_16K 0x00000020 | ||
352 | #define PPC44x_TLB_64K 0x00000030 | ||
353 | #define PPC44x_TLB_256K 0x00000040 | ||
354 | #define PPC44x_TLB_1M 0x00000050 | ||
355 | #define PPC44x_TLB_16M 0x00000070 | ||
356 | #define PPC44x_TLB_256M 0x00000090 | ||
357 | |||
358 | /* Translation fields */ | ||
359 | #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ | ||
360 | #define PPC44x_TLB_ERPN_MASK 0x0000000f | ||
361 | |||
362 | /* Storage attribute and access control fields */ | ||
363 | #define PPC44x_TLB_ATTR_MASK 0x0000ff80 | ||
364 | #define PPC44x_TLB_U0 0x00008000 /* User 0 */ | ||
365 | #define PPC44x_TLB_U1 0x00004000 /* User 1 */ | ||
366 | #define PPC44x_TLB_U2 0x00002000 /* User 2 */ | ||
367 | #define PPC44x_TLB_U3 0x00001000 /* User 3 */ | ||
368 | #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ | ||
369 | #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ | ||
370 | #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ | ||
371 | #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ | ||
372 | #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ | ||
373 | |||
374 | #define PPC44x_TLB_PERM_MASK 0x0000003f | ||
375 | #define PPC44x_TLB_UX 0x00000020 /* User execution */ | ||
376 | #define PPC44x_TLB_UW 0x00000010 /* User write */ | ||
377 | #define PPC44x_TLB_UR 0x00000008 /* User read */ | ||
378 | #define PPC44x_TLB_SX 0x00000004 /* Super execution */ | ||
379 | #define PPC44x_TLB_SW 0x00000002 /* Super write */ | ||
380 | #define PPC44x_TLB_SR 0x00000001 /* Super read */ | ||
381 | |||
382 | /* Book-E defined page sizes */ | ||
383 | #define BOOKE_PAGESZ_1K 0 | ||
384 | #define BOOKE_PAGESZ_4K 1 | ||
385 | #define BOOKE_PAGESZ_16K 2 | ||
386 | #define BOOKE_PAGESZ_64K 3 | ||
387 | #define BOOKE_PAGESZ_256K 4 | ||
388 | #define BOOKE_PAGESZ_1M 5 | ||
389 | #define BOOKE_PAGESZ_4M 6 | ||
390 | #define BOOKE_PAGESZ_16M 7 | ||
391 | #define BOOKE_PAGESZ_64M 8 | ||
392 | #define BOOKE_PAGESZ_256M 9 | ||
393 | #define BOOKE_PAGESZ_1GB 10 | ||
394 | #define BOOKE_PAGESZ_4GB 11 | ||
395 | #define BOOKE_PAGESZ_16GB 12 | ||
396 | #define BOOKE_PAGESZ_64GB 13 | ||
397 | #define BOOKE_PAGESZ_256GB 14 | ||
398 | #define BOOKE_PAGESZ_1TB 15 | ||
399 | |||
400 | /* | ||
401 | * Freescale Book-E MMU support | ||
402 | */ | ||
403 | |||
404 | #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) | ||
405 | #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) | ||
406 | #define MAS0_NV 0x00000FFF | ||
407 | |||
408 | #define MAS1_VALID 0x80000000 | ||
409 | #define MAS1_IPROT 0x40000000 | ||
410 | #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) | ||
411 | #define MAS1_TS 0x00001000 | ||
412 | #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) | ||
413 | |||
414 | #define MAS2_EPN 0xFFFFF000 | ||
415 | #define MAS2_X0 0x00000040 | ||
416 | #define MAS2_X1 0x00000020 | ||
417 | #define MAS2_W 0x00000010 | ||
418 | #define MAS2_I 0x00000008 | ||
419 | #define MAS2_M 0x00000004 | ||
420 | #define MAS2_G 0x00000002 | ||
421 | #define MAS2_E 0x00000001 | ||
422 | |||
423 | #define MAS3_RPN 0xFFFFF000 | ||
424 | #define MAS3_U0 0x00000200 | ||
425 | #define MAS3_U1 0x00000100 | ||
426 | #define MAS3_U2 0x00000080 | ||
427 | #define MAS3_U3 0x00000040 | ||
428 | #define MAS3_UX 0x00000020 | ||
429 | #define MAS3_SX 0x00000010 | ||
430 | #define MAS3_UW 0x00000008 | ||
431 | #define MAS3_SW 0x00000004 | ||
432 | #define MAS3_UR 0x00000002 | ||
433 | #define MAS3_SR 0x00000001 | ||
434 | |||
435 | #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) | ||
436 | #define MAS4_TIDDSEL 0x000F0000 | ||
437 | #define MAS4_TSIZED(x) MAS1_TSIZE(x) | ||
438 | #define MAS4_X0D 0x00000040 | ||
439 | #define MAS4_X1D 0x00000020 | ||
440 | #define MAS4_WD 0x00000010 | ||
441 | #define MAS4_ID 0x00000008 | ||
442 | #define MAS4_MD 0x00000004 | ||
443 | #define MAS4_GD 0x00000002 | ||
444 | #define MAS4_ED 0x00000001 | ||
445 | |||
446 | #define MAS6_SPID0 0x3FFF0000 | ||
447 | #define MAS6_SPID1 0x00007FFE | ||
448 | #define MAS6_SAS 0x00000001 | ||
449 | #define MAS6_SPID MAS6_SPID0 | ||
450 | |||
451 | #define MAS7_RPN 0xFFFFFFFF | ||
452 | |||
453 | #endif /* _PPC_MMU_H_ */ | ||
454 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h new file mode 100644 index 000000000000..9222fa6ca172 --- /dev/null +++ b/include/asm-ppc/mmu_context.h | |||
@@ -0,0 +1,197 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef __PPC_MMU_CONTEXT_H | ||
3 | #define __PPC_MMU_CONTEXT_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <asm/atomic.h> | ||
7 | #include <asm/bitops.h> | ||
8 | #include <asm/mmu.h> | ||
9 | #include <asm/cputable.h> | ||
10 | |||
11 | /* | ||
12 | * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs | ||
13 | * (virtual segment identifiers) for each context. Although the | ||
14 | * hardware supports 24-bit VSIDs, and thus >1 million contexts, | ||
15 | * we only use 32,768 of them. That is ample, since there can be | ||
16 | * at most around 30,000 tasks in the system anyway, and it means | ||
17 | * that we can use a bitmap to indicate which contexts are in use. | ||
18 | * Using a bitmap means that we entirely avoid all of the problems | ||
19 | * that we used to have when the context number overflowed, | ||
20 | * particularly on SMP systems. | ||
21 | * -- paulus. | ||
22 | */ | ||
23 | |||
24 | /* | ||
25 | * This function defines the mapping from contexts to VSIDs (virtual | ||
26 | * segment IDs). We use a skew on both the context and the high 4 bits | ||
27 | * of the 32-bit virtual address (the "effective segment ID") in order | ||
28 | * to spread out the entries in the MMU hash table. Note, if this | ||
29 | * function is changed then arch/ppc/mm/hashtable.S will have to be | ||
30 | * changed to correspond. | ||
31 | */ | ||
32 | #define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ | ||
33 | & 0xffffff) | ||
34 | |||
35 | /* | ||
36 | The MPC8xx has only 16 contexts. We rotate through them on each | ||
37 | task switch. A better way would be to keep track of tasks that | ||
38 | own contexts, and implement an LRU usage. That way very active | ||
39 | tasks don't always have to pay the TLB reload overhead. The | ||
40 | kernel pages are mapped shared, so the kernel can run on behalf | ||
41 | of any task that makes a kernel entry. Shared does not mean they | ||
42 | are not protected, just that the ASID comparison is not performed. | ||
43 | -- Dan | ||
44 | |||
45 | The IBM4xx has 256 contexts, so we can just rotate through these | ||
46 | as a way of "switching" contexts. If the TID of the TLB is zero, | ||
47 | the PID/TID comparison is disabled, so we can use a TID of zero | ||
48 | to represent all kernel pages as shared among all contexts. | ||
49 | -- Dan | ||
50 | */ | ||
51 | |||
52 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
53 | { | ||
54 | } | ||
55 | |||
56 | #ifdef CONFIG_8xx | ||
57 | #define NO_CONTEXT 16 | ||
58 | #define LAST_CONTEXT 15 | ||
59 | #define FIRST_CONTEXT 0 | ||
60 | |||
61 | #elif defined(CONFIG_4xx) | ||
62 | #define NO_CONTEXT 256 | ||
63 | #define LAST_CONTEXT 255 | ||
64 | #define FIRST_CONTEXT 1 | ||
65 | |||
66 | #elif defined(CONFIG_E500) | ||
67 | #define NO_CONTEXT 256 | ||
68 | #define LAST_CONTEXT 255 | ||
69 | #define FIRST_CONTEXT 1 | ||
70 | |||
71 | #else | ||
72 | |||
73 | /* PPC 6xx, 7xx CPUs */ | ||
74 | #define NO_CONTEXT ((mm_context_t) -1) | ||
75 | #define LAST_CONTEXT 32767 | ||
76 | #define FIRST_CONTEXT 1 | ||
77 | #endif | ||
78 | |||
79 | /* | ||
80 | * Set the current MMU context. | ||
81 | * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by | ||
82 | * loading up the segment registers for the user part of the address space. | ||
83 | * | ||
84 | * Since the PGD is immediately available, it is much faster to simply | ||
85 | * pass this along as a second parameter, which is required for 8xx and | ||
86 | * can be used for debugging on all processors (if you happen to have | ||
87 | * an Abatron). | ||
88 | */ | ||
89 | extern void set_context(mm_context_t context, pgd_t *pgd); | ||
90 | |||
91 | /* | ||
92 | * Bitmap of contexts in use. | ||
93 | * The size of this bitmap is LAST_CONTEXT + 1 bits. | ||
94 | */ | ||
95 | extern unsigned long context_map[]; | ||
96 | |||
97 | /* | ||
98 | * This caches the next context number that we expect to be free. | ||
99 | * Its use is an optimization only, we can't rely on this context | ||
100 | * number to be free, but it usually will be. | ||
101 | */ | ||
102 | extern mm_context_t next_mmu_context; | ||
103 | |||
104 | /* | ||
105 | * If we don't have sufficient contexts to give one to every task | ||
106 | * that could be in the system, we need to be able to steal contexts. | ||
107 | * These variables support that. | ||
108 | */ | ||
109 | #if LAST_CONTEXT < 30000 | ||
110 | #define FEW_CONTEXTS 1 | ||
111 | extern atomic_t nr_free_contexts; | ||
112 | extern struct mm_struct *context_mm[LAST_CONTEXT+1]; | ||
113 | extern void steal_context(void); | ||
114 | #endif | ||
115 | |||
116 | /* | ||
117 | * Get a new mmu context for the address space described by `mm'. | ||
118 | */ | ||
119 | static inline void get_mmu_context(struct mm_struct *mm) | ||
120 | { | ||
121 | mm_context_t ctx; | ||
122 | |||
123 | if (mm->context != NO_CONTEXT) | ||
124 | return; | ||
125 | #ifdef FEW_CONTEXTS | ||
126 | while (atomic_dec_if_positive(&nr_free_contexts) < 0) | ||
127 | steal_context(); | ||
128 | #endif | ||
129 | ctx = next_mmu_context; | ||
130 | while (test_and_set_bit(ctx, context_map)) { | ||
131 | ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); | ||
132 | if (ctx > LAST_CONTEXT) | ||
133 | ctx = 0; | ||
134 | } | ||
135 | next_mmu_context = (ctx + 1) & LAST_CONTEXT; | ||
136 | mm->context = ctx; | ||
137 | #ifdef FEW_CONTEXTS | ||
138 | context_mm[ctx] = mm; | ||
139 | #endif | ||
140 | } | ||
141 | |||
142 | /* | ||
143 | * Set up the context for a new address space. | ||
144 | */ | ||
145 | #define init_new_context(tsk,mm) (((mm)->context = NO_CONTEXT), 0) | ||
146 | |||
147 | /* | ||
148 | * We're finished using the context for an address space. | ||
149 | */ | ||
150 | static inline void destroy_context(struct mm_struct *mm) | ||
151 | { | ||
152 | if (mm->context != NO_CONTEXT) { | ||
153 | clear_bit(mm->context, context_map); | ||
154 | mm->context = NO_CONTEXT; | ||
155 | #ifdef FEW_CONTEXTS | ||
156 | atomic_inc(&nr_free_contexts); | ||
157 | #endif | ||
158 | } | ||
159 | } | ||
160 | |||
161 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
162 | struct task_struct *tsk) | ||
163 | { | ||
164 | #ifdef CONFIG_ALTIVEC | ||
165 | asm volatile ( | ||
166 | BEGIN_FTR_SECTION | ||
167 | "dssall;\n" | ||
168 | #ifndef CONFIG_POWER4 | ||
169 | "sync;\n" /* G4 needs a sync here, G5 apparently not */ | ||
170 | #endif | ||
171 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | ||
172 | : : ); | ||
173 | #endif /* CONFIG_ALTIVEC */ | ||
174 | |||
175 | tsk->thread.pgdir = next->pgd; | ||
176 | |||
177 | /* No need to flush userspace segments if the mm doesnt change */ | ||
178 | if (prev == next) | ||
179 | return; | ||
180 | |||
181 | /* Setup new userspace context */ | ||
182 | get_mmu_context(next); | ||
183 | set_context(next->context, next->pgd); | ||
184 | } | ||
185 | |||
186 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
187 | |||
188 | /* | ||
189 | * After we have set current->mm to a new value, this activates | ||
190 | * the context for the new mm so we see the new mappings. | ||
191 | */ | ||
192 | #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current) | ||
193 | |||
194 | extern void mmu_context_init(void); | ||
195 | |||
196 | #endif /* __PPC_MMU_CONTEXT_H */ | ||
197 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/module.h b/include/asm-ppc/module.h new file mode 100644 index 000000000000..fb63492562b0 --- /dev/null +++ b/include/asm-ppc/module.h | |||
@@ -0,0 +1,44 @@ | |||
1 | #ifndef _ASM_PPC_MODULE_H | ||
2 | #define _ASM_PPC_MODULE_H | ||
3 | /* Module stuff for PPC. (C) 2001 Rusty Russell */ | ||
4 | |||
5 | #include <linux/list.h> | ||
6 | #include <asm/bug.h> | ||
7 | |||
8 | /* Thanks to Paul M for explaining this. | ||
9 | |||
10 | PPC can only do rel jumps += 32MB, and often the kernel and other | ||
11 | modules are furthur away than this. So, we jump to a table of | ||
12 | trampolines attached to the module (the Procedure Linkage Table) | ||
13 | whenever that happens. | ||
14 | */ | ||
15 | |||
16 | struct ppc_plt_entry | ||
17 | { | ||
18 | /* 16 byte jump instruction sequence (4 instructions) */ | ||
19 | unsigned int jump[4]; | ||
20 | }; | ||
21 | |||
22 | struct mod_arch_specific | ||
23 | { | ||
24 | /* Indices of PLT sections within module. */ | ||
25 | unsigned int core_plt_section, init_plt_section; | ||
26 | |||
27 | /* List of BUG addresses, source line numbers and filenames */ | ||
28 | struct list_head bug_list; | ||
29 | struct bug_entry *bug_table; | ||
30 | unsigned int num_bugs; | ||
31 | }; | ||
32 | |||
33 | extern struct bug_entry *module_find_bug(unsigned long bugaddr); | ||
34 | |||
35 | #define Elf_Shdr Elf32_Shdr | ||
36 | #define Elf_Sym Elf32_Sym | ||
37 | #define Elf_Ehdr Elf32_Ehdr | ||
38 | |||
39 | /* Make empty sections for module_frob_arch_sections to expand. */ | ||
40 | #ifdef MODULE | ||
41 | asm(".section .plt,\"ax\",@nobits; .align 3; .previous"); | ||
42 | asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous"); | ||
43 | #endif | ||
44 | #endif /* _ASM_PPC_MODULE_H */ | ||
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h new file mode 100644 index 000000000000..d8e7e2d6128e --- /dev/null +++ b/include/asm-ppc/mpc10x.h | |||
@@ -0,0 +1,174 @@ | |||
1 | /* | ||
2 | * arch/ppc/kernel/mpc10x.h | ||
3 | * | ||
4 | * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem | ||
5 | * ctlr/EPIC/etc. | ||
6 | * | ||
7 | * Author: Mark A. Greer | ||
8 | * mgreer@mvista.com | ||
9 | * | ||
10 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
11 | * the terms of the GNU General Public License version 2. This program | ||
12 | * is licensed "as is" without any warranty of any kind, whether express | ||
13 | * or implied. | ||
14 | */ | ||
15 | #ifndef __PPC_KERNEL_MPC10X_H | ||
16 | #define __PPC_KERNEL_MPC10X_H | ||
17 | |||
18 | #include <linux/pci_ids.h> | ||
19 | #include <asm/pci-bridge.h> | ||
20 | |||
21 | /* | ||
22 | * The values here don't completely map everything but should work in most | ||
23 | * cases. | ||
24 | * | ||
25 | * MAP A (PReP Map) | ||
26 | * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff | ||
27 | * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff | ||
28 | * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 | ||
29 | * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) | ||
30 | * | ||
31 | * MAP B (CHRP Map) | ||
32 | * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff | ||
33 | * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff | ||
34 | * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 | ||
35 | * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) | ||
36 | */ | ||
37 | |||
38 | /* | ||
39 | * Define the vendor/device IDs for the various bridges--should be added to | ||
40 | * <linux/pci_ids.h> | ||
41 | */ | ||
42 | #define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ | ||
43 | PCI_VENDOR_ID_MOTOROLA) | ||
44 | #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
45 | #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
46 | #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) | ||
47 | |||
48 | /* Define the type of map to use */ | ||
49 | #define MPC10X_MEM_MAP_A 1 | ||
50 | #define MPC10X_MEM_MAP_B 2 | ||
51 | |||
52 | /* Map A (PReP Map) Defines */ | ||
53 | #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 | ||
54 | #define MPC10X_MAPA_CNFG_DATA 0x80000cfc | ||
55 | |||
56 | #define MPC10X_MAPA_ISA_IO_BASE 0x80000000 | ||
57 | #define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 | ||
58 | #define MPC10X_MAPA_DRAM_OFFSET 0x80000000 | ||
59 | |||
60 | #define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 | ||
61 | #define MPC10X_MAPA_PCI_IO_START 0x00000000 | ||
62 | #define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) | ||
63 | #define MPC10X_MAPA_PCI_MEM_START 0x00000000 | ||
64 | #define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) | ||
65 | |||
66 | #define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ | ||
67 | MPC10X_MAPA_PCI_MEM_START) | ||
68 | |||
69 | /* Map B (CHRP Map) Defines */ | ||
70 | #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 | ||
71 | #define MPC10X_MAPB_CNFG_DATA 0xfee00000 | ||
72 | |||
73 | #define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 | ||
74 | #define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 | ||
75 | #define MPC10X_MAPB_DRAM_OFFSET 0x00000000 | ||
76 | |||
77 | #define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 | ||
78 | #define MPC10X_MAPB_PCI_IO_START 0x00000000 | ||
79 | #define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) | ||
80 | #define MPC10X_MAPB_PCI_MEM_START 0x80000000 | ||
81 | #define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) | ||
82 | |||
83 | #define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ | ||
84 | MPC10X_MAPB_PCI_MEM_START) | ||
85 | |||
86 | /* Set hose members to values appropriate for the mem map used */ | ||
87 | #define MPC10X_SETUP_HOSE(hose, map) { \ | ||
88 | (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ | ||
89 | (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ | ||
90 | (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ | ||
91 | (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ | ||
92 | (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ | ||
93 | (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ | ||
94 | } | ||
95 | |||
96 | |||
97 | /* Miscellaneous Configuration register offsets */ | ||
98 | #define MPC10X_CFG_PIR_REG 0x09 | ||
99 | #define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 | ||
100 | #define MPC10X_CFG_PIR_AGENT 0x01 | ||
101 | |||
102 | #define MPC10X_CFG_EUMBBAR 0x78 | ||
103 | |||
104 | #define MPC10X_CFG_PICR1_REG 0xa8 | ||
105 | #define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 | ||
106 | #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 | ||
107 | #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 | ||
108 | #define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 | ||
109 | #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 | ||
110 | |||
111 | #define MPC10X_CFG_PICR2_REG 0xac | ||
112 | #define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 | ||
113 | |||
114 | #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 | ||
115 | #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ | ||
116 | #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ | ||
117 | #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ | ||
118 | #define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ | ||
119 | #define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ | ||
120 | |||
121 | /* Define offsets for the memory controller registers in the config space */ | ||
122 | #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ | ||
123 | #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ | ||
124 | #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ | ||
125 | #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ | ||
126 | |||
127 | #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ | ||
128 | #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ | ||
129 | #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ | ||
130 | #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ | ||
131 | |||
132 | #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 | ||
133 | |||
134 | /* Define some offset in the EUMB */ | ||
135 | #define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ | ||
136 | |||
137 | #define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ | ||
138 | #define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ | ||
139 | #define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ | ||
140 | #define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ | ||
141 | #define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ | ||
142 | #define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ | ||
143 | #define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ | ||
144 | #define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ | ||
145 | #define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ | ||
146 | #define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ | ||
147 | #define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ | ||
148 | #define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ | ||
149 | #define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ | ||
150 | #define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ | ||
151 | #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ | ||
152 | #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ | ||
153 | |||
154 | /* | ||
155 | * Define some recommended places to put the EUMB regs. | ||
156 | * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. | ||
157 | */ | ||
158 | extern unsigned long ioremap_base; | ||
159 | #define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) | ||
160 | #define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE | ||
161 | |||
162 | |||
163 | int mpc10x_bridge_init(struct pci_controller *hose, | ||
164 | uint current_map, | ||
165 | uint new_map, | ||
166 | uint phys_eumb_base); | ||
167 | unsigned long mpc10x_get_mem_size(uint mem_map); | ||
168 | int mpc10x_enable_store_gathering(struct pci_controller *hose); | ||
169 | int mpc10x_disable_store_gathering(struct pci_controller *hose); | ||
170 | |||
171 | /* For MPC107 boards that use the built-in openpic */ | ||
172 | void mpc10x_set_openpic(void); | ||
173 | |||
174 | #endif /* __PPC_KERNEL_MPC10X_H */ | ||
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h new file mode 100644 index 000000000000..e5f80c22fbfc --- /dev/null +++ b/include/asm-ppc/mpc52xx.h | |||
@@ -0,0 +1,445 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mpc52xx.h | ||
3 | * | ||
4 | * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips | ||
5 | * May need to be cleaned as the port goes on ... | ||
6 | * | ||
7 | * | ||
8 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | ||
9 | * | ||
10 | * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> | ||
11 | * for the 2.4 kernel. | ||
12 | * | ||
13 | * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> | ||
14 | * Copyright (C) 2003 MontaVista, Software, Inc. | ||
15 | * | ||
16 | * This file is licensed under the terms of the GNU General Public License | ||
17 | * version 2. This program is licensed "as is" without any warranty of any | ||
18 | * kind, whether express or implied. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_MPC52xx_H__ | ||
22 | #define __ASM_MPC52xx_H__ | ||
23 | |||
24 | #ifndef __ASSEMBLY__ | ||
25 | #include <asm/ppcboot.h> | ||
26 | #include <asm/types.h> | ||
27 | |||
28 | struct pt_regs; | ||
29 | #endif /* __ASSEMBLY__ */ | ||
30 | |||
31 | |||
32 | /* ======================================================================== */ | ||
33 | /* PPC Sys devices definition */ | ||
34 | /* ======================================================================== */ | ||
35 | |||
36 | enum ppc_sys_devices { | ||
37 | MPC52xx_MSCAN1, | ||
38 | MPC52xx_MSCAN2, | ||
39 | MPC52xx_SPI, | ||
40 | MPC52xx_USB, | ||
41 | MPC52xx_BDLC, | ||
42 | MPC52xx_PSC1, | ||
43 | MPC52xx_PSC2, | ||
44 | MPC52xx_PSC3, | ||
45 | MPC52xx_PSC4, | ||
46 | MPC52xx_PSC5, | ||
47 | MPC52xx_PSC6, | ||
48 | MPC52xx_FEC, | ||
49 | MPC52xx_ATA, | ||
50 | MPC52xx_I2C1, | ||
51 | MPC52xx_I2C2, | ||
52 | }; | ||
53 | |||
54 | |||
55 | /* ======================================================================== */ | ||
56 | /* Main registers/struct addresses */ | ||
57 | /* ======================================================================== */ | ||
58 | |||
59 | /* MBAR position */ | ||
60 | #define MPC52xx_MBAR 0xf0000000 /* Phys address */ | ||
61 | #define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */ | ||
62 | #define MPC52xx_MBAR_SIZE 0x00010000 | ||
63 | |||
64 | #define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x))) | ||
65 | #define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x))) | ||
66 | |||
67 | /* Registers zone offset/size */ | ||
68 | #define MPC52xx_MMAP_CTL_OFFSET 0x0000 | ||
69 | #define MPC52xx_MMAP_CTL_SIZE 0x068 | ||
70 | #define MPC52xx_SDRAM_OFFSET 0x0100 | ||
71 | #define MPC52xx_SDRAM_SIZE 0x010 | ||
72 | #define MPC52xx_CDM_OFFSET 0x0200 | ||
73 | #define MPC52xx_CDM_SIZE 0x038 | ||
74 | #define MPC52xx_INTR_OFFSET 0x0500 | ||
75 | #define MPC52xx_INTR_SIZE 0x04c | ||
76 | #define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4)) | ||
77 | #define MPC52xx_GPT_SIZE 0x010 | ||
78 | #define MPC52xx_RTC_OFFSET 0x0800 | ||
79 | #define MPC52xx_RTC_SIZE 0x024 | ||
80 | #define MPC52xx_GPIO_OFFSET 0x0b00 | ||
81 | #define MPC52xx_GPIO_SIZE 0x040 | ||
82 | #define MPC52xx_GPIO_WKUP_OFFSET 0x0c00 | ||
83 | #define MPC52xx_GPIO_WKUP_SIZE 0x028 | ||
84 | #define MPC52xx_PCI_OFFSET 0x0d00 | ||
85 | #define MPC52xx_PCI_SIZE 0x100 | ||
86 | #define MPC52xx_SDMA_OFFSET 0x1200 | ||
87 | #define MPC52xx_SDMA_SIZE 0x100 | ||
88 | #define MPC52xx_XLB_OFFSET 0x1f00 | ||
89 | #define MPC52xx_XLB_SIZE 0x100 | ||
90 | #define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00) | ||
91 | #define MPC52xx_PSC_SIZE 0x0a0 | ||
92 | |||
93 | /* SRAM used for SDMA */ | ||
94 | #define MPC52xx_SRAM_OFFSET 0x8000 | ||
95 | #define MPC52xx_SRAM_SIZE 0x4000 | ||
96 | |||
97 | |||
98 | /* ======================================================================== */ | ||
99 | /* IRQ mapping */ | ||
100 | /* ======================================================================== */ | ||
101 | /* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change | ||
102 | * this | ||
103 | */ | ||
104 | |||
105 | #define MPC52xx_CRIT_IRQ_NUM 4 | ||
106 | #define MPC52xx_MAIN_IRQ_NUM 17 | ||
107 | #define MPC52xx_SDMA_IRQ_NUM 17 | ||
108 | #define MPC52xx_PERP_IRQ_NUM 23 | ||
109 | |||
110 | #define MPC52xx_CRIT_IRQ_BASE 0 | ||
111 | #define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM) | ||
112 | #define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM) | ||
113 | #define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM) | ||
114 | |||
115 | #define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0) | ||
116 | #define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1) | ||
117 | #define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2) | ||
118 | #define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3) | ||
119 | |||
120 | #define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1) | ||
121 | #define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2) | ||
122 | #define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3) | ||
123 | |||
124 | #define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0) | ||
125 | #define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1) | ||
126 | #define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2) | ||
127 | #define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3) | ||
128 | #define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | ||
129 | #define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4) | ||
130 | #define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5) | ||
131 | #define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6) | ||
132 | #define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7) | ||
133 | #define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8) | ||
134 | #define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9) | ||
135 | #define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10) | ||
136 | #define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11) | ||
137 | #define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12) | ||
138 | #define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13) | ||
139 | #define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14) | ||
140 | #define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15) | ||
141 | #define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16) | ||
142 | #define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17) | ||
143 | #define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18) | ||
144 | #define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19) | ||
145 | #define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20) | ||
146 | #define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21) | ||
147 | #define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22) | ||
148 | |||
149 | |||
150 | |||
151 | /* ======================================================================== */ | ||
152 | /* Structures mapping of some unit register set */ | ||
153 | /* ======================================================================== */ | ||
154 | |||
155 | #ifndef __ASSEMBLY__ | ||
156 | |||
157 | /* Memory Mapping Control */ | ||
158 | struct mpc52xx_mmap_ctl { | ||
159 | u32 mbar; /* MMAP_CTRL + 0x00 */ | ||
160 | |||
161 | u32 cs0_start; /* MMAP_CTRL + 0x04 */ | ||
162 | u32 cs0_stop; /* MMAP_CTRL + 0x08 */ | ||
163 | u32 cs1_start; /* MMAP_CTRL + 0x0c */ | ||
164 | u32 cs1_stop; /* MMAP_CTRL + 0x10 */ | ||
165 | u32 cs2_start; /* MMAP_CTRL + 0x14 */ | ||
166 | u32 cs2_stop; /* MMAP_CTRL + 0x18 */ | ||
167 | u32 cs3_start; /* MMAP_CTRL + 0x1c */ | ||
168 | u32 cs3_stop; /* MMAP_CTRL + 0x20 */ | ||
169 | u32 cs4_start; /* MMAP_CTRL + 0x24 */ | ||
170 | u32 cs4_stop; /* MMAP_CTRL + 0x28 */ | ||
171 | u32 cs5_start; /* MMAP_CTRL + 0x2c */ | ||
172 | u32 cs5_stop; /* MMAP_CTRL + 0x30 */ | ||
173 | |||
174 | u32 sdram0; /* MMAP_CTRL + 0x34 */ | ||
175 | u32 sdram1; /* MMAP_CTRL + 0X38 */ | ||
176 | |||
177 | u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */ | ||
178 | |||
179 | u32 boot_start; /* MMAP_CTRL + 0x4c */ | ||
180 | u32 boot_stop; /* MMAP_CTRL + 0x50 */ | ||
181 | |||
182 | u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */ | ||
183 | |||
184 | u32 cs6_start; /* MMAP_CTRL + 0x58 */ | ||
185 | u32 cs6_stop; /* MMAP_CTRL + 0x5c */ | ||
186 | u32 cs7_start; /* MMAP_CTRL + 0x60 */ | ||
187 | u32 cs7_stop; /* MMAP_CTRL + 0x64 */ | ||
188 | }; | ||
189 | |||
190 | /* SDRAM control */ | ||
191 | struct mpc52xx_sdram { | ||
192 | u32 mode; /* SDRAM + 0x00 */ | ||
193 | u32 ctrl; /* SDRAM + 0x04 */ | ||
194 | u32 config1; /* SDRAM + 0x08 */ | ||
195 | u32 config2; /* SDRAM + 0x0c */ | ||
196 | }; | ||
197 | |||
198 | /* Interrupt controller */ | ||
199 | struct mpc52xx_intr { | ||
200 | u32 per_mask; /* INTR + 0x00 */ | ||
201 | u32 per_pri1; /* INTR + 0x04 */ | ||
202 | u32 per_pri2; /* INTR + 0x08 */ | ||
203 | u32 per_pri3; /* INTR + 0x0c */ | ||
204 | u32 ctrl; /* INTR + 0x10 */ | ||
205 | u32 main_mask; /* INTR + 0x14 */ | ||
206 | u32 main_pri1; /* INTR + 0x18 */ | ||
207 | u32 main_pri2; /* INTR + 0x1c */ | ||
208 | u32 reserved1; /* INTR + 0x20 */ | ||
209 | u32 enc_status; /* INTR + 0x24 */ | ||
210 | u32 crit_status; /* INTR + 0x28 */ | ||
211 | u32 main_status; /* INTR + 0x2c */ | ||
212 | u32 per_status; /* INTR + 0x30 */ | ||
213 | u32 reserved2; /* INTR + 0x34 */ | ||
214 | u32 per_error; /* INTR + 0x38 */ | ||
215 | }; | ||
216 | |||
217 | /* SDMA */ | ||
218 | struct mpc52xx_sdma { | ||
219 | u32 taskBar; /* SDMA + 0x00 */ | ||
220 | u32 currentPointer; /* SDMA + 0x04 */ | ||
221 | u32 endPointer; /* SDMA + 0x08 */ | ||
222 | u32 variablePointer;/* SDMA + 0x0c */ | ||
223 | |||
224 | u8 IntVect1; /* SDMA + 0x10 */ | ||
225 | u8 IntVect2; /* SDMA + 0x11 */ | ||
226 | u16 PtdCntrl; /* SDMA + 0x12 */ | ||
227 | |||
228 | u32 IntPend; /* SDMA + 0x14 */ | ||
229 | u32 IntMask; /* SDMA + 0x18 */ | ||
230 | |||
231 | u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ | ||
232 | |||
233 | u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */ | ||
234 | |||
235 | u32 cReqSelect; /* SDMA + 0x5c */ | ||
236 | u32 task_size0; /* SDMA + 0x60 */ | ||
237 | u32 task_size1; /* SDMA + 0x64 */ | ||
238 | u32 MDEDebug; /* SDMA + 0x68 */ | ||
239 | u32 ADSDebug; /* SDMA + 0x6c */ | ||
240 | u32 Value1; /* SDMA + 0x70 */ | ||
241 | u32 Value2; /* SDMA + 0x74 */ | ||
242 | u32 Control; /* SDMA + 0x78 */ | ||
243 | u32 Status; /* SDMA + 0x7c */ | ||
244 | u32 PTDDebug; /* SDMA + 0x80 */ | ||
245 | }; | ||
246 | |||
247 | /* GPT */ | ||
248 | struct mpc52xx_gpt { | ||
249 | u32 mode; /* GPTx + 0x00 */ | ||
250 | u32 count; /* GPTx + 0x04 */ | ||
251 | u32 pwm; /* GPTx + 0x08 */ | ||
252 | u32 status; /* GPTx + 0X0c */ | ||
253 | }; | ||
254 | |||
255 | /* RTC */ | ||
256 | struct mpc52xx_rtc { | ||
257 | u32 time_set; /* RTC + 0x00 */ | ||
258 | u32 date_set; /* RTC + 0x04 */ | ||
259 | u32 stopwatch; /* RTC + 0x08 */ | ||
260 | u32 int_enable; /* RTC + 0x0c */ | ||
261 | u32 time; /* RTC + 0x10 */ | ||
262 | u32 date; /* RTC + 0x14 */ | ||
263 | u32 stopwatch_intr; /* RTC + 0x18 */ | ||
264 | u32 bus_error; /* RTC + 0x1c */ | ||
265 | u32 dividers; /* RTC + 0x20 */ | ||
266 | }; | ||
267 | |||
268 | /* GPIO */ | ||
269 | struct mpc52xx_gpio { | ||
270 | u32 port_config; /* GPIO + 0x00 */ | ||
271 | u32 simple_gpioe; /* GPIO + 0x04 */ | ||
272 | u32 simple_ode; /* GPIO + 0x08 */ | ||
273 | u32 simple_ddr; /* GPIO + 0x0c */ | ||
274 | u32 simple_dvo; /* GPIO + 0x10 */ | ||
275 | u32 simple_ival; /* GPIO + 0x14 */ | ||
276 | u8 outo_gpioe; /* GPIO + 0x18 */ | ||
277 | u8 reserved1[3]; /* GPIO + 0x19 */ | ||
278 | u8 outo_dvo; /* GPIO + 0x1c */ | ||
279 | u8 reserved2[3]; /* GPIO + 0x1d */ | ||
280 | u8 sint_gpioe; /* GPIO + 0x20 */ | ||
281 | u8 reserved3[3]; /* GPIO + 0x21 */ | ||
282 | u8 sint_ode; /* GPIO + 0x24 */ | ||
283 | u8 reserved4[3]; /* GPIO + 0x25 */ | ||
284 | u8 sint_ddr; /* GPIO + 0x28 */ | ||
285 | u8 reserved5[3]; /* GPIO + 0x29 */ | ||
286 | u8 sint_dvo; /* GPIO + 0x2c */ | ||
287 | u8 reserved6[3]; /* GPIO + 0x2d */ | ||
288 | u8 sint_inten; /* GPIO + 0x30 */ | ||
289 | u8 reserved7[3]; /* GPIO + 0x31 */ | ||
290 | u16 sint_itype; /* GPIO + 0x34 */ | ||
291 | u16 reserved8; /* GPIO + 0x36 */ | ||
292 | u8 gpio_control; /* GPIO + 0x38 */ | ||
293 | u8 reserved9[3]; /* GPIO + 0x39 */ | ||
294 | u8 sint_istat; /* GPIO + 0x3c */ | ||
295 | u8 sint_ival; /* GPIO + 0x3d */ | ||
296 | u8 bus_errs; /* GPIO + 0x3e */ | ||
297 | u8 reserved10; /* GPIO + 0x3f */ | ||
298 | }; | ||
299 | |||
300 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4 | ||
301 | #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5 | ||
302 | #define MPC52xx_GPIO_PCI_DIS (1<<15) | ||
303 | |||
304 | /* GPIO with WakeUp*/ | ||
305 | struct mpc52xx_gpio_wkup { | ||
306 | u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */ | ||
307 | u8 reserved1[3]; /* GPIO_WKUP + 0x03 */ | ||
308 | u8 wkup_ode; /* GPIO_WKUP + 0x04 */ | ||
309 | u8 reserved2[3]; /* GPIO_WKUP + 0x05 */ | ||
310 | u8 wkup_ddr; /* GPIO_WKUP + 0x08 */ | ||
311 | u8 reserved3[3]; /* GPIO_WKUP + 0x09 */ | ||
312 | u8 wkup_dvo; /* GPIO_WKUP + 0x0C */ | ||
313 | u8 reserved4[3]; /* GPIO_WKUP + 0x0D */ | ||
314 | u8 wkup_inten; /* GPIO_WKUP + 0x10 */ | ||
315 | u8 reserved5[3]; /* GPIO_WKUP + 0x11 */ | ||
316 | u8 wkup_iinten; /* GPIO_WKUP + 0x14 */ | ||
317 | u8 reserved6[3]; /* GPIO_WKUP + 0x15 */ | ||
318 | u16 wkup_itype; /* GPIO_WKUP + 0x18 */ | ||
319 | u8 reserved7[2]; /* GPIO_WKUP + 0x1A */ | ||
320 | u8 wkup_maste; /* GPIO_WKUP + 0x1C */ | ||
321 | u8 reserved8[3]; /* GPIO_WKUP + 0x1D */ | ||
322 | u8 wkup_ival; /* GPIO_WKUP + 0x20 */ | ||
323 | u8 reserved9[3]; /* GPIO_WKUP + 0x21 */ | ||
324 | u8 wkup_istat; /* GPIO_WKUP + 0x24 */ | ||
325 | u8 reserved10[3]; /* GPIO_WKUP + 0x25 */ | ||
326 | }; | ||
327 | |||
328 | /* XLB Bus control */ | ||
329 | struct mpc52xx_xlb { | ||
330 | u8 reserved[0x40]; | ||
331 | u32 config; /* XLB + 0x40 */ | ||
332 | u32 version; /* XLB + 0x44 */ | ||
333 | u32 status; /* XLB + 0x48 */ | ||
334 | u32 int_enable; /* XLB + 0x4c */ | ||
335 | u32 addr_capture; /* XLB + 0x50 */ | ||
336 | u32 bus_sig_capture; /* XLB + 0x54 */ | ||
337 | u32 addr_timeout; /* XLB + 0x58 */ | ||
338 | u32 data_timeout; /* XLB + 0x5c */ | ||
339 | u32 bus_act_timeout; /* XLB + 0x60 */ | ||
340 | u32 master_pri_enable; /* XLB + 0x64 */ | ||
341 | u32 master_priority; /* XLB + 0x68 */ | ||
342 | u32 base_address; /* XLB + 0x6c */ | ||
343 | u32 snoop_window; /* XLB + 0x70 */ | ||
344 | }; | ||
345 | |||
346 | #define MPC52xx_XLB_CFG_SNOOP (1 << 15) | ||
347 | |||
348 | /* Clock Distribution control */ | ||
349 | struct mpc52xx_cdm { | ||
350 | u32 jtag_id; /* CDM + 0x00 reg0 read only */ | ||
351 | u32 rstcfg; /* CDM + 0x04 reg1 read only */ | ||
352 | u32 breadcrumb; /* CDM + 0x08 reg2 */ | ||
353 | |||
354 | u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */ | ||
355 | u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */ | ||
356 | u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */ | ||
357 | u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */ | ||
358 | |||
359 | u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */ | ||
360 | u8 fd_enable; /* CDM + 0x11 reg4 byte1 */ | ||
361 | u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */ | ||
362 | |||
363 | u32 clk_enables; /* CDM + 0x14 reg5 */ | ||
364 | |||
365 | u8 osc_disable; /* CDM + 0x18 reg6 byte0 */ | ||
366 | u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */ | ||
367 | |||
368 | u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */ | ||
369 | u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */ | ||
370 | u8 reserved1; /* CDM + 0x1e reg7 byte2 */ | ||
371 | u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */ | ||
372 | |||
373 | u8 soft_reset; /* CDM + 0x20 u8 byte0 */ | ||
374 | u8 no_ckstp; /* CDM + 0x21 u8 byte0 */ | ||
375 | u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */ | ||
376 | |||
377 | u8 pll_lock; /* CDM + 0x24 reg9 byte0 */ | ||
378 | u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */ | ||
379 | u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */ | ||
380 | u8 reserved3; /* CDM + 0x27 reg9 byte3 */ | ||
381 | |||
382 | u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */ | ||
383 | u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */ | ||
384 | |||
385 | u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */ | ||
386 | u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */ | ||
387 | |||
388 | u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */ | ||
389 | u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */ | ||
390 | |||
391 | u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */ | ||
392 | u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */ | ||
393 | }; | ||
394 | |||
395 | #endif /* __ASSEMBLY__ */ | ||
396 | |||
397 | |||
398 | /* ========================================================================= */ | ||
399 | /* Prototypes for MPC52xx syslib */ | ||
400 | /* ========================================================================= */ | ||
401 | |||
402 | #ifndef __ASSEMBLY__ | ||
403 | |||
404 | extern void mpc52xx_init_irq(void); | ||
405 | extern int mpc52xx_get_irq(struct pt_regs *regs); | ||
406 | |||
407 | extern unsigned long mpc52xx_find_end_of_memory(void); | ||
408 | extern void mpc52xx_set_bat(void); | ||
409 | extern void mpc52xx_map_io(void); | ||
410 | extern void mpc52xx_restart(char *cmd); | ||
411 | extern void mpc52xx_halt(void); | ||
412 | extern void mpc52xx_power_off(void); | ||
413 | extern void mpc52xx_progress(char *s, unsigned short hex); | ||
414 | extern void mpc52xx_calibrate_decr(void); | ||
415 | |||
416 | extern void mpc52xx_find_bridges(void); | ||
417 | |||
418 | |||
419 | /* Matching of PSC function */ | ||
420 | struct mpc52xx_psc_func { | ||
421 | int id; | ||
422 | char *func; | ||
423 | }; | ||
424 | |||
425 | extern int mpc52xx_match_psc_function(int psc_idx, const char *func); | ||
426 | extern struct mpc52xx_psc_func mpc52xx_psc_functions[]; | ||
427 | /* This array is to be defined in platform file */ | ||
428 | |||
429 | #endif /* __ASSEMBLY__ */ | ||
430 | |||
431 | |||
432 | /* ========================================================================= */ | ||
433 | /* Platform configuration */ | ||
434 | /* ========================================================================= */ | ||
435 | |||
436 | /* The U-Boot platform information struct */ | ||
437 | extern bd_t __res; | ||
438 | |||
439 | /* Platform options */ | ||
440 | #if defined(CONFIG_LITE5200) | ||
441 | #include <platforms/lite5200.h> | ||
442 | #endif | ||
443 | |||
444 | |||
445 | #endif /* __ASM_MPC52xx_H__ */ | ||
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h new file mode 100644 index 000000000000..9d850b2b20b8 --- /dev/null +++ b/include/asm-ppc/mpc52xx_psc.h | |||
@@ -0,0 +1,191 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mpc52xx_psc.h | ||
3 | * | ||
4 | * Definitions of consts/structs to drive the Freescale MPC52xx OnChip | ||
5 | * PSCs. Theses are shared between multiple drivers since a PSC can be | ||
6 | * UART, AC97, IR, I2S, ... So this header is in asm-ppc. | ||
7 | * | ||
8 | * | ||
9 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | ||
10 | * | ||
11 | * Based/Extracted from some header of the 2.4 originally written by | ||
12 | * Dale Farnsworth <dfarnsworth@mvista.com> | ||
13 | * | ||
14 | * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> | ||
15 | * Copyright (C) 2003 MontaVista, Software, Inc. | ||
16 | * | ||
17 | * This file is licensed under the terms of the GNU General Public License | ||
18 | * version 2. This program is licensed "as is" without any warranty of any | ||
19 | * kind, whether express or implied. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ASM_MPC52xx_PSC_H__ | ||
23 | #define __ASM_MPC52xx_PSC_H__ | ||
24 | |||
25 | #include <asm/types.h> | ||
26 | |||
27 | /* Max number of PSCs */ | ||
28 | #define MPC52xx_PSC_MAXNUM 6 | ||
29 | |||
30 | /* Programmable Serial Controller (PSC) status register bits */ | ||
31 | #define MPC52xx_PSC_SR_CDE 0x0080 | ||
32 | #define MPC52xx_PSC_SR_RXRDY 0x0100 | ||
33 | #define MPC52xx_PSC_SR_RXFULL 0x0200 | ||
34 | #define MPC52xx_PSC_SR_TXRDY 0x0400 | ||
35 | #define MPC52xx_PSC_SR_TXEMP 0x0800 | ||
36 | #define MPC52xx_PSC_SR_OE 0x1000 | ||
37 | #define MPC52xx_PSC_SR_PE 0x2000 | ||
38 | #define MPC52xx_PSC_SR_FE 0x4000 | ||
39 | #define MPC52xx_PSC_SR_RB 0x8000 | ||
40 | |||
41 | /* PSC Command values */ | ||
42 | #define MPC52xx_PSC_RX_ENABLE 0x0001 | ||
43 | #define MPC52xx_PSC_RX_DISABLE 0x0002 | ||
44 | #define MPC52xx_PSC_TX_ENABLE 0x0004 | ||
45 | #define MPC52xx_PSC_TX_DISABLE 0x0008 | ||
46 | #define MPC52xx_PSC_SEL_MODE_REG_1 0x0010 | ||
47 | #define MPC52xx_PSC_RST_RX 0x0020 | ||
48 | #define MPC52xx_PSC_RST_TX 0x0030 | ||
49 | #define MPC52xx_PSC_RST_ERR_STAT 0x0040 | ||
50 | #define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050 | ||
51 | #define MPC52xx_PSC_START_BRK 0x0060 | ||
52 | #define MPC52xx_PSC_STOP_BRK 0x0070 | ||
53 | |||
54 | /* PSC TxRx FIFO status bits */ | ||
55 | #define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040 | ||
56 | #define MPC52xx_PSC_RXTX_FIFO_UF 0x0020 | ||
57 | #define MPC52xx_PSC_RXTX_FIFO_OF 0x0010 | ||
58 | #define MPC52xx_PSC_RXTX_FIFO_FR 0x0008 | ||
59 | #define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004 | ||
60 | #define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002 | ||
61 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 | ||
62 | |||
63 | /* PSC interrupt mask bits */ | ||
64 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 | ||
65 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 | ||
66 | #define MPC52xx_PSC_IMR_DB 0x0400 | ||
67 | #define MPC52xx_PSC_IMR_IPC 0x8000 | ||
68 | |||
69 | /* PSC input port change bit */ | ||
70 | #define MPC52xx_PSC_CTS 0x01 | ||
71 | #define MPC52xx_PSC_DCD 0x02 | ||
72 | #define MPC52xx_PSC_D_CTS 0x10 | ||
73 | #define MPC52xx_PSC_D_DCD 0x20 | ||
74 | |||
75 | /* PSC mode fields */ | ||
76 | #define MPC52xx_PSC_MODE_5_BITS 0x00 | ||
77 | #define MPC52xx_PSC_MODE_6_BITS 0x01 | ||
78 | #define MPC52xx_PSC_MODE_7_BITS 0x02 | ||
79 | #define MPC52xx_PSC_MODE_8_BITS 0x03 | ||
80 | #define MPC52xx_PSC_MODE_BITS_MASK 0x03 | ||
81 | #define MPC52xx_PSC_MODE_PAREVEN 0x00 | ||
82 | #define MPC52xx_PSC_MODE_PARODD 0x04 | ||
83 | #define MPC52xx_PSC_MODE_PARFORCE 0x08 | ||
84 | #define MPC52xx_PSC_MODE_PARNONE 0x10 | ||
85 | #define MPC52xx_PSC_MODE_ERR 0x20 | ||
86 | #define MPC52xx_PSC_MODE_FFULL 0x40 | ||
87 | #define MPC52xx_PSC_MODE_RXRTS 0x80 | ||
88 | |||
89 | #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 | ||
90 | #define MPC52xx_PSC_MODE_ONE_STOP 0x07 | ||
91 | #define MPC52xx_PSC_MODE_TWO_STOP 0x0f | ||
92 | |||
93 | #define MPC52xx_PSC_RFNUM_MASK 0x01ff | ||
94 | |||
95 | |||
96 | /* Structure of the hardware registers */ | ||
97 | struct mpc52xx_psc { | ||
98 | u8 mode; /* PSC + 0x00 */ | ||
99 | u8 reserved0[3]; | ||
100 | union { /* PSC + 0x04 */ | ||
101 | u16 status; | ||
102 | u16 clock_select; | ||
103 | } sr_csr; | ||
104 | #define mpc52xx_psc_status sr_csr.status | ||
105 | #define mpc52xx_psc_clock_select sr_csr.clock_select | ||
106 | u16 reserved1; | ||
107 | u8 command; /* PSC + 0x08 */ | ||
108 | u8 reserved2[3]; | ||
109 | union { /* PSC + 0x0c */ | ||
110 | u8 buffer_8; | ||
111 | u16 buffer_16; | ||
112 | u32 buffer_32; | ||
113 | } buffer; | ||
114 | #define mpc52xx_psc_buffer_8 buffer.buffer_8 | ||
115 | #define mpc52xx_psc_buffer_16 buffer.buffer_16 | ||
116 | #define mpc52xx_psc_buffer_32 buffer.buffer_32 | ||
117 | union { /* PSC + 0x10 */ | ||
118 | u8 ipcr; | ||
119 | u8 acr; | ||
120 | } ipcr_acr; | ||
121 | #define mpc52xx_psc_ipcr ipcr_acr.ipcr | ||
122 | #define mpc52xx_psc_acr ipcr_acr.acr | ||
123 | u8 reserved3[3]; | ||
124 | union { /* PSC + 0x14 */ | ||
125 | u16 isr; | ||
126 | u16 imr; | ||
127 | } isr_imr; | ||
128 | #define mpc52xx_psc_isr isr_imr.isr | ||
129 | #define mpc52xx_psc_imr isr_imr.imr | ||
130 | u16 reserved4; | ||
131 | u8 ctur; /* PSC + 0x18 */ | ||
132 | u8 reserved5[3]; | ||
133 | u8 ctlr; /* PSC + 0x1c */ | ||
134 | u8 reserved6[3]; | ||
135 | u16 ccr; /* PSC + 0x20 */ | ||
136 | u8 reserved7[14]; | ||
137 | u8 ivr; /* PSC + 0x30 */ | ||
138 | u8 reserved8[3]; | ||
139 | u8 ip; /* PSC + 0x34 */ | ||
140 | u8 reserved9[3]; | ||
141 | u8 op1; /* PSC + 0x38 */ | ||
142 | u8 reserved10[3]; | ||
143 | u8 op0; /* PSC + 0x3c */ | ||
144 | u8 reserved11[3]; | ||
145 | u32 sicr; /* PSC + 0x40 */ | ||
146 | u8 ircr1; /* PSC + 0x44 */ | ||
147 | u8 reserved13[3]; | ||
148 | u8 ircr2; /* PSC + 0x44 */ | ||
149 | u8 reserved14[3]; | ||
150 | u8 irsdr; /* PSC + 0x4c */ | ||
151 | u8 reserved15[3]; | ||
152 | u8 irmdr; /* PSC + 0x50 */ | ||
153 | u8 reserved16[3]; | ||
154 | u8 irfdr; /* PSC + 0x54 */ | ||
155 | u8 reserved17[3]; | ||
156 | u16 rfnum; /* PSC + 0x58 */ | ||
157 | u16 reserved18; | ||
158 | u16 tfnum; /* PSC + 0x5c */ | ||
159 | u16 reserved19; | ||
160 | u32 rfdata; /* PSC + 0x60 */ | ||
161 | u16 rfstat; /* PSC + 0x64 */ | ||
162 | u16 reserved20; | ||
163 | u8 rfcntl; /* PSC + 0x68 */ | ||
164 | u8 reserved21[5]; | ||
165 | u16 rfalarm; /* PSC + 0x6e */ | ||
166 | u16 reserved22; | ||
167 | u16 rfrptr; /* PSC + 0x72 */ | ||
168 | u16 reserved23; | ||
169 | u16 rfwptr; /* PSC + 0x76 */ | ||
170 | u16 reserved24; | ||
171 | u16 rflrfptr; /* PSC + 0x7a */ | ||
172 | u16 reserved25; | ||
173 | u16 rflwfptr; /* PSC + 0x7e */ | ||
174 | u32 tfdata; /* PSC + 0x80 */ | ||
175 | u16 tfstat; /* PSC + 0x84 */ | ||
176 | u16 reserved26; | ||
177 | u8 tfcntl; /* PSC + 0x88 */ | ||
178 | u8 reserved27[5]; | ||
179 | u16 tfalarm; /* PSC + 0x8e */ | ||
180 | u16 reserved28; | ||
181 | u16 tfrptr; /* PSC + 0x92 */ | ||
182 | u16 reserved29; | ||
183 | u16 tfwptr; /* PSC + 0x96 */ | ||
184 | u16 reserved30; | ||
185 | u16 tflrfptr; /* PSC + 0x9a */ | ||
186 | u16 reserved31; | ||
187 | u16 tflwfptr; /* PSC + 0x9e */ | ||
188 | }; | ||
189 | |||
190 | |||
191 | #endif /* __ASM_MPC52xx_PSC_H__ */ | ||
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h new file mode 100644 index 000000000000..d820894e5991 --- /dev/null +++ b/include/asm-ppc/mpc8260.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * Since there are many different boards and no standard configuration, | ||
3 | * we have a unique include file for each. Rather than change every | ||
4 | * file that has to include MPC8260 configuration, they all include | ||
5 | * this one and the configuration switching is done here. | ||
6 | */ | ||
7 | #ifdef __KERNEL__ | ||
8 | #ifndef __ASM_PPC_MPC8260_H__ | ||
9 | #define __ASM_PPC_MPC8260_H__ | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | |||
13 | #ifdef CONFIG_8260 | ||
14 | |||
15 | #ifdef CONFIG_EST8260 | ||
16 | #include <platforms/est8260.h> | ||
17 | #endif | ||
18 | |||
19 | #ifdef CONFIG_SBC82xx | ||
20 | #include <platforms/sbc82xx.h> | ||
21 | #endif | ||
22 | |||
23 | #ifdef CONFIG_SBS8260 | ||
24 | #include <platforms/sbs8260.h> | ||
25 | #endif | ||
26 | |||
27 | #ifdef CONFIG_RPX8260 | ||
28 | #include <platforms/rpx8260.h> | ||
29 | #endif | ||
30 | |||
31 | #ifdef CONFIG_WILLOW | ||
32 | #include <platforms/willow.h> | ||
33 | #endif | ||
34 | |||
35 | #ifdef CONFIG_TQM8260 | ||
36 | #include <platforms/tqm8260.h> | ||
37 | #endif | ||
38 | |||
39 | #if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS) | ||
40 | #include <platforms/pq2ads.h> | ||
41 | #endif | ||
42 | |||
43 | #ifdef CONFIG_PCI_8260 | ||
44 | #include <syslib/m8260_pci.h> | ||
45 | #endif | ||
46 | |||
47 | /* Make sure the memory translation stuff is there if PCI not used. | ||
48 | */ | ||
49 | #ifndef _IO_BASE | ||
50 | #define _IO_BASE 0 | ||
51 | #endif | ||
52 | |||
53 | #ifndef _ISA_MEM_BASE | ||
54 | #define _ISA_MEM_BASE 0 | ||
55 | #endif | ||
56 | |||
57 | #ifndef PCI_DRAM_OFFSET | ||
58 | #define PCI_DRAM_OFFSET 0 | ||
59 | #endif | ||
60 | |||
61 | /* Map 256MB I/O region | ||
62 | */ | ||
63 | #ifndef IO_PHYS_ADDR | ||
64 | #define IO_PHYS_ADDR 0xe0000000 | ||
65 | #endif | ||
66 | #ifndef IO_VIRT_ADDR | ||
67 | #define IO_VIRT_ADDR IO_PHYS_ADDR | ||
68 | #endif | ||
69 | |||
70 | #ifndef __ASSEMBLY__ | ||
71 | /* The "residual" data board information structure the boot loader | ||
72 | * hands to us. | ||
73 | */ | ||
74 | extern unsigned char __res[]; | ||
75 | #endif | ||
76 | |||
77 | #endif /* CONFIG_8260 */ | ||
78 | #endif /* !__ASM_PPC_MPC8260_H__ */ | ||
79 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc8260_pci9.h b/include/asm-ppc/mpc8260_pci9.h new file mode 100644 index 000000000000..26b3f6e787bc --- /dev/null +++ b/include/asm-ppc/mpc8260_pci9.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* include/asm-ppc/mpc8260_pci9.h | ||
2 | * | ||
3 | * Undefine the PCI read* and in* macros so we can define them as functions | ||
4 | * that implement the workaround for the MPC8260 device erratum PCI 9. | ||
5 | * | ||
6 | * This header file should only be included at the end of include/asm-ppc/io.h | ||
7 | * and never included directly anywhere else. | ||
8 | * | ||
9 | * Author: andy_lowe@mvista.com | ||
10 | * | ||
11 | * 2003 (c) MontaVista Software, Inc. This file is licensed under | ||
12 | * the terms of the GNU General Public License version 2. This program | ||
13 | * is licensed "as is" without any warranty of any kind, whether express | ||
14 | * or implied. | ||
15 | */ | ||
16 | #ifndef _PPC_IO_H | ||
17 | #error "Do not include mpc8260_pci9.h directly." | ||
18 | #endif | ||
19 | |||
20 | #ifdef __KERNEL__ | ||
21 | #ifndef __CONFIG_8260_PCI9_DEFS | ||
22 | #define __CONFIG_8260_PCI9_DEFS | ||
23 | |||
24 | #undef readb | ||
25 | #undef readw | ||
26 | #undef readl | ||
27 | #undef insb | ||
28 | #undef insw | ||
29 | #undef insl | ||
30 | #undef inb | ||
31 | #undef inw | ||
32 | #undef inl | ||
33 | #undef insw_ns | ||
34 | #undef insl_ns | ||
35 | #undef memcpy_fromio | ||
36 | |||
37 | extern int readb(volatile unsigned char *addr); | ||
38 | extern int readw(volatile unsigned short *addr); | ||
39 | extern unsigned readl(volatile unsigned *addr); | ||
40 | extern void insb(unsigned port, void *buf, int ns); | ||
41 | extern void insw(unsigned port, void *buf, int ns); | ||
42 | extern void insl(unsigned port, void *buf, int nl); | ||
43 | extern int inb(unsigned port); | ||
44 | extern int inw(unsigned port); | ||
45 | extern unsigned inl(unsigned port); | ||
46 | extern void insw_ns(unsigned port, void *buf, int ns); | ||
47 | extern void insl_ns(unsigned port, void *buf, int nl); | ||
48 | extern void *memcpy_fromio(void *dest, unsigned long src, size_t count); | ||
49 | |||
50 | #endif /* !__CONFIG_8260_PCI9_DEFS */ | ||
51 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h new file mode 100644 index 000000000000..bb1b0576c947 --- /dev/null +++ b/include/asm-ppc/mpc83xx.h | |||
@@ -0,0 +1,114 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mpc83xx.h | ||
3 | * | ||
4 | * MPC83xx definitions | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | ||
7 | * | ||
8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_MPC83xx_H__ | ||
18 | #define __ASM_MPC83xx_H__ | ||
19 | |||
20 | #include <linux/config.h> | ||
21 | #include <asm/mmu.h> | ||
22 | |||
23 | #ifdef CONFIG_83xx | ||
24 | |||
25 | #ifdef CONFIG_MPC834x_SYS | ||
26 | #include <platforms/83xx/mpc834x_sys.h> | ||
27 | #endif | ||
28 | |||
29 | #define _IO_BASE isa_io_base | ||
30 | #define _ISA_MEM_BASE isa_mem_base | ||
31 | #ifdef CONFIG_PCI | ||
32 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
33 | #else | ||
34 | #define PCI_DRAM_OFFSET 0 | ||
35 | #endif | ||
36 | |||
37 | /* | ||
38 | * The "residual" board information structure the boot loader passes | ||
39 | * into the kernel. | ||
40 | */ | ||
41 | extern unsigned char __res[]; | ||
42 | |||
43 | /* Internal IRQs on MPC83xx OpenPIC */ | ||
44 | /* Not all of these exist on all MPC83xx implementations */ | ||
45 | |||
46 | #ifndef MPC83xx_IPIC_IRQ_OFFSET | ||
47 | #define MPC83xx_IPIC_IRQ_OFFSET 0 | ||
48 | #endif | ||
49 | |||
50 | #define NR_IPIC_INTS 128 | ||
51 | |||
52 | #define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET) | ||
53 | #define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET) | ||
54 | #define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET) | ||
55 | #define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET) | ||
56 | #define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET) | ||
57 | #define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET) | ||
58 | #define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET) | ||
59 | #define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET) | ||
60 | #define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET) | ||
61 | #define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET) | ||
62 | #define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET) | ||
63 | #define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET) | ||
64 | #define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET) | ||
65 | #define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET) | ||
66 | #define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET) | ||
67 | #define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET) | ||
68 | #define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET) | ||
69 | #define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET) | ||
70 | #define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET) | ||
71 | #define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET) | ||
72 | #define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET) | ||
73 | #define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET) | ||
74 | #define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET) | ||
75 | #define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET) | ||
76 | #define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET) | ||
77 | #define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET) | ||
78 | #define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET) | ||
79 | #define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET) | ||
80 | #define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET) | ||
81 | #define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET) | ||
82 | #define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET) | ||
83 | #define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET) | ||
84 | #define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET) | ||
85 | #define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET) | ||
86 | #define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET) | ||
87 | #define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET) | ||
88 | #define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET) | ||
89 | #define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET) | ||
90 | #define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET) | ||
91 | #define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET) | ||
92 | #define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET) | ||
93 | #define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET) | ||
94 | #define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET) | ||
95 | |||
96 | #define MPC83xx_CCSRBAR_SIZE (1024*1024) | ||
97 | |||
98 | /* Let modules/drivers get at immrbar (physical) */ | ||
99 | extern phys_addr_t immrbar; | ||
100 | |||
101 | enum ppc_sys_devices { | ||
102 | MPC83xx_TSEC1, | ||
103 | MPC83xx_TSEC2, | ||
104 | MPC83xx_IIC1, | ||
105 | MPC83xx_IIC2, | ||
106 | MPC83xx_DUART, | ||
107 | MPC83xx_SEC2, | ||
108 | MPC83xx_USB2_DR, | ||
109 | MPC83xx_USB2_MPH, | ||
110 | }; | ||
111 | |||
112 | #endif /* CONFIG_83xx */ | ||
113 | #endif /* __ASM_MPC83xx_H__ */ | ||
114 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h new file mode 100644 index 000000000000..22713e331585 --- /dev/null +++ b/include/asm-ppc/mpc85xx.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mpc85xx.h | ||
3 | * | ||
4 | * MPC85xx definitions | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | ||
7 | * | ||
8 | * Copyright 2004 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_MPC85xx_H__ | ||
18 | #define __ASM_MPC85xx_H__ | ||
19 | |||
20 | #include <linux/config.h> | ||
21 | #include <asm/mmu.h> | ||
22 | |||
23 | #ifdef CONFIG_85xx | ||
24 | |||
25 | #ifdef CONFIG_MPC8540_ADS | ||
26 | #include <platforms/85xx/mpc8540_ads.h> | ||
27 | #endif | ||
28 | #ifdef CONFIG_MPC8555_CDS | ||
29 | #include <platforms/85xx/mpc8555_cds.h> | ||
30 | #endif | ||
31 | #ifdef CONFIG_MPC8560_ADS | ||
32 | #include <platforms/85xx/mpc8560_ads.h> | ||
33 | #endif | ||
34 | #ifdef CONFIG_SBC8560 | ||
35 | #include <platforms/85xx/sbc8560.h> | ||
36 | #endif | ||
37 | #ifdef CONFIG_STX_GP3 | ||
38 | #include <platforms/85xx/stx_gp3.h> | ||
39 | #endif | ||
40 | |||
41 | #define _IO_BASE isa_io_base | ||
42 | #define _ISA_MEM_BASE isa_mem_base | ||
43 | #ifdef CONFIG_PCI | ||
44 | #define PCI_DRAM_OFFSET pci_dram_offset | ||
45 | #else | ||
46 | #define PCI_DRAM_OFFSET 0 | ||
47 | #endif | ||
48 | |||
49 | /* | ||
50 | * The "residual" board information structure the boot loader passes | ||
51 | * into the kernel. | ||
52 | */ | ||
53 | extern unsigned char __res[]; | ||
54 | |||
55 | /* Offset from CCSRBAR */ | ||
56 | #define MPC85xx_CPM_OFFSET (0x80000) | ||
57 | #define MPC85xx_CPM_SIZE (0x40000) | ||
58 | #define MPC85xx_DMA_OFFSET (0x21000) | ||
59 | #define MPC85xx_DMA_SIZE (0x01000) | ||
60 | #define MPC85xx_DMA0_OFFSET (0x21100) | ||
61 | #define MPC85xx_DMA0_SIZE (0x00080) | ||
62 | #define MPC85xx_DMA1_OFFSET (0x21180) | ||
63 | #define MPC85xx_DMA1_SIZE (0x00080) | ||
64 | #define MPC85xx_DMA2_OFFSET (0x21200) | ||
65 | #define MPC85xx_DMA2_SIZE (0x00080) | ||
66 | #define MPC85xx_DMA3_OFFSET (0x21280) | ||
67 | #define MPC85xx_DMA3_SIZE (0x00080) | ||
68 | #define MPC85xx_ENET1_OFFSET (0x24000) | ||
69 | #define MPC85xx_ENET1_SIZE (0x01000) | ||
70 | #define MPC85xx_ENET2_OFFSET (0x25000) | ||
71 | #define MPC85xx_ENET2_SIZE (0x01000) | ||
72 | #define MPC85xx_ENET3_OFFSET (0x26000) | ||
73 | #define MPC85xx_ENET3_SIZE (0x01000) | ||
74 | #define MPC85xx_GUTS_OFFSET (0xe0000) | ||
75 | #define MPC85xx_GUTS_SIZE (0x01000) | ||
76 | #define MPC85xx_IIC1_OFFSET (0x03000) | ||
77 | #define MPC85xx_IIC1_SIZE (0x01000) | ||
78 | #define MPC85xx_OPENPIC_OFFSET (0x40000) | ||
79 | #define MPC85xx_OPENPIC_SIZE (0x40000) | ||
80 | #define MPC85xx_PCI1_OFFSET (0x08000) | ||
81 | #define MPC85xx_PCI1_SIZE (0x01000) | ||
82 | #define MPC85xx_PCI2_OFFSET (0x09000) | ||
83 | #define MPC85xx_PCI2_SIZE (0x01000) | ||
84 | #define MPC85xx_PERFMON_OFFSET (0xe1000) | ||
85 | #define MPC85xx_PERFMON_SIZE (0x01000) | ||
86 | #define MPC85xx_SEC2_OFFSET (0x30000) | ||
87 | #define MPC85xx_SEC2_SIZE (0x10000) | ||
88 | #define MPC85xx_UART0_OFFSET (0x04500) | ||
89 | #define MPC85xx_UART0_SIZE (0x00100) | ||
90 | #define MPC85xx_UART1_OFFSET (0x04600) | ||
91 | #define MPC85xx_UART1_SIZE (0x00100) | ||
92 | |||
93 | #define MPC85xx_CCSRBAR_SIZE (1024*1024) | ||
94 | |||
95 | /* Let modules/drivers get at CCSRBAR */ | ||
96 | extern phys_addr_t get_ccsrbar(void); | ||
97 | |||
98 | #ifdef MODULE | ||
99 | #define CCSRBAR get_ccsrbar() | ||
100 | #else | ||
101 | #define CCSRBAR BOARD_CCSRBAR | ||
102 | #endif | ||
103 | |||
104 | enum ppc_sys_devices { | ||
105 | MPC85xx_TSEC1, | ||
106 | MPC85xx_TSEC2, | ||
107 | MPC85xx_FEC, | ||
108 | MPC85xx_IIC1, | ||
109 | MPC85xx_DMA0, | ||
110 | MPC85xx_DMA1, | ||
111 | MPC85xx_DMA2, | ||
112 | MPC85xx_DMA3, | ||
113 | MPC85xx_DUART, | ||
114 | MPC85xx_PERFMON, | ||
115 | MPC85xx_SEC2, | ||
116 | MPC85xx_CPM_SPI, | ||
117 | MPC85xx_CPM_I2C, | ||
118 | MPC85xx_CPM_USB, | ||
119 | MPC85xx_CPM_SCC1, | ||
120 | MPC85xx_CPM_SCC2, | ||
121 | MPC85xx_CPM_SCC3, | ||
122 | MPC85xx_CPM_SCC4, | ||
123 | MPC85xx_CPM_FCC1, | ||
124 | MPC85xx_CPM_FCC2, | ||
125 | MPC85xx_CPM_FCC3, | ||
126 | MPC85xx_CPM_MCC1, | ||
127 | MPC85xx_CPM_MCC2, | ||
128 | MPC85xx_CPM_SMC1, | ||
129 | MPC85xx_CPM_SMC2, | ||
130 | }; | ||
131 | |||
132 | #endif /* CONFIG_85xx */ | ||
133 | #endif /* __ASM_MPC85xx_H__ */ | ||
134 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h new file mode 100644 index 000000000000..714d69c819d3 --- /dev/null +++ b/include/asm-ppc/mpc8xx.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /* This is the single file included by all MPC8xx build options. | ||
2 | * Since there are many different boards and no standard configuration, | ||
3 | * we have a unique include file for each. Rather than change every | ||
4 | * file that has to include MPC8xx configuration, they all include | ||
5 | * this one and the configuration switching is done here. | ||
6 | */ | ||
7 | #ifdef __KERNEL__ | ||
8 | #ifndef __CONFIG_8xx_DEFS | ||
9 | #define __CONFIG_8xx_DEFS | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | |||
13 | #ifdef CONFIG_8xx | ||
14 | |||
15 | #ifdef CONFIG_MBX | ||
16 | #include <platforms/mbx.h> | ||
17 | #endif | ||
18 | |||
19 | #ifdef CONFIG_FADS | ||
20 | #include <platforms/fads.h> | ||
21 | #endif | ||
22 | |||
23 | #ifdef CONFIG_RPXLITE | ||
24 | #include <platforms/rpxlite.h> | ||
25 | #endif | ||
26 | |||
27 | #ifdef CONFIG_BSEIP | ||
28 | #include <platforms/bseip.h> | ||
29 | #endif | ||
30 | |||
31 | #ifdef CONFIG_RPXCLASSIC | ||
32 | #include <platforms/rpxclassic.h> | ||
33 | #endif | ||
34 | |||
35 | #if defined(CONFIG_TQM8xxL) | ||
36 | #include <platforms/tqm8xx.h> | ||
37 | #endif | ||
38 | |||
39 | #if defined(CONFIG_SPD823TS) | ||
40 | #include <platforms/spd8xx.h> | ||
41 | #endif | ||
42 | |||
43 | #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) | ||
44 | #include <platforms/ivms8.h> | ||
45 | #endif | ||
46 | |||
47 | #if defined(CONFIG_HERMES_PRO) | ||
48 | #include <platforms/hermes.h> | ||
49 | #endif | ||
50 | |||
51 | #if defined(CONFIG_IP860) | ||
52 | #include <platforms/ip860.h> | ||
53 | #endif | ||
54 | |||
55 | #if defined(CONFIG_LWMON) | ||
56 | #include <platforms/lwmon.h> | ||
57 | #endif | ||
58 | |||
59 | #if defined(CONFIG_PCU_E) | ||
60 | #include <platforms/pcu_e.h> | ||
61 | #endif | ||
62 | |||
63 | #if defined(CONFIG_CCM) | ||
64 | #include <platforms/ccm.h> | ||
65 | #endif | ||
66 | |||
67 | #if defined(CONFIG_LANTEC) | ||
68 | #include <platforms/lantec.h> | ||
69 | #endif | ||
70 | |||
71 | /* Currently, all 8xx boards that support a processor to PCI/ISA bridge | ||
72 | * use the same memory map. | ||
73 | */ | ||
74 | #if 0 | ||
75 | #if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR) | ||
76 | #define _IO_BASE PCI_ISA_IO_ADDR | ||
77 | #define _ISA_MEM_BASE PCI_ISA_MEM_ADDR | ||
78 | #define PCI_DRAM_OFFSET 0x80000000 | ||
79 | #else | ||
80 | #define _IO_BASE 0 | ||
81 | #define _ISA_MEM_BASE 0 | ||
82 | #define PCI_DRAM_OFFSET 0 | ||
83 | #endif | ||
84 | #else | ||
85 | #if !defined(_IO_BASE) /* defined in board specific header */ | ||
86 | #define _IO_BASE 0 | ||
87 | #endif | ||
88 | #define _ISA_MEM_BASE 0 | ||
89 | #define PCI_DRAM_OFFSET 0 | ||
90 | #endif | ||
91 | |||
92 | #ifndef __ASSEMBLY__ | ||
93 | /* The "residual" data board information structure the boot loader | ||
94 | * hands to us. | ||
95 | */ | ||
96 | extern unsigned char __res[]; | ||
97 | |||
98 | struct pt_regs; | ||
99 | |||
100 | #endif /* !__ASSEMBLY__ */ | ||
101 | #endif /* CONFIG_8xx */ | ||
102 | #endif /* __CONFIG_8xx_DEFS */ | ||
103 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/msgbuf.h b/include/asm-ppc/msgbuf.h new file mode 100644 index 000000000000..1053452a9376 --- /dev/null +++ b/include/asm-ppc/msgbuf.h | |||
@@ -0,0 +1,25 @@ | |||
1 | #ifndef _PPC_MSGBUF_H | ||
2 | #define _PPC_MSGBUF_H | ||
3 | |||
4 | /* | ||
5 | * The msqid64_ds structure for the PPC architecture. | ||
6 | */ | ||
7 | |||
8 | struct msqid64_ds { | ||
9 | struct ipc64_perm msg_perm; | ||
10 | unsigned int __unused1; | ||
11 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
12 | unsigned int __unused2; | ||
13 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
14 | unsigned int __unused3; | ||
15 | __kernel_time_t msg_ctime; /* last change time */ | ||
16 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
17 | unsigned long msg_qnum; /* number of messages in queue */ | ||
18 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
19 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
20 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
21 | unsigned long __unused4; | ||
22 | unsigned long __unused5; | ||
23 | }; | ||
24 | |||
25 | #endif /* _PPC_MSGBUF_H */ | ||
diff --git a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h new file mode 100644 index 000000000000..cc25b921ad4f --- /dev/null +++ b/include/asm-ppc/mv64x60.h | |||
@@ -0,0 +1,345 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mv64x60.h | ||
3 | * | ||
4 | * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines. | ||
5 | * | ||
6 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
7 | * | ||
8 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | #ifndef __ASMPPC_MV64x60_H | ||
14 | #define __ASMPPC_MV64x60_H | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/pci.h> | ||
19 | #include <linux/slab.h> | ||
20 | #include <linux/config.h> | ||
21 | |||
22 | #include <asm/byteorder.h> | ||
23 | #include <asm/io.h> | ||
24 | #include <asm/irq.h> | ||
25 | #include <asm/uaccess.h> | ||
26 | #include <asm/machdep.h> | ||
27 | #include <asm/pci-bridge.h> | ||
28 | #include <asm/mv64x60_defs.h> | ||
29 | |||
30 | extern u8 mv64x60_pci_exclude_bridge; | ||
31 | |||
32 | extern spinlock_t mv64x60_lock; | ||
33 | |||
34 | /* 32-bit Window table entry defines */ | ||
35 | #define MV64x60_CPU2MEM_0_WIN 0 | ||
36 | #define MV64x60_CPU2MEM_1_WIN 1 | ||
37 | #define MV64x60_CPU2MEM_2_WIN 2 | ||
38 | #define MV64x60_CPU2MEM_3_WIN 3 | ||
39 | #define MV64x60_CPU2DEV_0_WIN 4 | ||
40 | #define MV64x60_CPU2DEV_1_WIN 5 | ||
41 | #define MV64x60_CPU2DEV_2_WIN 6 | ||
42 | #define MV64x60_CPU2DEV_3_WIN 7 | ||
43 | #define MV64x60_CPU2BOOT_WIN 8 | ||
44 | #define MV64x60_CPU2PCI0_IO_WIN 9 | ||
45 | #define MV64x60_CPU2PCI0_MEM_0_WIN 10 | ||
46 | #define MV64x60_CPU2PCI0_MEM_1_WIN 11 | ||
47 | #define MV64x60_CPU2PCI0_MEM_2_WIN 12 | ||
48 | #define MV64x60_CPU2PCI0_MEM_3_WIN 13 | ||
49 | #define MV64x60_CPU2PCI1_IO_WIN 14 | ||
50 | #define MV64x60_CPU2PCI1_MEM_0_WIN 15 | ||
51 | #define MV64x60_CPU2PCI1_MEM_1_WIN 16 | ||
52 | #define MV64x60_CPU2PCI1_MEM_2_WIN 17 | ||
53 | #define MV64x60_CPU2PCI1_MEM_3_WIN 18 | ||
54 | #define MV64x60_CPU2SRAM_WIN 19 | ||
55 | #define MV64x60_CPU2PCI0_IO_REMAP_WIN 20 | ||
56 | #define MV64x60_CPU2PCI1_IO_REMAP_WIN 21 | ||
57 | #define MV64x60_CPU_PROT_0_WIN 22 | ||
58 | #define MV64x60_CPU_PROT_1_WIN 23 | ||
59 | #define MV64x60_CPU_PROT_2_WIN 24 | ||
60 | #define MV64x60_CPU_PROT_3_WIN 25 | ||
61 | #define MV64x60_CPU_SNOOP_0_WIN 26 | ||
62 | #define MV64x60_CPU_SNOOP_1_WIN 27 | ||
63 | #define MV64x60_CPU_SNOOP_2_WIN 28 | ||
64 | #define MV64x60_CPU_SNOOP_3_WIN 29 | ||
65 | #define MV64x60_PCI02MEM_REMAP_0_WIN 30 | ||
66 | #define MV64x60_PCI02MEM_REMAP_1_WIN 31 | ||
67 | #define MV64x60_PCI02MEM_REMAP_2_WIN 32 | ||
68 | #define MV64x60_PCI02MEM_REMAP_3_WIN 33 | ||
69 | #define MV64x60_PCI12MEM_REMAP_0_WIN 34 | ||
70 | #define MV64x60_PCI12MEM_REMAP_1_WIN 35 | ||
71 | #define MV64x60_PCI12MEM_REMAP_2_WIN 36 | ||
72 | #define MV64x60_PCI12MEM_REMAP_3_WIN 37 | ||
73 | #define MV64x60_ENET2MEM_0_WIN 38 | ||
74 | #define MV64x60_ENET2MEM_1_WIN 39 | ||
75 | #define MV64x60_ENET2MEM_2_WIN 40 | ||
76 | #define MV64x60_ENET2MEM_3_WIN 41 | ||
77 | #define MV64x60_ENET2MEM_4_WIN 42 | ||
78 | #define MV64x60_ENET2MEM_5_WIN 43 | ||
79 | #define MV64x60_MPSC2MEM_0_WIN 44 | ||
80 | #define MV64x60_MPSC2MEM_1_WIN 45 | ||
81 | #define MV64x60_MPSC2MEM_2_WIN 46 | ||
82 | #define MV64x60_MPSC2MEM_3_WIN 47 | ||
83 | #define MV64x60_IDMA2MEM_0_WIN 48 | ||
84 | #define MV64x60_IDMA2MEM_1_WIN 49 | ||
85 | #define MV64x60_IDMA2MEM_2_WIN 50 | ||
86 | #define MV64x60_IDMA2MEM_3_WIN 51 | ||
87 | #define MV64x60_IDMA2MEM_4_WIN 52 | ||
88 | #define MV64x60_IDMA2MEM_5_WIN 53 | ||
89 | #define MV64x60_IDMA2MEM_6_WIN 54 | ||
90 | #define MV64x60_IDMA2MEM_7_WIN 55 | ||
91 | |||
92 | #define MV64x60_32BIT_WIN_COUNT 56 | ||
93 | |||
94 | /* 64-bit Window table entry defines */ | ||
95 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0 | ||
96 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1 | ||
97 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2 | ||
98 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3 | ||
99 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4 | ||
100 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5 | ||
101 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6 | ||
102 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7 | ||
103 | #define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8 | ||
104 | #define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9 | ||
105 | #define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10 | ||
106 | #define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11 | ||
107 | #define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12 | ||
108 | #define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13 | ||
109 | #define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14 | ||
110 | #define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15 | ||
111 | #define MV64x60_PCI02MEM_SNOOP_0_WIN 16 | ||
112 | #define MV64x60_PCI02MEM_SNOOP_1_WIN 17 | ||
113 | #define MV64x60_PCI02MEM_SNOOP_2_WIN 18 | ||
114 | #define MV64x60_PCI02MEM_SNOOP_3_WIN 19 | ||
115 | #define MV64x60_PCI12MEM_SNOOP_0_WIN 20 | ||
116 | #define MV64x60_PCI12MEM_SNOOP_1_WIN 21 | ||
117 | #define MV64x60_PCI12MEM_SNOOP_2_WIN 22 | ||
118 | #define MV64x60_PCI12MEM_SNOOP_3_WIN 23 | ||
119 | |||
120 | #define MV64x60_64BIT_WIN_COUNT 24 | ||
121 | |||
122 | /* | ||
123 | * Define a structure that's used to pass in config information to the | ||
124 | * core routines. | ||
125 | */ | ||
126 | struct mv64x60_pci_window { | ||
127 | u32 cpu_base; | ||
128 | u32 pci_base_hi; | ||
129 | u32 pci_base_lo; | ||
130 | u32 size; | ||
131 | u32 swap; | ||
132 | }; | ||
133 | |||
134 | struct mv64x60_pci_info { | ||
135 | u8 enable_bus; /* allow access to this PCI bus? */ | ||
136 | |||
137 | struct mv64x60_pci_window pci_io; | ||
138 | struct mv64x60_pci_window pci_mem[3]; | ||
139 | |||
140 | u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS]; | ||
141 | u32 snoop_options[MV64x60_CPU2MEM_WINDOWS]; | ||
142 | u16 pci_cmd_bits; | ||
143 | u16 latency_timer; | ||
144 | }; | ||
145 | |||
146 | struct mv64x60_setup_info { | ||
147 | u32 phys_reg_base; | ||
148 | u32 window_preserve_mask_32_hi; | ||
149 | u32 window_preserve_mask_32_lo; | ||
150 | u32 window_preserve_mask_64; | ||
151 | |||
152 | u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS]; | ||
153 | u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS]; | ||
154 | u32 enet_options[MV64x60_CPU2MEM_WINDOWS]; | ||
155 | u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS]; | ||
156 | u32 idma_options[MV64x60_CPU2MEM_WINDOWS]; | ||
157 | |||
158 | struct mv64x60_pci_info pci_0; | ||
159 | struct mv64x60_pci_info pci_1; | ||
160 | }; | ||
161 | |||
162 | /* Define what the top bits in the extra member of a window entry means. */ | ||
163 | #define MV64x60_EXTRA_INVALID 0x00000000 | ||
164 | #define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000 | ||
165 | #define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000 | ||
166 | #define MV64x60_EXTRA_ENET_ENAB 0x30000000 | ||
167 | #define MV64x60_EXTRA_MPSC_ENAB 0x40000000 | ||
168 | #define MV64x60_EXTRA_IDMA_ENAB 0x50000000 | ||
169 | #define MV64x60_EXTRA_PCIACC_ENAB 0x60000000 | ||
170 | |||
171 | #define MV64x60_EXTRA_MASK 0xf0000000 | ||
172 | |||
173 | /* | ||
174 | * Define the 'handle' struct that will be passed between the 64x60 core | ||
175 | * code and the platform-specific code that will use it. The handle | ||
176 | * will contain pointers to chip-specific routines & information. | ||
177 | */ | ||
178 | struct mv64x60_32bit_window { | ||
179 | u32 base_reg; | ||
180 | u32 size_reg; | ||
181 | u8 base_bits; | ||
182 | u8 size_bits; | ||
183 | u32 (*get_from_field)(u32 val, u32 num_bits); | ||
184 | u32 (*map_to_field)(u32 val, u32 num_bits); | ||
185 | u32 extra; | ||
186 | }; | ||
187 | |||
188 | struct mv64x60_64bit_window { | ||
189 | u32 base_hi_reg; | ||
190 | u32 base_lo_reg; | ||
191 | u32 size_reg; | ||
192 | u8 base_lo_bits; | ||
193 | u8 size_bits; | ||
194 | u32 (*get_from_field)(u32 val, u32 num_bits); | ||
195 | u32 (*map_to_field)(u32 val, u32 num_bits); | ||
196 | u32 extra; | ||
197 | }; | ||
198 | |||
199 | typedef struct mv64x60_handle mv64x60_handle_t; | ||
200 | struct mv64x60_chip_info { | ||
201 | u32 (*translate_size)(u32 base, u32 size, u32 num_bits); | ||
202 | u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits); | ||
203 | void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus, | ||
204 | u32 window, u32 base); | ||
205 | void (*set_pci2regs_window)(struct mv64x60_handle *bh, | ||
206 | struct pci_controller *hose, u32 bus, u32 base); | ||
207 | u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window); | ||
208 | void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window); | ||
209 | void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window); | ||
210 | void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window); | ||
211 | void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window); | ||
212 | void (*disable_all_windows)(mv64x60_handle_t *bh, | ||
213 | struct mv64x60_setup_info *si); | ||
214 | void (*config_io2mem_windows)(mv64x60_handle_t *bh, | ||
215 | struct mv64x60_setup_info *si, | ||
216 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
217 | void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base); | ||
218 | void (*chip_specific_init)(mv64x60_handle_t *bh, | ||
219 | struct mv64x60_setup_info *si); | ||
220 | |||
221 | struct mv64x60_32bit_window *window_tab_32bit; | ||
222 | struct mv64x60_64bit_window *window_tab_64bit; | ||
223 | }; | ||
224 | |||
225 | struct mv64x60_handle { | ||
226 | u32 type; /* type of bridge */ | ||
227 | u32 rev; /* revision of bridge */ | ||
228 | void *v_base; /* virtual base addr of bridge regs */ | ||
229 | phys_addr_t p_base; /* physical base addr of bridge regs */ | ||
230 | |||
231 | u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/ | ||
232 | u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/ | ||
233 | |||
234 | u32 io_base_a; /* vaddr of pci 0's I/O space */ | ||
235 | u32 io_base_b; /* vaddr of pci 1's I/O space */ | ||
236 | |||
237 | struct pci_controller *hose_a; | ||
238 | struct pci_controller *hose_b; | ||
239 | |||
240 | struct mv64x60_chip_info *ci; /* chip/bridge-specific info */ | ||
241 | }; | ||
242 | |||
243 | |||
244 | /* Define I/O routines for accessing registers on the 64x60 bridge. */ | ||
245 | extern inline void | ||
246 | mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) { | ||
247 | ulong flags; | ||
248 | |||
249 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
250 | out_le32(bh->v_base + offset, val); | ||
251 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
252 | } | ||
253 | |||
254 | extern inline u32 | ||
255 | mv64x60_read(struct mv64x60_handle *bh, u32 offset) { | ||
256 | ulong flags; | ||
257 | u32 reg; | ||
258 | |||
259 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
260 | reg = in_le32(bh->v_base + offset); | ||
261 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
262 | return reg; | ||
263 | } | ||
264 | |||
265 | extern inline void | ||
266 | mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask) | ||
267 | { | ||
268 | u32 reg; | ||
269 | ulong flags; | ||
270 | |||
271 | spin_lock_irqsave(&mv64x60_lock, flags); | ||
272 | reg = in_le32(bh->v_base + offs) & (~mask); | ||
273 | reg |= data & mask; | ||
274 | out_le32(bh->v_base + offs, reg); | ||
275 | spin_unlock_irqrestore(&mv64x60_lock, flags); | ||
276 | } | ||
277 | |||
278 | #define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits) | ||
279 | #define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits) | ||
280 | |||
281 | |||
282 | /* Externally visible function prototypes */ | ||
283 | int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si); | ||
284 | u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type); | ||
285 | void mv64x60_early_init(struct mv64x60_handle *bh, | ||
286 | struct mv64x60_setup_info *si); | ||
287 | void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, | ||
288 | u32 cfg_data, struct pci_controller **hose); | ||
289 | int mv64x60_get_type(struct mv64x60_handle *bh); | ||
290 | int mv64x60_setup_for_chip(struct mv64x60_handle *bh); | ||
291 | void *mv64x60_get_bridge_vbase(void); | ||
292 | u32 mv64x60_get_bridge_type(void); | ||
293 | u32 mv64x60_get_bridge_rev(void); | ||
294 | void mv64x60_get_mem_windows(struct mv64x60_handle *bh, | ||
295 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
296 | void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, | ||
297 | struct mv64x60_setup_info *si, | ||
298 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
299 | void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, | ||
300 | struct mv64x60_pci_info *pi, u32 bus); | ||
301 | void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, | ||
302 | struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus, | ||
303 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
304 | void mv64x60_config_resources(struct pci_controller *hose, | ||
305 | struct mv64x60_pci_info *pi, u32 io_base); | ||
306 | void mv64x60_config_pci_params(struct pci_controller *hose, | ||
307 | struct mv64x60_pci_info *pi); | ||
308 | void mv64x60_pd_fixup(struct mv64x60_handle *bh, | ||
309 | struct platform_device *pd_devs[], u32 entries); | ||
310 | void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, | ||
311 | u32 *base, u32 *size); | ||
312 | void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base, | ||
313 | u32 size, u32 other_bits); | ||
314 | void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, | ||
315 | u32 *base_hi, u32 *base_lo, u32 *size); | ||
316 | void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, | ||
317 | u32 base_hi, u32 base_lo, u32 size, u32 other_bits); | ||
318 | void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus); | ||
319 | int mv64x60_pci_exclude_device(u8 bus, u8 devfn); | ||
320 | |||
321 | |||
322 | void gt64260_init_irq(void); | ||
323 | int gt64260_get_irq(struct pt_regs *regs); | ||
324 | void mv64360_init_irq(void); | ||
325 | int mv64360_get_irq(struct pt_regs *regs); | ||
326 | |||
327 | u32 mv64x60_mask(u32 val, u32 num_bits); | ||
328 | u32 mv64x60_shift_left(u32 val, u32 num_bits); | ||
329 | u32 mv64x60_shift_right(u32 val, u32 num_bits); | ||
330 | u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh, | ||
331 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | ||
332 | |||
333 | void mv64x60_progress_init(u32 base); | ||
334 | void mv64x60_mpsc_progress(char *s, unsigned short hex); | ||
335 | |||
336 | extern struct mv64x60_32bit_window | ||
337 | gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT]; | ||
338 | extern struct mv64x60_64bit_window | ||
339 | gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT]; | ||
340 | extern struct mv64x60_32bit_window | ||
341 | mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT]; | ||
342 | extern struct mv64x60_64bit_window | ||
343 | mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT]; | ||
344 | |||
345 | #endif /* __ASMPPC_MV64x60_H */ | ||
diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h new file mode 100644 index 000000000000..2f428746c02b --- /dev/null +++ b/include/asm-ppc/mv64x60_defs.h | |||
@@ -0,0 +1,973 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/gt64260_defs.h | ||
3 | * | ||
4 | * Register definitions for the Marvell/Galileo GT64260, MV64360, etc. | ||
5 | * host bridges. | ||
6 | * | ||
7 | * Author: Mark A. Greer <mgreer@mvista.com> | ||
8 | * | ||
9 | * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
10 | * the terms of the GNU General Public License version 2. This program | ||
11 | * is licensed "as is" without any warranty of any kind, whether express | ||
12 | * or implied. | ||
13 | */ | ||
14 | #ifndef __ASMPPC_MV64x60_DEFS_H | ||
15 | #define __ASMPPC_MV64x60_DEFS_H | ||
16 | |||
17 | /* | ||
18 | * Define the Marvell bridges that are supported | ||
19 | */ | ||
20 | #define MV64x60_TYPE_INVALID 0 | ||
21 | #define MV64x60_TYPE_GT64260A 1 | ||
22 | #define MV64x60_TYPE_GT64260B 2 | ||
23 | #define MV64x60_TYPE_MV64360 3 | ||
24 | #define MV64x60_TYPE_MV64361 4 | ||
25 | #define MV64x60_TYPE_MV64362 5 | ||
26 | #define MV64x60_TYPE_MV64460 6 | ||
27 | |||
28 | |||
29 | /* Revisions of each supported chip */ | ||
30 | #define GT64260_REV_A 0x10 | ||
31 | #define GT64260_REV_B 0x20 | ||
32 | #define MV64360 0x01 | ||
33 | #define MV64460 0x01 | ||
34 | |||
35 | /* Minimum window size supported by 64260 is 1MB */ | ||
36 | #define GT64260_WINDOW_SIZE_MIN 0x00100000 | ||
37 | #define MV64360_WINDOW_SIZE_MIN 0x00010000 | ||
38 | |||
39 | #define MV64x60_TCLK_FREQ_MAX 133333333U | ||
40 | |||
41 | /* IRQ's for embedded controllers */ | ||
42 | #define MV64x60_IRQ_DEV 1 | ||
43 | #define MV64x60_IRQ_CPU_ERR 3 | ||
44 | #define MV64x60_IRQ_TIMER_0_1 8 | ||
45 | #define MV64x60_IRQ_TIMER_2_3 9 | ||
46 | #define MV64x60_IRQ_TIMER_4_5 10 | ||
47 | #define MV64x60_IRQ_TIMER_6_7 11 | ||
48 | #define MV64x60_IRQ_P1_GPP_0_7 24 | ||
49 | #define MV64x60_IRQ_P1_GPP_8_15 25 | ||
50 | #define MV64x60_IRQ_P1_GPP_16_23 26 | ||
51 | #define MV64x60_IRQ_P1_GPP_24_31 27 | ||
52 | #define MV64x60_IRQ_DOORBELL 28 | ||
53 | #define MV64x60_IRQ_ETH_0 32 | ||
54 | #define MV64x60_IRQ_ETH_1 33 | ||
55 | #define MV64x60_IRQ_ETH_2 34 | ||
56 | #define MV64x60_IRQ_SDMA_0 36 | ||
57 | #define MV64x60_IRQ_I2C 37 | ||
58 | #define MV64x60_IRQ_BRG 39 | ||
59 | #define MV64x60_IRQ_MPSC_0 40 | ||
60 | #define MV64x60_IRQ_MPSC_1 42 | ||
61 | #define MV64x60_IRQ_COMM 43 | ||
62 | #define MV64x60_IRQ_P0_GPP_0_7 56 | ||
63 | #define MV64x60_IRQ_P0_GPP_8_15 57 | ||
64 | #define MV64x60_IRQ_P0_GPP_16_23 58 | ||
65 | #define MV64x60_IRQ_P0_GPP_24_31 59 | ||
66 | |||
67 | #define MV64360_IRQ_PCI0 12 | ||
68 | #define MV64360_IRQ_SRAM_PAR_ERR 13 | ||
69 | #define MV64360_IRQ_PCI1 16 | ||
70 | #define MV64360_IRQ_SDMA_1 38 | ||
71 | |||
72 | #define MV64x60_IRQ_GPP0 64 | ||
73 | #define MV64x60_IRQ_GPP1 65 | ||
74 | #define MV64x60_IRQ_GPP2 66 | ||
75 | #define MV64x60_IRQ_GPP3 67 | ||
76 | #define MV64x60_IRQ_GPP4 68 | ||
77 | #define MV64x60_IRQ_GPP5 69 | ||
78 | #define MV64x60_IRQ_GPP6 70 | ||
79 | #define MV64x60_IRQ_GPP7 71 | ||
80 | #define MV64x60_IRQ_GPP8 72 | ||
81 | #define MV64x60_IRQ_GPP9 73 | ||
82 | #define MV64x60_IRQ_GPP10 74 | ||
83 | #define MV64x60_IRQ_GPP11 75 | ||
84 | #define MV64x60_IRQ_GPP12 76 | ||
85 | #define MV64x60_IRQ_GPP13 77 | ||
86 | #define MV64x60_IRQ_GPP14 78 | ||
87 | #define MV64x60_IRQ_GPP15 79 | ||
88 | #define MV64x60_IRQ_GPP16 80 | ||
89 | #define MV64x60_IRQ_GPP17 81 | ||
90 | #define MV64x60_IRQ_GPP18 82 | ||
91 | #define MV64x60_IRQ_GPP19 83 | ||
92 | #define MV64x60_IRQ_GPP20 84 | ||
93 | #define MV64x60_IRQ_GPP21 85 | ||
94 | #define MV64x60_IRQ_GPP22 86 | ||
95 | #define MV64x60_IRQ_GPP23 87 | ||
96 | #define MV64x60_IRQ_GPP24 88 | ||
97 | #define MV64x60_IRQ_GPP25 89 | ||
98 | #define MV64x60_IRQ_GPP26 90 | ||
99 | #define MV64x60_IRQ_GPP27 91 | ||
100 | #define MV64x60_IRQ_GPP28 92 | ||
101 | #define MV64x60_IRQ_GPP29 93 | ||
102 | #define MV64x60_IRQ_GPP30 94 | ||
103 | #define MV64x60_IRQ_GPP31 95 | ||
104 | |||
105 | /* Offsets for register blocks */ | ||
106 | #define GT64260_ENET_PHY_ADDR 0x2000 | ||
107 | #define GT64260_ENET_ESMIR 0x2010 | ||
108 | #define GT64260_ENET_0_OFFSET 0x2400 | ||
109 | #define GT64260_ENET_1_OFFSET 0x2800 | ||
110 | #define GT64260_ENET_2_OFFSET 0x2c00 | ||
111 | #define MV64x60_SDMA_0_OFFSET 0x4000 | ||
112 | #define MV64x60_SDMA_1_OFFSET 0x6000 | ||
113 | #define MV64x60_MPSC_0_OFFSET 0x8000 | ||
114 | #define MV64x60_MPSC_1_OFFSET 0x9000 | ||
115 | #define MV64x60_MPSC_ROUTING_OFFSET 0xb400 | ||
116 | #define MV64x60_SDMA_INTR_OFFSET 0xb800 | ||
117 | #define MV64x60_BRG_0_OFFSET 0xb200 | ||
118 | #define MV64x60_BRG_1_OFFSET 0xb208 | ||
119 | |||
120 | /* | ||
121 | ***************************************************************************** | ||
122 | * | ||
123 | * CPU Interface Registers | ||
124 | * | ||
125 | ***************************************************************************** | ||
126 | */ | ||
127 | |||
128 | /* CPU physical address of bridge's registers */ | ||
129 | #define MV64x60_INTERNAL_SPACE_DECODE 0x0068 | ||
130 | #define MV64x60_INTERNAL_SPACE_SIZE 0x10000 | ||
131 | #define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 | ||
132 | |||
133 | #define MV64360_CPU_BAR_ENABLE 0x0278 | ||
134 | |||
135 | /* CPU Memory Controller Window Registers (4 windows) */ | ||
136 | #define MV64x60_CPU2MEM_WINDOWS 4 | ||
137 | |||
138 | #define MV64x60_CPU2MEM_0_BASE 0x0008 | ||
139 | #define MV64x60_CPU2MEM_0_SIZE 0x0010 | ||
140 | #define MV64x60_CPU2MEM_1_BASE 0x0208 | ||
141 | #define MV64x60_CPU2MEM_1_SIZE 0x0210 | ||
142 | #define MV64x60_CPU2MEM_2_BASE 0x0018 | ||
143 | #define MV64x60_CPU2MEM_2_SIZE 0x0020 | ||
144 | #define MV64x60_CPU2MEM_3_BASE 0x0218 | ||
145 | #define MV64x60_CPU2MEM_3_SIZE 0x0220 | ||
146 | |||
147 | /* CPU Device Controller Window Registers (4 windows) */ | ||
148 | #define MV64x60_CPU2DEV_WINDOWS 4 | ||
149 | |||
150 | #define MV64x60_CPU2DEV_0_BASE 0x0028 | ||
151 | #define MV64x60_CPU2DEV_0_SIZE 0x0030 | ||
152 | #define MV64x60_CPU2DEV_1_BASE 0x0228 | ||
153 | #define MV64x60_CPU2DEV_1_SIZE 0x0230 | ||
154 | #define MV64x60_CPU2DEV_2_BASE 0x0248 | ||
155 | #define MV64x60_CPU2DEV_2_SIZE 0x0250 | ||
156 | #define MV64x60_CPU2DEV_3_BASE 0x0038 | ||
157 | #define MV64x60_CPU2DEV_3_SIZE 0x0040 | ||
158 | |||
159 | #define MV64x60_CPU2BOOT_0_BASE 0x0238 | ||
160 | #define MV64x60_CPU2BOOT_0_SIZE 0x0240 | ||
161 | |||
162 | #define MV64360_CPU2SRAM_BASE 0x0268 | ||
163 | |||
164 | /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ | ||
165 | #define MV64x60_PCI_BUSES 2 | ||
166 | #define MV64x60_PCI_IO_WINDOWS_PER_BUS 1 | ||
167 | #define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4 | ||
168 | |||
169 | #define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000 | ||
170 | #define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 | ||
171 | #define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000 | ||
172 | #define MV64x60_CPU2PCI_SWAP_WORD 0x03000000 | ||
173 | |||
174 | #define MV64x60_CPU2PCI_MEM_REQ64 (1<<27) | ||
175 | |||
176 | #define MV64x60_CPU2PCI0_IO_BASE 0x0048 | ||
177 | #define MV64x60_CPU2PCI0_IO_SIZE 0x0050 | ||
178 | #define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 | ||
179 | #define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 | ||
180 | #define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080 | ||
181 | #define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088 | ||
182 | #define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258 | ||
183 | #define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260 | ||
184 | #define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280 | ||
185 | #define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288 | ||
186 | |||
187 | #define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 | ||
188 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 | ||
189 | #define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 | ||
190 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100 | ||
191 | #define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328 | ||
192 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8 | ||
193 | #define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330 | ||
194 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300 | ||
195 | #define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338 | ||
196 | |||
197 | #define MV64x60_CPU2PCI1_IO_BASE 0x0090 | ||
198 | #define MV64x60_CPU2PCI1_IO_SIZE 0x0098 | ||
199 | #define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 | ||
200 | #define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 | ||
201 | #define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0 | ||
202 | #define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8 | ||
203 | #define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0 | ||
204 | #define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8 | ||
205 | #define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0 | ||
206 | #define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8 | ||
207 | |||
208 | #define MV64x60_CPU2PCI1_IO_REMAP 0x0108 | ||
209 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 | ||
210 | #define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 | ||
211 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118 | ||
212 | #define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348 | ||
213 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310 | ||
214 | #define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350 | ||
215 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318 | ||
216 | #define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358 | ||
217 | |||
218 | /* CPU Control Registers */ | ||
219 | #define MV64x60_CPU_CONFIG 0x0000 | ||
220 | #define MV64x60_CPU_MODE 0x0120 | ||
221 | #define MV64x60_CPU_MASTER_CNTL 0x0160 | ||
222 | #define MV64x60_CPU_XBAR_CNTL_LO 0x0150 | ||
223 | #define MV64x60_CPU_XBAR_CNTL_HI 0x0158 | ||
224 | #define MV64x60_CPU_XBAR_TO 0x0168 | ||
225 | |||
226 | #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 | ||
227 | #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 | ||
228 | |||
229 | #define MV64360_CPU_PADS_CALIBRATION 0x03b4 | ||
230 | #define MV64360_CPU_RESET_SAMPLE_LO 0x03c4 | ||
231 | #define MV64360_CPU_RESET_SAMPLE_HI 0x03d4 | ||
232 | |||
233 | /* SMP Register Map */ | ||
234 | #define MV64360_WHO_AM_I 0x0200 | ||
235 | #define MV64360_CPU0_DOORBELL 0x0214 | ||
236 | #define MV64360_CPU0_DOORBELL_CLR 0x021c | ||
237 | #define MV64360_CPU0_DOORBELL_MASK 0x0234 | ||
238 | #define MV64360_CPU1_DOORBELL 0x0224 | ||
239 | #define MV64360_CPU1_DOORBELL_CLR 0x022c | ||
240 | #define MV64360_CPU1_DOORBELL_MASK 0x023c | ||
241 | #define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10)) | ||
242 | #define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10)) | ||
243 | #define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08)) | ||
244 | #define MV64360_SEMAPHORE_0 0x0244 | ||
245 | #define MV64360_SEMAPHORE_1 0x024c | ||
246 | #define MV64360_SEMAPHORE_2 0x0254 | ||
247 | #define MV64360_SEMAPHORE_3 0x025c | ||
248 | #define MV64360_SEMAPHORE_4 0x0264 | ||
249 | #define MV64360_SEMAPHORE_5 0x026c | ||
250 | #define MV64360_SEMAPHORE_6 0x0274 | ||
251 | #define MV64360_SEMAPHORE_7 0x027c | ||
252 | |||
253 | /* CPU Sync Barrier Registers */ | ||
254 | #define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0 | ||
255 | #define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8 | ||
256 | |||
257 | #define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0 | ||
258 | #define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8 | ||
259 | #define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0 | ||
260 | #define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8 | ||
261 | |||
262 | /* CPU Deadlock and Ordering registers (Rev B part only) */ | ||
263 | #define GT64260_CPU_DEADLOCK_ORDERING 0x02d0 | ||
264 | #define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8 | ||
265 | #define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0 | ||
266 | |||
267 | /* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */ | ||
268 | #define MV64x260_CPU_PROT_WINDOWS 4 | ||
269 | |||
270 | #define GT64260_CPU_PROT_ACCPROTECT (1<<16) | ||
271 | #define GT64260_CPU_PROT_WRPROTECT (1<<17) | ||
272 | #define GT64260_CPU_PROT_CACHEPROTECT (1<<18) | ||
273 | |||
274 | #define MV64360_CPU_PROT_ACCPROTECT (1<<20) | ||
275 | #define MV64360_CPU_PROT_WRPROTECT (1<<21) | ||
276 | #define MV64360_CPU_PROT_CACHEPROTECT (1<<22) | ||
277 | #define MV64360_CPU_PROT_WIN_ENABLE (1<<31) | ||
278 | |||
279 | #define MV64x60_CPU_PROT_BASE_0 0x0180 | ||
280 | #define MV64x60_CPU_PROT_SIZE_0 0x0188 | ||
281 | #define MV64x60_CPU_PROT_BASE_1 0x0190 | ||
282 | #define MV64x60_CPU_PROT_SIZE_1 0x0198 | ||
283 | #define MV64x60_CPU_PROT_BASE_2 0x01a0 | ||
284 | #define MV64x60_CPU_PROT_SIZE_2 0x01a8 | ||
285 | #define MV64x60_CPU_PROT_BASE_3 0x01b0 | ||
286 | #define MV64x60_CPU_PROT_SIZE_3 0x01b8 | ||
287 | |||
288 | #define GT64260_CPU_PROT_BASE_4 0x01c0 | ||
289 | #define GT64260_CPU_PROT_SIZE_4 0x01c8 | ||
290 | #define GT64260_CPU_PROT_BASE_5 0x01d0 | ||
291 | #define GT64260_CPU_PROT_SIZE_5 0x01d8 | ||
292 | #define GT64260_CPU_PROT_BASE_6 0x01e0 | ||
293 | #define GT64260_CPU_PROT_SIZE_6 0x01e8 | ||
294 | #define GT64260_CPU_PROT_BASE_7 0x01f0 | ||
295 | #define GT64260_CPU_PROT_SIZE_7 0x01f8 | ||
296 | |||
297 | /* CPU Snoop Control Registers (64260 only) */ | ||
298 | #define GT64260_CPU_SNOOP_WINDOWS 4 | ||
299 | |||
300 | #define GT64260_CPU_SNOOP_NONE 0x00000000 | ||
301 | #define GT64260_CPU_SNOOP_WT 0x00010000 | ||
302 | #define GT64260_CPU_SNOOP_WB 0x00020000 | ||
303 | #define GT64260_CPU_SNOOP_MASK 0x00030000 | ||
304 | #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK | ||
305 | |||
306 | #define GT64260_CPU_SNOOP_BASE_0 0x0380 | ||
307 | #define GT64260_CPU_SNOOP_SIZE_0 0x0388 | ||
308 | #define GT64260_CPU_SNOOP_BASE_1 0x0390 | ||
309 | #define GT64260_CPU_SNOOP_SIZE_1 0x0398 | ||
310 | #define GT64260_CPU_SNOOP_BASE_2 0x03a0 | ||
311 | #define GT64260_CPU_SNOOP_SIZE_2 0x03a8 | ||
312 | #define GT64260_CPU_SNOOP_BASE_3 0x03b0 | ||
313 | #define GT64260_CPU_SNOOP_SIZE_3 0x03b8 | ||
314 | |||
315 | /* CPU Snoop Control Registers (64360 only) */ | ||
316 | #define MV64360_CPU_SNOOP_WINDOWS 4 | ||
317 | #define MV64360_CPU_SNOOP_NONE 0x00000000 | ||
318 | #define MV64360_CPU_SNOOP_WT 0x00010000 | ||
319 | #define MV64360_CPU_SNOOP_WB 0x00020000 | ||
320 | #define MV64360_CPU_SNOOP_MASK 0x00030000 | ||
321 | #define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK | ||
322 | |||
323 | |||
324 | /* CPU Error Report Registers */ | ||
325 | #define MV64x60_CPU_ERR_ADDR_LO 0x0070 | ||
326 | #define MV64x60_CPU_ERR_ADDR_HI 0x0078 | ||
327 | #define MV64x60_CPU_ERR_DATA_LO 0x0128 | ||
328 | #define MV64x60_CPU_ERR_DATA_HI 0x0130 | ||
329 | #define MV64x60_CPU_ERR_PARITY 0x0138 | ||
330 | #define MV64x60_CPU_ERR_CAUSE 0x0140 | ||
331 | #define MV64x60_CPU_ERR_MASK 0x0148 | ||
332 | |||
333 | /* | ||
334 | ***************************************************************************** | ||
335 | * | ||
336 | * SRAM Cotnroller Registers | ||
337 | * | ||
338 | ***************************************************************************** | ||
339 | */ | ||
340 | |||
341 | #define MV64360_SRAM_CONFIG 0x0380 | ||
342 | #define MV64360_SRAM_TEST_MODE 0x03f4 | ||
343 | #define MV64360_SRAM_ERR_CAUSE 0x0388 | ||
344 | #define MV64360_SRAM_ERR_ADDR_LO 0x0390 | ||
345 | #define MV64360_SRAM_ERR_ADDR_HI 0x03f8 | ||
346 | #define MV64360_SRAM_ERR_DATA_LO 0x0398 | ||
347 | #define MV64360_SRAM_ERR_DATA_HI 0x03a0 | ||
348 | #define MV64360_SRAM_ERR_PARITY 0x03a8 | ||
349 | |||
350 | #define MV64360_SRAM_SIZE 0x00040000 /* 2Mb/256KB SRAM */ | ||
351 | |||
352 | /* | ||
353 | ***************************************************************************** | ||
354 | * | ||
355 | * SDRAM/MEM Cotnroller Registers | ||
356 | * | ||
357 | ***************************************************************************** | ||
358 | */ | ||
359 | |||
360 | /* SDRAM Config Registers (64260) */ | ||
361 | #define GT64260_SDRAM_CONFIG 0x0448 | ||
362 | |||
363 | /* SDRAM Error Report Registers (64260) */ | ||
364 | #define GT64260_SDRAM_ERR_DATA_LO 0x0484 | ||
365 | #define GT64260_SDRAM_ERR_DATA_HI 0x0480 | ||
366 | #define GT64260_SDRAM_ERR_ADDR 0x0490 | ||
367 | #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 | ||
368 | #define GT64260_SDRAM_ERR_ECC_CALC 0x048c | ||
369 | #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 | ||
370 | #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 | ||
371 | |||
372 | /* SDRAM Config Registers (64360) */ | ||
373 | #define MV64360_SDRAM_CONFIG 0x1400 | ||
374 | |||
375 | /* SDRAM Control Registers */ | ||
376 | #define MV64360_D_UNIT_CONTROL_LOW 0x1404 | ||
377 | #define MV64360_D_UNIT_CONTROL_HIGH 0x1424 | ||
378 | |||
379 | /* SDRAM Error Report Registers (64360) */ | ||
380 | #define MV64360_SDRAM_ERR_DATA_LO 0x1444 | ||
381 | #define MV64360_SDRAM_ERR_DATA_HI 0x1440 | ||
382 | #define MV64360_SDRAM_ERR_ADDR 0x1450 | ||
383 | #define MV64360_SDRAM_ERR_ECC_RCVD 0x1448 | ||
384 | #define MV64360_SDRAM_ERR_ECC_CALC 0x144c | ||
385 | #define MV64360_SDRAM_ERR_ECC_CNTL 0x1454 | ||
386 | #define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458 | ||
387 | |||
388 | /* | ||
389 | ***************************************************************************** | ||
390 | * | ||
391 | * Device/BOOT Cotnroller Registers | ||
392 | * | ||
393 | ***************************************************************************** | ||
394 | */ | ||
395 | |||
396 | /* Device Control Registers */ | ||
397 | #define MV64x60_DEV_BANK_PARAMS_0 0x045c | ||
398 | #define MV64x60_DEV_BANK_PARAMS_1 0x0460 | ||
399 | #define MV64x60_DEV_BANK_PARAMS_2 0x0464 | ||
400 | #define MV64x60_DEV_BANK_PARAMS_3 0x0468 | ||
401 | #define MV64x60_DEV_BOOT_PARAMS 0x046c | ||
402 | #define MV64x60_DEV_IF_CNTL 0x04c0 | ||
403 | #define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8 | ||
404 | #define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc | ||
405 | #define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4 | ||
406 | |||
407 | /* Device Interrupt Registers */ | ||
408 | #define MV64x60_DEV_INTR_CAUSE 0x04d0 | ||
409 | #define MV64x60_DEV_INTR_MASK 0x04d4 | ||
410 | #define MV64x60_DEV_INTR_ERR_ADDR 0x04d8 | ||
411 | |||
412 | #define MV64360_DEV_INTR_ERR_DATA 0x04dc | ||
413 | #define MV64360_DEV_INTR_ERR_PAR 0x04e0 | ||
414 | |||
415 | /* | ||
416 | ***************************************************************************** | ||
417 | * | ||
418 | * PCI Bridge Interface Registers | ||
419 | * | ||
420 | ***************************************************************************** | ||
421 | */ | ||
422 | |||
423 | /* PCI Configuration Access Registers */ | ||
424 | #define MV64x60_PCI0_CONFIG_ADDR 0x0cf8 | ||
425 | #define MV64x60_PCI0_CONFIG_DATA 0x0cfc | ||
426 | #define MV64x60_PCI0_IACK 0x0c34 | ||
427 | |||
428 | #define MV64x60_PCI1_CONFIG_ADDR 0x0c78 | ||
429 | #define MV64x60_PCI1_CONFIG_DATA 0x0c7c | ||
430 | #define MV64x60_PCI1_IACK 0x0cb4 | ||
431 | |||
432 | /* PCI Control Registers */ | ||
433 | #define MV64x60_PCI0_CMD 0x0c00 | ||
434 | #define MV64x60_PCI0_MODE 0x0d00 | ||
435 | #define MV64x60_PCI0_TO_RETRY 0x0c04 | ||
436 | #define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04 | ||
437 | #define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38 | ||
438 | #define MV64x60_PCI0_ARBITER_CNTL 0x1d00 | ||
439 | #define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08 | ||
440 | #define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c | ||
441 | #define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04 | ||
442 | #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18 | ||
443 | #define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c | ||
444 | #define MV64x60_PCI0_SYNC_BARRIER 0x1d10 | ||
445 | #define MV64x60_PCI0_P2P_CONFIG 0x1d14 | ||
446 | #define MV64x60_PCI0_INTR_MASK | ||
447 | |||
448 | #define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54 | ||
449 | |||
450 | #define MV64x60_PCI1_CMD 0x0c80 | ||
451 | #define MV64x60_PCI1_MODE 0x0d80 | ||
452 | #define MV64x60_PCI1_TO_RETRY 0x0c84 | ||
453 | #define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84 | ||
454 | #define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8 | ||
455 | #define MV64x60_PCI1_ARBITER_CNTL 0x1d80 | ||
456 | #define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88 | ||
457 | #define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c | ||
458 | #define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84 | ||
459 | #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98 | ||
460 | #define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c | ||
461 | #define MV64x60_PCI1_SYNC_BARRIER 0x1d90 | ||
462 | #define MV64x60_PCI1_P2P_CONFIG 0x1d94 | ||
463 | |||
464 | #define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4 | ||
465 | |||
466 | /* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */ | ||
467 | #define MV64x60_PCIMODE_CONVENTIONAL 0 | ||
468 | #define MV64x60_PCIMODE_PCIX_66 (1 << 4) | ||
469 | #define MV64x60_PCIMODE_PCIX_100 (2 << 4) | ||
470 | #define MV64x60_PCIMODE_PCIX_133 (3 << 4) | ||
471 | #define MV64x60_PCIMODE_MASK (0x3 << 4) | ||
472 | |||
473 | /* PCI Access Control Regions Registers */ | ||
474 | #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) | ||
475 | #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) | ||
476 | #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) | ||
477 | #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) | ||
478 | #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) | ||
479 | #define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000 | ||
480 | #define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000 | ||
481 | #define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000 | ||
482 | #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 | ||
483 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
484 | #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 | ||
485 | #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 | ||
486 | #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 | ||
487 | #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 | ||
488 | #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) | ||
489 | #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) | ||
490 | |||
491 | #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ | ||
492 | GT64260_PCI_ACC_CNTL_DREADEN | \ | ||
493 | GT64260_PCI_ACC_CNTL_RDPREFETCH | \ | ||
494 | GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ | ||
495 | GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ | ||
496 | GT64260_PCI_ACC_CNTL_MBURST_MASK | \ | ||
497 | GT64260_PCI_ACC_CNTL_SWAP_MASK | \ | ||
498 | GT64260_PCI_ACC_CNTL_ACCPROT| \ | ||
499 | GT64260_PCI_ACC_CNTL_WRPROT) | ||
500 | |||
501 | #define MV64360_PCI_ACC_CNTL_ENABLE (1<<0) | ||
502 | #define MV64360_PCI_ACC_CNTL_REQ64 (1<<1) | ||
503 | #define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 | ||
504 | #define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004 | ||
505 | #define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008 | ||
506 | #define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c | ||
507 | #define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4) | ||
508 | #define MV64360_PCI_ACC_CNTL_WRPROT (1<<5) | ||
509 | #define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 | ||
510 | #define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040 | ||
511 | #define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 | ||
512 | #define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 | ||
513 | #define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 | ||
514 | #define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 | ||
515 | #define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 | ||
516 | #define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 | ||
517 | #define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300 | ||
518 | #define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 | ||
519 | #define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 | ||
520 | #define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 | ||
521 | #define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 | ||
522 | #define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 | ||
523 | |||
524 | #define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \ | ||
525 | MV64360_PCI_ACC_CNTL_REQ64 | \ | ||
526 | MV64360_PCI_ACC_CNTL_SNOOP_MASK | \ | ||
527 | MV64360_PCI_ACC_CNTL_ACCPROT | \ | ||
528 | MV64360_PCI_ACC_CNTL_WRPROT | \ | ||
529 | MV64360_PCI_ACC_CNTL_SWAP_MASK | \ | ||
530 | MV64360_PCI_ACC_CNTL_MBURST_MASK | \ | ||
531 | MV64360_PCI_ACC_CNTL_RDSIZE_MASK) | ||
532 | |||
533 | #define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 | ||
534 | #define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 | ||
535 | #define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 | ||
536 | #define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 | ||
537 | #define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 | ||
538 | #define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 | ||
539 | #define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 | ||
540 | #define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 | ||
541 | #define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 | ||
542 | #define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 | ||
543 | #define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 | ||
544 | #define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 | ||
545 | #define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 | ||
546 | #define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 | ||
547 | #define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 | ||
548 | #define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 | ||
549 | #define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 | ||
550 | #define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 | ||
551 | |||
552 | #define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60 | ||
553 | #define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64 | ||
554 | #define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68 | ||
555 | #define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70 | ||
556 | #define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74 | ||
557 | #define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78 | ||
558 | |||
559 | #define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 | ||
560 | #define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 | ||
561 | #define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 | ||
562 | #define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 | ||
563 | #define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 | ||
564 | #define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 | ||
565 | #define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 | ||
566 | #define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 | ||
567 | #define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 | ||
568 | #define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 | ||
569 | #define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 | ||
570 | #define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 | ||
571 | #define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 | ||
572 | #define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 | ||
573 | #define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 | ||
574 | #define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 | ||
575 | #define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 | ||
576 | #define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 | ||
577 | |||
578 | #define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0 | ||
579 | #define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4 | ||
580 | #define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8 | ||
581 | #define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0 | ||
582 | #define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4 | ||
583 | #define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8 | ||
584 | |||
585 | /* PCI Snoop Control Registers (64260 only) */ | ||
586 | #define GT64260_PCI_SNOOP_NONE 0x00000000 | ||
587 | #define GT64260_PCI_SNOOP_WT 0x00001000 | ||
588 | #define GT64260_PCI_SNOOP_WB 0x00002000 | ||
589 | |||
590 | #define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00 | ||
591 | #define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04 | ||
592 | #define GT64260_PCI0_SNOOP_0_SIZE 0x1f08 | ||
593 | #define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10 | ||
594 | #define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14 | ||
595 | #define GT64260_PCI0_SNOOP_1_SIZE 0x1f18 | ||
596 | #define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20 | ||
597 | #define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24 | ||
598 | #define GT64260_PCI0_SNOOP_2_SIZE 0x1f28 | ||
599 | #define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30 | ||
600 | #define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34 | ||
601 | #define GT64260_PCI0_SNOOP_3_SIZE 0x1f38 | ||
602 | |||
603 | #define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80 | ||
604 | #define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84 | ||
605 | #define GT64260_PCI1_SNOOP_0_SIZE 0x1f88 | ||
606 | #define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90 | ||
607 | #define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94 | ||
608 | #define GT64260_PCI1_SNOOP_1_SIZE 0x1f98 | ||
609 | #define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0 | ||
610 | #define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4 | ||
611 | #define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8 | ||
612 | #define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0 | ||
613 | #define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4 | ||
614 | #define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8 | ||
615 | |||
616 | /* PCI Error Report Registers */ | ||
617 | #define MV64x60_PCI0_ERR_SERR_MASK 0x0c28 | ||
618 | #define MV64x60_PCI0_ERR_ADDR_LO 0x1d40 | ||
619 | #define MV64x60_PCI0_ERR_ADDR_HI 0x1d44 | ||
620 | #define MV64x60_PCI0_ERR_DATA_LO 0x1d48 | ||
621 | #define MV64x60_PCI0_ERR_DATA_HI 0x1d4c | ||
622 | #define MV64x60_PCI0_ERR_CMD 0x1d50 | ||
623 | #define MV64x60_PCI0_ERR_CAUSE 0x1d58 | ||
624 | #define MV64x60_PCI0_ERR_MASK 0x1d5c | ||
625 | |||
626 | #define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8 | ||
627 | #define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0 | ||
628 | #define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4 | ||
629 | #define MV64x60_PCI1_ERR_DATA_LO 0x1dc8 | ||
630 | #define MV64x60_PCI1_ERR_DATA_HI 0x1dcc | ||
631 | #define MV64x60_PCI1_ERR_CMD 0x1dd0 | ||
632 | #define MV64x60_PCI1_ERR_CAUSE 0x1dd8 | ||
633 | #define MV64x60_PCI1_ERR_MASK 0x1ddc | ||
634 | |||
635 | /* PCI Slave Address Decoding Registers */ | ||
636 | #define MV64x60_PCI0_MEM_0_SIZE 0x0c08 | ||
637 | #define MV64x60_PCI0_MEM_1_SIZE 0x0d08 | ||
638 | #define MV64x60_PCI0_MEM_2_SIZE 0x0c0c | ||
639 | #define MV64x60_PCI0_MEM_3_SIZE 0x0d0c | ||
640 | #define MV64x60_PCI1_MEM_0_SIZE 0x0c88 | ||
641 | #define MV64x60_PCI1_MEM_1_SIZE 0x0d88 | ||
642 | #define MV64x60_PCI1_MEM_2_SIZE 0x0c8c | ||
643 | #define MV64x60_PCI1_MEM_3_SIZE 0x0d8c | ||
644 | |||
645 | #define MV64x60_PCI0_BAR_ENABLE 0x0c3c | ||
646 | #define MV64x60_PCI1_BAR_ENABLE 0x0cbc | ||
647 | |||
648 | #define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c | ||
649 | #define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc | ||
650 | |||
651 | #define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48 | ||
652 | #define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48 | ||
653 | #define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c | ||
654 | #define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c | ||
655 | #define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50 | ||
656 | #define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50 | ||
657 | #define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58 | ||
658 | #define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54 | ||
659 | #define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54 | ||
660 | #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c | ||
661 | #define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 | ||
662 | #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 | ||
663 | #define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 | ||
664 | #define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c | ||
665 | #define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70 | ||
666 | |||
667 | #define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8 | ||
668 | #define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8 | ||
669 | #define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc | ||
670 | #define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc | ||
671 | #define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0 | ||
672 | #define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0 | ||
673 | #define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8 | ||
674 | #define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4 | ||
675 | #define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4 | ||
676 | #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc | ||
677 | #define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 | ||
678 | #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 | ||
679 | #define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 | ||
680 | #define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec | ||
681 | #define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0 | ||
682 | |||
683 | /* | ||
684 | ***************************************************************************** | ||
685 | * | ||
686 | * ENET Controller Interface Registers | ||
687 | * | ||
688 | ***************************************************************************** | ||
689 | */ | ||
690 | |||
691 | /* ENET Controller Window Registers (6 windows) */ | ||
692 | #define MV64360_ENET2MEM_WINDOWS 6 | ||
693 | |||
694 | #define MV64360_ENET2MEM_0_BASE 0x2200 | ||
695 | #define MV64360_ENET2MEM_0_SIZE 0x2204 | ||
696 | #define MV64360_ENET2MEM_1_BASE 0x2208 | ||
697 | #define MV64360_ENET2MEM_1_SIZE 0x220c | ||
698 | #define MV64360_ENET2MEM_2_BASE 0x2210 | ||
699 | #define MV64360_ENET2MEM_2_SIZE 0x2214 | ||
700 | #define MV64360_ENET2MEM_3_BASE 0x2218 | ||
701 | #define MV64360_ENET2MEM_3_SIZE 0x221c | ||
702 | #define MV64360_ENET2MEM_4_BASE 0x2220 | ||
703 | #define MV64360_ENET2MEM_4_SIZE 0x2224 | ||
704 | #define MV64360_ENET2MEM_5_BASE 0x2228 | ||
705 | #define MV64360_ENET2MEM_5_SIZE 0x222c | ||
706 | |||
707 | #define MV64360_ENET2MEM_SNOOP_NONE 0x00000000 | ||
708 | #define MV64360_ENET2MEM_SNOOP_WT 0x00001000 | ||
709 | #define MV64360_ENET2MEM_SNOOP_WB 0x00002000 | ||
710 | |||
711 | #define MV64360_ENET2MEM_BAR_ENABLE 0x2290 | ||
712 | |||
713 | #define MV64360_ENET2MEM_ACC_PROT_0 0x2294 | ||
714 | #define MV64360_ENET2MEM_ACC_PROT_1 0x2298 | ||
715 | #define MV64360_ENET2MEM_ACC_PROT_2 0x229c | ||
716 | |||
717 | /* | ||
718 | ***************************************************************************** | ||
719 | * | ||
720 | * MPSC Controller Interface Registers | ||
721 | * | ||
722 | ***************************************************************************** | ||
723 | */ | ||
724 | |||
725 | /* MPSC Controller Window Registers (4 windows) */ | ||
726 | #define MV64360_MPSC2MEM_WINDOWS 4 | ||
727 | |||
728 | #define MV64360_MPSC2MEM_0_BASE 0xf200 | ||
729 | #define MV64360_MPSC2MEM_0_SIZE 0xf204 | ||
730 | #define MV64360_MPSC2MEM_1_BASE 0xf208 | ||
731 | #define MV64360_MPSC2MEM_1_SIZE 0xf20c | ||
732 | #define MV64360_MPSC2MEM_2_BASE 0xf210 | ||
733 | #define MV64360_MPSC2MEM_2_SIZE 0xf214 | ||
734 | #define MV64360_MPSC2MEM_3_BASE 0xf218 | ||
735 | #define MV64360_MPSC2MEM_3_SIZE 0xf21c | ||
736 | |||
737 | #define MV64360_MPSC_0_REMAP 0xf240 | ||
738 | #define MV64360_MPSC_1_REMAP 0xf244 | ||
739 | |||
740 | #define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000 | ||
741 | #define MV64360_MPSC2MEM_SNOOP_WT 0x00001000 | ||
742 | #define MV64360_MPSC2MEM_SNOOP_WB 0x00002000 | ||
743 | |||
744 | #define MV64360_MPSC2MEM_BAR_ENABLE 0xf250 | ||
745 | |||
746 | #define MV64360_MPSC2MEM_ACC_PROT_0 0xf254 | ||
747 | #define MV64360_MPSC2MEM_ACC_PROT_1 0xf258 | ||
748 | |||
749 | #define MV64360_MPSC2REGS_BASE 0xf25c | ||
750 | |||
751 | /* | ||
752 | ***************************************************************************** | ||
753 | * | ||
754 | * Timer/Counter Interface Registers | ||
755 | * | ||
756 | ***************************************************************************** | ||
757 | */ | ||
758 | |||
759 | #define MV64x60_TIMR_CNTR_0 0x0850 | ||
760 | #define MV64x60_TIMR_CNTR_1 0x0854 | ||
761 | #define MV64x60_TIMR_CNTR_2 0x0858 | ||
762 | #define MV64x60_TIMR_CNTR_3 0x085c | ||
763 | #define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864 | ||
764 | #define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868 | ||
765 | #define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c | ||
766 | |||
767 | #define GT64260_TIMR_CNTR_4 0x0950 | ||
768 | #define GT64260_TIMR_CNTR_5 0x0954 | ||
769 | #define GT64260_TIMR_CNTR_6 0x0958 | ||
770 | #define GT64260_TIMR_CNTR_7 0x095c | ||
771 | #define GT64260_TIMR_CNTR_4_7_CNTL 0x0964 | ||
772 | #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968 | ||
773 | #define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c | ||
774 | |||
775 | /* | ||
776 | ***************************************************************************** | ||
777 | * | ||
778 | * Communications Controller | ||
779 | * | ||
780 | ***************************************************************************** | ||
781 | */ | ||
782 | |||
783 | #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 | ||
784 | #define GT64260_SER_INIT_LAST_DATA 0xf324 | ||
785 | #define GT64260_SER_INIT_CONTROL 0xf328 | ||
786 | #define GT64260_SER_INIT_STATUS 0xf32c | ||
787 | |||
788 | #define MV64x60_COMM_ARBITER_CNTL 0xf300 | ||
789 | #define MV64x60_COMM_CONFIG 0xb40c | ||
790 | #define MV64x60_COMM_XBAR_TO 0xf304 | ||
791 | #define MV64x60_COMM_INTR_CAUSE 0xf310 | ||
792 | #define MV64x60_COMM_INTR_MASK 0xf314 | ||
793 | #define MV64x60_COMM_ERR_ADDR 0xf318 | ||
794 | |||
795 | #define MV64360_COMM_ARBITER_CNTL 0xf300 | ||
796 | |||
797 | /* | ||
798 | ***************************************************************************** | ||
799 | * | ||
800 | * IDMA Controller Interface Registers | ||
801 | * | ||
802 | ***************************************************************************** | ||
803 | */ | ||
804 | |||
805 | /* IDMA Controller Window Registers (8 windows) */ | ||
806 | #define MV64360_IDMA2MEM_WINDOWS 8 | ||
807 | |||
808 | #define MV64360_IDMA2MEM_0_BASE 0x0a00 | ||
809 | #define MV64360_IDMA2MEM_0_SIZE 0x0a04 | ||
810 | #define MV64360_IDMA2MEM_1_BASE 0x0a08 | ||
811 | #define MV64360_IDMA2MEM_1_SIZE 0x0a0c | ||
812 | #define MV64360_IDMA2MEM_2_BASE 0x0a10 | ||
813 | #define MV64360_IDMA2MEM_2_SIZE 0x0a14 | ||
814 | #define MV64360_IDMA2MEM_3_BASE 0x0a18 | ||
815 | #define MV64360_IDMA2MEM_3_SIZE 0x0a1c | ||
816 | #define MV64360_IDMA2MEM_4_BASE 0x0a20 | ||
817 | #define MV64360_IDMA2MEM_4_SIZE 0x0a24 | ||
818 | #define MV64360_IDMA2MEM_5_BASE 0x0a28 | ||
819 | #define MV64360_IDMA2MEM_5_SIZE 0x0a2c | ||
820 | #define MV64360_IDMA2MEM_6_BASE 0x0a30 | ||
821 | #define MV64360_IDMA2MEM_6_SIZE 0x0a34 | ||
822 | #define MV64360_IDMA2MEM_7_BASE 0x0a38 | ||
823 | #define MV64360_IDMA2MEM_7_SIZE 0x0a3c | ||
824 | |||
825 | #define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000 | ||
826 | #define MV64360_IDMA2MEM_SNOOP_WT 0x00001000 | ||
827 | #define MV64360_IDMA2MEM_SNOOP_WB 0x00002000 | ||
828 | |||
829 | #define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80 | ||
830 | |||
831 | #define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70 | ||
832 | #define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74 | ||
833 | #define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78 | ||
834 | #define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c | ||
835 | |||
836 | #define MV64x60_IDMA_0_OFFSET 0x0800 | ||
837 | #define MV64x60_IDMA_1_OFFSET 0x0804 | ||
838 | #define MV64x60_IDMA_2_OFFSET 0x0808 | ||
839 | #define MV64x60_IDMA_3_OFFSET 0x080c | ||
840 | #define MV64x60_IDMA_4_OFFSET 0x0900 | ||
841 | #define MV64x60_IDMA_5_OFFSET 0x0904 | ||
842 | #define MV64x60_IDMA_6_OFFSET 0x0908 | ||
843 | #define MV64x60_IDMA_7_OFFSET 0x090c | ||
844 | |||
845 | #define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET) | ||
846 | #define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET) | ||
847 | #define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET) | ||
848 | #define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET) | ||
849 | #define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET) | ||
850 | #define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET) | ||
851 | #define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET) | ||
852 | #define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET) | ||
853 | #define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET) | ||
854 | #define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET) | ||
855 | |||
856 | #define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860 | ||
857 | #define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960 | ||
858 | |||
859 | #define MV64x60_IDMA_0_3_XBAR_TO 0x08d0 | ||
860 | #define MV64x60_IDMA_4_7_XBAR_TO 0x09d0 | ||
861 | |||
862 | #define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0 | ||
863 | #define MV64x60_IDMA_0_3_INTR_MASK 0x08c4 | ||
864 | #define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8 | ||
865 | #define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc | ||
866 | #define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0 | ||
867 | #define MV64x60_IDMA_4_7_INTR_MASK 0x09c4 | ||
868 | #define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8 | ||
869 | #define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc | ||
870 | |||
871 | /* | ||
872 | ***************************************************************************** | ||
873 | * | ||
874 | * Watchdog Timer Interface Registers | ||
875 | * | ||
876 | ***************************************************************************** | ||
877 | */ | ||
878 | |||
879 | #define MV64x60_WDT_WDC 0xb410 | ||
880 | #define MV64x60_WDT_WDV 0xb414 | ||
881 | |||
882 | |||
883 | /* | ||
884 | ***************************************************************************** | ||
885 | * | ||
886 | * General Purpose Pins Controller Interface Registers | ||
887 | * | ||
888 | ***************************************************************************** | ||
889 | */ | ||
890 | |||
891 | #define MV64x60_GPP_IO_CNTL 0xf100 | ||
892 | #define MV64x60_GPP_LEVEL_CNTL 0xf110 | ||
893 | #define MV64x60_GPP_VALUE 0xf104 | ||
894 | #define MV64x60_GPP_INTR_CAUSE 0xf108 | ||
895 | #define MV64x60_GPP_INTR_MASK 0xf10c | ||
896 | #define MV64x60_GPP_VALUE_SET 0xf118 | ||
897 | #define MV64x60_GPP_VALUE_CLR 0xf11c | ||
898 | |||
899 | |||
900 | /* | ||
901 | ***************************************************************************** | ||
902 | * | ||
903 | * Multi-Purpose Pins Controller Interface Registers | ||
904 | * | ||
905 | ***************************************************************************** | ||
906 | */ | ||
907 | |||
908 | #define MV64x60_MPP_CNTL_0 0xf000 | ||
909 | #define MV64x60_MPP_CNTL_1 0xf004 | ||
910 | #define MV64x60_MPP_CNTL_2 0xf008 | ||
911 | #define MV64x60_MPP_CNTL_3 0xf00c | ||
912 | #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 | ||
913 | |||
914 | #define MV64x60_ETH_BAR_GAP 0x8 | ||
915 | #define MV64x60_ETH_SIZE_REG_GAP 0x8 | ||
916 | #define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 | ||
917 | #define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4 | ||
918 | |||
919 | #define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00 | ||
920 | #define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00 | ||
921 | #define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00 | ||
922 | #define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700 | ||
923 | |||
924 | #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 | ||
925 | #define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 | ||
926 | #define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000 | ||
927 | #define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800 | ||
928 | |||
929 | |||
930 | /* | ||
931 | ***************************************************************************** | ||
932 | * | ||
933 | * Interrupt Controller Interface Registers | ||
934 | * | ||
935 | ***************************************************************************** | ||
936 | */ | ||
937 | |||
938 | #define GT64260_IC_OFFSET 0x0c18 | ||
939 | |||
940 | #define GT64260_IC_MAIN_CAUSE_LO 0x0c18 | ||
941 | #define GT64260_IC_MAIN_CAUSE_HI 0x0c68 | ||
942 | #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c | ||
943 | #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c | ||
944 | #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 | ||
945 | #define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24 | ||
946 | #define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64 | ||
947 | #define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74 | ||
948 | #define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4 | ||
949 | #define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4 | ||
950 | #define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4 | ||
951 | #define GT64260_IC_CPU_INT_0_MASK 0x0e60 | ||
952 | #define GT64260_IC_CPU_INT_1_MASK 0x0e64 | ||
953 | #define GT64260_IC_CPU_INT_2_MASK 0x0e68 | ||
954 | #define GT64260_IC_CPU_INT_3_MASK 0x0e6c | ||
955 | |||
956 | #define MV64360_IC_OFFSET 0x0000 | ||
957 | |||
958 | #define MV64360_IC_MAIN_CAUSE_LO 0x0004 | ||
959 | #define MV64360_IC_MAIN_CAUSE_HI 0x000c | ||
960 | #define MV64360_IC_CPU0_INTR_MASK_LO 0x0014 | ||
961 | #define MV64360_IC_CPU0_INTR_MASK_HI 0x001c | ||
962 | #define MV64360_IC_CPU0_SELECT_CAUSE 0x0024 | ||
963 | #define MV64360_IC_CPU1_INTR_MASK_LO 0x0034 | ||
964 | #define MV64360_IC_CPU1_INTR_MASK_HI 0x003c | ||
965 | #define MV64360_IC_CPU1_SELECT_CAUSE 0x0044 | ||
966 | #define MV64360_IC_INT0_MASK_LO 0x0054 | ||
967 | #define MV64360_IC_INT0_MASK_HI 0x005c | ||
968 | #define MV64360_IC_INT0_SELECT_CAUSE 0x0064 | ||
969 | #define MV64360_IC_INT1_MASK_LO 0x0074 | ||
970 | #define MV64360_IC_INT1_MASK_HI 0x007c | ||
971 | #define MV64360_IC_INT1_SELECT_CAUSE 0x0084 | ||
972 | |||
973 | #endif /* __ASMPPC_MV64x60_DEFS_H */ | ||
diff --git a/include/asm-ppc/namei.h b/include/asm-ppc/namei.h new file mode 100644 index 000000000000..29c9ec832133 --- /dev/null +++ b/include/asm-ppc/namei.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/namei.h | ||
3 | * Adapted from include/asm-alpha/namei.h | ||
4 | * | ||
5 | * Included from fs/namei.c | ||
6 | */ | ||
7 | |||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef __PPC_NAMEI_H | ||
10 | #define __PPC_NAMEI_H | ||
11 | |||
12 | /* This dummy routine maybe changed to something useful | ||
13 | * for /usr/gnemul/ emulation stuff. | ||
14 | * Look at asm-sparc/namei.h for details. | ||
15 | */ | ||
16 | |||
17 | #define __emul_prefix() NULL | ||
18 | |||
19 | #endif /* __PPC_NAMEI_H */ | ||
20 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/nvram.h b/include/asm-ppc/nvram.h new file mode 100644 index 000000000000..31ef16e3fc4f --- /dev/null +++ b/include/asm-ppc/nvram.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * PreP compliant NVRAM access | ||
3 | */ | ||
4 | |||
5 | #ifdef __KERNEL__ | ||
6 | #ifndef _PPC_NVRAM_H | ||
7 | #define _PPC_NVRAM_H | ||
8 | |||
9 | #define NVRAM_AS0 0x74 | ||
10 | #define NVRAM_AS1 0x75 | ||
11 | #define NVRAM_DATA 0x77 | ||
12 | |||
13 | |||
14 | /* RTC Offsets */ | ||
15 | |||
16 | #define MOTO_RTC_SECONDS 0x1FF9 | ||
17 | #define MOTO_RTC_MINUTES 0x1FFA | ||
18 | #define MOTO_RTC_HOURS 0x1FFB | ||
19 | #define MOTO_RTC_DAY_OF_WEEK 0x1FFC | ||
20 | #define MOTO_RTC_DAY_OF_MONTH 0x1FFD | ||
21 | #define MOTO_RTC_MONTH 0x1FFE | ||
22 | #define MOTO_RTC_YEAR 0x1FFF | ||
23 | #define MOTO_RTC_CONTROLA 0x1FF8 | ||
24 | #define MOTO_RTC_CONTROLB 0x1FF9 | ||
25 | |||
26 | /* PowerMac specific nvram stuffs */ | ||
27 | |||
28 | enum { | ||
29 | pmac_nvram_OF, /* Open Firmware partition */ | ||
30 | pmac_nvram_XPRAM, /* MacOS XPRAM partition */ | ||
31 | pmac_nvram_NR /* MacOS Name Registry partition */ | ||
32 | }; | ||
33 | |||
34 | /* Return partition offset in nvram */ | ||
35 | extern int pmac_get_partition(int partition); | ||
36 | |||
37 | /* Direct access to XPRAM on PowerMacs */ | ||
38 | extern u8 pmac_xpram_read(int xpaddr); | ||
39 | extern void pmac_xpram_write(int xpaddr, u8 data); | ||
40 | |||
41 | /* Synchronize NVRAM */ | ||
42 | extern void nvram_sync(void); | ||
43 | |||
44 | /* Normal access to NVRAM */ | ||
45 | extern unsigned char nvram_read_byte(int i); | ||
46 | extern void nvram_write_byte(unsigned char c, int i); | ||
47 | |||
48 | /* Some offsets in XPRAM */ | ||
49 | #define PMAC_XPRAM_MACHINE_LOC 0xe4 | ||
50 | #define PMAC_XPRAM_SOUND_VOLUME 0x08 | ||
51 | |||
52 | /* Machine location structure in PowerMac XPRAM */ | ||
53 | struct pmac_machine_location { | ||
54 | unsigned int latitude; /* 2+30 bit Fractional number */ | ||
55 | unsigned int longitude; /* 2+30 bit Fractional number */ | ||
56 | unsigned int delta; /* mix of GMT delta and DLS */ | ||
57 | }; | ||
58 | |||
59 | /* | ||
60 | * /dev/nvram ioctls | ||
61 | * | ||
62 | * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is | ||
63 | * definitely obsolete. Do not use it if you can avoid it | ||
64 | */ | ||
65 | |||
66 | #define OBSOLETE_PMAC_NVRAM_GET_OFFSET \ | ||
67 | _IOWR('p', 0x40, int) | ||
68 | |||
69 | #define IOC_NVRAM_GET_OFFSET _IOWR('p', 0x42, int) /* Get NVRAM partition offset */ | ||
70 | #define IOC_NVRAM_SYNC _IO('p', 0x43) /* Sync NVRAM image */ | ||
71 | |||
72 | #endif | ||
73 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h new file mode 100644 index 000000000000..5ea44cabfaa4 --- /dev/null +++ b/include/asm-ppc/ocp.h | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * ocp.h | ||
3 | * | ||
4 | * (c) Benjamin Herrenschmidt (benh@kernel.crashing.org) | ||
5 | * Mipsys - France | ||
6 | * | ||
7 | * Derived from work (c) Armin Kuster akuster@pacbell.net | ||
8 | * | ||
9 | * Additional support and port to 2.6 LDM/sysfs by | ||
10 | * Matt Porter <mporter@kernel.crashing.org> | ||
11 | * Copyright 2003-2004 MontaVista Software, Inc. | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify it | ||
14 | * under the terms of the GNU General Public License as published by the | ||
15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
16 | * option) any later version. | ||
17 | * | ||
18 | * TODO: - Add get/put interface & fixup locking to provide same API for | ||
19 | * 2.4 and 2.5 | ||
20 | * - Rework PM callbacks | ||
21 | */ | ||
22 | |||
23 | #ifdef __KERNEL__ | ||
24 | #ifndef __OCP_H__ | ||
25 | #define __OCP_H__ | ||
26 | |||
27 | #include <linux/init.h> | ||
28 | #include <linux/list.h> | ||
29 | #include <linux/config.h> | ||
30 | #include <linux/devfs_fs_kernel.h> | ||
31 | #include <linux/device.h> | ||
32 | |||
33 | #include <asm/mmu.h> | ||
34 | #include <asm/ocp_ids.h> | ||
35 | #include <asm/rwsem.h> | ||
36 | #include <asm/semaphore.h> | ||
37 | |||
38 | #ifdef CONFIG_PPC_OCP | ||
39 | |||
40 | #define OCP_MAX_IRQS 7 | ||
41 | #define MAX_EMACS 4 | ||
42 | #define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */ | ||
43 | #define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */ | ||
44 | #define OCP_NULL_TYPE -1 /* used to mark end of list */ | ||
45 | #define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */ | ||
46 | #define OCP_PADDR_NA 0 /* No MMIO registers */ | ||
47 | |||
48 | #define OCP_ANY_ID (~0) | ||
49 | #define OCP_ANY_INDEX -1 | ||
50 | |||
51 | extern struct list_head ocp_devices; | ||
52 | extern struct rw_semaphore ocp_devices_sem; | ||
53 | |||
54 | struct ocp_device_id { | ||
55 | unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */ | ||
56 | unsigned long driver_data; /* Data private to the driver */ | ||
57 | }; | ||
58 | |||
59 | |||
60 | /* | ||
61 | * Static definition of an OCP device. | ||
62 | * | ||
63 | * @vendor: Vendor code. It is _STRONGLY_ discouraged to use | ||
64 | * the vendor code as a way to match a unique device, | ||
65 | * though I kept that possibility open, you should | ||
66 | * really define different function codes for different | ||
67 | * device types | ||
68 | * @function: This is the function code for this device. | ||
69 | * @index: This index is used for mapping the Nth function of a | ||
70 | * given core. This is typically used for cross-driver | ||
71 | * matching, like looking for a given MAL or ZMII from | ||
72 | * an EMAC or for getting to the proper set of DCRs. | ||
73 | * Indices are no longer magically calculated based on | ||
74 | * structure ordering, they have to be actually coded | ||
75 | * into the ocp_def to avoid any possible confusion | ||
76 | * I _STRONGLY_ (again ? wow !) encourage anybody relying | ||
77 | * on index mapping to encode the "target" index in an | ||
78 | * associated structure pointed to by "additions", see | ||
79 | * how it's done for the EMAC driver. | ||
80 | * @paddr: Device physical address (may not mean anything...) | ||
81 | * @irq: Interrupt line for this device (TODO: think about making | ||
82 | * an array with this) | ||
83 | * @pm: Currently, contains the bitmask in CPMFR DCR for the device | ||
84 | * @additions: Optionally points to a function specific structure | ||
85 | * providing additional informations for a given device | ||
86 | * instance. It's currently used by the EMAC driver for MAL | ||
87 | * channel & ZMII port mapping among others. | ||
88 | * @show: Optionally points to a function specific structure | ||
89 | * providing a sysfs show routine for additions fields. | ||
90 | */ | ||
91 | struct ocp_def { | ||
92 | unsigned int vendor; | ||
93 | unsigned int function; | ||
94 | int index; | ||
95 | phys_addr_t paddr; | ||
96 | int irq; | ||
97 | unsigned long pm; | ||
98 | void *additions; | ||
99 | void (*show)(struct device *); | ||
100 | }; | ||
101 | |||
102 | |||
103 | /* Struct for a given device instance */ | ||
104 | struct ocp_device { | ||
105 | struct list_head link; | ||
106 | char name[80]; /* device name */ | ||
107 | struct ocp_def *def; /* device definition */ | ||
108 | void *drvdata; /* driver data for this device */ | ||
109 | struct ocp_driver *driver; | ||
110 | u32 current_state; /* Current operating state. In ACPI-speak, | ||
111 | this is D0-D3, D0 being fully functional, | ||
112 | and D3 being off. */ | ||
113 | struct device dev; | ||
114 | }; | ||
115 | |||
116 | struct ocp_driver { | ||
117 | struct list_head node; | ||
118 | char *name; | ||
119 | const struct ocp_device_id *id_table; /* NULL if wants all devices */ | ||
120 | int (*probe) (struct ocp_device *dev); /* New device inserted */ | ||
121 | void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | ||
122 | int (*suspend) (struct ocp_device *dev, u32 state); /* Device suspended */ | ||
123 | int (*resume) (struct ocp_device *dev); /* Device woken up */ | ||
124 | struct device_driver driver; | ||
125 | }; | ||
126 | |||
127 | #define to_ocp_dev(n) container_of(n, struct ocp_device, dev) | ||
128 | #define to_ocp_drv(n) container_of(n, struct ocp_driver, driver) | ||
129 | |||
130 | /* Similar to the helpers above, these manipulate per-ocp_dev | ||
131 | * driver-specific data. Currently stored as ocp_dev::ocpdev, | ||
132 | * a void pointer, but it is not present on older kernels. | ||
133 | */ | ||
134 | static inline void * | ||
135 | ocp_get_drvdata(struct ocp_device *pdev) | ||
136 | { | ||
137 | return pdev->drvdata; | ||
138 | } | ||
139 | |||
140 | static inline void | ||
141 | ocp_set_drvdata(struct ocp_device *pdev, void *data) | ||
142 | { | ||
143 | pdev->drvdata = data; | ||
144 | } | ||
145 | |||
146 | #if defined (CONFIG_PM) | ||
147 | /* | ||
148 | * This is right for the IBM 405 and 440 but will need to be | ||
149 | * generalized if the OCP stuff gets used on other processors. | ||
150 | */ | ||
151 | static inline void | ||
152 | ocp_force_power_off(struct ocp_device *odev) | ||
153 | { | ||
154 | mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); | ||
155 | } | ||
156 | |||
157 | static inline void | ||
158 | ocp_force_power_on(struct ocp_device *odev) | ||
159 | { | ||
160 | mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); | ||
161 | } | ||
162 | #else | ||
163 | #define ocp_force_power_off(x) (void)(x) | ||
164 | #define ocp_force_power_on(x) (void)(x) | ||
165 | #endif | ||
166 | |||
167 | /* Register/Unregister an OCP driver */ | ||
168 | extern int ocp_register_driver(struct ocp_driver *drv); | ||
169 | extern void ocp_unregister_driver(struct ocp_driver *drv); | ||
170 | |||
171 | /* Build list of devices */ | ||
172 | extern int ocp_early_init(void) __init; | ||
173 | |||
174 | /* Find a device by index */ | ||
175 | extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index); | ||
176 | |||
177 | /* Get a def by index */ | ||
178 | extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index); | ||
179 | |||
180 | /* Add a device by index */ | ||
181 | extern int ocp_add_one_device(struct ocp_def *def); | ||
182 | |||
183 | /* Remove a device by index */ | ||
184 | extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index); | ||
185 | |||
186 | /* Iterate over devices and execute a routine */ | ||
187 | extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg); | ||
188 | |||
189 | /* Sysfs support */ | ||
190 | #define OCP_SYSFS_ADDTL(type, format, name, field) \ | ||
191 | static ssize_t \ | ||
192 | show_##name##_##field(struct device *dev, char *buf) \ | ||
193 | { \ | ||
194 | struct ocp_device *odev = to_ocp_dev(dev); \ | ||
195 | type *add = odev->def->additions; \ | ||
196 | \ | ||
197 | return sprintf(buf, format, add->field); \ | ||
198 | } \ | ||
199 | static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL); | ||
200 | |||
201 | #ifdef CONFIG_IBM_OCP | ||
202 | #include <asm/ibm_ocp.h> | ||
203 | #endif | ||
204 | |||
205 | #ifdef CONFIG_FSL_OCP | ||
206 | #include <asm/fsl_ocp.h> | ||
207 | #endif | ||
208 | |||
209 | #endif /* CONFIG_PPC_OCP */ | ||
210 | #endif /* __OCP_H__ */ | ||
211 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h new file mode 100644 index 000000000000..8ae4b311a37c --- /dev/null +++ b/include/asm-ppc/ocp_ids.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * ocp_ids.h | ||
3 | * | ||
4 | * OCP device ids based on the ideas from PCI | ||
5 | * | ||
6 | * The numbers below are almost completely arbitrary, and in fact | ||
7 | * strings might work better. -- paulus | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * Vender device | ||
17 | * [xxxx] [xxxx] | ||
18 | * | ||
19 | * Keep in order, please | ||
20 | */ | ||
21 | |||
22 | /* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */ | ||
23 | |||
24 | #define OCP_VENDOR_INVALID 0x0000 | ||
25 | #define OCP_VENDOR_ARM 0x0004 | ||
26 | #define OCP_VENDOR_FREESCALE 0x1057 | ||
27 | #define OCP_VENDOR_IBM 0x1014 | ||
28 | #define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE | ||
29 | #define OCP_VENDOR_XILINX 0x10ee | ||
30 | #define OCP_VENDOR_UNKNOWN 0xFFFF | ||
31 | |||
32 | /* device identification */ | ||
33 | |||
34 | /* define type */ | ||
35 | #define OCP_FUNC_INVALID 0x0000 | ||
36 | |||
37 | /* system 0x0001 - 0x001F */ | ||
38 | |||
39 | /* Timers 0x0020 - 0x002F */ | ||
40 | |||
41 | /* Serial 0x0030 - 0x006F*/ | ||
42 | #define OCP_FUNC_16550 0x0031 | ||
43 | #define OCP_FUNC_IIC 0x0032 | ||
44 | #define OCP_FUNC_USB 0x0033 | ||
45 | #define OCP_FUNC_PSC_UART 0x0034 | ||
46 | |||
47 | /* Memory devices 0x0090 - 0x009F */ | ||
48 | #define OCP_FUNC_MAL 0x0090 | ||
49 | #define OCP_FUNC_DMA 0x0091 | ||
50 | |||
51 | /* Display 0x00A0 - 0x00AF */ | ||
52 | |||
53 | /* Sound 0x00B0 - 0x00BF */ | ||
54 | |||
55 | /* Mass Storage 0x00C0 - 0xxCF */ | ||
56 | #define OCP_FUNC_IDE 0x00C0 | ||
57 | |||
58 | /* Misc 0x00D0 - 0x00DF*/ | ||
59 | #define OCP_FUNC_GPIO 0x00D0 | ||
60 | #define OCP_FUNC_ZMII 0x00D1 | ||
61 | #define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */ | ||
62 | #define OCP_FUNC_RGMII 0x00D3 | ||
63 | #define OCP_FUNC_TAH 0x00D4 | ||
64 | #define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */ | ||
65 | |||
66 | /* Network 0x0200 - 0x02FF */ | ||
67 | #define OCP_FUNC_EMAC 0x0200 | ||
68 | #define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */ | ||
69 | |||
70 | /* Bridge devices 0xE00 - 0xEFF */ | ||
71 | #define OCP_FUNC_OPB 0x0E00 | ||
72 | |||
73 | #define OCP_FUNC_UNKNOWN 0xFFFF | ||
diff --git a/include/asm-ppc/of_device.h b/include/asm-ppc/of_device.h new file mode 100644 index 000000000000..14441c629010 --- /dev/null +++ b/include/asm-ppc/of_device.h | |||
@@ -0,0 +1,74 @@ | |||
1 | #ifndef __OF_DEVICE_H__ | ||
2 | #define __OF_DEVICE_H__ | ||
3 | |||
4 | #include <linux/device.h> | ||
5 | #include <asm/prom.h> | ||
6 | |||
7 | /* | ||
8 | * The of_platform_bus_type is a bus type used by drivers that do not | ||
9 | * attach to a macio or similar bus but still use OF probing | ||
10 | * mecanism | ||
11 | */ | ||
12 | extern struct bus_type of_platform_bus_type; | ||
13 | |||
14 | /* | ||
15 | * The of_device is a kind of "base class" that is a superset of | ||
16 | * struct device for use by devices attached to an OF node and | ||
17 | * probed using OF properties | ||
18 | */ | ||
19 | struct of_device | ||
20 | { | ||
21 | struct device_node *node; /* OF device node */ | ||
22 | u64 dma_mask; /* DMA mask */ | ||
23 | struct device dev; /* Generic device interface */ | ||
24 | }; | ||
25 | #define to_of_device(d) container_of(d, struct of_device, dev) | ||
26 | |||
27 | /* | ||
28 | * Struct used for matching a device | ||
29 | */ | ||
30 | struct of_match | ||
31 | { | ||
32 | char *name; | ||
33 | char *type; | ||
34 | char *compatible; | ||
35 | void *data; | ||
36 | }; | ||
37 | #define OF_ANY_MATCH ((char *)-1L) | ||
38 | |||
39 | extern const struct of_match *of_match_device( | ||
40 | const struct of_match *matches, const struct of_device *dev); | ||
41 | |||
42 | extern struct of_device *of_dev_get(struct of_device *dev); | ||
43 | extern void of_dev_put(struct of_device *dev); | ||
44 | |||
45 | /* | ||
46 | * An of_platform_driver driver is attached to a basic of_device on | ||
47 | * the "platform bus" (of_platform_bus_type) | ||
48 | */ | ||
49 | struct of_platform_driver | ||
50 | { | ||
51 | char *name; | ||
52 | struct of_match *match_table; | ||
53 | struct module *owner; | ||
54 | |||
55 | int (*probe)(struct of_device* dev, const struct of_match *match); | ||
56 | int (*remove)(struct of_device* dev); | ||
57 | |||
58 | int (*suspend)(struct of_device* dev, u32 state); | ||
59 | int (*resume)(struct of_device* dev); | ||
60 | int (*shutdown)(struct of_device* dev); | ||
61 | |||
62 | struct device_driver driver; | ||
63 | }; | ||
64 | #define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver) | ||
65 | |||
66 | extern int of_register_driver(struct of_platform_driver *drv); | ||
67 | extern void of_unregister_driver(struct of_platform_driver *drv); | ||
68 | extern int of_device_register(struct of_device *ofdev); | ||
69 | extern void of_device_unregister(struct of_device *ofdev); | ||
70 | extern struct of_device *of_platform_device_create(struct device_node *np, const char *bus_id); | ||
71 | extern void of_release_dev(struct device *dev); | ||
72 | |||
73 | #endif /* __OF_DEVICE_H__ */ | ||
74 | |||
diff --git a/include/asm-ppc/ohare.h b/include/asm-ppc/ohare.h new file mode 100644 index 000000000000..023b59772231 --- /dev/null +++ b/include/asm-ppc/ohare.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* | ||
2 | * ohare.h: definitions for using the "O'Hare" I/O controller chip. | ||
3 | * | ||
4 | * Copyright (C) 1997 Paul Mackerras. | ||
5 | * | ||
6 | * BenH: Changed to match those of heathrow (but not all of them). Please | ||
7 | * check if I didn't break anything (especially the media bay). | ||
8 | */ | ||
9 | |||
10 | /* offset from ohare base for feature control register */ | ||
11 | #define OHARE_MBCR 0x34 | ||
12 | #define OHARE_FCR 0x38 | ||
13 | |||
14 | /* | ||
15 | * Bits in feature control register. | ||
16 | * These were mostly derived by experiment on a powerbook 3400 | ||
17 | * and may differ for other machines. | ||
18 | */ | ||
19 | #define OH_SCC_RESET 1 | ||
20 | #define OH_BAY_POWER_N 2 /* a guess */ | ||
21 | #define OH_BAY_PCI_ENABLE 4 /* a guess */ | ||
22 | #define OH_BAY_IDE_ENABLE 8 | ||
23 | #define OH_BAY_FLOPPY_ENABLE 0x10 | ||
24 | #define OH_IDE0_ENABLE 0x20 | ||
25 | #define OH_IDE0_RESET_N 0x40 /* a guess */ | ||
26 | #define OH_BAY_DEV_MASK 0x1c | ||
27 | #define OH_BAY_RESET_N 0x80 | ||
28 | #define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */ | ||
29 | #define OH_SCC_ENABLE 0x200 | ||
30 | #define OH_MESH_ENABLE 0x400 | ||
31 | #define OH_FLOPPY_ENABLE 0x800 | ||
32 | #define OH_SCCA_IO 0x4000 | ||
33 | #define OH_SCCB_IO 0x8000 | ||
34 | #define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */ | ||
35 | #define OH_IDE1_RESET_N 0x800000 | ||
36 | |||
37 | /* | ||
38 | * Bits to set in the feature control register on PowerBooks. | ||
39 | */ | ||
40 | #define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \ | ||
41 | OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO) | ||
42 | |||
43 | /* | ||
44 | * A magic value to put into the feature control register of the | ||
45 | * "ohare" I/O controller on Starmaxes to enable the IDE CD interface. | ||
46 | * Contributed by Harry Eaton. | ||
47 | */ | ||
48 | #define STARMAX_FEATURES 0xbeff7a | ||
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h new file mode 100644 index 000000000000..58545e4cdbc0 --- /dev/null +++ b/include/asm-ppc/open_pic.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling | ||
3 | * | ||
4 | * Copyright (C) 1997 Geert Uytterhoeven | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file COPYING in the main directory of this archive | ||
8 | * for more details. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef _PPC_KERNEL_OPEN_PIC_H | ||
13 | #define _PPC_KERNEL_OPEN_PIC_H | ||
14 | |||
15 | #include <linux/config.h> | ||
16 | #include <linux/irq.h> | ||
17 | |||
18 | #define OPENPIC_SIZE 0x40000 | ||
19 | |||
20 | /* | ||
21 | * Non-offset'ed vector numbers | ||
22 | */ | ||
23 | |||
24 | #define OPENPIC_VEC_TIMER 110 /* and up */ | ||
25 | #define OPENPIC_VEC_IPI 118 /* and up */ | ||
26 | #define OPENPIC_VEC_SPURIOUS 255 | ||
27 | |||
28 | /* OpenPIC IRQ controller structure */ | ||
29 | extern struct hw_interrupt_type open_pic; | ||
30 | |||
31 | /* OpenPIC IPI controller structure */ | ||
32 | #ifdef CONFIG_SMP | ||
33 | extern struct hw_interrupt_type open_pic_ipi; | ||
34 | #endif /* CONFIG_SMP */ | ||
35 | |||
36 | extern u_int OpenPIC_NumInitSenses; | ||
37 | extern u_char *OpenPIC_InitSenses; | ||
38 | extern void __iomem * OpenPIC_Addr; | ||
39 | extern int epic_serial_mode; | ||
40 | |||
41 | /* Exported functions */ | ||
42 | extern void openpic_set_sources(int first_irq, int num_irqs, void __iomem *isr); | ||
43 | extern void openpic_init(int linux_irq_offset); | ||
44 | extern void openpic_init_nmi_irq(u_int irq); | ||
45 | extern void openpic_hookup_cascade(u_int irq, char *name, | ||
46 | int (*cascade_fn)(struct pt_regs *)); | ||
47 | extern u_int openpic_irq(void); | ||
48 | extern void openpic_eoi(void); | ||
49 | extern void openpic_request_IPIs(void); | ||
50 | extern void do_openpic_setup_cpu(void); | ||
51 | extern int openpic_get_irq(struct pt_regs *regs); | ||
52 | extern void openpic_reset_processor_phys(u_int cpumask); | ||
53 | extern void openpic_setup_ISU(int isu_num, unsigned long addr); | ||
54 | extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); | ||
55 | extern void smp_openpic_message_pass(int target, int msg, unsigned long data, | ||
56 | int wait); | ||
57 | extern void openpic_set_k2_cascade(int irq); | ||
58 | extern void openpic_set_priority(u_int pri); | ||
59 | |||
60 | extern inline int openpic_to_irq(int irq) | ||
61 | { | ||
62 | /* IRQ 0 usually means 'disabled'.. don't mess with it | ||
63 | * exceptions to this (sandpoint maybe?) | ||
64 | * shouldn't use openpic_to_irq | ||
65 | */ | ||
66 | if (irq != 0){ | ||
67 | return irq += NUM_8259_INTERRUPTS; | ||
68 | } else { | ||
69 | return 0; | ||
70 | } | ||
71 | } | ||
72 | /* Support for second openpic on G5 macs */ | ||
73 | |||
74 | // FIXME: To be replaced by sane cascaded controller management */ | ||
75 | |||
76 | #define PMAC_OPENPIC2_OFFSET 128 | ||
77 | |||
78 | #define OPENPIC2_VEC_TIMER 110 /* and up */ | ||
79 | #define OPENPIC2_VEC_IPI 118 /* and up */ | ||
80 | #define OPENPIC2_VEC_SPURIOUS 127 | ||
81 | |||
82 | |||
83 | extern void* OpenPIC2_Addr; | ||
84 | |||
85 | /* Exported functions */ | ||
86 | extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr); | ||
87 | extern void openpic2_init(int linux_irq_offset); | ||
88 | extern void openpic2_init_nmi_irq(u_int irq); | ||
89 | extern u_int openpic2_irq(void); | ||
90 | extern void openpic2_eoi(void); | ||
91 | extern int openpic2_get_irq(struct pt_regs *regs); | ||
92 | extern void openpic2_setup_ISU(int isu_num, unsigned long addr); | ||
93 | #endif /* _PPC_KERNEL_OPEN_PIC_H */ | ||
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h new file mode 100644 index 000000000000..4789dc024240 --- /dev/null +++ b/include/asm-ppc/page.h | |||
@@ -0,0 +1,169 @@ | |||
1 | #ifndef _PPC_PAGE_H | ||
2 | #define _PPC_PAGE_H | ||
3 | |||
4 | /* PAGE_SHIFT determines the page size */ | ||
5 | #define PAGE_SHIFT 12 | ||
6 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
7 | |||
8 | /* | ||
9 | * Subtle: this is an int (not an unsigned long) and so it | ||
10 | * gets extended to 64 bits the way want (i.e. with 1s). -- paulus | ||
11 | */ | ||
12 | #define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) | ||
13 | |||
14 | #ifdef __KERNEL__ | ||
15 | #include <linux/config.h> | ||
16 | |||
17 | /* This must match what is in arch/ppc/Makefile */ | ||
18 | #define PAGE_OFFSET CONFIG_KERNEL_START | ||
19 | #define KERNELBASE PAGE_OFFSET | ||
20 | |||
21 | #ifndef __ASSEMBLY__ | ||
22 | |||
23 | /* | ||
24 | * The basic type of a PTE - 64 bits for those CPUs with > 32 bit | ||
25 | * physical addressing. For now this just the IBM PPC440. | ||
26 | */ | ||
27 | #ifdef CONFIG_PTE_64BIT | ||
28 | typedef unsigned long long pte_basic_t; | ||
29 | #define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */ | ||
30 | #define PTE_FMT "%16Lx" | ||
31 | #else | ||
32 | typedef unsigned long pte_basic_t; | ||
33 | #define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */ | ||
34 | #define PTE_FMT "%.8lx" | ||
35 | #endif | ||
36 | |||
37 | #undef STRICT_MM_TYPECHECKS | ||
38 | |||
39 | #ifdef STRICT_MM_TYPECHECKS | ||
40 | /* | ||
41 | * These are used to make use of C type-checking.. | ||
42 | */ | ||
43 | typedef struct { pte_basic_t pte; } pte_t; | ||
44 | typedef struct { unsigned long pmd; } pmd_t; | ||
45 | typedef struct { unsigned long pgd; } pgd_t; | ||
46 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
47 | |||
48 | #define pte_val(x) ((x).pte) | ||
49 | #define pmd_val(x) ((x).pmd) | ||
50 | #define pgd_val(x) ((x).pgd) | ||
51 | #define pgprot_val(x) ((x).pgprot) | ||
52 | |||
53 | #define __pte(x) ((pte_t) { (x) } ) | ||
54 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
55 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
56 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
57 | |||
58 | #else | ||
59 | /* | ||
60 | * .. while these make it easier on the compiler | ||
61 | */ | ||
62 | typedef pte_basic_t pte_t; | ||
63 | typedef unsigned long pmd_t; | ||
64 | typedef unsigned long pgd_t; | ||
65 | typedef unsigned long pgprot_t; | ||
66 | |||
67 | #define pte_val(x) (x) | ||
68 | #define pmd_val(x) (x) | ||
69 | #define pgd_val(x) (x) | ||
70 | #define pgprot_val(x) (x) | ||
71 | |||
72 | #define __pte(x) (x) | ||
73 | #define __pmd(x) (x) | ||
74 | #define __pgd(x) (x) | ||
75 | #define __pgprot(x) (x) | ||
76 | |||
77 | #endif | ||
78 | |||
79 | |||
80 | /* align addr on a size boundary - adjust address up if needed -- Cort */ | ||
81 | #define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) | ||
82 | |||
83 | /* to align the pointer to the (next) page boundary */ | ||
84 | #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) | ||
85 | |||
86 | struct page; | ||
87 | extern void clear_pages(void *page, int order); | ||
88 | static inline void clear_page(void *page) { clear_pages(page, 0); } | ||
89 | extern void copy_page(void *to, void *from); | ||
90 | extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); | ||
91 | extern void copy_user_page(void *to, void *from, unsigned long vaddr, | ||
92 | struct page *pg); | ||
93 | |||
94 | #ifndef CONFIG_APUS | ||
95 | #define PPC_MEMSTART 0 | ||
96 | #define PPC_PGSTART 0 | ||
97 | #define PPC_MEMOFFSET PAGE_OFFSET | ||
98 | #else | ||
99 | extern unsigned long ppc_memstart; | ||
100 | extern unsigned long ppc_pgstart; | ||
101 | extern unsigned long ppc_memoffset; | ||
102 | #define PPC_MEMSTART ppc_memstart | ||
103 | #define PPC_PGSTART ppc_pgstart | ||
104 | #define PPC_MEMOFFSET ppc_memoffset | ||
105 | #endif | ||
106 | |||
107 | #if defined(CONFIG_APUS) && !defined(MODULE) | ||
108 | /* map phys->virtual and virtual->phys for RAM pages */ | ||
109 | static inline unsigned long ___pa(unsigned long v) | ||
110 | { | ||
111 | unsigned long p; | ||
112 | asm volatile ("1: addis %0, %1, %2;" | ||
113 | ".section \".vtop_fixup\",\"aw\";" | ||
114 | ".align 1;" | ||
115 | ".long 1b;" | ||
116 | ".previous;" | ||
117 | : "=r" (p) | ||
118 | : "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff)); | ||
119 | |||
120 | return p; | ||
121 | } | ||
122 | static inline void* ___va(unsigned long p) | ||
123 | { | ||
124 | unsigned long v; | ||
125 | asm volatile ("1: addis %0, %1, %2;" | ||
126 | ".section \".ptov_fixup\",\"aw\";" | ||
127 | ".align 1;" | ||
128 | ".long 1b;" | ||
129 | ".previous;" | ||
130 | : "=r" (v) | ||
131 | : "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff)); | ||
132 | |||
133 | return (void*) v; | ||
134 | } | ||
135 | #else | ||
136 | #define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) | ||
137 | #define ___va(paddr) ((paddr)+PPC_MEMOFFSET) | ||
138 | #endif | ||
139 | |||
140 | extern int page_is_ram(unsigned long pfn); | ||
141 | |||
142 | #define __pa(x) ___pa((unsigned long)(x)) | ||
143 | #define __va(x) ((void *)(___va((unsigned long)(x)))) | ||
144 | |||
145 | #define pfn_to_page(pfn) (mem_map + ((pfn) - PPC_PGSTART)) | ||
146 | #define page_to_pfn(page) ((unsigned long)((page) - mem_map) + PPC_PGSTART) | ||
147 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | ||
148 | #define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT) | ||
149 | |||
150 | #define pfn_valid(pfn) (((pfn) - PPC_PGSTART) < max_mapnr) | ||
151 | #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) | ||
152 | |||
153 | /* Pure 2^n version of get_order */ | ||
154 | extern __inline__ int get_order(unsigned long size) | ||
155 | { | ||
156 | int lz; | ||
157 | |||
158 | size = (size-1) >> PAGE_SHIFT; | ||
159 | asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); | ||
160 | return 32 - lz; | ||
161 | } | ||
162 | |||
163 | #endif /* __ASSEMBLY__ */ | ||
164 | |||
165 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
166 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
167 | |||
168 | #endif /* __KERNEL__ */ | ||
169 | #endif /* _PPC_PAGE_H */ | ||
diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h new file mode 100644 index 000000000000..b24a4e37196a --- /dev/null +++ b/include/asm-ppc/param.h | |||
@@ -0,0 +1,22 @@ | |||
1 | #ifndef _ASM_PPC_PARAM_H | ||
2 | #define _ASM_PPC_PARAM_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | #define HZ 1000 /* internal timer frequency */ | ||
6 | #define USER_HZ 100 /* for user interfaces in "ticks" */ | ||
7 | #define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ | ||
8 | #endif /* __KERNEL__ */ | ||
9 | |||
10 | #ifndef HZ | ||
11 | #define HZ 100 | ||
12 | #endif | ||
13 | |||
14 | #define EXEC_PAGESIZE 4096 | ||
15 | |||
16 | #ifndef NOGROUP | ||
17 | #define NOGROUP (-1) | ||
18 | #endif | ||
19 | |||
20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
21 | |||
22 | #endif | ||
diff --git a/include/asm-ppc/parport.h b/include/asm-ppc/parport.h new file mode 100644 index 000000000000..11f96d3de5b6 --- /dev/null +++ b/include/asm-ppc/parport.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * parport.h: platform-specific PC-style parport initialisation | ||
3 | * | ||
4 | * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> | ||
5 | * | ||
6 | * This file should only be included by drivers/parport/parport_pc.c. | ||
7 | */ | ||
8 | |||
9 | #ifndef _ASM_PPC_PARPORT_H | ||
10 | #define _ASM_PPC_PARPORT_H | ||
11 | |||
12 | static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); | ||
13 | static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) | ||
14 | { | ||
15 | return parport_pc_find_isa_ports (autoirq, autodma); | ||
16 | } | ||
17 | |||
18 | #endif /* !(_ASM_PPC_PARPORT_H) */ | ||
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h new file mode 100644 index 000000000000..fa9cbb67ce3e --- /dev/null +++ b/include/asm-ppc/pc_serial.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/pc_serial.h | ||
3 | * | ||
4 | * This is basically a copy of include/asm-i386/serial.h. | ||
5 | * It is used on platforms which have an ISA bus and thus are likely | ||
6 | * to have PC-style serial ports at the legacy I/O port addresses. | ||
7 | * It also includes the definitions for the fourport, accent, boca | ||
8 | * and hub6 multiport serial cards, although I have never heard of | ||
9 | * anyone using any of those on a PPC platform. -- paulus | ||
10 | */ | ||
11 | |||
12 | #include <linux/config.h> | ||
13 | |||
14 | /* | ||
15 | * This assumes you have a 1.8432 MHz clock for your UART. | ||
16 | * | ||
17 | * It'd be nice if someone built a serial card with a 24.576 MHz | ||
18 | * clock, since the 16550A is capable of handling a top speed of 1.5 | ||
19 | * megabits/second; but this requires the faster clock. | ||
20 | */ | ||
21 | #define BASE_BAUD ( 1843200 / 16 ) | ||
22 | |||
23 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
24 | #define RS_TABLE_SIZE 64 | ||
25 | #else | ||
26 | #define RS_TABLE_SIZE 4 | ||
27 | #endif | ||
28 | |||
29 | /* Standard COM flags (except for COM4, because of the 8514 problem) */ | ||
30 | #ifdef CONFIG_SERIAL_DETECT_IRQ | ||
31 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) | ||
32 | #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) | ||
33 | #else | ||
34 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
35 | #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF | ||
36 | #endif | ||
37 | |||
38 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
39 | #define FOURPORT_FLAGS ASYNC_FOURPORT | ||
40 | #define ACCENT_FLAGS 0 | ||
41 | #define BOCA_FLAGS 0 | ||
42 | #define HUB6_FLAGS 0 | ||
43 | #endif | ||
44 | |||
45 | /* | ||
46 | * The following define the access methods for the HUB6 card. All | ||
47 | * access is through two ports for all 24 possible chips. The card is | ||
48 | * selected through the high 2 bits, the port on that card with the | ||
49 | * "middle" 3 bits, and the register on that port with the bottom | ||
50 | * 3 bits. | ||
51 | * | ||
52 | * While the access port and interrupt is configurable, the default | ||
53 | * port locations are 0x302 for the port control register, and 0x303 | ||
54 | * for the data read/write register. Normally, the interrupt is at irq3 | ||
55 | * but can be anything from 3 to 7 inclusive. Note that using 3 will | ||
56 | * require disabling com2. | ||
57 | */ | ||
58 | |||
59 | #define C_P(card,port) (((card)<<6|(port)<<3) + 1) | ||
60 | |||
61 | #define STD_SERIAL_PORT_DEFNS \ | ||
62 | /* UART CLK PORT IRQ FLAGS */ \ | ||
63 | { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ | ||
64 | { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ | ||
65 | { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ | ||
66 | { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ | ||
67 | |||
68 | |||
69 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
70 | #define EXTRA_SERIAL_PORT_DEFNS \ | ||
71 | { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ | ||
72 | { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ | ||
73 | { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ | ||
74 | { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ | ||
75 | { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ | ||
76 | { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ | ||
77 | { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ | ||
78 | { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ | ||
79 | { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ | ||
80 | { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ | ||
81 | { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ | ||
82 | { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ | ||
83 | { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ | ||
84 | { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ | ||
85 | { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ | ||
86 | { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ | ||
87 | { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ | ||
88 | { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ | ||
89 | { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ | ||
90 | { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ | ||
91 | { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ | ||
92 | { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ | ||
93 | { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ | ||
94 | { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ | ||
95 | { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ | ||
96 | { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ | ||
97 | { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ | ||
98 | { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ | ||
99 | #else | ||
100 | #define EXTRA_SERIAL_PORT_DEFNS | ||
101 | #endif | ||
102 | |||
103 | /* You can have up to four HUB6's in the system, but I've only | ||
104 | * included two cards here for a total of twelve ports. | ||
105 | */ | ||
106 | #if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) | ||
107 | #define HUB6_SERIAL_PORT_DFNS \ | ||
108 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ | ||
109 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ | ||
110 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ | ||
111 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ | ||
112 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ | ||
113 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ | ||
114 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ | ||
115 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ | ||
116 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ | ||
117 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ | ||
118 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ | ||
119 | { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ | ||
120 | #else | ||
121 | #define HUB6_SERIAL_PORT_DFNS | ||
122 | #endif | ||
123 | |||
124 | #define SERIAL_PORT_DFNS \ | ||
125 | STD_SERIAL_PORT_DEFNS \ | ||
126 | EXTRA_SERIAL_PORT_DEFNS \ | ||
127 | HUB6_SERIAL_PORT_DFNS | ||
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h new file mode 100644 index 000000000000..78e9be619f14 --- /dev/null +++ b/include/asm-ppc/pci-bridge.h | |||
@@ -0,0 +1,136 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _ASM_PCI_BRIDGE_H | ||
3 | #define _ASM_PCI_BRIDGE_H | ||
4 | |||
5 | #include <linux/ioport.h> | ||
6 | #include <linux/pci.h> | ||
7 | |||
8 | struct device_node; | ||
9 | struct pci_controller; | ||
10 | |||
11 | /* | ||
12 | * pci_io_base returns the memory address at which you can access | ||
13 | * the I/O space for PCI bus number `bus' (or NULL on error). | ||
14 | */ | ||
15 | extern void *pci_bus_io_base(unsigned int bus); | ||
16 | extern unsigned long pci_bus_io_base_phys(unsigned int bus); | ||
17 | extern unsigned long pci_bus_mem_base_phys(unsigned int bus); | ||
18 | |||
19 | /* Allocate a new PCI host bridge structure */ | ||
20 | extern struct pci_controller* pcibios_alloc_controller(void); | ||
21 | |||
22 | /* Helper function for setting up resources */ | ||
23 | extern void pci_init_resource(struct resource *res, unsigned long start, | ||
24 | unsigned long end, int flags, char *name); | ||
25 | |||
26 | /* Get the PCI host controller for a bus */ | ||
27 | extern struct pci_controller* pci_bus_to_hose(int bus); | ||
28 | |||
29 | /* Get the PCI host controller for an OF device */ | ||
30 | extern struct pci_controller* | ||
31 | pci_find_hose_for_OF_device(struct device_node* node); | ||
32 | |||
33 | /* Fill up host controller resources from the OF node */ | ||
34 | extern void | ||
35 | pci_process_bridge_OF_ranges(struct pci_controller *hose, | ||
36 | struct device_node *dev, int primary); | ||
37 | |||
38 | /* | ||
39 | * Structure of a PCI controller (host bridge) | ||
40 | */ | ||
41 | struct pci_controller { | ||
42 | int index; /* PCI domain number */ | ||
43 | struct pci_controller *next; | ||
44 | struct pci_bus *bus; | ||
45 | void *arch_data; | ||
46 | |||
47 | int first_busno; | ||
48 | int last_busno; | ||
49 | int bus_offset; | ||
50 | |||
51 | void *io_base_virt; | ||
52 | unsigned long io_base_phys; | ||
53 | |||
54 | /* Some machines (PReP) have a non 1:1 mapping of | ||
55 | * the PCI memory space in the CPU bus space | ||
56 | */ | ||
57 | unsigned long pci_mem_offset; | ||
58 | |||
59 | struct pci_ops *ops; | ||
60 | volatile unsigned int __iomem *cfg_addr; | ||
61 | volatile void __iomem *cfg_data; | ||
62 | /* | ||
63 | * If set, indirect method will set the cfg_type bit as | ||
64 | * needed to generate type 1 configuration transactions. | ||
65 | */ | ||
66 | int set_cfg_type; | ||
67 | |||
68 | /* Currently, we limit ourselves to 1 IO range and 3 mem | ||
69 | * ranges since the common pci_bus structure can't handle more | ||
70 | */ | ||
71 | struct resource io_resource; | ||
72 | struct resource mem_resources[3]; | ||
73 | int mem_resource_count; | ||
74 | |||
75 | /* Host bridge I/O and Memory space | ||
76 | * Used for BAR placement algorithms | ||
77 | */ | ||
78 | struct resource io_space; | ||
79 | struct resource mem_space; | ||
80 | }; | ||
81 | |||
82 | /* These are used for config access before all the PCI probing | ||
83 | has been done. */ | ||
84 | int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, | ||
85 | int where, u8 *val); | ||
86 | int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, | ||
87 | int where, u16 *val); | ||
88 | int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, | ||
89 | int where, u32 *val); | ||
90 | int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, | ||
91 | int where, u8 val); | ||
92 | int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, | ||
93 | int where, u16 val); | ||
94 | int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, | ||
95 | int where, u32 val); | ||
96 | |||
97 | extern void setup_indirect_pci_nomap(struct pci_controller* hose, | ||
98 | void __iomem *cfg_addr, void __iomem *cfg_data); | ||
99 | extern void setup_indirect_pci(struct pci_controller* hose, | ||
100 | u32 cfg_addr, u32 cfg_data); | ||
101 | extern void setup_grackle(struct pci_controller *hose); | ||
102 | |||
103 | extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); | ||
104 | |||
105 | /* | ||
106 | * The following code swizzles for exactly one bridge. The routine | ||
107 | * common_swizzle below handles multiple bridges. But there are a | ||
108 | * some boards that don't follow the PCI spec's suggestion so we | ||
109 | * break this piece out separately. | ||
110 | */ | ||
111 | static inline unsigned char bridge_swizzle(unsigned char pin, | ||
112 | unsigned char idsel) | ||
113 | { | ||
114 | return (((pin-1) + idsel) % 4) + 1; | ||
115 | } | ||
116 | |||
117 | /* | ||
118 | * The following macro is used to lookup irqs in a standard table | ||
119 | * format for those PPC systems that do not already have PCI | ||
120 | * interrupts properly routed. | ||
121 | */ | ||
122 | /* FIXME - double check this */ | ||
123 | #define PCI_IRQ_TABLE_LOOKUP \ | ||
124 | ({ long _ctl_ = -1; \ | ||
125 | if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ | ||
126 | _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ | ||
127 | _ctl_; }) | ||
128 | |||
129 | /* | ||
130 | * Scan the buses below a given PCI host bridge and assign suitable | ||
131 | * resources to all devices found. | ||
132 | */ | ||
133 | extern int pciauto_bus_scan(struct pci_controller *, int); | ||
134 | |||
135 | #endif | ||
136 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h new file mode 100644 index 000000000000..ce5ae6d048f5 --- /dev/null +++ b/include/asm-ppc/pci.h | |||
@@ -0,0 +1,108 @@ | |||
1 | #ifndef __PPC_PCI_H | ||
2 | #define __PPC_PCI_H | ||
3 | #ifdef __KERNEL__ | ||
4 | |||
5 | #include <linux/types.h> | ||
6 | #include <linux/slab.h> | ||
7 | #include <linux/string.h> | ||
8 | #include <linux/mm.h> | ||
9 | #include <asm/scatterlist.h> | ||
10 | #include <asm/io.h> | ||
11 | #include <asm/pci-bridge.h> | ||
12 | #include <asm-generic/pci-dma-compat.h> | ||
13 | |||
14 | struct pci_dev; | ||
15 | |||
16 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ | ||
17 | #define IOBASE_BRIDGE_NUMBER 0 | ||
18 | #define IOBASE_MEMORY 1 | ||
19 | #define IOBASE_IO 2 | ||
20 | #define IOBASE_ISA_IO 3 | ||
21 | #define IOBASE_ISA_MEM 4 | ||
22 | |||
23 | /* | ||
24 | * Set this to 1 if you want the kernel to re-assign all PCI | ||
25 | * bus numbers | ||
26 | */ | ||
27 | extern int pci_assign_all_busses; | ||
28 | |||
29 | #define pcibios_assign_all_busses() (pci_assign_all_busses) | ||
30 | #define pcibios_scan_all_fns(a, b) 0 | ||
31 | |||
32 | #define PCIBIOS_MIN_IO 0x1000 | ||
33 | #define PCIBIOS_MIN_MEM 0x10000000 | ||
34 | |||
35 | extern inline void pcibios_set_master(struct pci_dev *dev) | ||
36 | { | ||
37 | /* No special bus mastering setup handling */ | ||
38 | } | ||
39 | |||
40 | extern inline void pcibios_penalize_isa_irq(int irq) | ||
41 | { | ||
42 | /* We don't do dynamic PCI IRQ allocation */ | ||
43 | } | ||
44 | |||
45 | extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res); | ||
46 | |||
47 | /* | ||
48 | * The PCI bus bridge can translate addresses issued by the processor(s) | ||
49 | * into a different address on the PCI bus. On 32-bit cpus, we assume | ||
50 | * this mapping is 1-1, but on 64-bit systems it often isn't. | ||
51 | * | ||
52 | * Obsolete ! Drivers should now use pci_resource_to_bus | ||
53 | */ | ||
54 | extern unsigned long phys_to_bus(unsigned long pa); | ||
55 | extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr); | ||
56 | extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr); | ||
57 | |||
58 | /* The PCI address space does equal the physical memory | ||
59 | * address space. The networking and block device layers use | ||
60 | * this boolean for bounce buffer decisions. | ||
61 | */ | ||
62 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
63 | |||
64 | /* pci_unmap_{page,single} is a nop so... */ | ||
65 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | ||
66 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | ||
67 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | ||
68 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | ||
69 | #define pci_unmap_len(PTR, LEN_NAME) (0) | ||
70 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | ||
71 | |||
72 | /* | ||
73 | * At present there are very few 32-bit PPC machines that can have | ||
74 | * memory above the 4GB point, and we don't support that. | ||
75 | */ | ||
76 | #define pci_dac_dma_supported(pci_dev, mask) (0) | ||
77 | |||
78 | /* Return the index of the PCI controller for device PDEV. */ | ||
79 | #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index | ||
80 | |||
81 | /* Set the name of the bus as it appears in /proc/bus/pci */ | ||
82 | static inline int pci_proc_domain(struct pci_bus *bus) | ||
83 | { | ||
84 | return 0; | ||
85 | } | ||
86 | |||
87 | /* Map a range of PCI memory or I/O space for a device into user space */ | ||
88 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | ||
89 | enum pci_mmap_state mmap_state, int write_combine); | ||
90 | |||
91 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | ||
92 | #define HAVE_PCI_MMAP 1 | ||
93 | |||
94 | extern void | ||
95 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | ||
96 | struct resource *res); | ||
97 | |||
98 | extern void pcibios_add_platform_entries(struct pci_dev *dev); | ||
99 | |||
100 | struct file; | ||
101 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | ||
102 | unsigned long offset, | ||
103 | unsigned long size, | ||
104 | pgprot_t prot); | ||
105 | |||
106 | #endif /* __KERNEL__ */ | ||
107 | |||
108 | #endif /* __PPC_PCI_H */ | ||
diff --git a/include/asm-ppc/percpu.h b/include/asm-ppc/percpu.h new file mode 100644 index 000000000000..d66667cd5878 --- /dev/null +++ b/include/asm-ppc/percpu.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef __ARCH_PPC_PERCPU__ | ||
2 | #define __ARCH_PPC_PERCPU__ | ||
3 | |||
4 | #include <asm-generic/percpu.h> | ||
5 | |||
6 | #endif /* __ARCH_PPC_PERCPU__ */ | ||
diff --git a/include/asm-ppc/perfmon.h b/include/asm-ppc/perfmon.h new file mode 100644 index 000000000000..5e7a89c47b5b --- /dev/null +++ b/include/asm-ppc/perfmon.h | |||
@@ -0,0 +1,22 @@ | |||
1 | #ifndef __PERFMON_H | ||
2 | #define __PERFMON_H | ||
3 | |||
4 | extern void (*perf_irq)(struct pt_regs *); | ||
5 | |||
6 | int request_perfmon_irq(void (*handler)(struct pt_regs *)); | ||
7 | void free_perfmon_irq(void); | ||
8 | |||
9 | #ifdef CONFIG_FSL_BOOKE | ||
10 | void init_pmc_stop(int ctr); | ||
11 | void set_pmc_event(int ctr, int event); | ||
12 | void set_pmc_user_kernel(int ctr, int user, int kernel); | ||
13 | void set_pmc_marked(int ctr, int mark0, int mark1); | ||
14 | void pmc_start_ctr(int ctr, int enable); | ||
15 | void pmc_start_ctrs(int enable); | ||
16 | void pmc_stop_ctrs(void); | ||
17 | void dump_pmcs(void); | ||
18 | |||
19 | extern struct op_ppc32_model op_model_fsl_booke; | ||
20 | #endif | ||
21 | |||
22 | #endif /* __PERFMON_H */ | ||
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h new file mode 100644 index 000000000000..931b6de7ef53 --- /dev/null +++ b/include/asm-ppc/pgalloc.h | |||
@@ -0,0 +1,44 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_PGALLOC_H | ||
3 | #define _PPC_PGALLOC_H | ||
4 | |||
5 | #include <linux/config.h> | ||
6 | #include <linux/threads.h> | ||
7 | |||
8 | extern void __bad_pte(pmd_t *pmd); | ||
9 | |||
10 | extern pgd_t *pgd_alloc(struct mm_struct *mm); | ||
11 | extern void pgd_free(pgd_t *pgd); | ||
12 | |||
13 | /* | ||
14 | * We don't have any real pmd's, and this code never triggers because | ||
15 | * the pgd will always be present.. | ||
16 | */ | ||
17 | #define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) | ||
18 | #define pmd_free(x) do { } while (0) | ||
19 | #define __pmd_free_tlb(tlb,x) do { } while (0) | ||
20 | #define pgd_populate(mm, pmd, pte) BUG() | ||
21 | |||
22 | #ifndef CONFIG_BOOKE | ||
23 | #define pmd_populate_kernel(mm, pmd, pte) \ | ||
24 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) | ||
25 | #define pmd_populate(mm, pmd, pte) \ | ||
26 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) | ||
27 | #else | ||
28 | #define pmd_populate_kernel(mm, pmd, pte) \ | ||
29 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) | ||
30 | #define pmd_populate(mm, pmd, pte) \ | ||
31 | (pmd_val(*(pmd)) = (unsigned long)page_to_virt(pte) | _PMD_PRESENT) | ||
32 | #endif | ||
33 | |||
34 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); | ||
35 | extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr); | ||
36 | extern void pte_free_kernel(pte_t *pte); | ||
37 | extern void pte_free(struct page *pte); | ||
38 | |||
39 | #define __pte_free_tlb(tlb, pte) pte_free((pte)) | ||
40 | |||
41 | #define check_pgt_cache() do { } while (0) | ||
42 | |||
43 | #endif /* _PPC_PGALLOC_H */ | ||
44 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h new file mode 100644 index 000000000000..19dfb7abaa21 --- /dev/null +++ b/include/asm-ppc/pgtable.h | |||
@@ -0,0 +1,776 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_PGTABLE_H | ||
3 | #define _PPC_PGTABLE_H | ||
4 | |||
5 | #include <asm-generic/4level-fixup.h> | ||
6 | |||
7 | #include <linux/config.h> | ||
8 | |||
9 | #ifndef __ASSEMBLY__ | ||
10 | #include <linux/sched.h> | ||
11 | #include <linux/threads.h> | ||
12 | #include <asm/processor.h> /* For TASK_SIZE */ | ||
13 | #include <asm/mmu.h> | ||
14 | #include <asm/page.h> | ||
15 | |||
16 | extern unsigned long va_to_phys(unsigned long address); | ||
17 | extern pte_t *va_to_pte(unsigned long address); | ||
18 | extern unsigned long ioremap_bot, ioremap_base; | ||
19 | #endif /* __ASSEMBLY__ */ | ||
20 | |||
21 | /* | ||
22 | * The PowerPC MMU uses a hash table containing PTEs, together with | ||
23 | * a set of 16 segment registers (on 32-bit implementations), to define | ||
24 | * the virtual to physical address mapping. | ||
25 | * | ||
26 | * We use the hash table as an extended TLB, i.e. a cache of currently | ||
27 | * active mappings. We maintain a two-level page table tree, much | ||
28 | * like that used by the i386, for the sake of the Linux memory | ||
29 | * management code. Low-level assembler code in hashtable.S | ||
30 | * (procedure hash_page) is responsible for extracting ptes from the | ||
31 | * tree and putting them into the hash table when necessary, and | ||
32 | * updating the accessed and modified bits in the page table tree. | ||
33 | */ | ||
34 | |||
35 | /* | ||
36 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. | ||
37 | * We also use the two level tables, but we can put the real bits in them | ||
38 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, | ||
39 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has | ||
40 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit | ||
41 | * based upon user/super access. The TLB does not have accessed nor write | ||
42 | * protect. We assume that if the TLB get loaded with an entry it is | ||
43 | * accessed, and overload the changed bit for write protect. We use | ||
44 | * two bits in the software pte that are supposed to be set to zero in | ||
45 | * the TLB entry (24 and 25) for these indicators. Although the level 1 | ||
46 | * descriptor contains the guarded and writethrough/copyback bits, we can | ||
47 | * set these at the page level since they get copied from the Mx_TWC | ||
48 | * register when the TLB entry is loaded. We will use bit 27 for guard, since | ||
49 | * that is where it exists in the MD_TWC, and bit 26 for writethrough. | ||
50 | * These will get masked from the level 2 descriptor at TLB load time, and | ||
51 | * copied to the MD_TWC before it gets loaded. | ||
52 | * Large page sizes added. We currently support two sizes, 4K and 8M. | ||
53 | * This also allows a TLB hander optimization because we can directly | ||
54 | * load the PMD into MD_TWC. The 8M pages are only used for kernel | ||
55 | * mapping of well known areas. The PMD (PGD) entries contain control | ||
56 | * flags in addition to the address, so care must be taken that the | ||
57 | * software no longer assumes these are only pointers. | ||
58 | */ | ||
59 | |||
60 | /* | ||
61 | * At present, all PowerPC 400-class processors share a similar TLB | ||
62 | * architecture. The instruction and data sides share a unified, | ||
63 | * 64-entry, fully-associative TLB which is maintained totally under | ||
64 | * software control. In addition, the instruction side has a | ||
65 | * hardware-managed, 4-entry, fully-associative TLB which serves as a | ||
66 | * first level to the shared TLB. These two TLBs are known as the UTLB | ||
67 | * and ITLB, respectively (see "mmu.h" for definitions). | ||
68 | */ | ||
69 | |||
70 | /* | ||
71 | * The normal case is that PTEs are 32-bits and we have a 1-page | ||
72 | * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus | ||
73 | * | ||
74 | * For any >32-bit physical address platform, we can use the following | ||
75 | * two level page table layout where the pgdir is 8KB and the MS 13 bits | ||
76 | * are an index to the second level table. The combined pgdir/pmd first | ||
77 | * level has 2048 entries and the second level has 512 64-bit PTE entries. | ||
78 | * -Matt | ||
79 | */ | ||
80 | /* PMD_SHIFT determines the size of the area mapped by the PTE pages */ | ||
81 | #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) | ||
82 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
83 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
84 | |||
85 | /* PGDIR_SHIFT determines what a top-level page table entry can map */ | ||
86 | #define PGDIR_SHIFT PMD_SHIFT | ||
87 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
88 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
89 | |||
90 | /* | ||
91 | * entries per page directory level: our page-table tree is two-level, so | ||
92 | * we don't really have any PMD directory. | ||
93 | */ | ||
94 | #define PTRS_PER_PTE (1 << PTE_SHIFT) | ||
95 | #define PTRS_PER_PMD 1 | ||
96 | #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) | ||
97 | |||
98 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) | ||
99 | #define FIRST_USER_PGD_NR 0 | ||
100 | |||
101 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) | ||
102 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) | ||
103 | |||
104 | #define pte_ERROR(e) \ | ||
105 | printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e)) | ||
106 | #define pmd_ERROR(e) \ | ||
107 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
108 | #define pgd_ERROR(e) \ | ||
109 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
110 | |||
111 | /* | ||
112 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
113 | * current 64MB value just means that there will be a 64MB "hole" after the | ||
114 | * physical memory until the kernel virtual memory starts. That means that | ||
115 | * any out-of-bounds memory accesses will hopefully be caught. | ||
116 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
117 | * area for the same reason. ;) | ||
118 | * | ||
119 | * We no longer map larger than phys RAM with the BATs so we don't have | ||
120 | * to worry about the VMALLOC_OFFSET causing problems. We do have to worry | ||
121 | * about clashes between our early calls to ioremap() that start growing down | ||
122 | * from ioremap_base being run into the VM area allocations (growing upwards | ||
123 | * from VMALLOC_START). For this reason we have ioremap_bot to check when | ||
124 | * we actually run into our mappings setup in the early boot with the VM | ||
125 | * system. This really does become a problem for machines with good amounts | ||
126 | * of RAM. -- Cort | ||
127 | */ | ||
128 | #define VMALLOC_OFFSET (0x1000000) /* 16M */ | ||
129 | #ifdef CONFIG_44x | ||
130 | #include <asm/ibm44x.h> | ||
131 | #define VMALLOC_START (((_ALIGN((long)high_memory, PPC44x_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) | ||
132 | #else | ||
133 | #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) | ||
134 | #endif | ||
135 | #define VMALLOC_END ioremap_bot | ||
136 | |||
137 | /* | ||
138 | * Bits in a linux-style PTE. These match the bits in the | ||
139 | * (hardware-defined) PowerPC PTE as closely as possible. | ||
140 | */ | ||
141 | |||
142 | #if defined(CONFIG_40x) | ||
143 | |||
144 | /* There are several potential gotchas here. The 40x hardware TLBLO | ||
145 | field looks like this: | ||
146 | |||
147 | 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
148 | RPN..................... 0 0 EX WR ZSEL....... W I M G | ||
149 | |||
150 | Where possible we make the Linux PTE bits match up with this | ||
151 | |||
152 | - bits 20 and 21 must be cleared, because we use 4k pages (40x can | ||
153 | support down to 1k pages), this is done in the TLBMiss exception | ||
154 | handler. | ||
155 | - We use only zones 0 (for kernel pages) and 1 (for user pages) | ||
156 | of the 16 available. Bit 24-26 of the TLB are cleared in the TLB | ||
157 | miss handler. Bit 27 is PAGE_USER, thus selecting the correct | ||
158 | zone. | ||
159 | - PRESENT *must* be in the bottom two bits because swap cache | ||
160 | entries use the top 30 bits. Because 40x doesn't support SMP | ||
161 | anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 | ||
162 | is cleared in the TLB miss handler before the TLB entry is loaded. | ||
163 | - All other bits of the PTE are loaded into TLBLO without | ||
164 | modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for | ||
165 | software PTE bits. We actually use use bits 21, 24, 25, and | ||
166 | 30 respectively for the software bits: ACCESSED, DIRTY, RW, and | ||
167 | PRESENT. | ||
168 | */ | ||
169 | |||
170 | /* Definitions for 40x embedded chips. */ | ||
171 | #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ | ||
172 | #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ | ||
173 | #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ | ||
174 | #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ | ||
175 | #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ | ||
176 | #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ | ||
177 | #define _PAGE_RW 0x040 /* software: Writes permitted */ | ||
178 | #define _PAGE_DIRTY 0x080 /* software: dirty page */ | ||
179 | #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ | ||
180 | #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ | ||
181 | #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ | ||
182 | |||
183 | #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ | ||
184 | #define _PMD_BAD 0x802 | ||
185 | #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */ | ||
186 | #define _PMD_SIZE_4M 0x0c0 | ||
187 | #define _PMD_SIZE_16M 0x0e0 | ||
188 | #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) | ||
189 | |||
190 | #elif defined(CONFIG_44x) | ||
191 | /* | ||
192 | * Definitions for PPC440 | ||
193 | * | ||
194 | * Because of the 3 word TLB entries to support 36-bit addressing, | ||
195 | * the attribute are difficult to map in such a fashion that they | ||
196 | * are easily loaded during exception processing. I decided to | ||
197 | * organize the entry so the ERPN is the only portion in the | ||
198 | * upper word of the PTE and the attribute bits below are packed | ||
199 | * in as sensibly as they can be in the area below a 4KB page size | ||
200 | * oriented RPN. This at least makes it easy to load the RPN and | ||
201 | * ERPN fields in the TLB. -Matt | ||
202 | * | ||
203 | * Note that these bits preclude future use of a page size | ||
204 | * less than 4KB. | ||
205 | */ | ||
206 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ | ||
207 | #define _PAGE_RW 0x00000002 /* S: Write permission */ | ||
208 | #define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ | ||
209 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ | ||
210 | #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ | ||
211 | #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ | ||
212 | #define _PAGE_USER 0x00000040 /* S: User page */ | ||
213 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ | ||
214 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ | ||
215 | #define _PAGE_COHERENT 0x00000200 /* H: M bit */ | ||
216 | #define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */ | ||
217 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ | ||
218 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ | ||
219 | |||
220 | /* TODO: Add large page lowmem mapping support */ | ||
221 | #define _PMD_PRESENT 0 | ||
222 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
223 | #define _PMD_BAD (~PAGE_MASK) | ||
224 | |||
225 | /* ERPN in a PTE never gets cleared, ignore it */ | ||
226 | #define _PTE_NONE_MASK 0xffffffff00000000ULL | ||
227 | |||
228 | #elif defined(CONFIG_E500) | ||
229 | |||
230 | /* | ||
231 | MMU Assist Register 3: | ||
232 | |||
233 | 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | ||
234 | RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR | ||
235 | |||
236 | - PRESENT *must* be in the bottom three bits because swap cache | ||
237 | entries use the top 29 bits. | ||
238 | |||
239 | - FILE *must* be in the bottom three bits because swap cache | ||
240 | entries use the top 29 bits. | ||
241 | */ | ||
242 | |||
243 | /* Definitions for e500 core */ | ||
244 | #define _PAGE_PRESENT 0x001 /* S: PTE contains a translation */ | ||
245 | #define _PAGE_USER 0x002 /* S: User page (maps to UR) */ | ||
246 | #define _PAGE_FILE 0x002 /* S: when !present: nonlinear file mapping */ | ||
247 | #define _PAGE_ACCESSED 0x004 /* S: Page referenced */ | ||
248 | #define _PAGE_HWWRITE 0x008 /* H: Dirty & RW, set in exception */ | ||
249 | #define _PAGE_RW 0x010 /* S: Write permission */ | ||
250 | #define _PAGE_HWEXEC 0x020 /* H: UX permission */ | ||
251 | |||
252 | #define _PAGE_ENDIAN 0x040 /* H: E bit */ | ||
253 | #define _PAGE_GUARDED 0x080 /* H: G bit */ | ||
254 | #define _PAGE_COHERENT 0x100 /* H: M bit */ | ||
255 | #define _PAGE_NO_CACHE 0x200 /* H: I bit */ | ||
256 | #define _PAGE_WRITETHRU 0x400 /* H: W bit */ | ||
257 | #define _PAGE_DIRTY 0x800 /* S: Page dirty */ | ||
258 | |||
259 | #define _PMD_PRESENT 0 | ||
260 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
261 | #define _PMD_BAD (~PAGE_MASK) | ||
262 | |||
263 | #define NUM_TLBCAMS (16) | ||
264 | |||
265 | #elif defined(CONFIG_8xx) | ||
266 | /* Definitions for 8xx embedded chips. */ | ||
267 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ | ||
268 | #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ | ||
269 | #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ | ||
270 | #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ | ||
271 | |||
272 | /* These five software bits must be masked out when the entry is loaded | ||
273 | * into the TLB. | ||
274 | */ | ||
275 | #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ | ||
276 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ | ||
277 | #define _PAGE_DIRTY 0x0020 /* software: page changed */ | ||
278 | #define _PAGE_RW 0x0040 /* software: user write access allowed */ | ||
279 | #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ | ||
280 | |||
281 | /* Setting any bits in the nibble with the follow two controls will | ||
282 | * require a TLB exception handler change. It is assumed unused bits | ||
283 | * are always zero. | ||
284 | */ | ||
285 | #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ | ||
286 | #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ | ||
287 | |||
288 | #define _PMD_PRESENT 0x0001 | ||
289 | #define _PMD_BAD 0x0ff0 | ||
290 | #define _PMD_PAGE_MASK 0x000c | ||
291 | #define _PMD_PAGE_8M 0x000c | ||
292 | |||
293 | /* | ||
294 | * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE | ||
295 | * for an address even if _PAGE_PRESENT is not set, as a performance | ||
296 | * optimization. This is a bug if you ever want to use swap unless | ||
297 | * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific | ||
298 | * definitions for __swp_entry etc. below, which would be gross. | ||
299 | * -- paulus | ||
300 | */ | ||
301 | #define _PTE_NONE_MASK _PAGE_ACCESSED | ||
302 | |||
303 | #else /* CONFIG_6xx */ | ||
304 | /* Definitions for 60x, 740/750, etc. */ | ||
305 | #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ | ||
306 | #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ | ||
307 | #define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */ | ||
308 | #define _PAGE_USER 0x004 /* usermode access allowed */ | ||
309 | #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ | ||
310 | #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ | ||
311 | #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ | ||
312 | #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ | ||
313 | #define _PAGE_DIRTY 0x080 /* C: page changed */ | ||
314 | #define _PAGE_ACCESSED 0x100 /* R: page referenced */ | ||
315 | #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ | ||
316 | #define _PAGE_RW 0x400 /* software: user write access allowed */ | ||
317 | |||
318 | #define _PTE_NONE_MASK _PAGE_HASHPTE | ||
319 | |||
320 | #define _PMD_PRESENT 0 | ||
321 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
322 | #define _PMD_BAD (~PAGE_MASK) | ||
323 | #endif | ||
324 | |||
325 | /* | ||
326 | * Some bits are only used on some cpu families... | ||
327 | */ | ||
328 | #ifndef _PAGE_HASHPTE | ||
329 | #define _PAGE_HASHPTE 0 | ||
330 | #endif | ||
331 | #ifndef _PTE_NONE_MASK | ||
332 | #define _PTE_NONE_MASK 0 | ||
333 | #endif | ||
334 | #ifndef _PAGE_SHARED | ||
335 | #define _PAGE_SHARED 0 | ||
336 | #endif | ||
337 | #ifndef _PAGE_HWWRITE | ||
338 | #define _PAGE_HWWRITE 0 | ||
339 | #endif | ||
340 | #ifndef _PAGE_HWEXEC | ||
341 | #define _PAGE_HWEXEC 0 | ||
342 | #endif | ||
343 | #ifndef _PAGE_EXEC | ||
344 | #define _PAGE_EXEC 0 | ||
345 | #endif | ||
346 | #ifndef _PMD_PRESENT_MASK | ||
347 | #define _PMD_PRESENT_MASK _PMD_PRESENT | ||
348 | #endif | ||
349 | #ifndef _PMD_SIZE | ||
350 | #define _PMD_SIZE 0 | ||
351 | #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() | ||
352 | #endif | ||
353 | |||
354 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) | ||
355 | |||
356 | /* | ||
357 | * Note: the _PAGE_COHERENT bit automatically gets set in the hardware | ||
358 | * PTE if CONFIG_SMP is defined (hash_page does this); there is no need | ||
359 | * to have it in the Linux PTE, and in fact the bit could be reused for | ||
360 | * another purpose. -- paulus. | ||
361 | */ | ||
362 | |||
363 | #ifdef CONFIG_44x | ||
364 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) | ||
365 | #else | ||
366 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) | ||
367 | #endif | ||
368 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) | ||
369 | #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) | ||
370 | |||
371 | #ifdef CONFIG_PPC_STD_MMU | ||
372 | /* On standard PPC MMU, no user access implies kernel read/write access, | ||
373 | * so to write-protect kernel memory we must turn on user access */ | ||
374 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER) | ||
375 | #else | ||
376 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED) | ||
377 | #endif | ||
378 | |||
379 | #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) | ||
380 | #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) | ||
381 | |||
382 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) | ||
383 | /* We want the debuggers to be able to set breakpoints anywhere, so | ||
384 | * don't write protect the kernel text */ | ||
385 | #define _PAGE_RAM_TEXT _PAGE_RAM | ||
386 | #else | ||
387 | #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC) | ||
388 | #endif | ||
389 | |||
390 | #define PAGE_NONE __pgprot(_PAGE_BASE) | ||
391 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) | ||
392 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | ||
393 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) | ||
394 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) | ||
395 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) | ||
396 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | ||
397 | |||
398 | #define PAGE_KERNEL __pgprot(_PAGE_RAM) | ||
399 | #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO) | ||
400 | |||
401 | /* | ||
402 | * The PowerPC can only do execute protection on a segment (256MB) basis, | ||
403 | * not on a page basis. So we consider execute permission the same as read. | ||
404 | * Also, write permissions imply read permissions. | ||
405 | * This is the closest we can get.. | ||
406 | */ | ||
407 | #define __P000 PAGE_NONE | ||
408 | #define __P001 PAGE_READONLY_X | ||
409 | #define __P010 PAGE_COPY | ||
410 | #define __P011 PAGE_COPY_X | ||
411 | #define __P100 PAGE_READONLY | ||
412 | #define __P101 PAGE_READONLY_X | ||
413 | #define __P110 PAGE_COPY | ||
414 | #define __P111 PAGE_COPY_X | ||
415 | |||
416 | #define __S000 PAGE_NONE | ||
417 | #define __S001 PAGE_READONLY_X | ||
418 | #define __S010 PAGE_SHARED | ||
419 | #define __S011 PAGE_SHARED_X | ||
420 | #define __S100 PAGE_READONLY | ||
421 | #define __S101 PAGE_READONLY_X | ||
422 | #define __S110 PAGE_SHARED | ||
423 | #define __S111 PAGE_SHARED_X | ||
424 | |||
425 | #ifndef __ASSEMBLY__ | ||
426 | /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a | ||
427 | * kernel without large page PMD support */ | ||
428 | extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); | ||
429 | |||
430 | /* | ||
431 | * Conversions between PTE values and page frame numbers. | ||
432 | */ | ||
433 | |||
434 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | ||
435 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
436 | |||
437 | #define pfn_pte(pfn, prot) __pte(((pte_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
438 | #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) | ||
439 | |||
440 | /* | ||
441 | * ZERO_PAGE is a global shared page that is always zero: used | ||
442 | * for zero-mapped memory areas etc.. | ||
443 | */ | ||
444 | extern unsigned long empty_zero_page[1024]; | ||
445 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
446 | |||
447 | #endif /* __ASSEMBLY__ */ | ||
448 | |||
449 | #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) | ||
450 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) | ||
451 | #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) | ||
452 | |||
453 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
454 | #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) | ||
455 | #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) | ||
456 | #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) | ||
457 | |||
458 | #ifndef __ASSEMBLY__ | ||
459 | /* | ||
460 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
461 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
462 | * into the pgd entry) | ||
463 | */ | ||
464 | static inline int pgd_none(pgd_t pgd) { return 0; } | ||
465 | static inline int pgd_bad(pgd_t pgd) { return 0; } | ||
466 | static inline int pgd_present(pgd_t pgd) { return 1; } | ||
467 | #define pgd_clear(xp) do { } while (0) | ||
468 | |||
469 | #define pgd_page(pgd) \ | ||
470 | ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) | ||
471 | |||
472 | /* | ||
473 | * The following only work if pte_present() is true. | ||
474 | * Undefined behaviour if not.. | ||
475 | */ | ||
476 | static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } | ||
477 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } | ||
478 | static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } | ||
479 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } | ||
480 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
481 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
482 | |||
483 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } | ||
484 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } | ||
485 | |||
486 | static inline pte_t pte_rdprotect(pte_t pte) { | ||
487 | pte_val(pte) &= ~_PAGE_USER; return pte; } | ||
488 | static inline pte_t pte_wrprotect(pte_t pte) { | ||
489 | pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } | ||
490 | static inline pte_t pte_exprotect(pte_t pte) { | ||
491 | pte_val(pte) &= ~_PAGE_EXEC; return pte; } | ||
492 | static inline pte_t pte_mkclean(pte_t pte) { | ||
493 | pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } | ||
494 | static inline pte_t pte_mkold(pte_t pte) { | ||
495 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | ||
496 | |||
497 | static inline pte_t pte_mkread(pte_t pte) { | ||
498 | pte_val(pte) |= _PAGE_USER; return pte; } | ||
499 | static inline pte_t pte_mkexec(pte_t pte) { | ||
500 | pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } | ||
501 | static inline pte_t pte_mkwrite(pte_t pte) { | ||
502 | pte_val(pte) |= _PAGE_RW; return pte; } | ||
503 | static inline pte_t pte_mkdirty(pte_t pte) { | ||
504 | pte_val(pte) |= _PAGE_DIRTY; return pte; } | ||
505 | static inline pte_t pte_mkyoung(pte_t pte) { | ||
506 | pte_val(pte) |= _PAGE_ACCESSED; return pte; } | ||
507 | |||
508 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
509 | { | ||
510 | pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); | ||
511 | return pte; | ||
512 | } | ||
513 | |||
514 | /* | ||
515 | * When flushing the tlb entry for a page, we also need to flush the hash | ||
516 | * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. | ||
517 | */ | ||
518 | extern int flush_hash_pages(unsigned context, unsigned long va, | ||
519 | unsigned long pmdval, int count); | ||
520 | |||
521 | /* Add an HPTE to the hash table */ | ||
522 | extern void add_hash_page(unsigned context, unsigned long va, | ||
523 | unsigned long pmdval); | ||
524 | |||
525 | /* | ||
526 | * Atomic PTE updates. | ||
527 | * | ||
528 | * pte_update clears and sets bit atomically, and returns | ||
529 | * the old pte value. | ||
530 | * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant | ||
531 | * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. | ||
532 | */ | ||
533 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, | ||
534 | unsigned long set) | ||
535 | { | ||
536 | unsigned long old, tmp; | ||
537 | |||
538 | __asm__ __volatile__("\ | ||
539 | 1: lwarx %0,0,%3\n\ | ||
540 | andc %1,%0,%4\n\ | ||
541 | or %1,%1,%5\n" | ||
542 | PPC405_ERR77(0,%3) | ||
543 | " stwcx. %1,0,%3\n\ | ||
544 | bne- 1b" | ||
545 | : "=&r" (old), "=&r" (tmp), "=m" (*p) | ||
546 | : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p) | ||
547 | : "cc" ); | ||
548 | return old; | ||
549 | } | ||
550 | |||
551 | /* | ||
552 | * set_pte stores a linux PTE into the linux page table. | ||
553 | * On machines which use an MMU hash table we avoid changing the | ||
554 | * _PAGE_HASHPTE bit. | ||
555 | */ | ||
556 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | ||
557 | pte_t *ptep, pte_t pte) | ||
558 | { | ||
559 | #if _PAGE_HASHPTE != 0 | ||
560 | pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); | ||
561 | #else | ||
562 | *ptep = pte; | ||
563 | #endif | ||
564 | } | ||
565 | |||
566 | /* | ||
567 | * 2.6 calles this without flushing the TLB entry, this is wrong | ||
568 | * for our hash-based implementation, we fix that up here | ||
569 | */ | ||
570 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | ||
571 | static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) | ||
572 | { | ||
573 | unsigned long old; | ||
574 | old = pte_update(ptep, _PAGE_ACCESSED, 0); | ||
575 | #if _PAGE_HASHPTE != 0 | ||
576 | if (old & _PAGE_HASHPTE) { | ||
577 | unsigned long ptephys = __pa(ptep) & PAGE_MASK; | ||
578 | flush_hash_pages(context, addr, ptephys, 1); | ||
579 | } | ||
580 | #endif | ||
581 | return (old & _PAGE_ACCESSED) != 0; | ||
582 | } | ||
583 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | ||
584 | __ptep_test_and_clear_young((__vma)->vm_mm->context, __addr, __ptep) | ||
585 | |||
586 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY | ||
587 | static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, | ||
588 | unsigned long addr, pte_t *ptep) | ||
589 | { | ||
590 | return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; | ||
591 | } | ||
592 | |||
593 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | ||
594 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, | ||
595 | pte_t *ptep) | ||
596 | { | ||
597 | return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); | ||
598 | } | ||
599 | |||
600 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | ||
601 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | ||
602 | pte_t *ptep) | ||
603 | { | ||
604 | pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); | ||
605 | } | ||
606 | |||
607 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | ||
608 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) | ||
609 | { | ||
610 | unsigned long bits = pte_val(entry) & | ||
611 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); | ||
612 | pte_update(ptep, 0, bits); | ||
613 | } | ||
614 | |||
615 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ | ||
616 | do { \ | ||
617 | __ptep_set_access_flags(__ptep, __entry, __dirty); \ | ||
618 | flush_tlb_page_nohash(__vma, __address); \ | ||
619 | } while(0) | ||
620 | |||
621 | /* | ||
622 | * Macro to mark a page protection value as "uncacheable". | ||
623 | */ | ||
624 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) | ||
625 | |||
626 | struct file; | ||
627 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, | ||
628 | unsigned long size, pgprot_t vma_prot); | ||
629 | #define __HAVE_PHYS_MEM_ACCESS_PROT | ||
630 | |||
631 | #define __HAVE_ARCH_PTE_SAME | ||
632 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) | ||
633 | |||
634 | /* | ||
635 | * Note that on Book E processors, the pmd contains the kernel virtual | ||
636 | * (lowmem) address of the pte page. The physical address is less useful | ||
637 | * because everything runs with translation enabled (even the TLB miss | ||
638 | * handler). On everything else the pmd contains the physical address | ||
639 | * of the pte page. -- paulus | ||
640 | */ | ||
641 | #ifndef CONFIG_BOOKE | ||
642 | #define pmd_page_kernel(pmd) \ | ||
643 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) | ||
644 | #define pmd_page(pmd) \ | ||
645 | (mem_map + (pmd_val(pmd) >> PAGE_SHIFT)) | ||
646 | #else | ||
647 | #define pmd_page_kernel(pmd) \ | ||
648 | ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) | ||
649 | #define pmd_page(pmd) \ | ||
650 | (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) | ||
651 | #endif | ||
652 | |||
653 | /* to find an entry in a kernel page-table-directory */ | ||
654 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
655 | |||
656 | /* to find an entry in a page-table-directory */ | ||
657 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) | ||
658 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | ||
659 | |||
660 | /* Find an entry in the second-level page table.. */ | ||
661 | static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) | ||
662 | { | ||
663 | return (pmd_t *) dir; | ||
664 | } | ||
665 | |||
666 | /* Find an entry in the third-level page table.. */ | ||
667 | #define pte_index(address) \ | ||
668 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
669 | #define pte_offset_kernel(dir, addr) \ | ||
670 | ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) | ||
671 | #define pte_offset_map(dir, addr) \ | ||
672 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) | ||
673 | #define pte_offset_map_nested(dir, addr) \ | ||
674 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) | ||
675 | |||
676 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) | ||
677 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) | ||
678 | |||
679 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
680 | |||
681 | extern void paging_init(void); | ||
682 | |||
683 | /* | ||
684 | * Encode and decode a swap entry. | ||
685 | * Note that the bits we use in a PTE for representing a swap entry | ||
686 | * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the | ||
687 | *_PAGE_HASHPTE bit (if used). -- paulus | ||
688 | */ | ||
689 | #define __swp_type(entry) ((entry).val & 0x1f) | ||
690 | #define __swp_offset(entry) ((entry).val >> 5) | ||
691 | #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) | ||
692 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) | ||
693 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) | ||
694 | |||
695 | /* Encode and decode a nonlinear file mapping entry */ | ||
696 | #define PTE_FILE_MAX_BITS 29 | ||
697 | #define pte_to_pgoff(pte) (pte_val(pte) >> 3) | ||
698 | #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) | ||
699 | |||
700 | /* CONFIG_APUS */ | ||
701 | /* For virtual address to physical address conversion */ | ||
702 | extern void cache_clear(__u32 addr, int length); | ||
703 | extern void cache_push(__u32 addr, int length); | ||
704 | extern int mm_end_of_chunk (unsigned long addr, int len); | ||
705 | extern unsigned long iopa(unsigned long addr); | ||
706 | extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; | ||
707 | |||
708 | /* Values for nocacheflag and cmode */ | ||
709 | /* These are not used by the APUS kernel_map, but prevents | ||
710 | compilation errors. */ | ||
711 | #define KERNELMAP_FULL_CACHING 0 | ||
712 | #define KERNELMAP_NOCACHE_SER 1 | ||
713 | #define KERNELMAP_NOCACHE_NONSER 2 | ||
714 | #define KERNELMAP_NO_COPYBACK 3 | ||
715 | |||
716 | /* | ||
717 | * Map some physical address range into the kernel address space. | ||
718 | */ | ||
719 | extern unsigned long kernel_map(unsigned long paddr, unsigned long size, | ||
720 | int nocacheflag, unsigned long *memavailp ); | ||
721 | |||
722 | /* | ||
723 | * Set cache mode of (kernel space) address range. | ||
724 | */ | ||
725 | extern void kernel_set_cachemode (unsigned long address, unsigned long size, | ||
726 | unsigned int cmode); | ||
727 | |||
728 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ | ||
729 | #define kern_addr_valid(addr) (1) | ||
730 | |||
731 | #ifdef CONFIG_PHYS_64BIT | ||
732 | extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, | ||
733 | unsigned long paddr, unsigned long size, pgprot_t prot); | ||
734 | static inline int io_remap_page_range(struct vm_area_struct *vma, | ||
735 | unsigned long vaddr, | ||
736 | unsigned long paddr, | ||
737 | unsigned long size, | ||
738 | pgprot_t prot) | ||
739 | { | ||
740 | phys_addr_t paddr64 = fixup_bigphys_addr(paddr, size); | ||
741 | return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot); | ||
742 | } | ||
743 | |||
744 | static inline int io_remap_pfn_range(struct vm_area_struct *vma, | ||
745 | unsigned long vaddr, | ||
746 | unsigned long pfn, | ||
747 | unsigned long size, | ||
748 | pgprot_t prot) | ||
749 | { | ||
750 | phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); | ||
751 | return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot); | ||
752 | } | ||
753 | #else | ||
754 | #define io_remap_page_range(vma, vaddr, paddr, size, prot) \ | ||
755 | remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) | ||
756 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ | ||
757 | remap_pfn_range(vma, vaddr, pfn, size, prot) | ||
758 | #endif | ||
759 | |||
760 | #define MK_IOSPACE_PFN(space, pfn) (pfn) | ||
761 | #define GET_IOSPACE(pfn) 0 | ||
762 | #define GET_PFN(pfn) (pfn) | ||
763 | |||
764 | /* | ||
765 | * No page table caches to initialise | ||
766 | */ | ||
767 | #define pgtable_cache_init() do { } while (0) | ||
768 | |||
769 | extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep); | ||
770 | |||
771 | #include <asm-generic/pgtable.h> | ||
772 | |||
773 | #endif /* !__ASSEMBLY__ */ | ||
774 | |||
775 | #endif /* _PPC_PGTABLE_H */ | ||
776 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h new file mode 100644 index 000000000000..98c206d8c024 --- /dev/null +++ b/include/asm-ppc/pmac_feature.h | |||
@@ -0,0 +1,365 @@ | |||
1 | /* | ||
2 | * Definition of platform feature hooks for PowerMacs | ||
3 | * | ||
4 | * This file is subject to the terms and conditions of the GNU General Public | ||
5 | * License. See the file "COPYING" in the main directory of this archive | ||
6 | * for more details. | ||
7 | * | ||
8 | * Copyright (C) 1998 Paul Mackerras & | ||
9 | * Ben. Herrenschmidt. | ||
10 | * | ||
11 | * | ||
12 | * Note: I removed media-bay details from the feature stuff, I believe it's | ||
13 | * not worth it, the media-bay driver can directly use the mac-io | ||
14 | * ASIC registers. | ||
15 | * | ||
16 | * Implementation note: Currently, none of these functions will block. | ||
17 | * However, they may internally protect themselves with a spinlock | ||
18 | * for way too long. Be prepared for at least some of these to block | ||
19 | * in the future. | ||
20 | * | ||
21 | * Unless specifically defined, the result code is assumed to be an | ||
22 | * error when negative, 0 is the default success result. Some functions | ||
23 | * may return additional positive result values. | ||
24 | * | ||
25 | * To keep implementation simple, all feature calls are assumed to have | ||
26 | * the prototype parameters (struct device_node* node, int value). | ||
27 | * When either is not used, pass 0. | ||
28 | */ | ||
29 | |||
30 | #ifdef __KERNEL__ | ||
31 | #ifndef __PPC_ASM_PMAC_FEATURE_H | ||
32 | #define __PPC_ASM_PMAC_FEATURE_H | ||
33 | |||
34 | #include <asm/macio.h> | ||
35 | |||
36 | /* | ||
37 | * Known Mac motherboard models | ||
38 | * | ||
39 | * Please, report any error here to benh@kernel.crashing.org, thanks ! | ||
40 | * | ||
41 | * Note that I don't fully maintain this list for Core99 & MacRISC2 | ||
42 | * and I'm considering removing all NewWorld entries from it and | ||
43 | * entirely rely on the model string. | ||
44 | */ | ||
45 | |||
46 | /* PowerSurge are the first generation of PCI Pmacs. This include | ||
47 | * all of the Grand-Central based machines. We currently don't | ||
48 | * differenciate most of them. | ||
49 | */ | ||
50 | #define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */ | ||
51 | #define PMAC_TYPE_ANS 0x11 /* Apple Network Server */ | ||
52 | |||
53 | /* Here is the infamous serie of OHare based machines | ||
54 | */ | ||
55 | #define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */ | ||
56 | #define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */ | ||
57 | #define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */ | ||
58 | #define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */ | ||
59 | #define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */ | ||
60 | #define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */ | ||
61 | |||
62 | /* Here are the Heathrow based machines | ||
63 | * FIXME: Differenciate wallstreet,mainstreet,wallstreetII | ||
64 | */ | ||
65 | #define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */ | ||
66 | #define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */ | ||
67 | #define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/ | ||
68 | #define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */ | ||
69 | |||
70 | /* Here are newworld machines based on Paddington (heathrow derivative) | ||
71 | */ | ||
72 | #define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */ | ||
73 | #define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */ | ||
74 | #define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */ | ||
75 | #define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */ | ||
76 | #define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */ | ||
77 | |||
78 | /* Core99 machines based on UniNorth 1.0 and 1.5 | ||
79 | * | ||
80 | * Note: A single entry here may cover several actual models according | ||
81 | * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most | ||
82 | * FireWire based iMacs, etc...). Those machines are too similar to be | ||
83 | * distinguished here, when they need to be differencied, use the | ||
84 | * device-tree "model" or "compatible" property. | ||
85 | */ | ||
86 | #define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */ | ||
87 | #define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */ | ||
88 | #define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */ | ||
89 | #define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */ | ||
90 | #define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */ | ||
91 | #define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */ | ||
92 | #define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */ | ||
93 | #define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */ | ||
94 | #define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */ | ||
95 | #define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */ | ||
96 | #define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */ | ||
97 | #define PMAC_TYPE_EMAC 0x50 /* eMac */ | ||
98 | #define PMAC_TYPE_UNKNOWN_CORE99 0x5f | ||
99 | |||
100 | /* MacRisc2 with UniNorth 2.0 */ | ||
101 | #define PMAC_TYPE_RACKMAC 0x80 /* XServe */ | ||
102 | #define PMAC_TYPE_WINDTUNNEL 0x81 | ||
103 | |||
104 | /* MacRISC2 machines based on the Pangea chipset | ||
105 | */ | ||
106 | #define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */ | ||
107 | #define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */ | ||
108 | #define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */ | ||
109 | #define PMAC_TYPE_UNKNOWN_PANGEA 0x10f | ||
110 | |||
111 | /* MacRISC2 machines based on the Intrepid chipset | ||
112 | */ | ||
113 | #define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */ | ||
114 | |||
115 | /* MacRISC4 / G5 machines. We don't have per-machine selection here anymore, | ||
116 | * but rather machine families | ||
117 | */ | ||
118 | #define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */ | ||
119 | #define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */ | ||
120 | #define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */ | ||
121 | #define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */ | ||
122 | #define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */ | ||
123 | |||
124 | /* | ||
125 | * Motherboard flags | ||
126 | */ | ||
127 | |||
128 | #define PMAC_MB_CAN_SLEEP 0x00000001 | ||
129 | #define PMAC_MB_HAS_FW_POWER 0x00000002 | ||
130 | #define PMAC_MB_OLD_CORE99 0x00000004 | ||
131 | #define PMAC_MB_MOBILE 0x00000008 | ||
132 | #define PMAC_MB_MAY_SLEEP 0x00000010 | ||
133 | |||
134 | /* | ||
135 | * Feature calls supported on pmac | ||
136 | * | ||
137 | */ | ||
138 | |||
139 | /* | ||
140 | * Use this inline wrapper | ||
141 | */ | ||
142 | struct device_node; | ||
143 | |||
144 | static inline long pmac_call_feature(int selector, struct device_node* node, | ||
145 | long param, long value) | ||
146 | { | ||
147 | if (!ppc_md.feature_call) | ||
148 | return -ENODEV; | ||
149 | return ppc_md.feature_call(selector, node, param, value); | ||
150 | } | ||
151 | |||
152 | /* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value) | ||
153 | * enable/disable an SCC side. Pass the node corresponding to the | ||
154 | * channel side as a parameter. | ||
155 | * param is the type of port | ||
156 | * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled | ||
157 | * for use by xmon. | ||
158 | */ | ||
159 | #define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0) | ||
160 | #define PMAC_SCC_ASYNC 0 | ||
161 | #define PMAC_SCC_IRDA 1 | ||
162 | #define PMAC_SCC_I2S1 2 | ||
163 | #define PMAC_SCC_FLAG_XMON 0x00001000 | ||
164 | |||
165 | /* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value) | ||
166 | * enable/disable the internal modem. | ||
167 | */ | ||
168 | #define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1) | ||
169 | |||
170 | /* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value) | ||
171 | * enable/disable the swim3 (floppy) cell of a mac-io ASIC | ||
172 | */ | ||
173 | #define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2) | ||
174 | |||
175 | /* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value) | ||
176 | * enable/disable the mesh (scsi) cell of a mac-io ASIC | ||
177 | */ | ||
178 | #define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3) | ||
179 | |||
180 | /* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value) | ||
181 | * enable/disable an IDE port of a mac-io ASIC | ||
182 | * pass the busID parameter | ||
183 | */ | ||
184 | #define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4) | ||
185 | |||
186 | /* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value) | ||
187 | * assert(1)/release(0) an IDE reset line (mac-io IDE only) | ||
188 | */ | ||
189 | #define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5) | ||
190 | |||
191 | /* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value) | ||
192 | * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive | ||
193 | * it's reset line | ||
194 | */ | ||
195 | #define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6) | ||
196 | |||
197 | /* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value) | ||
198 | * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This | ||
199 | * control the cell's clock. | ||
200 | */ | ||
201 | #define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7) | ||
202 | |||
203 | /* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0) | ||
204 | * Perform a HW reset of the PHY connected to a gmac controller. | ||
205 | * Pass the gmac device node, not the PHY node. | ||
206 | */ | ||
207 | #define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8) | ||
208 | |||
209 | /* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value) | ||
210 | * enable/disable the sound chip, whatever it is and provided it can | ||
211 | * acually be controlled | ||
212 | */ | ||
213 | #define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9) | ||
214 | |||
215 | /* -- add various tweaks related to sound routing -- */ | ||
216 | |||
217 | /* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value) | ||
218 | * enable/disable the airport card | ||
219 | */ | ||
220 | #define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10) | ||
221 | |||
222 | /* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0) | ||
223 | * toggle the reset line of a CPU on an uninorth-based SMP machine | ||
224 | */ | ||
225 | #define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11) | ||
226 | |||
227 | /* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value) | ||
228 | * enable/disable an USB cell, along with the power of the USB "pad" | ||
229 | * on keylargo based machines | ||
230 | */ | ||
231 | #define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12) | ||
232 | |||
233 | /* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value) | ||
234 | * enable/disable the firewire cell of an uninorth ASIC. | ||
235 | */ | ||
236 | #define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13) | ||
237 | |||
238 | /* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value) | ||
239 | * enable/disable the firewire cable power supply of the uninorth | ||
240 | * firewire cell | ||
241 | */ | ||
242 | #define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14) | ||
243 | |||
244 | /* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value) | ||
245 | * set the sleep state of the motherboard. | ||
246 | * | ||
247 | * Pass -1 as value to query for sleep capability | ||
248 | * Pass 1 to set IOs to sleep | ||
249 | * Pass 0 to set IOs to wake | ||
250 | */ | ||
251 | #define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15) | ||
252 | |||
253 | /* PMAC_FTR_GET_MB_INFO (NULL, selector, 0) | ||
254 | * | ||
255 | * returns some motherboard infos. | ||
256 | * selector: 0 - model id | ||
257 | * 1 - model flags (capabilities) | ||
258 | * 2 - model name (cast to const char *) | ||
259 | */ | ||
260 | #define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16) | ||
261 | #define PMAC_MB_INFO_MODEL 0 | ||
262 | #define PMAC_MB_INFO_FLAGS 1 | ||
263 | #define PMAC_MB_INFO_NAME 2 | ||
264 | |||
265 | /* PMAC_FTR_READ_GPIO (NULL, int index, 0) | ||
266 | * | ||
267 | * read a GPIO from a mac-io controller of type KeyLargo or Pangea. | ||
268 | * the value returned is a byte (positive), or a negative error code | ||
269 | */ | ||
270 | #define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17) | ||
271 | |||
272 | /* PMAC_FTR_WRITE_GPIO (NULL, int index, int value) | ||
273 | * | ||
274 | * write a GPIO of a mac-io controller of type KeyLargo or Pangea. | ||
275 | */ | ||
276 | #define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18) | ||
277 | |||
278 | /* PMAC_FTR_ENABLE_MPIC | ||
279 | * | ||
280 | * Enable the MPIC cell | ||
281 | */ | ||
282 | #define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19) | ||
283 | |||
284 | /* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0) | ||
285 | * | ||
286 | * Enable/disable the AACK delay on the northbridge for systems using DFS | ||
287 | */ | ||
288 | #define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20) | ||
289 | |||
290 | /* PMAC_FTR_DEVICE_CAN_WAKE | ||
291 | * | ||
292 | * Used by video drivers to inform system that they can actually perform | ||
293 | * wakeup from sleep | ||
294 | */ | ||
295 | #define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22) | ||
296 | |||
297 | |||
298 | /* Don't use those directly, they are for the sake of pmac_setup.c */ | ||
299 | extern long pmac_do_feature_call(unsigned int selector, ...); | ||
300 | extern void pmac_feature_init(void); | ||
301 | |||
302 | /* Video suspend tweak */ | ||
303 | extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data); | ||
304 | extern void pmac_call_early_video_resume(void); | ||
305 | |||
306 | #define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x)) | ||
307 | |||
308 | |||
309 | /* | ||
310 | * The part below is for use by macio_asic.c only, do not rely | ||
311 | * on the data structures or constants below in a normal driver | ||
312 | * | ||
313 | */ | ||
314 | |||
315 | #define MAX_MACIO_CHIPS 2 | ||
316 | |||
317 | enum { | ||
318 | macio_unknown = 0, | ||
319 | macio_grand_central, | ||
320 | macio_ohare, | ||
321 | macio_ohareII, | ||
322 | macio_heathrow, | ||
323 | macio_gatwick, | ||
324 | macio_paddington, | ||
325 | macio_keylargo, | ||
326 | macio_pangea, | ||
327 | macio_intrepid, | ||
328 | macio_keylargo2, | ||
329 | }; | ||
330 | |||
331 | struct macio_chip | ||
332 | { | ||
333 | struct device_node *of_node; | ||
334 | int type; | ||
335 | const char *name; | ||
336 | int rev; | ||
337 | volatile u32 __iomem *base; | ||
338 | unsigned long flags; | ||
339 | |||
340 | /* For use by macio_asic PCI driver */ | ||
341 | struct macio_bus lbus; | ||
342 | }; | ||
343 | |||
344 | extern struct macio_chip macio_chips[MAX_MACIO_CHIPS]; | ||
345 | |||
346 | #define MACIO_FLAG_SCCA_ON 0x00000001 | ||
347 | #define MACIO_FLAG_SCCB_ON 0x00000002 | ||
348 | #define MACIO_FLAG_SCC_LOCKED 0x00000004 | ||
349 | #define MACIO_FLAG_AIRPORT_ON 0x00000010 | ||
350 | #define MACIO_FLAG_FW_SUPPORTED 0x00000020 | ||
351 | |||
352 | extern struct macio_chip* macio_find(struct device_node* child, int type); | ||
353 | |||
354 | #define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2)) | ||
355 | #define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r)) | ||
356 | |||
357 | #define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r))) | ||
358 | #define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v))) | ||
359 | #define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v))) | ||
360 | #define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v))) | ||
361 | #define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r))) | ||
362 | #define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v))) | ||
363 | |||
364 | #endif /* __PPC_ASM_PMAC_FEATURE_H */ | ||
365 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/pmac_low_i2c.h b/include/asm-ppc/pmac_low_i2c.h new file mode 100644 index 000000000000..809a5963d5e7 --- /dev/null +++ b/include/asm-ppc/pmac_low_i2c.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/pmac_low_i2c.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | #ifndef __PMAC_LOW_I2C_H__ | ||
13 | #define __PMAC_LOW_I2C_H__ | ||
14 | |||
15 | /* i2c mode (based on the platform functions format) */ | ||
16 | enum { | ||
17 | pmac_low_i2c_mode_dumb = 1, | ||
18 | pmac_low_i2c_mode_std = 2, | ||
19 | pmac_low_i2c_mode_stdsub = 3, | ||
20 | pmac_low_i2c_mode_combined = 4, | ||
21 | }; | ||
22 | |||
23 | /* RW bit in address */ | ||
24 | enum { | ||
25 | pmac_low_i2c_read = 0x01, | ||
26 | pmac_low_i2c_write = 0x00 | ||
27 | }; | ||
28 | |||
29 | /* Init, called early during boot */ | ||
30 | extern void pmac_init_low_i2c(void); | ||
31 | |||
32 | /* Locking functions exposed to i2c-keywest */ | ||
33 | int pmac_low_i2c_lock(struct device_node *np); | ||
34 | int pmac_low_i2c_unlock(struct device_node *np); | ||
35 | |||
36 | /* Access functions for platform code */ | ||
37 | int pmac_low_i2c_open(struct device_node *np, int channel); | ||
38 | int pmac_low_i2c_close(struct device_node *np); | ||
39 | int pmac_low_i2c_setmode(struct device_node *np, int mode); | ||
40 | int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len); | ||
41 | |||
42 | |||
43 | #endif /* __PMAC_LOW_I2C_H__ */ | ||
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h new file mode 100644 index 000000000000..6f6760b30dd8 --- /dev/null +++ b/include/asm-ppc/pnp.h | |||
@@ -0,0 +1,645 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | /* 11/02/95 */ | ||
3 | /*----------------------------------------------------------------------------*/ | ||
4 | /* Plug and Play header definitions */ | ||
5 | /*----------------------------------------------------------------------------*/ | ||
6 | |||
7 | /* Structure map for PnP on PowerPC Reference Platform */ | ||
8 | /* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ | ||
9 | /* (or later versions) is available on Compuserve in the PLUGPLAY area. */ | ||
10 | /* This code has extensions to that specification, namely new short and */ | ||
11 | /* long tag types for platform dependent information */ | ||
12 | |||
13 | /* Warning: LE notation used throughout this file */ | ||
14 | |||
15 | /* For enum's: if given in hex then they are bit significant, i.e. */ | ||
16 | /* only one bit is on for each enum */ | ||
17 | |||
18 | #ifndef _PNP_ | ||
19 | #define _PNP_ | ||
20 | |||
21 | #ifndef __ASSEMBLY__ | ||
22 | #define MAX_MEM_REGISTERS 9 | ||
23 | #define MAX_IO_PORTS 20 | ||
24 | #define MAX_IRQS 7 | ||
25 | /*#define MAX_DMA_CHANNELS 7*/ | ||
26 | |||
27 | /* Interrupt controllers */ | ||
28 | |||
29 | #define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ | ||
30 | #define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ | ||
31 | #define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ | ||
32 | #define PNPinterrupt3 "PNP0003" /* APIC */ | ||
33 | #define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ | ||
34 | |||
35 | /* Timers */ | ||
36 | |||
37 | #define PNPtimer0 "PNP0100" /* AT Timer */ | ||
38 | #define PNPtimer1 "PNP0101" /* EISA Timer */ | ||
39 | #define PNPtimer2 "PNP0102" /* MCA Timer */ | ||
40 | |||
41 | /* DMA controllers */ | ||
42 | |||
43 | #define PNPdma0 "PNP0200" /* AT DMA Controller */ | ||
44 | #define PNPdma1 "PNP0201" /* EISA DMA Controller */ | ||
45 | #define PNPdma2 "PNP0202" /* MCA DMA Controller */ | ||
46 | |||
47 | /* start of August 15, 1994 additions */ | ||
48 | /* CMOS */ | ||
49 | #define PNPCMOS "IBM0009" /* CMOS */ | ||
50 | |||
51 | /* L2 Cache */ | ||
52 | #define PNPL2 "IBM0007" /* L2 Cache */ | ||
53 | |||
54 | /* NVRAM */ | ||
55 | #define PNPNVRAM "IBM0008" /* NVRAM */ | ||
56 | |||
57 | /* Power Management */ | ||
58 | #define PNPPM "IBM0005" /* Power Management */ | ||
59 | /* end of August 15, 1994 additions */ | ||
60 | |||
61 | /* Keyboards */ | ||
62 | |||
63 | #define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ | ||
64 | #define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ | ||
65 | #define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ | ||
66 | #define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ | ||
67 | #define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ | ||
68 | #define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ | ||
69 | #define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ | ||
70 | #define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ | ||
71 | |||
72 | /* Parallel port controllers */ | ||
73 | |||
74 | #define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ | ||
75 | #define PNPparallel1 "PNP0401" /* ECP Parallel Port */ | ||
76 | #define PNPepp "IBM001C" /* EPP Parallel Port */ | ||
77 | |||
78 | /* Serial port controllers */ | ||
79 | |||
80 | #define PNPserial0 "PNP0500" /* Standard PC Serial port */ | ||
81 | #define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ | ||
82 | |||
83 | /* Disk controllers */ | ||
84 | |||
85 | #define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ | ||
86 | #define PNPdisk1 "PNP0601" /* Plus Hardcard II */ | ||
87 | #define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ | ||
88 | |||
89 | /* Diskette controllers */ | ||
90 | |||
91 | #define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ | ||
92 | |||
93 | /* Display controllers */ | ||
94 | |||
95 | #define PNPdisplay0 "PNP0900" /* VGA Compatible */ | ||
96 | #define PNPdisplay1 "PNP0901" /* Video Seven VGA */ | ||
97 | #define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ | ||
98 | #define PNPdisplay3 "PNP0903" /* Trident VGA */ | ||
99 | #define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ | ||
100 | #define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ | ||
101 | #define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ | ||
102 | #define PNPdisplay7 "PNP0907" /* Western Digital VGA */ | ||
103 | #define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ | ||
104 | #define PNPdisplay9 "PNP0909" /* S3 */ | ||
105 | #define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ | ||
106 | #define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ | ||
107 | #define PNPdisplayC "PNP090C" /* XGA Compatible */ | ||
108 | #define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ | ||
109 | #define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ | ||
110 | #define PNPdisplayF "PNP090F" /* Oak Technology VGA */ | ||
111 | |||
112 | /* Peripheral busses */ | ||
113 | |||
114 | #define PNPbuses0 "PNP0A00" /* ISA Bus */ | ||
115 | #define PNPbuses1 "PNP0A01" /* EISA Bus */ | ||
116 | #define PNPbuses2 "PNP0A02" /* MCA Bus */ | ||
117 | #define PNPbuses3 "PNP0A03" /* PCI Bus */ | ||
118 | #define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ | ||
119 | |||
120 | /* RTC, BIOS, planar devices */ | ||
121 | |||
122 | #define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ | ||
123 | #define PNPrtc0 "PNP0B00" /* AT RTC */ | ||
124 | #define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ | ||
125 | #define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ | ||
126 | #define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ | ||
127 | #define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ | ||
128 | |||
129 | /* PCMCIA controller */ | ||
130 | |||
131 | #define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ | ||
132 | |||
133 | /* Mice */ | ||
134 | |||
135 | #define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ | ||
136 | #define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ | ||
137 | #define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ | ||
138 | #define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ | ||
139 | #define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ | ||
140 | #define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ | ||
141 | #define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ | ||
142 | #define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ | ||
143 | #define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ | ||
144 | #define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ | ||
145 | #define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ | ||
146 | #define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ | ||
147 | |||
148 | /* Modems */ | ||
149 | |||
150 | #define PNPmodem0 "PNP9000" /* Specific IDs TBD */ | ||
151 | |||
152 | /* Network controllers */ | ||
153 | |||
154 | #define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ | ||
155 | #define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ | ||
156 | #define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ | ||
157 | #define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ | ||
158 | #define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ | ||
159 | #define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ | ||
160 | #define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ | ||
161 | #define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ | ||
162 | |||
163 | /* SCSI controllers */ | ||
164 | |||
165 | #define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ | ||
166 | #define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ | ||
167 | #define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ | ||
168 | #define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ | ||
169 | #define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ | ||
170 | #define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ | ||
171 | #define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ | ||
172 | |||
173 | /* Sound/Video, Multimedia */ | ||
174 | |||
175 | #define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ | ||
176 | #define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ | ||
177 | #define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ | ||
178 | #define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ | ||
179 | #define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ | ||
180 | #define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ | ||
181 | #define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ | ||
182 | #define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ | ||
183 | |||
184 | /* Operator Panel */ | ||
185 | #define PNPopctl "IBM000B" /* Operator's panel */ | ||
186 | |||
187 | /* Service Processor */ | ||
188 | #define PNPsp "IBM0011" /* IBM Service Processor */ | ||
189 | #define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ | ||
190 | #define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ | ||
191 | |||
192 | /* Memory Controller */ | ||
193 | #define PNPmemctl "IBM000A" /* Memory controller */ | ||
194 | |||
195 | /* Graphics Assist */ | ||
196 | #define PNPg_assist "IBM0014" /* Graphics Assist */ | ||
197 | |||
198 | /* Miscellaneous Device Controllers */ | ||
199 | #define PNPtablet "IBM0019" /* IBM Tablet Controller */ | ||
200 | |||
201 | /* PNP Packet Handles */ | ||
202 | |||
203 | #define S1_Packet 0x0A /* Version resource */ | ||
204 | #define S2_Packet 0x15 /* Logical DEVID (without flags) */ | ||
205 | #define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ | ||
206 | #define S3_Packet 0x1C /* Compatible device ID */ | ||
207 | #define S4_Packet 0x22 /* IRQ resource (without flags) */ | ||
208 | #define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ | ||
209 | #define S5_Packet 0x2A /* DMA resource */ | ||
210 | #define S6_Packet 0x30 /* Depend funct start (w/o priority) */ | ||
211 | #define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ | ||
212 | #define S7_Packet 0x38 /* Depend funct end */ | ||
213 | #define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ | ||
214 | #define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ | ||
215 | #define S14_Packet 0x71 /* Vendor defined */ | ||
216 | #define S15_Packet 0x78 /* End of resource (w/o checksum) */ | ||
217 | #define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ | ||
218 | #define L1_Packet 0x81 /* Memory range */ | ||
219 | #define L1_Shadow 0x20 /* Memory is shadowable */ | ||
220 | #define L1_32bit_mem 0x18 /* 32-bit memory only */ | ||
221 | #define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ | ||
222 | #define L1_Decode_Hi 0x04 /* decode supports high address */ | ||
223 | #define L1_Cache 0x02 /* read cacheable, write-through */ | ||
224 | #define L1_Writeable 0x01 /* Memory is writeable */ | ||
225 | #define L2_Packet 0x82 /* ANSI ID string */ | ||
226 | #define L3_Packet 0x83 /* Unicode ID string */ | ||
227 | #define L4_Packet 0x84 /* Vendor defined */ | ||
228 | #define L5_Packet 0x85 /* Large I/O */ | ||
229 | #define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ | ||
230 | #define END_TAG 0x78 /* End of resource */ | ||
231 | #define DF_START_TAG 0x30 /* Dependent function start */ | ||
232 | #define DF_START_TAG_priority 0x31 /* Dependent function start */ | ||
233 | #define DF_END_TAG 0x38 /* Dependent function end */ | ||
234 | #define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ | ||
235 | |||
236 | /* Device Base Type Codes */ | ||
237 | |||
238 | typedef enum _PnP_BASE_TYPE { | ||
239 | Reserved = 0, | ||
240 | MassStorageDevice = 1, | ||
241 | NetworkInterfaceController = 2, | ||
242 | DisplayController = 3, | ||
243 | MultimediaController = 4, | ||
244 | MemoryController = 5, | ||
245 | BridgeController = 6, | ||
246 | CommunicationsDevice = 7, | ||
247 | SystemPeripheral = 8, | ||
248 | InputDevice = 9, | ||
249 | ServiceProcessor = 0x0A, /* 11/2/95 */ | ||
250 | } PnP_BASE_TYPE; | ||
251 | |||
252 | /* Device Sub Type Codes */ | ||
253 | |||
254 | typedef enum _PnP_SUB_TYPE { | ||
255 | SCSIController = 0, | ||
256 | IDEController = 1, | ||
257 | FloppyController = 2, | ||
258 | IPIController = 3, | ||
259 | OtherMassStorageController = 0x80, | ||
260 | |||
261 | EthernetController = 0, | ||
262 | TokenRingController = 1, | ||
263 | FDDIController = 2, | ||
264 | OtherNetworkController = 0x80, | ||
265 | |||
266 | VGAController= 0, | ||
267 | SVGAController= 1, | ||
268 | XGAController= 2, | ||
269 | OtherDisplayController = 0x80, | ||
270 | |||
271 | VideoController = 0, | ||
272 | AudioController = 1, | ||
273 | OtherMultimediaController = 0x80, | ||
274 | |||
275 | RAM = 0, | ||
276 | FLASH = 1, | ||
277 | OtherMemoryDevice = 0x80, | ||
278 | |||
279 | HostProcessorBridge = 0, | ||
280 | ISABridge = 1, | ||
281 | EISABridge = 2, | ||
282 | MicroChannelBridge = 3, | ||
283 | PCIBridge = 4, | ||
284 | PCMCIABridge = 5, | ||
285 | VMEBridge = 6, | ||
286 | OtherBridgeDevice = 0x80, | ||
287 | |||
288 | RS232Device = 0, | ||
289 | ATCompatibleParallelPort = 1, | ||
290 | OtherCommunicationsDevice = 0x80, | ||
291 | |||
292 | ProgrammableInterruptController = 0, | ||
293 | DMAController = 1, | ||
294 | SystemTimer = 2, | ||
295 | RealTimeClock = 3, | ||
296 | L2Cache = 4, | ||
297 | NVRAM = 5, | ||
298 | PowerManagement = 6, | ||
299 | CMOS = 7, | ||
300 | OperatorPanel = 8, | ||
301 | ServiceProcessorClass1 = 9, | ||
302 | ServiceProcessorClass2 = 0xA, | ||
303 | ServiceProcessorClass3 = 0xB, | ||
304 | GraphicAssist = 0xC, | ||
305 | SystemPlanar = 0xF, /* 10/5/95 */ | ||
306 | OtherSystemPeripheral = 0x80, | ||
307 | |||
308 | KeyboardController = 0, | ||
309 | Digitizer = 1, | ||
310 | MouseController = 2, | ||
311 | TabletController = 3, /* 10/27/95 */ | ||
312 | OtherInputController = 0x80, | ||
313 | |||
314 | GeneralMemoryController = 0, | ||
315 | } PnP_SUB_TYPE; | ||
316 | |||
317 | /* Device Interface Type Codes */ | ||
318 | |||
319 | typedef enum _PnP_INTERFACE { | ||
320 | General = 0, | ||
321 | GeneralSCSI = 0, | ||
322 | GeneralIDE = 0, | ||
323 | ATACompatible = 1, | ||
324 | |||
325 | GeneralFloppy = 0, | ||
326 | Compatible765 = 1, | ||
327 | NS398_Floppy = 2, /* NS Super I/O wired to use index | ||
328 | register at port 398 and data | ||
329 | register at port 399 */ | ||
330 | NS26E_Floppy = 3, /* Ports 26E and 26F */ | ||
331 | NS15C_Floppy = 4, /* Ports 15C and 15D */ | ||
332 | NS2E_Floppy = 5, /* Ports 2E and 2F */ | ||
333 | CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ | ||
334 | |||
335 | GeneralIPI = 0, | ||
336 | |||
337 | GeneralEther = 0, | ||
338 | GeneralToken = 0, | ||
339 | GeneralFDDI = 0, | ||
340 | |||
341 | GeneralVGA = 0, | ||
342 | GeneralSVGA = 0, | ||
343 | GeneralXGA = 0, | ||
344 | |||
345 | GeneralVideo = 0, | ||
346 | GeneralAudio = 0, | ||
347 | CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ | ||
348 | |||
349 | GeneralRAM = 0, | ||
350 | GeneralFLASH = 0, | ||
351 | PCIMemoryController = 0, /* PCI Config Method */ | ||
352 | RS6KMemoryController = 1, /* RS6K Config Method */ | ||
353 | |||
354 | GeneralHostBridge = 0, | ||
355 | GeneralISABridge = 0, | ||
356 | GeneralEISABridge = 0, | ||
357 | GeneralMCABridge = 0, | ||
358 | GeneralPCIBridge = 0, | ||
359 | PCIBridgeDirect = 0, | ||
360 | PCIBridgeIndirect = 1, | ||
361 | PCIBridgeRS6K = 2, | ||
362 | GeneralPCMCIABridge = 0, | ||
363 | GeneralVMEBridge = 0, | ||
364 | |||
365 | GeneralRS232 = 0, | ||
366 | COMx = 1, | ||
367 | Compatible16450 = 2, | ||
368 | Compatible16550 = 3, | ||
369 | NS398SerPort = 4, /* NS Super I/O wired to use index | ||
370 | register at port 398 and data | ||
371 | register at port 399 */ | ||
372 | NS26ESerPort = 5, /* Ports 26E and 26F */ | ||
373 | NS15CSerPort = 6, /* Ports 15C and 15D */ | ||
374 | NS2ESerPort = 7, /* Ports 2E and 2F */ | ||
375 | |||
376 | GeneralParPort = 0, | ||
377 | LPTx = 1, | ||
378 | NS398ParPort = 2, /* NS Super I/O wired to use index | ||
379 | register at port 398 and data | ||
380 | register at port 399 */ | ||
381 | NS26EParPort = 3, /* Ports 26E and 26F */ | ||
382 | NS15CParPort = 4, /* Ports 15C and 15D */ | ||
383 | NS2EParPort = 5, /* Ports 2E and 2F */ | ||
384 | |||
385 | GeneralPIC = 0, | ||
386 | ISA_PIC = 1, | ||
387 | EISA_PIC = 2, | ||
388 | MPIC = 3, | ||
389 | RS6K_PIC = 4, | ||
390 | |||
391 | GeneralDMA = 0, | ||
392 | ISA_DMA = 1, | ||
393 | EISA_DMA = 2, | ||
394 | |||
395 | GeneralTimer = 0, | ||
396 | ISA_Timer = 1, | ||
397 | EISA_Timer = 2, | ||
398 | GeneralRTC = 0, | ||
399 | ISA_RTC = 1, | ||
400 | |||
401 | StoreThruOnly = 1, | ||
402 | StoreInEnabled = 2, | ||
403 | RS6KL2Cache = 3, | ||
404 | |||
405 | IndirectNVRAM = 0, /* Indirectly addressed */ | ||
406 | DirectNVRAM = 1, /* Memory Mapped */ | ||
407 | IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ | ||
408 | |||
409 | GeneralPowerManagement = 0, | ||
410 | EPOWPowerManagement = 1, | ||
411 | PowerControl = 2, // d1378 | ||
412 | |||
413 | GeneralCMOS = 0, | ||
414 | |||
415 | GeneralOPPanel = 0, | ||
416 | HarddiskLight = 1, | ||
417 | CDROMLight = 2, | ||
418 | PowerLight = 3, | ||
419 | KeyLock = 4, | ||
420 | ANDisplay = 5, /* AlphaNumeric Display */ | ||
421 | SystemStatusLED = 6, /* 3 digit 7 segment LED */ | ||
422 | CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ | ||
423 | |||
424 | GeneralServiceProcessor = 0, | ||
425 | |||
426 | TransferData = 1, | ||
427 | IGMC32 = 2, | ||
428 | IGMC64 = 3, | ||
429 | |||
430 | GeneralSystemPlanar = 0, /* 10/5/95 */ | ||
431 | |||
432 | } PnP_INTERFACE; | ||
433 | |||
434 | /* PnP resources */ | ||
435 | |||
436 | /* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ | ||
437 | |||
438 | typedef struct _SERIAL_ID { | ||
439 | unsigned char VendorID0; /* Bit(7)=0 */ | ||
440 | /* Bits(6:2)=1st character in */ | ||
441 | /* compressed ASCII */ | ||
442 | /* Bits(1:0)=2nd character in */ | ||
443 | /* compressed ASCII bits(4:3) */ | ||
444 | unsigned char VendorID1; /* Bits(7:5)=2nd character in */ | ||
445 | /* compressed ASCII bits(2:0) */ | ||
446 | /* Bits(4:0)=3rd character in */ | ||
447 | /* compressed ASCII */ | ||
448 | unsigned char VendorID2; /* Product number - vendor assigned */ | ||
449 | unsigned char VendorID3; /* Product number - vendor assigned */ | ||
450 | |||
451 | /* Serial number is to provide uniqueness if more than one board of same */ | ||
452 | /* type is in system. Must be "FFFFFFFF" if feature not supported. */ | ||
453 | |||
454 | unsigned char Serial0; /* Unique serial number bits (7:0) */ | ||
455 | unsigned char Serial1; /* Unique serial number bits (15:8) */ | ||
456 | unsigned char Serial2; /* Unique serial number bits (23:16) */ | ||
457 | unsigned char Serial3; /* Unique serial number bits (31:24) */ | ||
458 | unsigned char Checksum; | ||
459 | } SERIAL_ID; | ||
460 | |||
461 | typedef enum _PnPItemName { | ||
462 | Unused = 0, | ||
463 | PnPVersion = 1, | ||
464 | LogicalDevice = 2, | ||
465 | CompatibleDevice = 3, | ||
466 | IRQFormat = 4, | ||
467 | DMAFormat = 5, | ||
468 | StartDepFunc = 6, | ||
469 | EndDepFunc = 7, | ||
470 | IOPort = 8, | ||
471 | FixedIOPort = 9, | ||
472 | Res1 = 10, | ||
473 | Res2 = 11, | ||
474 | Res3 = 12, | ||
475 | SmallVendorItem = 14, | ||
476 | EndTag = 15, | ||
477 | MemoryRange = 1, | ||
478 | ANSIIdentifier = 2, | ||
479 | UnicodeIdentifier = 3, | ||
480 | LargeVendorItem = 4, | ||
481 | MemoryRange32 = 5, | ||
482 | MemoryRangeFixed32 = 6, | ||
483 | } PnPItemName; | ||
484 | |||
485 | /* Define a bunch of access functions for the bits in the tag field */ | ||
486 | |||
487 | /* Tag type - 0 = small; 1 = large */ | ||
488 | #define tag_type(t) (((t) & 0x80)>>7) | ||
489 | #define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) | ||
490 | |||
491 | /* Small item name is 4 bits - one of PnPItemName enum above */ | ||
492 | #define tag_small_item_name(t) (((t) & 0x78)>>3) | ||
493 | #define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) | ||
494 | |||
495 | /* Small item count is 3 bits - count of further bytes in packet */ | ||
496 | #define tag_small_count(t) ((t) & 0x07) | ||
497 | #define set_tag_count(t,v) (t = (t & 0x78) | (v)) | ||
498 | |||
499 | /* Large item name is 7 bits - one of PnPItemName enum above */ | ||
500 | #define tag_large_item_name(t) ((t) & 0x7f) | ||
501 | #define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) | ||
502 | |||
503 | /* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ | ||
504 | |||
505 | typedef union _PnP_TAG_PACKET { | ||
506 | struct _S1_Pack{ /* VERSION PACKET */ | ||
507 | unsigned char Tag; /* small tag = 0x0a */ | ||
508 | unsigned char Version[2]; /* PnP version, Vendor version */ | ||
509 | } S1_Pack; | ||
510 | |||
511 | struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ | ||
512 | unsigned char Tag; /* small tag = 0x15 or 0x16 */ | ||
513 | unsigned char DevId[4]; /* Logical device id */ | ||
514 | unsigned char Flags[2]; /* bit(0) boot device; */ | ||
515 | /* bit(7:1) cmd in range x31-x37 */ | ||
516 | /* bit(7:0) cmd in range x28-x3f (opt)*/ | ||
517 | } S2_Pack; | ||
518 | |||
519 | struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ | ||
520 | unsigned char Tag; /* small tag = 0x1c */ | ||
521 | unsigned char CompatId[4]; /* Compatible device id */ | ||
522 | } S3_Pack; | ||
523 | |||
524 | struct _S4_Pack{ /* IRQ PACKET */ | ||
525 | unsigned char Tag; /* small tag = 0x22 or 0x23 */ | ||
526 | unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ | ||
527 | /* bit(0) is IRQ8 ... */ | ||
528 | unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ | ||
529 | /* bit(0) - high true edge sensitive */ | ||
530 | /* bit(1) - low true edge sensitive */ | ||
531 | /* bit(2) - high true level sensitive*/ | ||
532 | /* bit(3) - low true level sensitive */ | ||
533 | /* bit(7:4) - must be 0 */ | ||
534 | } S4_Pack; | ||
535 | |||
536 | struct _S5_Pack{ /* DMA PACKET */ | ||
537 | unsigned char Tag; /* small tag = 0x2a */ | ||
538 | unsigned char DMAMask; /* bit(0) is channel 0 ... */ | ||
539 | unsigned char DMAInfo; | ||
540 | } S5_Pack; | ||
541 | |||
542 | struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ | ||
543 | unsigned char Tag; /* small tag = 0x30 or 0x31 */ | ||
544 | unsigned char Priority; /* Optional; if missing then x01; else*/ | ||
545 | /* x00 = best possible */ | ||
546 | /* x01 = acceptible */ | ||
547 | /* x02 = sub-optimal but functional */ | ||
548 | } S6_Pack; | ||
549 | |||
550 | struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ | ||
551 | unsigned char Tag; /* small tag = 0x38 */ | ||
552 | } S7_Pack; | ||
553 | |||
554 | struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ | ||
555 | unsigned char Tag; /* small tag x47 */ | ||
556 | unsigned char IOInfo; /* x0 = decode only bits(9:0); */ | ||
557 | #define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ | ||
558 | unsigned char RangeMin[2]; /* Min base address */ | ||
559 | unsigned char RangeMax[2]; /* Max base address */ | ||
560 | unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ | ||
561 | unsigned char IONum; /* number of contiguous I/O ports */ | ||
562 | } S8_Pack; | ||
563 | |||
564 | struct _S9_Pack{ /* FIXED I/O PORT PACKET */ | ||
565 | unsigned char Tag; /* small tag = 0x4b */ | ||
566 | unsigned char Range[2]; /* base address 10 bits */ | ||
567 | unsigned char IONum; /* number of contiguous I/O ports */ | ||
568 | } S9_Pack; | ||
569 | |||
570 | struct _S14_Pack{ /* VENDOR DEFINED PACKET */ | ||
571 | unsigned char Tag; /* small tag = 0x7m m = 1-7 */ | ||
572 | union _S14_Data{ | ||
573 | unsigned char Data[7]; /* Vendor defined */ | ||
574 | struct _S14_PPCPack{ /* Pr*p s14 pack */ | ||
575 | unsigned char Type; /* 00=non-IBM */ | ||
576 | unsigned char PPCData[6]; /* Vendor defined */ | ||
577 | } S14_PPCPack; | ||
578 | } S14_Data; | ||
579 | } S14_Pack; | ||
580 | |||
581 | struct _S15_Pack{ /* END PACKET */ | ||
582 | unsigned char Tag; /* small tag = 0x78 or 0x79 */ | ||
583 | unsigned char Check; /* optional - checksum */ | ||
584 | } S15_Pack; | ||
585 | |||
586 | struct _L1_Pack{ /* MEMORY RANGE PACKET */ | ||
587 | unsigned char Tag; /* large tag = 0x81 */ | ||
588 | unsigned char Count0; /* x09 */ | ||
589 | unsigned char Count1; /* x00 */ | ||
590 | unsigned char Data[9]; /* a variable array of bytes, */ | ||
591 | /* count in tag */ | ||
592 | } L1_Pack; | ||
593 | |||
594 | struct _L2_Pack{ /* ANSI ID STRING PACKET */ | ||
595 | unsigned char Tag; /* large tag = 0x82 */ | ||
596 | unsigned char Count0; /* Length of string */ | ||
597 | unsigned char Count1; | ||
598 | unsigned char Identifier[1]; /* a variable array of bytes, */ | ||
599 | /* count in tag */ | ||
600 | } L2_Pack; | ||
601 | |||
602 | struct _L3_Pack{ /* UNICODE ID STRING PACKET */ | ||
603 | unsigned char Tag; /* large tag = 0x83 */ | ||
604 | unsigned char Count0; /* Length + 2 of string */ | ||
605 | unsigned char Count1; | ||
606 | unsigned char Country0; /* TBD */ | ||
607 | unsigned char Country1; /* TBD */ | ||
608 | unsigned char Identifier[1]; /* a variable array of bytes, */ | ||
609 | /* count in tag */ | ||
610 | } L3_Pack; | ||
611 | |||
612 | struct _L4_Pack{ /* VENDOR DEFINED PACKET */ | ||
613 | unsigned char Tag; /* large tag = 0x84 */ | ||
614 | unsigned char Count0; | ||
615 | unsigned char Count1; | ||
616 | union _L4_Data{ | ||
617 | unsigned char Data[1]; /* a variable array of bytes, */ | ||
618 | /* count in tag */ | ||
619 | struct _L4_PPCPack{ /* Pr*p L4 packet */ | ||
620 | unsigned char Type; /* 00=non-IBM */ | ||
621 | unsigned char PPCData[1]; /* a variable array of bytes, */ | ||
622 | /* count in tag */ | ||
623 | } L4_PPCPack; | ||
624 | } L4_Data; | ||
625 | } L4_Pack; | ||
626 | |||
627 | struct _L5_Pack{ | ||
628 | unsigned char Tag; /* large tag = 0x85 */ | ||
629 | unsigned char Count0; /* Count = 17 */ | ||
630 | unsigned char Count1; | ||
631 | unsigned char Data[17]; | ||
632 | } L5_Pack; | ||
633 | |||
634 | struct _L6_Pack{ | ||
635 | unsigned char Tag; /* large tag = 0x86 */ | ||
636 | unsigned char Count0; /* Count = 9 */ | ||
637 | unsigned char Count1; | ||
638 | unsigned char Data[9]; | ||
639 | } L6_Pack; | ||
640 | |||
641 | } PnP_TAG_PACKET; | ||
642 | |||
643 | #endif /* __ASSEMBLY__ */ | ||
644 | #endif /* ndef _PNP_ */ | ||
645 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/poll.h b/include/asm-ppc/poll.h new file mode 100644 index 000000000000..be5024913c62 --- /dev/null +++ b/include/asm-ppc/poll.h | |||
@@ -0,0 +1,23 @@ | |||
1 | #ifndef __PPC_POLL_H | ||
2 | #define __PPC_POLL_H | ||
3 | |||
4 | #define POLLIN 0x0001 | ||
5 | #define POLLPRI 0x0002 | ||
6 | #define POLLOUT 0x0004 | ||
7 | #define POLLERR 0x0008 | ||
8 | #define POLLHUP 0x0010 | ||
9 | #define POLLNVAL 0x0020 | ||
10 | #define POLLRDNORM 0x0040 | ||
11 | #define POLLRDBAND 0x0080 | ||
12 | #define POLLWRNORM 0x0100 | ||
13 | #define POLLWRBAND 0x0200 | ||
14 | #define POLLMSG 0x0400 | ||
15 | #define POLLREMOVE 0x1000 | ||
16 | |||
17 | struct pollfd { | ||
18 | int fd; | ||
19 | short events; | ||
20 | short revents; | ||
21 | }; | ||
22 | |||
23 | #endif | ||
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h new file mode 100644 index 000000000000..a14a82abe8d2 --- /dev/null +++ b/include/asm-ppc/posix_types.h | |||
@@ -0,0 +1,111 @@ | |||
1 | #ifndef _PPC_POSIX_TYPES_H | ||
2 | #define _PPC_POSIX_TYPES_H | ||
3 | |||
4 | /* | ||
5 | * This file is generally used by user-level software, so you need to | ||
6 | * be a little careful about namespace pollution etc. Also, we cannot | ||
7 | * assume GCC is being used. | ||
8 | */ | ||
9 | |||
10 | typedef unsigned long __kernel_ino_t; | ||
11 | typedef unsigned int __kernel_mode_t; | ||
12 | typedef unsigned short __kernel_nlink_t; | ||
13 | typedef long __kernel_off_t; | ||
14 | typedef int __kernel_pid_t; | ||
15 | typedef unsigned int __kernel_uid_t; | ||
16 | typedef unsigned int __kernel_gid_t; | ||
17 | typedef unsigned int __kernel_size_t; | ||
18 | typedef int __kernel_ssize_t; | ||
19 | typedef long __kernel_ptrdiff_t; | ||
20 | typedef long __kernel_time_t; | ||
21 | typedef long __kernel_suseconds_t; | ||
22 | typedef long __kernel_clock_t; | ||
23 | typedef int __kernel_timer_t; | ||
24 | typedef int __kernel_clockid_t; | ||
25 | typedef int __kernel_daddr_t; | ||
26 | typedef char * __kernel_caddr_t; | ||
27 | typedef short __kernel_ipc_pid_t; | ||
28 | typedef unsigned short __kernel_uid16_t; | ||
29 | typedef unsigned short __kernel_gid16_t; | ||
30 | typedef unsigned int __kernel_uid32_t; | ||
31 | typedef unsigned int __kernel_gid32_t; | ||
32 | |||
33 | typedef unsigned int __kernel_old_uid_t; | ||
34 | typedef unsigned int __kernel_old_gid_t; | ||
35 | typedef unsigned int __kernel_old_dev_t; | ||
36 | |||
37 | #ifdef __GNUC__ | ||
38 | typedef long long __kernel_loff_t; | ||
39 | #endif | ||
40 | |||
41 | typedef struct { | ||
42 | int val[2]; | ||
43 | } __kernel_fsid_t; | ||
44 | |||
45 | #ifndef __GNUC__ | ||
46 | |||
47 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | ||
48 | #define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) | ||
49 | #define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) | ||
50 | #define __FD_ZERO(set) \ | ||
51 | ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set))) | ||
52 | |||
53 | #else /* __GNUC__ */ | ||
54 | |||
55 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ | ||
56 | || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) | ||
57 | /* With GNU C, use inline functions instead so args are evaluated only once: */ | ||
58 | |||
59 | #undef __FD_SET | ||
60 | static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) | ||
61 | { | ||
62 | unsigned long _tmp = fd / __NFDBITS; | ||
63 | unsigned long _rem = fd % __NFDBITS; | ||
64 | fdsetp->fds_bits[_tmp] |= (1UL<<_rem); | ||
65 | } | ||
66 | |||
67 | #undef __FD_CLR | ||
68 | static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp) | ||
69 | { | ||
70 | unsigned long _tmp = fd / __NFDBITS; | ||
71 | unsigned long _rem = fd % __NFDBITS; | ||
72 | fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem); | ||
73 | } | ||
74 | |||
75 | #undef __FD_ISSET | ||
76 | static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p) | ||
77 | { | ||
78 | unsigned long _tmp = fd / __NFDBITS; | ||
79 | unsigned long _rem = fd % __NFDBITS; | ||
80 | return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0; | ||
81 | } | ||
82 | |||
83 | /* | ||
84 | * This will unroll the loop for the normal constant case (8 ints, | ||
85 | * for a 256-bit fd_set) | ||
86 | */ | ||
87 | #undef __FD_ZERO | ||
88 | static __inline__ void __FD_ZERO(__kernel_fd_set *p) | ||
89 | { | ||
90 | unsigned int *tmp = (unsigned int *)p->fds_bits; | ||
91 | int i; | ||
92 | |||
93 | if (__builtin_constant_p(__FDSET_LONGS)) { | ||
94 | switch (__FDSET_LONGS) { | ||
95 | case 8: | ||
96 | tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0; | ||
97 | tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0; | ||
98 | return; | ||
99 | } | ||
100 | } | ||
101 | i = __FDSET_LONGS; | ||
102 | while (i) { | ||
103 | i--; | ||
104 | *tmp = 0; | ||
105 | tmp++; | ||
106 | } | ||
107 | } | ||
108 | |||
109 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | ||
110 | #endif /* __GNUC__ */ | ||
111 | #endif /* _PPC_POSIX_TYPES_H */ | ||
diff --git a/include/asm-ppc/ppc4xx_dma.h b/include/asm-ppc/ppc4xx_dma.h new file mode 100644 index 000000000000..8636cdbf6f8f --- /dev/null +++ b/include/asm-ppc/ppc4xx_dma.h | |||
@@ -0,0 +1,583 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ppc4xx_dma.h | ||
3 | * | ||
4 | * IBM PPC4xx DMA engine library | ||
5 | * | ||
6 | * Copyright 2000-2004 MontaVista Software Inc. | ||
7 | * | ||
8 | * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org> | ||
9 | * | ||
10 | * Original code by Armin Kuster <akuster@mvista.com> | ||
11 | * and Pete Popov <ppopov@mvista.com> | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify it | ||
14 | * under the terms of the GNU General Public License as published by the | ||
15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
16 | * option) any later version. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #ifdef __KERNEL__ | ||
24 | #ifndef __ASMPPC_PPC4xx_DMA_H | ||
25 | #define __ASMPPC_PPC4xx_DMA_H | ||
26 | |||
27 | #include <linux/config.h> | ||
28 | #include <linux/types.h> | ||
29 | #include <asm/mmu.h> | ||
30 | #include <asm/ibm4xx.h> | ||
31 | |||
32 | #undef DEBUG_4xxDMA | ||
33 | |||
34 | #define MAX_PPC4xx_DMA_CHANNELS 4 | ||
35 | |||
36 | /* in arch/ppc/kernel/setup.c -- Cort */ | ||
37 | extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; | ||
38 | |||
39 | /* | ||
40 | * Function return status codes | ||
41 | * These values are used to indicate whether or not the function | ||
42 | * call was successful, or a bad/invalid parameter was passed. | ||
43 | */ | ||
44 | #define DMA_STATUS_GOOD 0 | ||
45 | #define DMA_STATUS_BAD_CHANNEL 1 | ||
46 | #define DMA_STATUS_BAD_HANDLE 2 | ||
47 | #define DMA_STATUS_BAD_MODE 3 | ||
48 | #define DMA_STATUS_NULL_POINTER 4 | ||
49 | #define DMA_STATUS_OUT_OF_MEMORY 5 | ||
50 | #define DMA_STATUS_SGL_LIST_EMPTY 6 | ||
51 | #define DMA_STATUS_GENERAL_ERROR 7 | ||
52 | #define DMA_STATUS_CHANNEL_NOTFREE 8 | ||
53 | |||
54 | #define DMA_CHANNEL_BUSY 0x80000000 | ||
55 | |||
56 | /* | ||
57 | * These indicate status as returned from the DMA Status Register. | ||
58 | */ | ||
59 | #define DMA_STATUS_NO_ERROR 0 | ||
60 | #define DMA_STATUS_CS 1 /* Count Status */ | ||
61 | #define DMA_STATUS_TS 2 /* Transfer Status */ | ||
62 | #define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ | ||
63 | #define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ | ||
64 | |||
65 | |||
66 | /* | ||
67 | * DMA Channel Control Registers | ||
68 | */ | ||
69 | |||
70 | #ifdef CONFIG_44x | ||
71 | #define PPC4xx_DMA_64BIT | ||
72 | #define DMA_CR_OFFSET 1 | ||
73 | #else | ||
74 | #define DMA_CR_OFFSET 0 | ||
75 | #endif | ||
76 | |||
77 | #define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */ | ||
78 | #define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31) | ||
79 | #define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31) | ||
80 | |||
81 | #define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ | ||
82 | #define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) | ||
83 | #define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) | ||
84 | |||
85 | #define DMA_TD (1<<29) | ||
86 | #define SET_DMA_TD(x) (((x)&0x1)<<29) | ||
87 | #define GET_DMA_TD(x) (((x)&DMA_TD)>>29) | ||
88 | |||
89 | #define DMA_PL (1<<28) /* Peripheral Location */ | ||
90 | #define SET_DMA_PL(x) (((x)&0x1)<<28) | ||
91 | #define GET_DMA_PL(x) (((x)&DMA_PL)>>28) | ||
92 | |||
93 | #define EXTERNAL_PERIPHERAL 0 | ||
94 | #define INTERNAL_PERIPHERAL 1 | ||
95 | |||
96 | #define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */ | ||
97 | #define DMA_PW_MASK SET_DMA_PW(3) | ||
98 | #define PW_8 0 | ||
99 | #define PW_16 1 | ||
100 | #define PW_32 2 | ||
101 | #define PW_64 3 | ||
102 | /* FIXME: Add PW_128 support for 440GP DMA block */ | ||
103 | #define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET)) | ||
104 | |||
105 | #define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */ | ||
106 | #define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET)) | ||
107 | |||
108 | #define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */ | ||
109 | #define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET)) | ||
110 | |||
111 | #define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */ | ||
112 | #define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET)) | ||
113 | |||
114 | #define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */ | ||
115 | #define DMA_TM_MASK SET_DMA_TM(3) | ||
116 | #define TM_PERIPHERAL 0 /* Peripheral */ | ||
117 | #define TM_RESERVED 1 /* Reserved */ | ||
118 | #define TM_S_MM 2 /* Memory to Memory */ | ||
119 | #define TM_D_MM 3 /* Device Paced Memory to Memory */ | ||
120 | #define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET)) | ||
121 | |||
122 | #define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */ | ||
123 | #define DMA_PSC_MASK SET_DMA_PSC(3) | ||
124 | #define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET)) | ||
125 | |||
126 | #define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */ | ||
127 | #define DMA_PWC_MASK SET_DMA_PWC(0x3F) | ||
128 | #define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET)) | ||
129 | |||
130 | #define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */ | ||
131 | #define DMA_PHC_MASK SET_DMA_PHC(0x7) | ||
132 | #define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET)) | ||
133 | |||
134 | #define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */ | ||
135 | #define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET)) | ||
136 | |||
137 | #define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET)) | ||
138 | #define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET)) | ||
139 | |||
140 | #define DMA_DEC (1<<(2)) /* Address Decrement */ | ||
141 | #define SET_DMA_DEC(x) (((x)&0x1)<<2) | ||
142 | #define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) | ||
143 | |||
144 | |||
145 | /* | ||
146 | * Transfer Modes | ||
147 | * These modes are defined in a way that makes it possible to | ||
148 | * simply "or" in the value in the control register. | ||
149 | */ | ||
150 | |||
151 | #define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ | ||
152 | |||
153 | /* Device-paced memory to memory, */ | ||
154 | /* device is at source address */ | ||
155 | #define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) | ||
156 | |||
157 | /* Device-paced memory to memory, */ | ||
158 | /* device is at destination address */ | ||
159 | #define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) | ||
160 | |||
161 | /* 405gp/440gp */ | ||
162 | #define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */ | ||
163 | #define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) | ||
164 | #define PREFETCH_1 0 /* Prefetch 1 Double Word */ | ||
165 | #define PREFETCH_2 1 | ||
166 | #define PREFETCH_4 2 | ||
167 | #define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET)) | ||
168 | |||
169 | #define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */ | ||
170 | #define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET)) | ||
171 | #define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET)) | ||
172 | |||
173 | /* stb3x */ | ||
174 | |||
175 | #define DMA_ECE_ENABLE (1<<5) | ||
176 | #define SET_DMA_ECE(x) (((x)&0x1)<<5) | ||
177 | #define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5) | ||
178 | |||
179 | #define DMA_TCD_DISABLE (1<<4) | ||
180 | #define SET_DMA_TCD(x) (((x)&0x1)<<4) | ||
181 | #define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4) | ||
182 | |||
183 | typedef uint32_t sgl_handle_t; | ||
184 | |||
185 | #ifdef CONFIG_PPC4xx_EDMA | ||
186 | |||
187 | #define SGL_LIST_SIZE 4096 | ||
188 | #define DMA_PPC4xx_SIZE SGL_LIST_SIZE | ||
189 | |||
190 | #define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */ | ||
191 | #define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) | ||
192 | #define PRIORITY_LOW 0 | ||
193 | #define PRIORITY_MID_LOW 1 | ||
194 | #define PRIORITY_MID_HIGH 2 | ||
195 | #define PRIORITY_HIGH 3 | ||
196 | #define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET)) | ||
197 | |||
198 | /* | ||
199 | * DMA Polarity Configuration Register | ||
200 | */ | ||
201 | #define DMAReq_ActiveLow(chan) (1<<(31-(chan*3))) | ||
202 | #define DMAAck_ActiveLow(chan) (1<<(30-(chan*3))) | ||
203 | #define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */ | ||
204 | |||
205 | /* | ||
206 | * DMA Sleep Mode Register | ||
207 | */ | ||
208 | #define SLEEP_MODE_ENABLE (1<<21) | ||
209 | |||
210 | /* | ||
211 | * DMA Status Register | ||
212 | */ | ||
213 | #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ | ||
214 | #define DMA_CS1 (1<<30) | ||
215 | #define DMA_CS2 (1<<29) | ||
216 | #define DMA_CS3 (1<<28) | ||
217 | |||
218 | #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ | ||
219 | #define DMA_TS1 (1<<26) | ||
220 | #define DMA_TS2 (1<<25) | ||
221 | #define DMA_TS3 (1<<24) | ||
222 | |||
223 | #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ | ||
224 | #define DMA_CH1_ERR (1<<22) | ||
225 | #define DMA_CH2_ERR (1<<21) | ||
226 | #define DMA_CH3_ERR (1<<20) | ||
227 | |||
228 | #define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ | ||
229 | #define DMA_IN_DMA_REQ1 (1<<18) | ||
230 | #define DMA_IN_DMA_REQ2 (1<<17) | ||
231 | #define DMA_IN_DMA_REQ3 (1<<16) | ||
232 | |||
233 | #define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ | ||
234 | #define DMA_EXT_DMA_REQ1 (1<<14) | ||
235 | #define DMA_EXT_DMA_REQ2 (1<<13) | ||
236 | #define DMA_EXT_DMA_REQ3 (1<<12) | ||
237 | |||
238 | #define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ | ||
239 | #define DMA_CH1_BUSY (1<<10) | ||
240 | #define DMA_CH2_BUSY (1<<9) | ||
241 | #define DMA_CH3_BUSY (1<<8) | ||
242 | |||
243 | #define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ | ||
244 | #define DMA_SG1 (1<<6) | ||
245 | #define DMA_SG2 (1<<5) | ||
246 | #define DMA_SG3 (1<<4) | ||
247 | |||
248 | /* DMA Channel Count Register */ | ||
249 | #define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */ | ||
250 | #define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */ | ||
251 | #define DMA_CTC_BSIZ_2 (0) | ||
252 | #define DMA_CTC_BSIZ_4 (1<<21) | ||
253 | #define DMA_CTC_BSIZ_8 (2<<21) | ||
254 | #define DMA_CTC_BSIZ_16 (3<<21) | ||
255 | |||
256 | /* | ||
257 | * DMA SG Command Register | ||
258 | */ | ||
259 | #define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */ | ||
260 | #define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */ | ||
261 | |||
262 | /* | ||
263 | * DMA Scatter/Gather Descriptor Bit fields | ||
264 | */ | ||
265 | #define SG_LINK (1<<31) /* Link */ | ||
266 | #define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ | ||
267 | #define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ | ||
268 | #define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ | ||
269 | #define SG_COUNT_MASK 0xFFFF /* Count Field */ | ||
270 | |||
271 | #define SET_DMA_CONTROL \ | ||
272 | (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ | ||
273 | SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\ | ||
274 | SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ | ||
275 | SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ | ||
276 | SET_DMA_PL(p_init->pl) | /* peripheral location */ \ | ||
277 | SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ | ||
278 | SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ | ||
279 | SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ | ||
280 | SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ | ||
281 | SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ | ||
282 | SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ | ||
283 | SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ | ||
284 | SET_DMA_PREFETCH(p_init->pf) /* read prefetch */) | ||
285 | |||
286 | #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan)) | ||
287 | |||
288 | #elif defined(CONFIG_STBXXX_DMA) /* stb03xxx */ | ||
289 | |||
290 | #define DMA_PPC4xx_SIZE 4096 | ||
291 | |||
292 | /* | ||
293 | * DMA Status Register | ||
294 | */ | ||
295 | |||
296 | #define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */ | ||
297 | #define DMA_PRIORITY_MASK 0x00800001 | ||
298 | #define PRIORITY_LOW 0x00000000 | ||
299 | #define PRIORITY_MID_LOW 0x00000001 | ||
300 | #define PRIORITY_MID_HIGH 0x00800000 | ||
301 | #define PRIORITY_HIGH 0x00800001 | ||
302 | #define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001)) | ||
303 | |||
304 | #define DMA_CS0 (1<<31) /* Terminal Count has been reached */ | ||
305 | #define DMA_CS1 (1<<30) | ||
306 | #define DMA_CS2 (1<<29) | ||
307 | #define DMA_CS3 (1<<28) | ||
308 | |||
309 | #define DMA_TS0 (1<<27) /* End of Transfer has been requested */ | ||
310 | #define DMA_TS1 (1<<26) | ||
311 | #define DMA_TS2 (1<<25) | ||
312 | #define DMA_TS3 (1<<24) | ||
313 | |||
314 | #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ | ||
315 | #define DMA_CH1_ERR (1<<22) | ||
316 | #define DMA_CH2_ERR (1<<21) | ||
317 | #define DMA_CH3_ERR (1<<20) | ||
318 | |||
319 | #define DMA_CT0 (1<<19) /* Chained transfere */ | ||
320 | |||
321 | #define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */ | ||
322 | #define DMA_IN_DMA_REQ1 (1<<17) | ||
323 | #define DMA_IN_DMA_REQ2 (1<<16) | ||
324 | #define DMA_IN_DMA_REQ3 (1<<15) | ||
325 | |||
326 | #define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */ | ||
327 | #define DMA_EXT_DMA_REQ1 (1<<13) | ||
328 | #define DMA_EXT_DMA_REQ2 (1<<12) | ||
329 | #define DMA_EXT_DMA_REQ3 (1<<11) | ||
330 | |||
331 | #define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */ | ||
332 | #define DMA_CH1_BUSY (1<<9) | ||
333 | #define DMA_CH2_BUSY (1<<8) | ||
334 | #define DMA_CH3_BUSY (1<<7) | ||
335 | |||
336 | #define DMA_CT1 (1<<6) /* Chained transfere */ | ||
337 | #define DMA_CT2 (1<<5) | ||
338 | #define DMA_CT3 (1<<4) | ||
339 | |||
340 | #define DMA_CH_ENABLE (1<<7) | ||
341 | #define SET_DMA_CH(x) (((x)&0x1)<<7) | ||
342 | #define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7) | ||
343 | |||
344 | /* STBx25xxx dma unique */ | ||
345 | /* enable device port on a dma channel | ||
346 | * example ext 0 on dma 1 | ||
347 | */ | ||
348 | |||
349 | #define SSP0_RECV 15 | ||
350 | #define SSP0_XMIT 14 | ||
351 | #define EXT_DMA_0 12 | ||
352 | #define SC1_XMIT 11 | ||
353 | #define SC1_RECV 10 | ||
354 | #define EXT_DMA_2 9 | ||
355 | #define EXT_DMA_3 8 | ||
356 | #define SERIAL2_XMIT 7 | ||
357 | #define SERIAL2_RECV 6 | ||
358 | #define SC0_XMIT 5 | ||
359 | #define SC0_RECV 4 | ||
360 | #define SERIAL1_XMIT 3 | ||
361 | #define SERIAL1_RECV 2 | ||
362 | #define SERIAL0_XMIT 1 | ||
363 | #define SERIAL0_RECV 0 | ||
364 | |||
365 | #define DMA_CHAN_0 1 | ||
366 | #define DMA_CHAN_1 2 | ||
367 | #define DMA_CHAN_2 3 | ||
368 | #define DMA_CHAN_3 4 | ||
369 | |||
370 | /* end STBx25xx */ | ||
371 | |||
372 | /* | ||
373 | * Bit 30 must be one for Redwoods, otherwise transfers may receive errors. | ||
374 | */ | ||
375 | #define DMA_CR_MB0 0x2 | ||
376 | |||
377 | #define SET_DMA_CONTROL \ | ||
378 | (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \ | ||
379 | SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \ | ||
380 | SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \ | ||
381 | SET_DMA_PL(p_init->pl) | /* peripheral location */ \ | ||
382 | SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \ | ||
383 | SET_DMA_SAI(p_init->sai) | /* src addr increment */ \ | ||
384 | SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \ | ||
385 | SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \ | ||
386 | SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \ | ||
387 | SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \ | ||
388 | SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \ | ||
389 | SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \ | ||
390 | SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \ | ||
391 | SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \ | ||
392 | DMA_CR_MB0 /* must be one */) | ||
393 | |||
394 | #define GET_DMA_POLARITY(chan) chan | ||
395 | |||
396 | #endif | ||
397 | |||
398 | typedef struct { | ||
399 | unsigned short in_use; /* set when channel is being used, clr when | ||
400 | * available. | ||
401 | */ | ||
402 | /* | ||
403 | * Valid polarity settings: | ||
404 | * DMAReq_ActiveLow(n) | ||
405 | * DMAAck_ActiveLow(n) | ||
406 | * EOT_ActiveLow(n) | ||
407 | * | ||
408 | * n is 0 to max dma chans | ||
409 | */ | ||
410 | unsigned int polarity; | ||
411 | |||
412 | char buffer_enable; /* Boolean: buffer enable */ | ||
413 | char tce_enable; /* Boolean: terminal count enable */ | ||
414 | char etd_output; /* Boolean: eot pin is a tc output */ | ||
415 | char pce; /* Boolean: parity check enable */ | ||
416 | |||
417 | /* | ||
418 | * Peripheral location: | ||
419 | * INTERNAL_PERIPHERAL (UART0 on the 405GP) | ||
420 | * EXTERNAL_PERIPHERAL | ||
421 | */ | ||
422 | char pl; /* internal/external peripheral */ | ||
423 | |||
424 | /* | ||
425 | * Valid pwidth settings: | ||
426 | * PW_8 | ||
427 | * PW_16 | ||
428 | * PW_32 | ||
429 | * PW_64 | ||
430 | */ | ||
431 | unsigned int pwidth; | ||
432 | |||
433 | char dai; /* Boolean: dst address increment */ | ||
434 | char sai; /* Boolean: src address increment */ | ||
435 | |||
436 | /* | ||
437 | * Valid psc settings: 0-3 | ||
438 | */ | ||
439 | unsigned int psc; /* Peripheral Setup Cycles */ | ||
440 | |||
441 | /* | ||
442 | * Valid pwc settings: | ||
443 | * 0-63 | ||
444 | */ | ||
445 | unsigned int pwc; /* Peripheral Wait Cycles */ | ||
446 | |||
447 | /* | ||
448 | * Valid phc settings: | ||
449 | * 0-7 | ||
450 | */ | ||
451 | unsigned int phc; /* Peripheral Hold Cycles */ | ||
452 | |||
453 | /* | ||
454 | * Valid cp (channel priority) settings: | ||
455 | * PRIORITY_LOW | ||
456 | * PRIORITY_MID_LOW | ||
457 | * PRIORITY_MID_HIGH | ||
458 | * PRIORITY_HIGH | ||
459 | */ | ||
460 | unsigned int cp; /* channel priority */ | ||
461 | |||
462 | /* | ||
463 | * Valid pf (memory read prefetch) settings: | ||
464 | * | ||
465 | * PREFETCH_1 | ||
466 | * PREFETCH_2 | ||
467 | * PREFETCH_4 | ||
468 | */ | ||
469 | unsigned int pf; /* memory read prefetch */ | ||
470 | |||
471 | /* | ||
472 | * Boolean: channel interrupt enable | ||
473 | * NOTE: for sgl transfers, only the last descriptor will be setup to | ||
474 | * interrupt. | ||
475 | */ | ||
476 | char int_enable; | ||
477 | |||
478 | char shift; /* easy access to byte_count shift, based on */ | ||
479 | /* the width of the channel */ | ||
480 | |||
481 | uint32_t control; /* channel control word */ | ||
482 | |||
483 | /* These variabled are used ONLY in single dma transfers */ | ||
484 | unsigned int mode; /* transfer mode */ | ||
485 | phys_addr_t addr; | ||
486 | char ce; /* channel enable */ | ||
487 | #ifdef CONFIG_STB03xxx | ||
488 | char ch_enable; | ||
489 | char tcd_disable; | ||
490 | char ece_enable; | ||
491 | char td; /* transfer direction */ | ||
492 | #endif | ||
493 | |||
494 | char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */ | ||
495 | } ppc_dma_ch_t; | ||
496 | |||
497 | /* | ||
498 | * PPC44x DMA implementations have a slightly different | ||
499 | * descriptor layout. Probably moved about due to the | ||
500 | * change to 64-bit addresses and link pointer. I don't | ||
501 | * know why they didn't just leave control_count after | ||
502 | * the dst_addr. | ||
503 | */ | ||
504 | #ifdef PPC4xx_DMA_64BIT | ||
505 | typedef struct { | ||
506 | uint32_t control; | ||
507 | uint32_t control_count; | ||
508 | phys_addr_t src_addr; | ||
509 | phys_addr_t dst_addr; | ||
510 | phys_addr_t next; | ||
511 | } ppc_sgl_t; | ||
512 | #else | ||
513 | typedef struct { | ||
514 | uint32_t control; | ||
515 | phys_addr_t src_addr; | ||
516 | phys_addr_t dst_addr; | ||
517 | uint32_t control_count; | ||
518 | uint32_t next; | ||
519 | } ppc_sgl_t; | ||
520 | #endif | ||
521 | |||
522 | typedef struct { | ||
523 | unsigned int dmanr; | ||
524 | uint32_t control; /* channel ctrl word; loaded from each descrptr */ | ||
525 | uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ | ||
526 | dma_addr_t dma_addr; /* dma (physical) address of this list */ | ||
527 | ppc_sgl_t *phead; | ||
528 | dma_addr_t phead_dma; | ||
529 | ppc_sgl_t *ptail; | ||
530 | dma_addr_t ptail_dma; | ||
531 | } sgl_list_info_t; | ||
532 | |||
533 | typedef struct { | ||
534 | phys_addr_t *src_addr; | ||
535 | phys_addr_t *dst_addr; | ||
536 | phys_addr_t dma_src_addr; | ||
537 | phys_addr_t dma_dst_addr; | ||
538 | } pci_alloc_desc_t; | ||
539 | |||
540 | extern ppc_dma_ch_t dma_channels[]; | ||
541 | |||
542 | /* | ||
543 | * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c | ||
544 | */ | ||
545 | extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *); | ||
546 | extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *); | ||
547 | extern int ppc4xx_set_channel_priority(unsigned int, unsigned int); | ||
548 | extern unsigned int ppc4xx_get_peripheral_width(unsigned int); | ||
549 | extern void ppc4xx_set_sg_addr(int, phys_addr_t); | ||
550 | extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int); | ||
551 | extern void ppc4xx_enable_dma_sgl(sgl_handle_t); | ||
552 | extern void ppc4xx_disable_dma_sgl(sgl_handle_t); | ||
553 | extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *); | ||
554 | extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *); | ||
555 | extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); | ||
556 | extern void ppc4xx_free_dma_handle(sgl_handle_t); | ||
557 | extern int ppc4xx_get_dma_status(void); | ||
558 | extern int ppc4xx_enable_burst(unsigned int); | ||
559 | extern int ppc4xx_disable_burst(unsigned int); | ||
560 | extern int ppc4xx_set_burst_size(unsigned int, unsigned int); | ||
561 | extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr); | ||
562 | extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr); | ||
563 | extern void ppc4xx_enable_dma(unsigned int dmanr); | ||
564 | extern void ppc4xx_disable_dma(unsigned int dmanr); | ||
565 | extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count); | ||
566 | extern int ppc4xx_get_dma_residue(unsigned int dmanr); | ||
567 | extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr, | ||
568 | phys_addr_t dst_dma_addr); | ||
569 | extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr); | ||
570 | extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr); | ||
571 | extern int ppc4xx_clr_dma_status(unsigned int dmanr); | ||
572 | extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); | ||
573 | extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan); | ||
574 | extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode); | ||
575 | |||
576 | /* These are in kernel/dma.c: */ | ||
577 | |||
578 | /* reserve a DMA channel */ | ||
579 | extern int request_dma(unsigned int dmanr, const char *device_id); | ||
580 | /* release it again */ | ||
581 | extern void free_dma(unsigned int dmanr); | ||
582 | #endif | ||
583 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h new file mode 100644 index 000000000000..c16c7f81cfd8 --- /dev/null +++ b/include/asm-ppc/ppc4xx_pic.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ppc4xx_pic.h | ||
3 | * | ||
4 | * Interrupt controller driver for PowerPC 4xx-based processors. | ||
5 | * | ||
6 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | ||
7 | * | ||
8 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | ||
9 | * Copyright (c) 2004 Zultys Technologies | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify it | ||
12 | * under the terms of the GNU General Public License as published by the | ||
13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
14 | * option) any later version. | ||
15 | */ | ||
16 | |||
17 | #ifndef __PPC4XX_PIC_H__ | ||
18 | #define __PPC4XX_PIC_H__ | ||
19 | |||
20 | #include <linux/config.h> | ||
21 | #include <linux/types.h> | ||
22 | #include <linux/irq.h> | ||
23 | |||
24 | /* "Fixed" UIC settings (they are chip, not board specific), | ||
25 | * e.g. polarity/triggerring for internal interrupt sources. | ||
26 | * | ||
27 | * Platform port should provide NR_UICS-sized array named ppc4xx_core_uic_cfg | ||
28 | * with these "fixed" settings: .polarity contains exact value which will | ||
29 | * be written (masked with "ext_irq_mask") into UICx_PR register, | ||
30 | * .triggering - to UICx_TR. | ||
31 | * | ||
32 | * Settings for external IRQs can be specified separately by the | ||
33 | * board support code. In this case properly sized array of unsigned | ||
34 | * char named ppc4xx_uic_ext_irq_cfg should be filled with correct | ||
35 | * values using IRQ_SENSE_XXXXX and IRQ_POLARITY_XXXXXXX defines. | ||
36 | * | ||
37 | * If these arrays aren't provided, UIC initialization code keeps firmware | ||
38 | * configuration. Also, ppc4xx_uic_ext_irq_cfg implies ppc4xx_core_uic_cfg | ||
39 | * is defined. | ||
40 | * | ||
41 | * Both ppc4xx_core_uic_cfg and ppc4xx_uic_ext_irq_cfg are declared as | ||
42 | * "weak" symbols in ppc4xx_pic.c | ||
43 | * | ||
44 | */ | ||
45 | struct ppc4xx_uic_settings { | ||
46 | u32 polarity; | ||
47 | u32 triggering; | ||
48 | u32 ext_irq_mask; | ||
49 | }; | ||
50 | |||
51 | extern void ppc4xx_pic_init(void); | ||
52 | |||
53 | #endif /* __PPC4XX_PIC_H__ */ | ||
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h new file mode 100644 index 000000000000..13fa8e7483c1 --- /dev/null +++ b/include/asm-ppc/ppc_asm.h | |||
@@ -0,0 +1,342 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ppc_asm.h | ||
3 | * | ||
4 | * Definitions used by various bits of low-level assembly code on PowerPC. | ||
5 | * | ||
6 | * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License | ||
10 | * as published by the Free Software Foundation; either version | ||
11 | * 2 of the License, or (at your option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <linux/config.h> | ||
15 | |||
16 | /* | ||
17 | * Macros for storing registers into and loading registers from | ||
18 | * exception frames. | ||
19 | */ | ||
20 | #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) | ||
21 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) | ||
22 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) | ||
23 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) | ||
24 | #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) | ||
25 | #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) | ||
26 | #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) | ||
27 | #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) | ||
28 | #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) | ||
29 | #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) | ||
30 | |||
31 | #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ | ||
32 | SAVE_10GPRS(22, base) | ||
33 | #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ | ||
34 | REST_10GPRS(22, base) | ||
35 | |||
36 | #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) | ||
37 | #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) | ||
38 | #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) | ||
39 | #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) | ||
40 | #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) | ||
41 | #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) | ||
42 | #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) | ||
43 | #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) | ||
44 | #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) | ||
45 | #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) | ||
46 | #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) | ||
47 | #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) | ||
48 | |||
49 | #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base | ||
50 | #define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) | ||
51 | #define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) | ||
52 | #define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) | ||
53 | #define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) | ||
54 | #define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) | ||
55 | #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base | ||
56 | #define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) | ||
57 | #define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) | ||
58 | #define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) | ||
59 | #define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base) | ||
60 | #define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base) | ||
61 | |||
62 | #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) | ||
63 | #define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) | ||
64 | #define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base) | ||
65 | #define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base) | ||
66 | #define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base) | ||
67 | #define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base) | ||
68 | |||
69 | #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n | ||
70 | #define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) | ||
71 | #define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base) | ||
72 | #define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base) | ||
73 | #define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base) | ||
74 | #define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base) | ||
75 | |||
76 | #ifdef CONFIG_PPC601_SYNC_FIX | ||
77 | #define SYNC \ | ||
78 | BEGIN_FTR_SECTION \ | ||
79 | sync; \ | ||
80 | isync; \ | ||
81 | END_FTR_SECTION_IFSET(CPU_FTR_601) | ||
82 | #define SYNC_601 \ | ||
83 | BEGIN_FTR_SECTION \ | ||
84 | sync; \ | ||
85 | END_FTR_SECTION_IFSET(CPU_FTR_601) | ||
86 | #define ISYNC_601 \ | ||
87 | BEGIN_FTR_SECTION \ | ||
88 | isync; \ | ||
89 | END_FTR_SECTION_IFSET(CPU_FTR_601) | ||
90 | #else | ||
91 | #define SYNC | ||
92 | #define SYNC_601 | ||
93 | #define ISYNC_601 | ||
94 | #endif | ||
95 | |||
96 | #ifndef CONFIG_SMP | ||
97 | #define TLBSYNC | ||
98 | #else /* CONFIG_SMP */ | ||
99 | /* tlbsync is not implemented on 601 */ | ||
100 | #define TLBSYNC \ | ||
101 | BEGIN_FTR_SECTION \ | ||
102 | tlbsync; \ | ||
103 | sync; \ | ||
104 | END_FTR_SECTION_IFCLR(CPU_FTR_601) | ||
105 | #endif | ||
106 | |||
107 | /* | ||
108 | * This instruction is not implemented on the PPC 603 or 601; however, on | ||
109 | * the 403GCX and 405GP tlbia IS defined and tlbie is not. | ||
110 | * All of these instructions exist in the 8xx, they have magical powers, | ||
111 | * and they must be used. | ||
112 | */ | ||
113 | |||
114 | #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) | ||
115 | #define tlbia \ | ||
116 | li r4,1024; \ | ||
117 | mtctr r4; \ | ||
118 | lis r4,KERNELBASE@h; \ | ||
119 | 0: tlbie r4; \ | ||
120 | addi r4,r4,0x1000; \ | ||
121 | bdnz 0b | ||
122 | #endif | ||
123 | |||
124 | #ifdef CONFIG_BOOKE | ||
125 | #define tophys(rd,rs) \ | ||
126 | addis rd,rs,0 | ||
127 | |||
128 | #define tovirt(rd,rs) \ | ||
129 | addis rd,rs,0 | ||
130 | |||
131 | #else /* CONFIG_BOOKE */ | ||
132 | /* | ||
133 | * On APUS (Amiga PowerPC cpu upgrade board), we don't know the | ||
134 | * physical base address of RAM at compile time. | ||
135 | */ | ||
136 | #define tophys(rd,rs) \ | ||
137 | 0: addis rd,rs,-KERNELBASE@h; \ | ||
138 | .section ".vtop_fixup","aw"; \ | ||
139 | .align 1; \ | ||
140 | .long 0b; \ | ||
141 | .previous | ||
142 | |||
143 | #define tovirt(rd,rs) \ | ||
144 | 0: addis rd,rs,KERNELBASE@h; \ | ||
145 | .section ".ptov_fixup","aw"; \ | ||
146 | .align 1; \ | ||
147 | .long 0b; \ | ||
148 | .previous | ||
149 | #endif /* CONFIG_BOOKE */ | ||
150 | |||
151 | /* | ||
152 | * On 64-bit cpus, we use the rfid instruction instead of rfi, but | ||
153 | * we then have to make sure we preserve the top 32 bits except for | ||
154 | * the 64-bit mode bit, which we clear. | ||
155 | */ | ||
156 | #ifdef CONFIG_PPC64BRIDGE | ||
157 | #define FIX_SRR1(ra, rb) \ | ||
158 | mr rb,ra; \ | ||
159 | mfmsr ra; \ | ||
160 | clrldi ra,ra,1; /* turn off 64-bit mode */ \ | ||
161 | rldimi ra,rb,0,32 | ||
162 | #define RFI .long 0x4c000024 /* rfid instruction */ | ||
163 | #define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */ | ||
164 | #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */ | ||
165 | |||
166 | #else | ||
167 | #define FIX_SRR1(ra, rb) | ||
168 | #ifndef CONFIG_40x | ||
169 | #define RFI rfi | ||
170 | #else | ||
171 | #define RFI rfi; b . /* Prevent prefetch past rfi */ | ||
172 | #endif | ||
173 | #define MTMSRD(r) mtmsr r | ||
174 | #define CLR_TOP32(r) | ||
175 | #endif /* CONFIG_PPC64BRIDGE */ | ||
176 | |||
177 | #define RFMCI .long 0x4c00004c /* rfmci instruction */ | ||
178 | |||
179 | #ifdef CONFIG_IBM405_ERR77 | ||
180 | #define PPC405_ERR77(ra,rb) dcbt ra, rb; | ||
181 | #define PPC405_ERR77_SYNC sync; | ||
182 | #else | ||
183 | #define PPC405_ERR77(ra,rb) | ||
184 | #define PPC405_ERR77_SYNC | ||
185 | #endif | ||
186 | |||
187 | /* The boring bits... */ | ||
188 | |||
189 | /* Condition Register Bit Fields */ | ||
190 | |||
191 | #define cr0 0 | ||
192 | #define cr1 1 | ||
193 | #define cr2 2 | ||
194 | #define cr3 3 | ||
195 | #define cr4 4 | ||
196 | #define cr5 5 | ||
197 | #define cr6 6 | ||
198 | #define cr7 7 | ||
199 | |||
200 | |||
201 | /* General Purpose Registers (GPRs) */ | ||
202 | |||
203 | #define r0 0 | ||
204 | #define r1 1 | ||
205 | #define r2 2 | ||
206 | #define r3 3 | ||
207 | #define r4 4 | ||
208 | #define r5 5 | ||
209 | #define r6 6 | ||
210 | #define r7 7 | ||
211 | #define r8 8 | ||
212 | #define r9 9 | ||
213 | #define r10 10 | ||
214 | #define r11 11 | ||
215 | #define r12 12 | ||
216 | #define r13 13 | ||
217 | #define r14 14 | ||
218 | #define r15 15 | ||
219 | #define r16 16 | ||
220 | #define r17 17 | ||
221 | #define r18 18 | ||
222 | #define r19 19 | ||
223 | #define r20 20 | ||
224 | #define r21 21 | ||
225 | #define r22 22 | ||
226 | #define r23 23 | ||
227 | #define r24 24 | ||
228 | #define r25 25 | ||
229 | #define r26 26 | ||
230 | #define r27 27 | ||
231 | #define r28 28 | ||
232 | #define r29 29 | ||
233 | #define r30 30 | ||
234 | #define r31 31 | ||
235 | |||
236 | |||
237 | /* Floating Point Registers (FPRs) */ | ||
238 | |||
239 | #define fr0 0 | ||
240 | #define fr1 1 | ||
241 | #define fr2 2 | ||
242 | #define fr3 3 | ||
243 | #define fr4 4 | ||
244 | #define fr5 5 | ||
245 | #define fr6 6 | ||
246 | #define fr7 7 | ||
247 | #define fr8 8 | ||
248 | #define fr9 9 | ||
249 | #define fr10 10 | ||
250 | #define fr11 11 | ||
251 | #define fr12 12 | ||
252 | #define fr13 13 | ||
253 | #define fr14 14 | ||
254 | #define fr15 15 | ||
255 | #define fr16 16 | ||
256 | #define fr17 17 | ||
257 | #define fr18 18 | ||
258 | #define fr19 19 | ||
259 | #define fr20 20 | ||
260 | #define fr21 21 | ||
261 | #define fr22 22 | ||
262 | #define fr23 23 | ||
263 | #define fr24 24 | ||
264 | #define fr25 25 | ||
265 | #define fr26 26 | ||
266 | #define fr27 27 | ||
267 | #define fr28 28 | ||
268 | #define fr29 29 | ||
269 | #define fr30 30 | ||
270 | #define fr31 31 | ||
271 | |||
272 | #define vr0 0 | ||
273 | #define vr1 1 | ||
274 | #define vr2 2 | ||
275 | #define vr3 3 | ||
276 | #define vr4 4 | ||
277 | #define vr5 5 | ||
278 | #define vr6 6 | ||
279 | #define vr7 7 | ||
280 | #define vr8 8 | ||
281 | #define vr9 9 | ||
282 | #define vr10 10 | ||
283 | #define vr11 11 | ||
284 | #define vr12 12 | ||
285 | #define vr13 13 | ||
286 | #define vr14 14 | ||
287 | #define vr15 15 | ||
288 | #define vr16 16 | ||
289 | #define vr17 17 | ||
290 | #define vr18 18 | ||
291 | #define vr19 19 | ||
292 | #define vr20 20 | ||
293 | #define vr21 21 | ||
294 | #define vr22 22 | ||
295 | #define vr23 23 | ||
296 | #define vr24 24 | ||
297 | #define vr25 25 | ||
298 | #define vr26 26 | ||
299 | #define vr27 27 | ||
300 | #define vr28 28 | ||
301 | #define vr29 29 | ||
302 | #define vr30 30 | ||
303 | #define vr31 31 | ||
304 | |||
305 | #define evr0 0 | ||
306 | #define evr1 1 | ||
307 | #define evr2 2 | ||
308 | #define evr3 3 | ||
309 | #define evr4 4 | ||
310 | #define evr5 5 | ||
311 | #define evr6 6 | ||
312 | #define evr7 7 | ||
313 | #define evr8 8 | ||
314 | #define evr9 9 | ||
315 | #define evr10 10 | ||
316 | #define evr11 11 | ||
317 | #define evr12 12 | ||
318 | #define evr13 13 | ||
319 | #define evr14 14 | ||
320 | #define evr15 15 | ||
321 | #define evr16 16 | ||
322 | #define evr17 17 | ||
323 | #define evr18 18 | ||
324 | #define evr19 19 | ||
325 | #define evr20 20 | ||
326 | #define evr21 21 | ||
327 | #define evr22 22 | ||
328 | #define evr23 23 | ||
329 | #define evr24 24 | ||
330 | #define evr25 25 | ||
331 | #define evr26 26 | ||
332 | #define evr27 27 | ||
333 | #define evr28 28 | ||
334 | #define evr29 29 | ||
335 | #define evr30 30 | ||
336 | #define evr31 31 | ||
337 | |||
338 | /* some stab codes */ | ||
339 | #define N_FUN 36 | ||
340 | #define N_RSYM 64 | ||
341 | #define N_SLINE 68 | ||
342 | #define N_SO 100 | ||
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h new file mode 100644 index 000000000000..24b991c42769 --- /dev/null +++ b/include/asm-ppc/ppc_sys.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/ppc_sys.h | ||
3 | * | ||
4 | * PPC system definitions and library functions | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | ||
7 | * | ||
8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_PPC_SYS_H | ||
18 | #define __ASM_PPC_SYS_H | ||
19 | |||
20 | #include <linux/init.h> | ||
21 | #include <linux/device.h> | ||
22 | #include <linux/types.h> | ||
23 | |||
24 | #if defined(CONFIG_83xx) | ||
25 | #include <asm/mpc83xx.h> | ||
26 | #elif defined(CONFIG_85xx) | ||
27 | #include <asm/mpc85xx.h> | ||
28 | #elif defined(CONFIG_PPC_MPC52xx) | ||
29 | #include <asm/mpc52xx.h> | ||
30 | #else | ||
31 | #error "need definition of ppc_sys_devices" | ||
32 | #endif | ||
33 | |||
34 | struct ppc_sys_spec { | ||
35 | /* PPC sys is matched via (ID & mask) == value, id could be | ||
36 | * PVR, SVR, IMMR, * etc. */ | ||
37 | u32 mask; | ||
38 | u32 value; | ||
39 | u32 num_devices; | ||
40 | char *ppc_sys_name; | ||
41 | enum ppc_sys_devices *device_list; | ||
42 | }; | ||
43 | |||
44 | /* describes all specific chips and which devices they have on them */ | ||
45 | extern struct ppc_sys_spec ppc_sys_specs[]; | ||
46 | extern struct ppc_sys_spec *cur_ppc_sys_spec; | ||
47 | |||
48 | /* determine which specific SOC we are */ | ||
49 | extern void identify_ppc_sys_by_id(u32 id) __init; | ||
50 | extern void identify_ppc_sys_by_name(char *name) __init; | ||
51 | |||
52 | /* describes all devices that may exist in a given family of processors */ | ||
53 | extern struct platform_device ppc_sys_platform_devices[]; | ||
54 | |||
55 | /* allow any platform_device fixup to occur before device is registered */ | ||
56 | extern int (*ppc_sys_device_fixup) (struct platform_device * pdev); | ||
57 | |||
58 | /* Update all memory resources by paddr, call before platform_device_register */ | ||
59 | extern void ppc_sys_fixup_mem_resource(struct platform_device *pdev, | ||
60 | phys_addr_t paddr) __init; | ||
61 | |||
62 | /* Get platform_data pointer out of platform device, call before platform_device_register */ | ||
63 | extern void *ppc_sys_get_pdata(enum ppc_sys_devices dev) __init; | ||
64 | |||
65 | /* remove a device from the system */ | ||
66 | extern void ppc_sys_device_remove(enum ppc_sys_devices dev); | ||
67 | |||
68 | #endif /* __ASM_PPC_SYS_H */ | ||
69 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h new file mode 100644 index 000000000000..fe24e4520208 --- /dev/null +++ b/include/asm-ppc/ppcboot.h | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * (C) Copyright 2000, 2001 | ||
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License as | ||
7 | * published by the Free Software Foundation; either version 2 of | ||
8 | * the License, or (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
18 | * MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_PPCBOOT_H__ | ||
22 | #define __ASM_PPCBOOT_H__ | ||
23 | |||
24 | /* | ||
25 | * Board information passed to kernel from PPCBoot | ||
26 | * | ||
27 | * include/asm-ppc/ppcboot.h | ||
28 | */ | ||
29 | |||
30 | #ifndef __ASSEMBLY__ | ||
31 | #include <linux/types.h> | ||
32 | |||
33 | typedef struct bd_info { | ||
34 | unsigned long bi_memstart; /* start of DRAM memory */ | ||
35 | unsigned long bi_memsize; /* size of DRAM memory in bytes */ | ||
36 | unsigned long bi_flashstart; /* start of FLASH memory */ | ||
37 | unsigned long bi_flashsize; /* size of FLASH memory */ | ||
38 | unsigned long bi_flashoffset; /* reserved area for startup monitor */ | ||
39 | unsigned long bi_sramstart; /* start of SRAM memory */ | ||
40 | unsigned long bi_sramsize; /* size of SRAM memory */ | ||
41 | #if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\ | ||
42 | defined(CONFIG_83xx) | ||
43 | unsigned long bi_immr_base; /* base of IMMR register */ | ||
44 | #endif | ||
45 | #if defined(CONFIG_PPC_MPC52xx) | ||
46 | unsigned long bi_mbar_base; /* base of internal registers */ | ||
47 | #endif | ||
48 | unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ | ||
49 | unsigned long bi_ip_addr; /* IP Address */ | ||
50 | unsigned char bi_enetaddr[6]; /* Ethernet address */ | ||
51 | unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ | ||
52 | unsigned long bi_intfreq; /* Internal Freq, in MHz */ | ||
53 | unsigned long bi_busfreq; /* Bus Freq, in MHz */ | ||
54 | #if defined(CONFIG_CPM2) | ||
55 | unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ | ||
56 | unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ | ||
57 | unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ | ||
58 | unsigned long bi_vco; /* VCO Out from PLL, in MHz */ | ||
59 | #endif | ||
60 | #if defined(CONFIG_PPC_MPC52xx) | ||
61 | unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ | ||
62 | unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ | ||
63 | #endif | ||
64 | unsigned long bi_baudrate; /* Console Baudrate */ | ||
65 | #if defined(CONFIG_4xx) | ||
66 | unsigned char bi_s_version[4]; /* Version of this structure */ | ||
67 | unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ | ||
68 | unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ | ||
69 | unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ | ||
70 | unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ | ||
71 | unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ | ||
72 | #endif | ||
73 | #if defined(CONFIG_HYMOD) | ||
74 | hymod_conf_t bi_hymod_conf; /* hymod configuration information */ | ||
75 | #endif | ||
76 | #if defined(CONFIG_EVB64260) || defined(CONFIG_44x) || defined(CONFIG_85xx) ||\ | ||
77 | defined(CONFIG_83xx) | ||
78 | /* second onboard ethernet port */ | ||
79 | unsigned char bi_enet1addr[6]; | ||
80 | #endif | ||
81 | #if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) || defined(CONFIG_85xx) | ||
82 | /* third onboard ethernet ports */ | ||
83 | unsigned char bi_enet2addr[6]; | ||
84 | #endif | ||
85 | #if defined(CONFIG_440GX) | ||
86 | /* fourth onboard ethernet ports */ | ||
87 | unsigned char bi_enet3addr[6]; | ||
88 | #endif | ||
89 | #if defined(CONFIG_4xx) | ||
90 | unsigned int bi_opbfreq; /* OB clock in Hz */ | ||
91 | int bi_iic_fast[2]; /* Use fast i2c mode */ | ||
92 | #endif | ||
93 | #if defined(CONFIG_440GX) | ||
94 | int bi_phynum[4]; /* phy mapping */ | ||
95 | int bi_phymode[4]; /* phy mode */ | ||
96 | #endif | ||
97 | } bd_t; | ||
98 | |||
99 | #endif /* __ASSEMBLY__ */ | ||
100 | #endif /* __ASM_PPCBOOT_H__ */ | ||
diff --git a/include/asm-ppc/prep_nvram.h b/include/asm-ppc/prep_nvram.h new file mode 100644 index 000000000000..6dbc36a84df2 --- /dev/null +++ b/include/asm-ppc/prep_nvram.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /* | ||
2 | * PreP compliant NVRAM access | ||
3 | */ | ||
4 | |||
5 | /* Corey Minyard (minyard@acm.org) - Stolen from PReP book. Per the | ||
6 | license I must say: | ||
7 | (C) Copyright (Corey Minyard), (1998). All rights reserved | ||
8 | */ | ||
9 | |||
10 | /* Structure map for NVRAM on PowerPC Reference Platform */ | ||
11 | /* All fields are either character/byte strings which are valid either | ||
12 | endian or they are big-endian numbers. | ||
13 | |||
14 | There are a number of Date and Time fields which are in RTC format, | ||
15 | big-endian. These are stored in UT (GMT). | ||
16 | |||
17 | For enum's: if given in hex then they are bit significant, i.e. only | ||
18 | one bit is on for each enum. | ||
19 | */ | ||
20 | #ifdef __KERNEL__ | ||
21 | #ifndef _PPC_PREP_NVRAM_H | ||
22 | #define _PPC_PREP_NVRAM_H | ||
23 | |||
24 | #define MAX_PREP_NVRAM 0x8000 | ||
25 | #define PREP_NVRAM_AS0 0x74 | ||
26 | #define PREP_NVRAM_AS1 0x75 | ||
27 | #define PREP_NVRAM_DATA 0x77 | ||
28 | |||
29 | #define NVSIZE 4096 /* size of NVRAM */ | ||
30 | #define OSAREASIZE 512 /* size of OSArea space */ | ||
31 | #define CONFSIZE 1024 /* guess at size of Configuration space */ | ||
32 | |||
33 | typedef struct _SECURITY { | ||
34 | unsigned long BootErrCnt; /* Count of boot password errors */ | ||
35 | unsigned long ConfigErrCnt; /* Count of config password errors */ | ||
36 | unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ | ||
37 | unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ | ||
38 | unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ | ||
39 | unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ | ||
40 | unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ | ||
41 | unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ | ||
42 | unsigned char Serial[16]; /* Box serial number */ | ||
43 | } SECURITY; | ||
44 | |||
45 | typedef enum _OS_ID { | ||
46 | Unknown = 0, | ||
47 | Firmware = 1, | ||
48 | AIX = 2, | ||
49 | NT = 3, | ||
50 | MKOS2 = 4, | ||
51 | MKAIX = 5, | ||
52 | Taligent = 6, | ||
53 | Solaris = 7, | ||
54 | MK = 12 | ||
55 | } OS_ID; | ||
56 | |||
57 | typedef struct _ERROR_LOG { | ||
58 | unsigned char ErrorLogEntry[40]; /* To be architected */ | ||
59 | } ERROR_LOG; | ||
60 | |||
61 | typedef enum _BOOT_STATUS { | ||
62 | BootStarted = 0x01, | ||
63 | BootFinished = 0x02, | ||
64 | RestartStarted = 0x04, | ||
65 | RestartFinished = 0x08, | ||
66 | PowerFailStarted = 0x10, | ||
67 | PowerFailFinished = 0x20, | ||
68 | ProcessorReady = 0x40, | ||
69 | ProcessorRunning = 0x80, | ||
70 | ProcessorStart = 0x0100 | ||
71 | } BOOT_STATUS; | ||
72 | |||
73 | typedef struct _RESTART_BLOCK { | ||
74 | unsigned short Version; | ||
75 | unsigned short Revision; | ||
76 | unsigned long ResumeReserve1[2]; | ||
77 | volatile unsigned long BootStatus; | ||
78 | unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ | ||
79 | void * RestartAddress; | ||
80 | void * SaveAreaAddr; | ||
81 | unsigned long SaveAreaLength; | ||
82 | } RESTART_BLOCK; | ||
83 | |||
84 | typedef enum _OSAREA_USAGE { | ||
85 | Empty = 0, | ||
86 | Used = 1 | ||
87 | } OSAREA_USAGE; | ||
88 | |||
89 | typedef enum _PM_MODE { | ||
90 | Suspend = 0x80, /* Part of state is in memory */ | ||
91 | Normal = 0x00 /* No power management in effect */ | ||
92 | } PMMODE; | ||
93 | |||
94 | typedef struct _HEADER { | ||
95 | unsigned short Size; /* NVRAM size in K(1024) */ | ||
96 | unsigned char Version; /* Structure map different */ | ||
97 | unsigned char Revision; /* Structure map the same -may | ||
98 | be new values in old fields | ||
99 | in other words old code still works */ | ||
100 | unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ | ||
101 | unsigned short Crc2; /* check sum of config */ | ||
102 | unsigned char LastOS; /* OS_ID */ | ||
103 | unsigned char Endian; /* B if big endian, L if little endian */ | ||
104 | unsigned char OSAreaUsage; /* OSAREA_USAGE */ | ||
105 | unsigned char PMMode; /* Shutdown mode */ | ||
106 | RESTART_BLOCK RestartBlock; | ||
107 | SECURITY Security; | ||
108 | ERROR_LOG ErrorLog[2]; | ||
109 | |||
110 | /* Global Environment information */ | ||
111 | void * GEAddress; | ||
112 | unsigned long GELength; | ||
113 | |||
114 | /* Date&Time from RTC of last change to Global Environment */ | ||
115 | unsigned long GELastWriteDT[2]; | ||
116 | |||
117 | /* Configuration information */ | ||
118 | void * ConfigAddress; | ||
119 | unsigned long ConfigLength; | ||
120 | |||
121 | /* Date&Time from RTC of last change to Configuration */ | ||
122 | unsigned long ConfigLastWriteDT[2]; | ||
123 | unsigned long ConfigCount; /* Count of entries in Configuration */ | ||
124 | |||
125 | /* OS dependent temp area */ | ||
126 | void * OSAreaAddress; | ||
127 | unsigned long OSAreaLength; | ||
128 | |||
129 | /* Date&Time from RTC of last change to OSAreaArea */ | ||
130 | unsigned long OSAreaLastWriteDT[2]; | ||
131 | } HEADER; | ||
132 | |||
133 | /* Here is the whole map of the NVRAM */ | ||
134 | typedef struct _NVRAM_MAP { | ||
135 | HEADER Header; | ||
136 | unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; | ||
137 | unsigned char OSArea[OSAREASIZE]; | ||
138 | unsigned char ConfigArea[CONFSIZE]; | ||
139 | } NVRAM_MAP; | ||
140 | |||
141 | /* Routines to manipulate the NVRAM */ | ||
142 | void init_prep_nvram(void); | ||
143 | char *prep_nvram_get_var(const char *name); | ||
144 | char *prep_nvram_first_var(void); | ||
145 | char *prep_nvram_next_var(char *name); | ||
146 | |||
147 | /* Routines to read and write directly to the NVRAM */ | ||
148 | unsigned char prep_nvram_read_val(int addr); | ||
149 | void prep_nvram_write_val(int addr, | ||
150 | unsigned char val); | ||
151 | |||
152 | #endif /* _PPC_PREP_NVRAM_H */ | ||
153 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h new file mode 100644 index 000000000000..b05b5d9cae20 --- /dev/null +++ b/include/asm-ppc/processor.h | |||
@@ -0,0 +1,201 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef __ASM_PPC_PROCESSOR_H | ||
3 | #define __ASM_PPC_PROCESSOR_H | ||
4 | |||
5 | /* | ||
6 | * Default implementation of macro that returns current | ||
7 | * instruction pointer ("program counter"). | ||
8 | */ | ||
9 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | #include <linux/stringify.h> | ||
13 | |||
14 | #include <asm/ptrace.h> | ||
15 | #include <asm/types.h> | ||
16 | #include <asm/mpc8xx.h> | ||
17 | #include <asm/reg.h> | ||
18 | |||
19 | /* We only need to define a new _MACH_xxx for machines which are part of | ||
20 | * a configuration which supports more than one type of different machine. | ||
21 | * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac. | ||
22 | * -- Tom | ||
23 | */ | ||
24 | #define _MACH_prep 0x00000001 | ||
25 | #define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ | ||
26 | #define _MACH_chrp 0x00000004 /* chrp machine */ | ||
27 | |||
28 | /* see residual.h for these */ | ||
29 | #define _PREP_Motorola 0x01 /* motorola prep */ | ||
30 | #define _PREP_Firm 0x02 /* firmworks prep */ | ||
31 | #define _PREP_IBM 0x00 /* ibm prep */ | ||
32 | #define _PREP_Bull 0x03 /* bull prep */ | ||
33 | |||
34 | /* these are arbitrary */ | ||
35 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ | ||
36 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ | ||
37 | #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ | ||
38 | |||
39 | #define _GLOBAL(n)\ | ||
40 | .stabs __stringify(n:F-1),N_FUN,0,0,n;\ | ||
41 | .globl n;\ | ||
42 | n: | ||
43 | |||
44 | /* | ||
45 | * this is the minimum allowable io space due to the location | ||
46 | * of the io areas on prep (first one at 0x80000000) but | ||
47 | * as soon as I get around to remapping the io areas with the BATs | ||
48 | * to match the mac we can raise this. -- Cort | ||
49 | */ | ||
50 | #define TASK_SIZE (CONFIG_TASK_SIZE) | ||
51 | |||
52 | #ifndef __ASSEMBLY__ | ||
53 | #ifdef CONFIG_PPC_MULTIPLATFORM | ||
54 | extern int _machine; | ||
55 | |||
56 | /* what kind of prep workstation we are */ | ||
57 | extern int _prep_type; | ||
58 | extern int _chrp_type; | ||
59 | |||
60 | /* | ||
61 | * This is used to identify the board type from a given PReP board | ||
62 | * vendor. Board revision is also made available. | ||
63 | */ | ||
64 | extern unsigned char ucSystemType; | ||
65 | extern unsigned char ucBoardRev; | ||
66 | extern unsigned char ucBoardRevMaj, ucBoardRevMin; | ||
67 | #else | ||
68 | #define _machine 0 | ||
69 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | ||
70 | |||
71 | struct task_struct; | ||
72 | void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); | ||
73 | void release_thread(struct task_struct *); | ||
74 | |||
75 | /* Prepare to copy thread state - unlazy all lazy status */ | ||
76 | extern void prepare_to_copy(struct task_struct *tsk); | ||
77 | |||
78 | /* | ||
79 | * Create a new kernel thread. | ||
80 | */ | ||
81 | extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | ||
82 | |||
83 | /* Lazy FPU handling on uni-processor */ | ||
84 | extern struct task_struct *last_task_used_math; | ||
85 | extern struct task_struct *last_task_used_altivec; | ||
86 | extern struct task_struct *last_task_used_spe; | ||
87 | |||
88 | /* This decides where the kernel will search for a free chunk of vm | ||
89 | * space during mmap's. | ||
90 | */ | ||
91 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) | ||
92 | |||
93 | typedef struct { | ||
94 | unsigned long seg; | ||
95 | } mm_segment_t; | ||
96 | |||
97 | struct thread_struct { | ||
98 | unsigned long ksp; /* Kernel stack pointer */ | ||
99 | struct pt_regs *regs; /* Pointer to saved register state */ | ||
100 | mm_segment_t fs; /* for get_fs() validation */ | ||
101 | void *pgdir; /* root of page-table tree */ | ||
102 | int fpexc_mode; /* floating-point exception mode */ | ||
103 | signed long last_syscall; | ||
104 | #if defined(CONFIG_4xx) || defined (CONFIG_BOOKE) | ||
105 | unsigned long dbcr0; /* debug control register values */ | ||
106 | unsigned long dbcr1; | ||
107 | #endif | ||
108 | double fpr[32]; /* Complete floating point set */ | ||
109 | unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ | ||
110 | unsigned long fpscr; /* Floating point status */ | ||
111 | #ifdef CONFIG_ALTIVEC | ||
112 | /* Complete AltiVec register set */ | ||
113 | vector128 vr[32] __attribute((aligned(16))); | ||
114 | /* AltiVec status */ | ||
115 | vector128 vscr __attribute((aligned(16))); | ||
116 | unsigned long vrsave; | ||
117 | int used_vr; /* set if process has used altivec */ | ||
118 | #endif /* CONFIG_ALTIVEC */ | ||
119 | #ifdef CONFIG_SPE | ||
120 | unsigned long evr[32]; /* upper 32-bits of SPE regs */ | ||
121 | u64 acc; /* Accumulator */ | ||
122 | unsigned long spefscr; /* SPE & eFP status */ | ||
123 | int used_spe; /* set if process has used spe */ | ||
124 | #endif /* CONFIG_SPE */ | ||
125 | }; | ||
126 | |||
127 | #define ARCH_MIN_TASKALIGN 16 | ||
128 | |||
129 | #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) | ||
130 | |||
131 | #define INIT_THREAD { \ | ||
132 | .ksp = INIT_SP, \ | ||
133 | .fs = KERNEL_DS, \ | ||
134 | .pgdir = swapper_pg_dir, \ | ||
135 | .fpexc_mode = MSR_FE0 | MSR_FE1, \ | ||
136 | } | ||
137 | |||
138 | /* | ||
139 | * Return saved PC of a blocked thread. For now, this is the "user" PC | ||
140 | */ | ||
141 | #define thread_saved_pc(tsk) \ | ||
142 | ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) | ||
143 | |||
144 | unsigned long get_wchan(struct task_struct *p); | ||
145 | |||
146 | #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) | ||
147 | #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) | ||
148 | |||
149 | /* Get/set floating-point exception mode */ | ||
150 | #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) | ||
151 | #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) | ||
152 | |||
153 | extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); | ||
154 | extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); | ||
155 | |||
156 | static inline unsigned int __unpack_fe01(unsigned int msr_bits) | ||
157 | { | ||
158 | return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); | ||
159 | } | ||
160 | |||
161 | static inline unsigned int __pack_fe01(unsigned int fpmode) | ||
162 | { | ||
163 | return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); | ||
164 | } | ||
165 | |||
166 | /* in process.c - for early bootup debug -- Cort */ | ||
167 | int ll_printk(const char *, ...); | ||
168 | void ll_puts(const char *); | ||
169 | |||
170 | /* In misc.c */ | ||
171 | void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | ||
172 | |||
173 | #define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac) | ||
174 | |||
175 | #define cpu_relax() barrier() | ||
176 | |||
177 | /* | ||
178 | * Prefetch macros. | ||
179 | */ | ||
180 | #define ARCH_HAS_PREFETCH | ||
181 | #define ARCH_HAS_PREFETCHW | ||
182 | #define ARCH_HAS_SPINLOCK_PREFETCH | ||
183 | |||
184 | extern inline void prefetch(const void *x) | ||
185 | { | ||
186 | __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); | ||
187 | } | ||
188 | |||
189 | extern inline void prefetchw(const void *x) | ||
190 | { | ||
191 | __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); | ||
192 | } | ||
193 | |||
194 | #define spin_lock_prefetch(x) prefetchw(x) | ||
195 | |||
196 | extern int emulate_altivec(struct pt_regs *regs); | ||
197 | |||
198 | #endif /* !__ASSEMBLY__ */ | ||
199 | |||
200 | #endif /* __ASM_PPC_PROCESSOR_H */ | ||
201 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h new file mode 100644 index 000000000000..56394c6cf52e --- /dev/null +++ b/include/asm-ppc/prom.h | |||
@@ -0,0 +1,143 @@ | |||
1 | /* | ||
2 | * Definitions for talking to the Open Firmware PROM on | ||
3 | * Power Macintosh computers. | ||
4 | * | ||
5 | * Copyright (C) 1996 Paul Mackerras. | ||
6 | */ | ||
7 | #ifdef __KERNEL__ | ||
8 | #ifndef _PPC_PROM_H | ||
9 | #define _PPC_PROM_H | ||
10 | |||
11 | #include <linux/config.h> | ||
12 | #include <linux/types.h> | ||
13 | |||
14 | typedef u32 phandle; | ||
15 | typedef u32 ihandle; | ||
16 | |||
17 | extern char *prom_display_paths[]; | ||
18 | extern unsigned int prom_num_displays; | ||
19 | |||
20 | struct address_range { | ||
21 | unsigned int space; | ||
22 | unsigned int address; | ||
23 | unsigned int size; | ||
24 | }; | ||
25 | |||
26 | struct interrupt_info { | ||
27 | int line; | ||
28 | int sense; /* +ve/-ve logic, edge or level, etc. */ | ||
29 | }; | ||
30 | |||
31 | struct reg_property { | ||
32 | unsigned int address; | ||
33 | unsigned int size; | ||
34 | }; | ||
35 | |||
36 | struct property { | ||
37 | char *name; | ||
38 | int length; | ||
39 | unsigned char *value; | ||
40 | struct property *next; | ||
41 | }; | ||
42 | |||
43 | /* | ||
44 | * Note: don't change this structure for now or you'll break BootX ! | ||
45 | */ | ||
46 | struct device_node { | ||
47 | char *name; | ||
48 | char *type; | ||
49 | phandle node; | ||
50 | int n_addrs; | ||
51 | struct address_range *addrs; | ||
52 | int n_intrs; | ||
53 | struct interrupt_info *intrs; | ||
54 | char *full_name; | ||
55 | struct property *properties; | ||
56 | struct device_node *parent; | ||
57 | struct device_node *child; | ||
58 | struct device_node *sibling; | ||
59 | struct device_node *next; /* next device of same type */ | ||
60 | struct device_node *allnext; /* next in list of all nodes */ | ||
61 | }; | ||
62 | |||
63 | struct prom_args; | ||
64 | typedef void (*prom_entry)(struct prom_args *); | ||
65 | |||
66 | /* OBSOLETE: Old style node lookup */ | ||
67 | extern struct device_node *find_devices(const char *name); | ||
68 | extern struct device_node *find_type_devices(const char *type); | ||
69 | extern struct device_node *find_path_device(const char *path); | ||
70 | extern struct device_node *find_compatible_devices(const char *type, | ||
71 | const char *compat); | ||
72 | extern struct device_node *find_all_nodes(void); | ||
73 | |||
74 | /* New style node lookup */ | ||
75 | extern struct device_node *of_find_node_by_name(struct device_node *from, | ||
76 | const char *name); | ||
77 | extern struct device_node *of_find_node_by_type(struct device_node *from, | ||
78 | const char *type); | ||
79 | extern struct device_node *of_find_compatible_node(struct device_node *from, | ||
80 | const char *type, const char *compat); | ||
81 | extern struct device_node *of_find_node_by_path(const char *path); | ||
82 | extern struct device_node *of_find_all_nodes(struct device_node *prev); | ||
83 | extern struct device_node *of_get_parent(const struct device_node *node); | ||
84 | extern struct device_node *of_get_next_child(const struct device_node *node, | ||
85 | struct device_node *prev); | ||
86 | extern struct device_node *of_node_get(struct device_node *node); | ||
87 | extern void of_node_put(struct device_node *node); | ||
88 | |||
89 | /* Other Prototypes */ | ||
90 | extern void abort(void); | ||
91 | extern unsigned long prom_init(int, int, prom_entry); | ||
92 | extern void prom_print(const char *msg); | ||
93 | extern void relocate_nodes(void); | ||
94 | extern void finish_device_tree(void); | ||
95 | extern int device_is_compatible(struct device_node *device, const char *); | ||
96 | extern int machine_is_compatible(const char *compat); | ||
97 | extern unsigned char *get_property(struct device_node *node, const char *name, | ||
98 | int *lenp); | ||
99 | extern void prom_add_property(struct device_node* np, struct property* prop); | ||
100 | extern void prom_get_irq_senses(unsigned char *, int, int); | ||
101 | extern int prom_n_addr_cells(struct device_node* np); | ||
102 | extern int prom_n_size_cells(struct device_node* np); | ||
103 | |||
104 | extern struct resource* | ||
105 | request_OF_resource(struct device_node* node, int index, const char* name_postfix); | ||
106 | extern int release_OF_resource(struct device_node* node, int index); | ||
107 | |||
108 | extern void print_properties(struct device_node *node); | ||
109 | extern int call_rtas(const char *service, int nargs, int nret, | ||
110 | unsigned long *outputs, ...); | ||
111 | |||
112 | /* | ||
113 | * PCI <-> OF matching functions | ||
114 | */ | ||
115 | struct pci_bus; | ||
116 | struct pci_dev; | ||
117 | extern int pci_device_from_OF_node(struct device_node *node, | ||
118 | u8* bus, u8* devfn); | ||
119 | extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int); | ||
120 | extern struct device_node* pci_device_to_OF_node(struct pci_dev *); | ||
121 | extern void pci_create_OF_bus_map(void); | ||
122 | |||
123 | /* | ||
124 | * When we call back to the Open Firmware client interface, we usually | ||
125 | * have to do that before the kernel is relocated to its final location | ||
126 | * (this is because we can't use OF after we have overwritten the | ||
127 | * exception vectors with our exception handlers). These macros assist | ||
128 | * in performing the address calculations that we need to do to access | ||
129 | * data when the kernel is running at an address that is different from | ||
130 | * the address that the kernel is linked at. The reloc_offset() function | ||
131 | * returns the difference between these two addresses and the macros | ||
132 | * simplify the process of adding or subtracting this offset to/from | ||
133 | * pointer values. See arch/ppc/kernel/prom.c for how these are used. | ||
134 | */ | ||
135 | extern unsigned long reloc_offset(void); | ||
136 | extern unsigned long add_reloc_offset(unsigned long); | ||
137 | extern unsigned long sub_reloc_offset(unsigned long); | ||
138 | |||
139 | #define PTRRELOC(x) ((typeof(x))add_reloc_offset((unsigned long)(x))) | ||
140 | #define PTRUNRELOC(x) ((typeof(x))sub_reloc_offset((unsigned long)(x))) | ||
141 | |||
142 | #endif /* _PPC_PROM_H */ | ||
143 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h new file mode 100644 index 000000000000..9d4e4ea530c3 --- /dev/null +++ b/include/asm-ppc/ptrace.h | |||
@@ -0,0 +1,145 @@ | |||
1 | #ifndef _PPC_PTRACE_H | ||
2 | #define _PPC_PTRACE_H | ||
3 | |||
4 | /* | ||
5 | * This struct defines the way the registers are stored on the | ||
6 | * kernel stack during a system call or other kernel entry. | ||
7 | * | ||
8 | * this should only contain volatile regs | ||
9 | * since we can keep non-volatile in the thread_struct | ||
10 | * should set this up when only volatiles are saved | ||
11 | * by intr code. | ||
12 | * | ||
13 | * Since this is going on the stack, *CARE MUST BE TAKEN* to insure | ||
14 | * that the overall structure is a multiple of 16 bytes in length. | ||
15 | * | ||
16 | * Note that the offsets of the fields in this struct correspond with | ||
17 | * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASSEMBLY__ | ||
21 | struct pt_regs { | ||
22 | unsigned long gpr[32]; | ||
23 | unsigned long nip; | ||
24 | unsigned long msr; | ||
25 | unsigned long orig_gpr3; /* Used for restarting system calls */ | ||
26 | unsigned long ctr; | ||
27 | unsigned long link; | ||
28 | unsigned long xer; | ||
29 | unsigned long ccr; | ||
30 | unsigned long mq; /* 601 only (not used at present) */ | ||
31 | /* Used on APUS to hold IPL value. */ | ||
32 | unsigned long trap; /* Reason for being here */ | ||
33 | /* N.B. for critical exceptions on 4xx, the dar and dsisr | ||
34 | fields are overloaded to hold srr0 and srr1. */ | ||
35 | unsigned long dar; /* Fault registers */ | ||
36 | unsigned long dsisr; /* on 4xx/Book-E used for ESR */ | ||
37 | unsigned long result; /* Result of a system call */ | ||
38 | }; | ||
39 | |||
40 | #endif /* __ASSEMBLY__ */ | ||
41 | |||
42 | #ifdef __KERNEL__ | ||
43 | #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ | ||
44 | |||
45 | /* Size of stack frame allocated when calling signal handler. */ | ||
46 | #define __SIGNAL_FRAMESIZE 64 | ||
47 | |||
48 | #ifndef __ASSEMBLY__ | ||
49 | #define instruction_pointer(regs) ((regs)->nip) | ||
50 | #ifdef CONFIG_SMP | ||
51 | extern unsigned long profile_pc(struct pt_regs *regs); | ||
52 | #else | ||
53 | #define profile_pc(regs) instruction_pointer(regs) | ||
54 | #endif | ||
55 | |||
56 | #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) | ||
57 | |||
58 | #define force_successful_syscall_return() \ | ||
59 | do { \ | ||
60 | current_thread_info()->local_flags |= _TIFL_FORCE_NOERROR; \ | ||
61 | } while(0) | ||
62 | |||
63 | /* | ||
64 | * We use the least-significant bit of the trap field to indicate | ||
65 | * whether we have saved the full set of registers, or only a | ||
66 | * partial set. A 1 there means the partial set. | ||
67 | * On 4xx we use the next bit to indicate whether the exception | ||
68 | * is a critical exception (1 means it is). | ||
69 | */ | ||
70 | #define FULL_REGS(regs) (((regs)->trap & 1) == 0) | ||
71 | #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0) | ||
72 | #define TRAP(regs) ((regs)->trap & ~0xF) | ||
73 | |||
74 | #define CHECK_FULL_REGS(regs) \ | ||
75 | do { \ | ||
76 | if ((regs)->trap & 1) \ | ||
77 | printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \ | ||
78 | } while (0) | ||
79 | #endif /* __ASSEMBLY__ */ | ||
80 | |||
81 | #endif /* __KERNEL__ */ | ||
82 | |||
83 | /* | ||
84 | * Offsets used by 'ptrace' system call interface. | ||
85 | * These can't be changed without breaking binary compatibility | ||
86 | * with MkLinux, etc. | ||
87 | */ | ||
88 | #define PT_R0 0 | ||
89 | #define PT_R1 1 | ||
90 | #define PT_R2 2 | ||
91 | #define PT_R3 3 | ||
92 | #define PT_R4 4 | ||
93 | #define PT_R5 5 | ||
94 | #define PT_R6 6 | ||
95 | #define PT_R7 7 | ||
96 | #define PT_R8 8 | ||
97 | #define PT_R9 9 | ||
98 | #define PT_R10 10 | ||
99 | #define PT_R11 11 | ||
100 | #define PT_R12 12 | ||
101 | #define PT_R13 13 | ||
102 | #define PT_R14 14 | ||
103 | #define PT_R15 15 | ||
104 | #define PT_R16 16 | ||
105 | #define PT_R17 17 | ||
106 | #define PT_R18 18 | ||
107 | #define PT_R19 19 | ||
108 | #define PT_R20 20 | ||
109 | #define PT_R21 21 | ||
110 | #define PT_R22 22 | ||
111 | #define PT_R23 23 | ||
112 | #define PT_R24 24 | ||
113 | #define PT_R25 25 | ||
114 | #define PT_R26 26 | ||
115 | #define PT_R27 27 | ||
116 | #define PT_R28 28 | ||
117 | #define PT_R29 29 | ||
118 | #define PT_R30 30 | ||
119 | #define PT_R31 31 | ||
120 | |||
121 | #define PT_NIP 32 | ||
122 | #define PT_MSR 33 | ||
123 | #ifdef __KERNEL__ | ||
124 | #define PT_ORIG_R3 34 | ||
125 | #endif | ||
126 | #define PT_CTR 35 | ||
127 | #define PT_LNK 36 | ||
128 | #define PT_XER 37 | ||
129 | #define PT_CCR 38 | ||
130 | #define PT_MQ 39 | ||
131 | |||
132 | #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ | ||
133 | #define PT_FPR31 (PT_FPR0 + 2*31) | ||
134 | #define PT_FPSCR (PT_FPR0 + 2*32 + 1) | ||
135 | |||
136 | /* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go */ | ||
137 | #define PTRACE_GETVRREGS 18 | ||
138 | #define PTRACE_SETVRREGS 19 | ||
139 | |||
140 | /* Get/set all the upper 32-bits of the SPE registers, accumulator, and | ||
141 | * spefscr, in one go */ | ||
142 | #define PTRACE_GETEVRREGS 20 | ||
143 | #define PTRACE_SETEVRREGS 21 | ||
144 | |||
145 | #endif | ||
diff --git a/include/asm-ppc/raven.h b/include/asm-ppc/raven.h new file mode 100644 index 000000000000..66f52cc0a03c --- /dev/null +++ b/include/asm-ppc/raven.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/raven.h -- Raven MPIC chip. | ||
3 | * | ||
4 | * Copyright (C) 1998 Johnnie Peters | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file COPYING in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | |||
11 | #ifdef __KERNEL__ | ||
12 | #ifndef _ASMPPC_RAVEN_H | ||
13 | #define _ASMPPC_RAVEN_H | ||
14 | |||
15 | #define MVME2600_INT_SIO 0 | ||
16 | #define MVME2600_INT_FALCN_ECC_ERR 1 | ||
17 | #define MVME2600_INT_PCI_ETHERNET 2 | ||
18 | #define MVME2600_INT_PCI_SCSI 3 | ||
19 | #define MVME2600_INT_PCI_GRAPHICS 4 | ||
20 | #define MVME2600_INT_PCI_VME0 5 | ||
21 | #define MVME2600_INT_PCI_VME1 6 | ||
22 | #define MVME2600_INT_PCI_VME2 7 | ||
23 | #define MVME2600_INT_PCI_VME3 8 | ||
24 | #define MVME2600_INT_PCI_INTA 9 | ||
25 | #define MVME2600_INT_PCI_INTB 10 | ||
26 | #define MVME2600_INT_PCI_INTC 11 | ||
27 | #define MVME2600_INT_PCI_INTD 12 | ||
28 | #define MVME2600_INT_LM_SIG0 13 | ||
29 | #define MVME2600_INT_LM_SIG1 14 | ||
30 | |||
31 | extern struct hw_interrupt_type raven_pic; | ||
32 | |||
33 | extern int raven_init(void); | ||
34 | #endif /* _ASMPPC_RAVEN_H */ | ||
35 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h new file mode 100644 index 000000000000..3372dee36a8c --- /dev/null +++ b/include/asm-ppc/reg.h | |||
@@ -0,0 +1,444 @@ | |||
1 | /* | ||
2 | * Contains the definition of registers common to all PowerPC variants. | ||
3 | * If a register definition has been changed in a different PowerPC | ||
4 | * variant, we will case it in #ifndef XXX ... #endif, and have the | ||
5 | * number used in the Programming Environments Manual For 32-Bit | ||
6 | * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. | ||
7 | */ | ||
8 | |||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef __ASM_PPC_REGS_H__ | ||
11 | #define __ASM_PPC_REGS_H__ | ||
12 | |||
13 | #include <linux/stringify.h> | ||
14 | |||
15 | /* Pickup Book E specific registers. */ | ||
16 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) | ||
17 | #include <asm/reg_booke.h> | ||
18 | #endif | ||
19 | |||
20 | /* Machine State Register (MSR) Fields */ | ||
21 | #define MSR_SF (1<<63) | ||
22 | #define MSR_ISF (1<<61) | ||
23 | #define MSR_VEC (1<<25) /* Enable AltiVec */ | ||
24 | #define MSR_POW (1<<18) /* Enable Power Management */ | ||
25 | #define MSR_WE (1<<18) /* Wait State Enable */ | ||
26 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ | ||
27 | #define MSR_CE (1<<17) /* Critical Interrupt Enable */ | ||
28 | #define MSR_ILE (1<<16) /* Interrupt Little Endian */ | ||
29 | #define MSR_EE (1<<15) /* External Interrupt Enable */ | ||
30 | #define MSR_PR (1<<14) /* Problem State / Privilege Level */ | ||
31 | #define MSR_FP (1<<13) /* Floating Point enable */ | ||
32 | #define MSR_ME (1<<12) /* Machine Check Enable */ | ||
33 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ | ||
34 | #define MSR_SE (1<<10) /* Single Step */ | ||
35 | #define MSR_BE (1<<9) /* Branch Trace */ | ||
36 | #define MSR_DE (1<<9) /* Debug Exception Enable */ | ||
37 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ | ||
38 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ | ||
39 | #define MSR_IR (1<<5) /* Instruction Relocate */ | ||
40 | #define MSR_DR (1<<4) /* Data Relocate */ | ||
41 | #define MSR_PE (1<<3) /* Protection Enable */ | ||
42 | #define MSR_PX (1<<2) /* Protection Exclusive Mode */ | ||
43 | #define MSR_RI (1<<1) /* Recoverable Exception */ | ||
44 | #define MSR_LE (1<<0) /* Little Endian */ | ||
45 | |||
46 | /* Default MSR for kernel mode. */ | ||
47 | #ifdef CONFIG_APUS_FAST_EXCEPT | ||
48 | #define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) | ||
49 | #endif | ||
50 | |||
51 | #ifndef MSR_KERNEL | ||
52 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) | ||
53 | #endif | ||
54 | |||
55 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) | ||
56 | |||
57 | /* Floating Point Status and Control Register (FPSCR) Fields */ | ||
58 | #define FPSCR_FX 0x80000000 /* FPU exception summary */ | ||
59 | #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ | ||
60 | #define FPSCR_VX 0x20000000 /* Invalid operation summary */ | ||
61 | #define FPSCR_OX 0x10000000 /* Overflow exception summary */ | ||
62 | #define FPSCR_UX 0x08000000 /* Underflow exception summary */ | ||
63 | #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ | ||
64 | #define FPSCR_XX 0x02000000 /* Inexact exception summary */ | ||
65 | #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ | ||
66 | #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ | ||
67 | #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ | ||
68 | #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ | ||
69 | #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ | ||
70 | #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ | ||
71 | #define FPSCR_FR 0x00040000 /* Fraction rounded */ | ||
72 | #define FPSCR_FI 0x00020000 /* Fraction inexact */ | ||
73 | #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ | ||
74 | #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ | ||
75 | #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ | ||
76 | #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ | ||
77 | #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ | ||
78 | #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ | ||
79 | #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ | ||
80 | #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ | ||
81 | #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ | ||
82 | #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ | ||
83 | #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ | ||
84 | #define FPSCR_RN 0x00000003 /* FPU rounding control */ | ||
85 | |||
86 | /* Special Purpose Registers (SPRNs)*/ | ||
87 | #define SPRN_CTR 0x009 /* Count Register */ | ||
88 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | ||
89 | #define SPRN_DAR 0x013 /* Data Address Register */ | ||
90 | #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ | ||
91 | #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ | ||
92 | #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ | ||
93 | #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ | ||
94 | #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ | ||
95 | #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ | ||
96 | #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ | ||
97 | #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ | ||
98 | #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ | ||
99 | #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ | ||
100 | #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ | ||
101 | #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ | ||
102 | #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ | ||
103 | #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ | ||
104 | #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ | ||
105 | #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ | ||
106 | #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ | ||
107 | #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ | ||
108 | #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ | ||
109 | #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ | ||
110 | #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ | ||
111 | |||
112 | #define SPRN_DEC 0x016 /* Decrement Register */ | ||
113 | #define SPRN_DER 0x095 /* Debug Enable Regsiter */ | ||
114 | #define DER_RSTE 0x40000000 /* Reset Interrupt */ | ||
115 | #define DER_CHSTPE 0x20000000 /* Check Stop */ | ||
116 | #define DER_MCIE 0x10000000 /* Machine Check Interrupt */ | ||
117 | #define DER_EXTIE 0x02000000 /* External Interrupt */ | ||
118 | #define DER_ALIE 0x01000000 /* Alignment Interrupt */ | ||
119 | #define DER_PRIE 0x00800000 /* Program Interrupt */ | ||
120 | #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ | ||
121 | #define DER_DECIE 0x00200000 /* Decrementer Interrupt */ | ||
122 | #define DER_SYSIE 0x00040000 /* System Call Interrupt */ | ||
123 | #define DER_TRE 0x00020000 /* Trace Interrupt */ | ||
124 | #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ | ||
125 | #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ | ||
126 | #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ | ||
127 | #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ | ||
128 | #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ | ||
129 | #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ | ||
130 | #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ | ||
131 | #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ | ||
132 | #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ | ||
133 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | ||
134 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ | ||
135 | #define SPRN_EAR 0x11A /* External Address Register */ | ||
136 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | ||
137 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ | ||
138 | #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ | ||
139 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ | ||
140 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ | ||
141 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ | ||
142 | #define HID0_SBCLK (1<<27) | ||
143 | #define HID0_EICE (1<<26) | ||
144 | #define HID0_TBEN (1<<26) /* Timebase enable - 745x */ | ||
145 | #define HID0_ECLK (1<<25) | ||
146 | #define HID0_PAR (1<<24) | ||
147 | #define HID0_STEN (1<<24) /* Software table search enable - 745x */ | ||
148 | #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ | ||
149 | #define HID0_DOZE (1<<23) | ||
150 | #define HID0_NAP (1<<22) | ||
151 | #define HID0_SLEEP (1<<21) | ||
152 | #define HID0_DPM (1<<20) | ||
153 | #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ | ||
154 | #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ | ||
155 | #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ | ||
156 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ | ||
157 | #define HID0_DCE (1<<14) /* Data Cache Enable */ | ||
158 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ | ||
159 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ | ||
160 | #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ | ||
161 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ | ||
162 | #define HID0_SPD (1<<9) /* Speculative disable */ | ||
163 | #define HID0_SGE (1<<7) /* Store Gathering Enable */ | ||
164 | #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ | ||
165 | #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ | ||
166 | #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ | ||
167 | #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ | ||
168 | #define HID0_ABE (1<<3) /* Address Broadcast Enable */ | ||
169 | #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ | ||
170 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ | ||
171 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ | ||
172 | #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ | ||
173 | #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ | ||
174 | |||
175 | #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | ||
176 | #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ | ||
177 | #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ | ||
178 | #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ | ||
179 | #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ | ||
180 | #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ | ||
181 | #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ | ||
182 | #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ | ||
183 | #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ | ||
184 | #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ | ||
185 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | ||
186 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ | ||
187 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ | ||
188 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) | ||
189 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ | ||
190 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | ||
191 | #endif | ||
192 | #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ | ||
193 | #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ | ||
194 | #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ | ||
195 | #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ | ||
196 | #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ | ||
197 | #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ | ||
198 | #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ | ||
199 | #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ | ||
200 | #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ | ||
201 | #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ | ||
202 | #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ | ||
203 | #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ | ||
204 | #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ | ||
205 | #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ | ||
206 | #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ | ||
207 | #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ | ||
208 | #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ | ||
209 | #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ | ||
210 | #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ | ||
211 | #define ICTRL_EICE 0x08000000 /* enable icache parity errs */ | ||
212 | #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ | ||
213 | #define ICTRL_EICP 0x00000100 /* enable icache par. check */ | ||
214 | #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ | ||
215 | #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ | ||
216 | #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ | ||
217 | #define SPRN_L2CR2 0x3f8 | ||
218 | #define L2CR_L2E 0x80000000 /* L2 enable */ | ||
219 | #define L2CR_L2PE 0x40000000 /* L2 parity enable */ | ||
220 | #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ | ||
221 | #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ | ||
222 | #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ | ||
223 | #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ | ||
224 | #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ | ||
225 | #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ | ||
226 | #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ | ||
227 | #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ | ||
228 | #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ | ||
229 | #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ | ||
230 | #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ | ||
231 | #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ | ||
232 | #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ | ||
233 | #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ | ||
234 | #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ | ||
235 | #define L2CR_L2DO 0x00400000 /* L2 data only */ | ||
236 | #define L2CR_L2I 0x00200000 /* L2 global invalidate */ | ||
237 | #define L2CR_L2CTL 0x00100000 /* L2 RAM control */ | ||
238 | #define L2CR_L2WT 0x00080000 /* L2 write-through */ | ||
239 | #define L2CR_L2TS 0x00040000 /* L2 test support */ | ||
240 | #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ | ||
241 | #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ | ||
242 | #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ | ||
243 | #define L2CR_L2SL 0x00008000 /* L2 DLL slow */ | ||
244 | #define L2CR_L2DF 0x00004000 /* L2 differential clock */ | ||
245 | #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ | ||
246 | #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ | ||
247 | #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ | ||
248 | #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ | ||
249 | #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ | ||
250 | #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ | ||
251 | #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ | ||
252 | #define L3CR_L3E 0x80000000 /* L3 enable */ | ||
253 | #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ | ||
254 | #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ | ||
255 | #define L3CR_L3SIZ 0x10000000 /* L3 size */ | ||
256 | #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ | ||
257 | #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ | ||
258 | #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ | ||
259 | #define L3CR_L3IO 0x00400000 /* L3 instruction only */ | ||
260 | #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ | ||
261 | #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ | ||
262 | #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ | ||
263 | #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ | ||
264 | #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ | ||
265 | #define L3CR_L3I 0x00000400 /* L3 global invalidate */ | ||
266 | #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ | ||
267 | #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ | ||
268 | #define L3CR_L3DO 0x00000040 /* L3 data only mode */ | ||
269 | #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ | ||
270 | #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ | ||
271 | #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ | ||
272 | #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ | ||
273 | #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ | ||
274 | #define SPRN_LDSTDB 0x3f4 /* */ | ||
275 | #define SPRN_LR 0x008 /* Link Register */ | ||
276 | #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ | ||
277 | #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ | ||
278 | #ifndef SPRN_PIR | ||
279 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | ||
280 | #endif | ||
281 | #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ | ||
282 | #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ | ||
283 | #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ | ||
284 | #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ | ||
285 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ | ||
286 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | ||
287 | #define SPRN_PVR 0x11F /* Processor Version Register */ | ||
288 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | ||
289 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | ||
290 | #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ | ||
291 | #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ | ||
292 | #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ | ||
293 | #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ | ||
294 | #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ | ||
295 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | ||
296 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ | ||
297 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ | ||
298 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ | ||
299 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ | ||
300 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ | ||
301 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | ||
302 | #ifndef SPRN_SVR | ||
303 | #define SPRN_SVR 0x11E /* System Version Register */ | ||
304 | #endif | ||
305 | #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ | ||
306 | /* these bits were defined in inverted endian sense originally, ugh, confusing */ | ||
307 | #define THRM1_TIN (1 << 31) | ||
308 | #define THRM1_TIV (1 << 30) | ||
309 | #define THRM1_THRES(x) ((x&0x7f)<<23) | ||
310 | #define THRM3_SITV(x) ((x&0x3fff)<<1) | ||
311 | #define THRM1_TID (1<<2) | ||
312 | #define THRM1_TIE (1<<1) | ||
313 | #define THRM1_V (1<<0) | ||
314 | #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ | ||
315 | #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ | ||
316 | #define THRM3_E (1<<0) | ||
317 | #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ | ||
318 | #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ | ||
319 | #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ | ||
320 | #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ | ||
321 | #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ | ||
322 | #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ | ||
323 | #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ | ||
324 | #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ | ||
325 | #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ | ||
326 | #define SPRN_XER 0x001 /* Fixed Point Exception Register */ | ||
327 | |||
328 | /* Bit definitions for MMCR0 and PMC1 / PMC2. */ | ||
329 | #define MMCR0_PMC1_CYCLES (1 << 7) | ||
330 | #define MMCR0_PMC1_ICACHEMISS (5 << 7) | ||
331 | #define MMCR0_PMC1_DTLB (6 << 7) | ||
332 | #define MMCR0_PMC2_DCACHEMISS 0x6 | ||
333 | #define MMCR0_PMC2_CYCLES 0x1 | ||
334 | #define MMCR0_PMC2_ITLB 0x7 | ||
335 | #define MMCR0_PMC2_LOADMISSTIME 0x5 | ||
336 | #define MMCR0_PMXE (1 << 26) | ||
337 | |||
338 | /* Processor Version Register */ | ||
339 | |||
340 | /* Processor Version Register (PVR) field extraction */ | ||
341 | |||
342 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | ||
343 | #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ | ||
344 | |||
345 | /* | ||
346 | * IBM has further subdivided the standard PowerPC 16-bit version and | ||
347 | * revision subfields of the PVR for the PowerPC 403s into the following: | ||
348 | */ | ||
349 | |||
350 | #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ | ||
351 | #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ | ||
352 | #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ | ||
353 | #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ | ||
354 | #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ | ||
355 | #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ | ||
356 | |||
357 | /* Processor Version Numbers */ | ||
358 | |||
359 | #define PVR_403GA 0x00200000 | ||
360 | #define PVR_403GB 0x00200100 | ||
361 | #define PVR_403GC 0x00200200 | ||
362 | #define PVR_403GCX 0x00201400 | ||
363 | #define PVR_405GP 0x40110000 | ||
364 | #define PVR_STB03XXX 0x40310000 | ||
365 | #define PVR_NP405H 0x41410000 | ||
366 | #define PVR_NP405L 0x41610000 | ||
367 | #define PVR_440GP_RB 0x40120440 | ||
368 | #define PVR_440GP_RC1 0x40120481 | ||
369 | #define PVR_440GP_RC2 0x40200481 | ||
370 | #define PVR_440GX_RA 0x51b21850 | ||
371 | #define PVR_440GX_RB 0x51b21851 | ||
372 | #define PVR_440GX_RC 0x51b21892 | ||
373 | #define PVR_601 0x00010000 | ||
374 | #define PVR_602 0x00050000 | ||
375 | #define PVR_603 0x00030000 | ||
376 | #define PVR_603e 0x00060000 | ||
377 | #define PVR_603ev 0x00070000 | ||
378 | #define PVR_603r 0x00071000 | ||
379 | #define PVR_604 0x00040000 | ||
380 | #define PVR_604e 0x00090000 | ||
381 | #define PVR_604r 0x000A0000 | ||
382 | #define PVR_620 0x00140000 | ||
383 | #define PVR_740 0x00080000 | ||
384 | #define PVR_750 PVR_740 | ||
385 | #define PVR_740P 0x10080000 | ||
386 | #define PVR_750P PVR_740P | ||
387 | #define PVR_7400 0x000C0000 | ||
388 | #define PVR_7410 0x800C0000 | ||
389 | #define PVR_7450 0x80000000 | ||
390 | #define PVR_8540 0x80200000 | ||
391 | #define PVR_8560 0x80200000 | ||
392 | /* | ||
393 | * For the 8xx processors, all of them report the same PVR family for | ||
394 | * the PowerPC core. The various versions of these processors must be | ||
395 | * differentiated by the version number in the Communication Processor | ||
396 | * Module (CPM). | ||
397 | */ | ||
398 | #define PVR_821 0x00500000 | ||
399 | #define PVR_823 PVR_821 | ||
400 | #define PVR_850 PVR_821 | ||
401 | #define PVR_860 PVR_821 | ||
402 | #define PVR_8240 0x00810100 | ||
403 | #define PVR_8245 0x80811014 | ||
404 | #define PVR_8260 PVR_8240 | ||
405 | |||
406 | #if 0 | ||
407 | /* Segment Registers */ | ||
408 | #define SR0 0 | ||
409 | #define SR1 1 | ||
410 | #define SR2 2 | ||
411 | #define SR3 3 | ||
412 | #define SR4 4 | ||
413 | #define SR5 5 | ||
414 | #define SR6 6 | ||
415 | #define SR7 7 | ||
416 | #define SR8 8 | ||
417 | #define SR9 9 | ||
418 | #define SR10 10 | ||
419 | #define SR11 11 | ||
420 | #define SR12 12 | ||
421 | #define SR13 13 | ||
422 | #define SR14 14 | ||
423 | #define SR15 15 | ||
424 | #endif | ||
425 | |||
426 | /* Macros for setting and retrieving special purpose registers */ | ||
427 | #ifndef __ASSEMBLY__ | ||
428 | #define mfmsr() ({unsigned int rval; \ | ||
429 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) | ||
430 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) | ||
431 | |||
432 | #define mfspr(rn) ({unsigned int rval; \ | ||
433 | asm volatile("mfspr %0," __stringify(rn) \ | ||
434 | : "=r" (rval)); rval;}) | ||
435 | #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) | ||
436 | |||
437 | #define mfsrin(v) ({unsigned int rval; \ | ||
438 | asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ | ||
439 | rval;}) | ||
440 | |||
441 | #define proc_trap() asm volatile("trap") | ||
442 | #endif /* __ASSEMBLY__ */ | ||
443 | #endif /* __ASM_PPC_REGS_H__ */ | ||
444 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h new file mode 100644 index 000000000000..4b03f8e26b72 --- /dev/null +++ b/include/asm-ppc/reg_booke.h | |||
@@ -0,0 +1,484 @@ | |||
1 | /* | ||
2 | * Contains register definitions common to the Book E PowerPC | ||
3 | * specification. Notice that while the IBM-40x series of CPUs | ||
4 | * are not true Book E PowerPCs, they borrowed a number of features | ||
5 | * before Book E was finalized, and are included here as well. Unfortunatly, | ||
6 | * they sometimes used different locations than true Book E CPUs did. | ||
7 | */ | ||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef __ASM_PPC_REG_BOOKE_H__ | ||
10 | #define __ASM_PPC_REG_BOOKE_H__ | ||
11 | |||
12 | #ifndef __ASSEMBLY__ | ||
13 | /* Device Control Registers */ | ||
14 | void __mtdcr(int reg, unsigned int val); | ||
15 | unsigned int __mfdcr(int reg); | ||
16 | #define mfdcr(rn) \ | ||
17 | ({unsigned int rval; \ | ||
18 | if (__builtin_constant_p(rn)) \ | ||
19 | asm volatile("mfdcr %0," __stringify(rn) \ | ||
20 | : "=r" (rval)); \ | ||
21 | else \ | ||
22 | rval = __mfdcr(rn); \ | ||
23 | rval;}) | ||
24 | |||
25 | #define mtdcr(rn, v) \ | ||
26 | do { \ | ||
27 | if (__builtin_constant_p(rn)) \ | ||
28 | asm volatile("mtdcr " __stringify(rn) ",%0" \ | ||
29 | : : "r" (v)); \ | ||
30 | else \ | ||
31 | __mtdcr(rn, v); \ | ||
32 | } while (0) | ||
33 | |||
34 | /* R/W of indirect DCRs make use of standard naming conventions for DCRs */ | ||
35 | #define mfdcri(base, reg) \ | ||
36 | ({ \ | ||
37 | mtdcr(base ## _CFGADDR, base ## _ ## reg); \ | ||
38 | mfdcr(base ## _CFGDATA); \ | ||
39 | }) | ||
40 | |||
41 | #define mtdcri(base, reg, data) \ | ||
42 | do { \ | ||
43 | mtdcr(base ## _CFGADDR, base ## _ ## reg); \ | ||
44 | mtdcr(base ## _CFGDATA, data); \ | ||
45 | } while (0) | ||
46 | |||
47 | /* Performance Monitor Registers */ | ||
48 | #define mfpmr(rn) ({unsigned int rval; \ | ||
49 | asm volatile("mfpmr %0," __stringify(rn) \ | ||
50 | : "=r" (rval)); rval;}) | ||
51 | #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) | ||
52 | #endif /* __ASSEMBLY__ */ | ||
53 | |||
54 | /* Freescale Book E Performance Monitor APU Registers */ | ||
55 | #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ | ||
56 | #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ | ||
57 | #define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ | ||
58 | #define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ | ||
59 | #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ | ||
60 | #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ | ||
61 | #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ | ||
62 | #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ | ||
63 | |||
64 | #define PMLCA_FC 0x80000000 /* Freeze Counter */ | ||
65 | #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ | ||
66 | #define PMLCA_FCU 0x20000000 /* Freeze in User */ | ||
67 | #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ | ||
68 | #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ | ||
69 | #define PMLCA_CE 0x04000000 /* Condition Enable */ | ||
70 | |||
71 | #define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ | ||
72 | #define PMLCA_EVENT_SHIFT 16 | ||
73 | |||
74 | #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ | ||
75 | #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ | ||
76 | #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ | ||
77 | #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ | ||
78 | |||
79 | #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ | ||
80 | #define PMLCB_THRESHMUL_SHIFT 8 | ||
81 | |||
82 | #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ | ||
83 | #define PMLCB_THRESHOLD_SHIFT 0 | ||
84 | |||
85 | #define PMRN_PMGC0 0x190 /* PM Global Control 0 */ | ||
86 | |||
87 | #define PMGC0_FAC 0x80000000 /* Freeze all Counters */ | ||
88 | #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ | ||
89 | #define PMGC0_FCECE 0x20000000 /* Freeze countes on | ||
90 | Enabled Condition or | ||
91 | Event */ | ||
92 | |||
93 | #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ | ||
94 | #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ | ||
95 | #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ | ||
96 | #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ | ||
97 | #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ | ||
98 | #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ | ||
99 | #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ | ||
100 | #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ | ||
101 | #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ | ||
102 | #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ | ||
103 | #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ | ||
104 | #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ | ||
105 | #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ | ||
106 | |||
107 | |||
108 | /* Machine State Register (MSR) Fields */ | ||
109 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ | ||
110 | #define MSR_SPE (1<<25) /* Enable SPE */ | ||
111 | #define MSR_DWE (1<<10) /* Debug Wait Enable */ | ||
112 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | ||
113 | #define MSR_IS MSR_IR /* Instruction Space */ | ||
114 | #define MSR_DS MSR_DR /* Data Space */ | ||
115 | #define MSR_PMM (1<<2) /* Performance monitor mark bit */ | ||
116 | |||
117 | /* Default MSR for kernel mode. */ | ||
118 | #if defined (CONFIG_40x) | ||
119 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) | ||
120 | #elif defined(CONFIG_BOOKE) | ||
121 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) | ||
122 | #endif | ||
123 | |||
124 | /* Special Purpose Registers (SPRNs)*/ | ||
125 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | ||
126 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | ||
127 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | ||
128 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ | ||
129 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | ||
130 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | ||
131 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | ||
132 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | ||
133 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | ||
134 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | ||
135 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | ||
136 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ | ||
137 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ | ||
138 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | ||
139 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | ||
140 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | ||
141 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | ||
142 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | ||
143 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | ||
144 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | ||
145 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | ||
146 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | ||
147 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | ||
148 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | ||
149 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | ||
150 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | ||
151 | #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ | ||
152 | #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ | ||
153 | #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ | ||
154 | #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ | ||
155 | #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ | ||
156 | #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ | ||
157 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ | ||
158 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | ||
159 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | ||
160 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ | ||
161 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | ||
162 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | ||
163 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | ||
164 | #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ | ||
165 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | ||
166 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | ||
167 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | ||
168 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ | ||
169 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | ||
170 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | ||
171 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | ||
172 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | ||
173 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | ||
174 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | ||
175 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | ||
176 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | ||
177 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ | ||
178 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | ||
179 | #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ | ||
180 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ | ||
181 | #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ | ||
182 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ | ||
183 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ | ||
184 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | ||
185 | #define SPRN_SLER 0x3BB /* Little-endian real mode */ | ||
186 | #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ | ||
187 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | ||
188 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | ||
189 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | ||
190 | #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ | ||
191 | #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ | ||
192 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ | ||
193 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ | ||
194 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | ||
195 | #define SPRN_SVR 0x3FF /* System Version Register */ | ||
196 | |||
197 | /* | ||
198 | * SPRs which have conflicting definitions on true Book E versus classic, | ||
199 | * or IBM 40x. | ||
200 | */ | ||
201 | #ifdef CONFIG_BOOKE | ||
202 | #define SPRN_PID 0x030 /* Process ID */ | ||
203 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | ||
204 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ | ||
205 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | ||
206 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | ||
207 | #define SPRN_ESR 0x03E /* Exception Syndrome Register */ | ||
208 | #define SPRN_PIR 0x11E /* Processor Identification Register */ | ||
209 | #define SPRN_DBSR 0x130 /* Debug Status Register */ | ||
210 | #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ | ||
211 | #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ | ||
212 | #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ | ||
213 | #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ | ||
214 | #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ | ||
215 | #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ | ||
216 | #define SPRN_TSR 0x150 /* Timer Status Register */ | ||
217 | #define SPRN_TCR 0x154 /* Timer Control Register */ | ||
218 | #endif /* Book E */ | ||
219 | #ifdef CONFIG_40x | ||
220 | #define SPRN_PID 0x3B1 /* Process ID */ | ||
221 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ | ||
222 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | ||
223 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | ||
224 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ | ||
225 | #define SPRN_TCR 0x3DA /* Timer Control Register */ | ||
226 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | ||
227 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | ||
228 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | ||
229 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | ||
230 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ | ||
231 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | ||
232 | #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ | ||
233 | #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ | ||
234 | #endif | ||
235 | |||
236 | /* Bit definitions for CCR1. */ | ||
237 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | ||
238 | |||
239 | /* Bit definitions for the MCSR. */ | ||
240 | #ifdef CONFIG_440A | ||
241 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ | ||
242 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | ||
243 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ | ||
244 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | ||
245 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ | ||
246 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | ||
247 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | ||
248 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | ||
249 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | ||
250 | #endif | ||
251 | #ifdef CONFIG_E500 | ||
252 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | ||
253 | #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ | ||
254 | #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ | ||
255 | #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ | ||
256 | #define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ | ||
257 | #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ | ||
258 | #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ | ||
259 | #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ | ||
260 | #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ | ||
261 | #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ | ||
262 | #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ | ||
263 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ | ||
264 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ | ||
265 | #endif | ||
266 | |||
267 | /* Bit definitions for the DBSR. */ | ||
268 | /* | ||
269 | * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. | ||
270 | */ | ||
271 | #ifdef CONFIG_BOOKE | ||
272 | #define DBSR_IC 0x08000000 /* Instruction Completion */ | ||
273 | #define DBSR_BT 0x04000000 /* Branch Taken */ | ||
274 | #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ | ||
275 | #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ | ||
276 | #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ | ||
277 | #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ | ||
278 | #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ | ||
279 | #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ | ||
280 | #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ | ||
281 | #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ | ||
282 | #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ | ||
283 | #endif | ||
284 | #ifdef CONFIG_40x | ||
285 | #define DBSR_IC 0x80000000 /* Instruction Completion */ | ||
286 | #define DBSR_BT 0x40000000 /* Branch taken */ | ||
287 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ | ||
288 | #define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */ | ||
289 | #define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */ | ||
290 | #define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */ | ||
291 | #define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */ | ||
292 | #define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */ | ||
293 | #define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */ | ||
294 | #define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */ | ||
295 | #define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */ | ||
296 | #endif | ||
297 | |||
298 | /* Bit definitions related to the ESR. */ | ||
299 | #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ | ||
300 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ | ||
301 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | ||
302 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | ||
303 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | ||
304 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | ||
305 | #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ | ||
306 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ | ||
307 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | ||
308 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | ||
309 | #define ESR_ST 0x00800000 /* Store Operation */ | ||
310 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | ||
311 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | ||
312 | #define ESR_BO 0x00020000 /* Byte Ordering */ | ||
313 | |||
314 | /* Bit definitions related to the DBCR0. */ | ||
315 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ | ||
316 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | ||
317 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | ||
318 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | ||
319 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | ||
320 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | ||
321 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | ||
322 | #define DBCR0_IC 0x08000000 /* Instruction Completion */ | ||
323 | #define DBCR0_BT 0x04000000 /* Branch Taken */ | ||
324 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ | ||
325 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ | ||
326 | #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ | ||
327 | #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ | ||
328 | #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ | ||
329 | #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ | ||
330 | #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ | ||
331 | #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ | ||
332 | #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ | ||
333 | #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ | ||
334 | #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ | ||
335 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | ||
336 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | ||
337 | |||
338 | /* Bit definitions related to the TCR. */ | ||
339 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ | ||
340 | #define TCR_WP_MASK TCR_WP(3) | ||
341 | #define WP_2_17 0 /* 2^17 clocks */ | ||
342 | #define WP_2_21 1 /* 2^21 clocks */ | ||
343 | #define WP_2_25 2 /* 2^25 clocks */ | ||
344 | #define WP_2_29 3 /* 2^29 clocks */ | ||
345 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | ||
346 | #define TCR_WRC_MASK TCR_WRC(3) | ||
347 | #define WRC_NONE 0 /* No reset will occur */ | ||
348 | #define WRC_CORE 1 /* Core reset will occur */ | ||
349 | #define WRC_CHIP 2 /* Chip reset will occur */ | ||
350 | #define WRC_SYSTEM 3 /* System reset will occur */ | ||
351 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | ||
352 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | ||
353 | #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ | ||
354 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | ||
355 | #define TCR_FP_MASK TCR_FP(3) | ||
356 | #define FP_2_9 0 /* 2^9 clocks */ | ||
357 | #define FP_2_13 1 /* 2^13 clocks */ | ||
358 | #define FP_2_17 2 /* 2^17 clocks */ | ||
359 | #define FP_2_21 3 /* 2^21 clocks */ | ||
360 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | ||
361 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | ||
362 | |||
363 | /* Bit definitions for the TSR. */ | ||
364 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ | ||
365 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | ||
366 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | ||
367 | #define WRS_NONE 0 /* No WDT reset occurred */ | ||
368 | #define WRS_CORE 1 /* WDT forced core reset */ | ||
369 | #define WRS_CHIP 2 /* WDT forced chip reset */ | ||
370 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | ||
371 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | ||
372 | #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ | ||
373 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | ||
374 | |||
375 | /* Bit definitions for the DCCR. */ | ||
376 | #define DCCR_NOCACHE 0 /* Noncacheable */ | ||
377 | #define DCCR_CACHE 1 /* Cacheable */ | ||
378 | |||
379 | /* Bit definitions for DCWR. */ | ||
380 | #define DCWR_COPY 0 /* Copy-back */ | ||
381 | #define DCWR_WRITE 1 /* Write-through */ | ||
382 | |||
383 | /* Bit definitions for ICCR. */ | ||
384 | #define ICCR_NOCACHE 0 /* Noncacheable */ | ||
385 | #define ICCR_CACHE 1 /* Cacheable */ | ||
386 | |||
387 | /* Bit definitions for L1CSR0. */ | ||
388 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | ||
389 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | ||
390 | |||
391 | /* Bit definitions for L1CSR0. */ | ||
392 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | ||
393 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | ||
394 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | ||
395 | |||
396 | /* Bit definitions for SGR. */ | ||
397 | #define SGR_NORMAL 0 /* Speculative fetching allowed. */ | ||
398 | #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ | ||
399 | |||
400 | /* Bit definitions for SPEFSCR. */ | ||
401 | #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ | ||
402 | #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ | ||
403 | #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ | ||
404 | #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ | ||
405 | #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ | ||
406 | #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ | ||
407 | #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ | ||
408 | #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ | ||
409 | #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ | ||
410 | #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ | ||
411 | #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ | ||
412 | #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ | ||
413 | #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ | ||
414 | #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ | ||
415 | #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ | ||
416 | #define SPEFSCR_OV 0x00004000 /* Integer overflow */ | ||
417 | #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ | ||
418 | #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ | ||
419 | #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ | ||
420 | #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ | ||
421 | #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ | ||
422 | #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ | ||
423 | #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ | ||
424 | #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ | ||
425 | #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ | ||
426 | #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ | ||
427 | #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ | ||
428 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | ||
429 | |||
430 | /* | ||
431 | * The IBM-403 is an even more odd special case, as it is much | ||
432 | * older than the IBM-405 series. We put these down here incase someone | ||
433 | * wishes to support these machines again. | ||
434 | */ | ||
435 | #ifdef CONFIG_403GCX | ||
436 | /* Special Purpose Registers (SPRNs)*/ | ||
437 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | ||
438 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | ||
439 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | ||
440 | #define SPRN_TBHI 0x3DC /* Time Base High */ | ||
441 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | ||
442 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ | ||
443 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | ||
444 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | ||
445 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | ||
446 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | ||
447 | |||
448 | |||
449 | /* Bit definitions for the DBCR. */ | ||
450 | #define DBCR_EDM DBCR0_EDM | ||
451 | #define DBCR_IDM DBCR0_IDM | ||
452 | #define DBCR_RST(x) (((x) & 0x3) << 28) | ||
453 | #define DBCR_RST_NONE 0 | ||
454 | #define DBCR_RST_CORE 1 | ||
455 | #define DBCR_RST_CHIP 2 | ||
456 | #define DBCR_RST_SYSTEM 3 | ||
457 | #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ | ||
458 | #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ | ||
459 | #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ | ||
460 | #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ | ||
461 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | ||
462 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | ||
463 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | ||
464 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | ||
465 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | ||
466 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | ||
467 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | ||
468 | #define DAC_BYTE 0 | ||
469 | #define DAC_HALF 1 | ||
470 | #define DAC_WORD 2 | ||
471 | #define DAC_QUAD 3 | ||
472 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | ||
473 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | ||
474 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | ||
475 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | ||
476 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | ||
477 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | ||
478 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | ||
479 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | ||
480 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | ||
481 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | ||
482 | #endif /* 403GCX */ | ||
483 | #endif /* __ASM_PPC_REG_BOOKE_H__ */ | ||
484 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h new file mode 100644 index 000000000000..934810d25667 --- /dev/null +++ b/include/asm-ppc/residual.h | |||
@@ -0,0 +1,350 @@ | |||
1 | /* 7/18/95 */ | ||
2 | /*----------------------------------------------------------------------------*/ | ||
3 | /* Residual Data header definitions and prototypes */ | ||
4 | /*----------------------------------------------------------------------------*/ | ||
5 | |||
6 | /* Structure map for RESIDUAL on PowerPC Reference Platform */ | ||
7 | /* residual.h - Residual data structure passed in r3. */ | ||
8 | /* Load point passed in r4 to boot image. */ | ||
9 | /* For enum's: if given in hex then they are bit significant, */ | ||
10 | /* i.e. only one bit is on for each enum */ | ||
11 | /* Reserved fields must be filled with zeros. */ | ||
12 | |||
13 | #ifdef __KERNEL__ | ||
14 | #ifndef _RESIDUAL_ | ||
15 | #define _RESIDUAL_ | ||
16 | |||
17 | #ifndef __ASSEMBLY__ | ||
18 | |||
19 | #define MAX_CPUS 32 /* These should be set to the maximum */ | ||
20 | #define MAX_MEMS 64 /* number possible for this system. */ | ||
21 | #define MAX_DEVICES 256 /* Changing these will change the */ | ||
22 | #define AVE_PNP_SIZE 32 /* structure, hence the version of */ | ||
23 | #define MAX_MEM_SEGS 64 /* this header file. */ | ||
24 | |||
25 | /*----------------------------------------------------------------------------*/ | ||
26 | /* Public structures... */ | ||
27 | /*----------------------------------------------------------------------------*/ | ||
28 | |||
29 | #include <asm/pnp.h> | ||
30 | |||
31 | typedef enum _L1CACHE_TYPE { | ||
32 | NoneCAC = 0, | ||
33 | SplitCAC = 1, | ||
34 | CombinedCAC = 2 | ||
35 | } L1CACHE_TYPE; | ||
36 | |||
37 | typedef enum _TLB_TYPE { | ||
38 | NoneTLB = 0, | ||
39 | SplitTLB = 1, | ||
40 | CombinedTLB = 2 | ||
41 | } TLB_TYPE; | ||
42 | |||
43 | typedef enum _FIRMWARE_SUPPORT { | ||
44 | Conventional = 0x01, | ||
45 | OpenFirmware = 0x02, | ||
46 | Diagnostics = 0x04, | ||
47 | LowDebug = 0x08, | ||
48 | Multiboot = 0x10, | ||
49 | LowClient = 0x20, | ||
50 | Hex41 = 0x40, | ||
51 | FAT = 0x80, | ||
52 | ISO9660 = 0x0100, | ||
53 | SCSI_InitiatorID_Override = 0x0200, | ||
54 | Tape_Boot = 0x0400, | ||
55 | FW_Boot_Path = 0x0800 | ||
56 | } FIRMWARE_SUPPORT; | ||
57 | |||
58 | typedef enum _FIRMWARE_SUPPLIERS { | ||
59 | IBMFirmware = 0x00, | ||
60 | MotoFirmware = 0x01, /* 7/18/95 */ | ||
61 | FirmWorks = 0x02, /* 10/5/95 */ | ||
62 | Bull = 0x03, /* 04/03/96 */ | ||
63 | } FIRMWARE_SUPPLIERS; | ||
64 | |||
65 | typedef enum _ENDIAN_SWITCH_METHODS { | ||
66 | UsePort92 = 0x01, | ||
67 | UsePCIConfigA8 = 0x02, | ||
68 | UseFF001030 = 0x03, | ||
69 | } ENDIAN_SWITCH_METHODS; | ||
70 | |||
71 | typedef enum _SPREAD_IO_METHODS { | ||
72 | UsePort850 = 0x00, | ||
73 | /*UsePCIConfigA8 = 0x02,*/ | ||
74 | } SPREAD_IO_METHODS; | ||
75 | |||
76 | typedef struct _VPD { | ||
77 | |||
78 | /* Box dependent stuff */ | ||
79 | unsigned char PrintableModel[32]; /* Null terminated string. | ||
80 | Must be of the form: | ||
81 | vvv,<20h>,<model designation>,<0x0> | ||
82 | where vvv is the vendor ID | ||
83 | e.g. IBM PPS MODEL 6015<0x0> */ | ||
84 | unsigned char Serial[16]; /* 12/94: | ||
85 | Serial Number; must be of the form: | ||
86 | vvv<serial number> where vvv is the | ||
87 | vendor ID. | ||
88 | e.g. IBM60151234567<20h><20h> */ | ||
89 | unsigned char Reserved[48]; | ||
90 | unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ | ||
91 | unsigned long FirmwareSupports; /* See FirmwareSupport enum */ | ||
92 | unsigned long NvramSize; /* Size of nvram in bytes */ | ||
93 | unsigned long NumSIMMSlots; | ||
94 | unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ | ||
95 | unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ | ||
96 | unsigned long SmpIar; | ||
97 | unsigned long RAMErrLogOffset; /* Heap offset to error log */ | ||
98 | unsigned long Reserved5; | ||
99 | unsigned long Reserved6; | ||
100 | unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ | ||
101 | unsigned long ProcessorBusHz; /* Processor bus clock frequency */ | ||
102 | unsigned long Reserved7; | ||
103 | unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ | ||
104 | unsigned long WordWidth; /* Word width in bits */ | ||
105 | unsigned long PageSize; /* Page size in bytes */ | ||
106 | unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache | ||
107 | for which coherency is maintained; | ||
108 | normally <= CacheLineSize. */ | ||
109 | unsigned long GranuleSize; /* Unit of lock allocation to avoid */ | ||
110 | /* false sharing of locks. */ | ||
111 | |||
112 | /* L1 Cache variables */ | ||
113 | unsigned long CacheSize; /* L1 Cache size in KB. This is the */ | ||
114 | /* total size of the L1, whether */ | ||
115 | /* combined or split */ | ||
116 | unsigned long CacheAttrib; /* L1CACHE_TYPE */ | ||
117 | unsigned long CacheAssoc; /* L1 Cache associativity. Use this | ||
118 | for combined cache. If split, put | ||
119 | zeros here. */ | ||
120 | unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use | ||
121 | for combined cache. If split, put | ||
122 | zeros here. */ | ||
123 | /* For split L1 Cache: (= combined if combined cache) */ | ||
124 | unsigned long I_CacheSize; | ||
125 | unsigned long I_CacheAssoc; | ||
126 | unsigned long I_CacheLineSize; | ||
127 | unsigned long D_CacheSize; | ||
128 | unsigned long D_CacheAssoc; | ||
129 | unsigned long D_CacheLineSize; | ||
130 | |||
131 | /* Translation Lookaside Buffer variables */ | ||
132 | unsigned long TLBSize; /* Total number of TLBs on the system */ | ||
133 | unsigned long TLBAttrib; /* Combined I+D or split TLB */ | ||
134 | unsigned long TLBAssoc; /* TLB Associativity. Use this for | ||
135 | combined TLB. If split, put zeros | ||
136 | here. */ | ||
137 | /* For split TLB: (= combined if combined TLB) */ | ||
138 | unsigned long I_TLBSize; | ||
139 | unsigned long I_TLBAssoc; | ||
140 | unsigned long D_TLBSize; | ||
141 | unsigned long D_TLBAssoc; | ||
142 | |||
143 | unsigned long ExtendedVPD; /* Offset to extended VPD area; | ||
144 | null if unused */ | ||
145 | } VPD; | ||
146 | |||
147 | typedef enum _DEVICE_FLAGS { | ||
148 | Enabled = 0x4000, /* 1 - PCI device is enabled */ | ||
149 | Integrated = 0x2000, | ||
150 | Failed = 0x1000, /* 1 - device failed POST code tests */ | ||
151 | Static = 0x0800, /* 0 - dynamically configurable | ||
152 | 1 - static */ | ||
153 | Dock = 0x0400, /* 0 - not a docking station device | ||
154 | 1 - is a docking station device */ | ||
155 | Boot = 0x0200, /* 0 - device cannot be used for BOOT | ||
156 | 1 - can be a BOOT device */ | ||
157 | Configurable = 0x0100, /* 1 - device is configurable */ | ||
158 | Disableable = 0x80, /* 1 - device can be disabled */ | ||
159 | PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ | ||
160 | ReadOnly = 0x20, /* 1 - device is read only */ | ||
161 | Removable = 0x10, /* 1 - device is removable */ | ||
162 | ConsoleIn = 0x08, | ||
163 | ConsoleOut = 0x04, | ||
164 | Input = 0x02, | ||
165 | Output = 0x01 | ||
166 | } DEVICE_FLAGS; | ||
167 | |||
168 | typedef enum _BUS_ID { | ||
169 | ISADEVICE = 0x01, | ||
170 | EISADEVICE = 0x02, | ||
171 | PCIDEVICE = 0x04, | ||
172 | PCMCIADEVICE = 0x08, | ||
173 | PNPISADEVICE = 0x10, | ||
174 | MCADEVICE = 0x20, | ||
175 | MXDEVICE = 0x40, /* Devices on mezzanine bus */ | ||
176 | PROCESSORDEVICE = 0x80, /* Devices on processor bus */ | ||
177 | VMEDEVICE = 0x100, | ||
178 | } BUS_ID; | ||
179 | |||
180 | typedef struct _DEVICE_ID { | ||
181 | unsigned long BusId; /* See BUS_ID enum above */ | ||
182 | unsigned long DevId; /* Big Endian format */ | ||
183 | unsigned long SerialNum; /* For multiple usage of a single | ||
184 | DevId */ | ||
185 | unsigned long Flags; /* See DEVICE_FLAGS enum above */ | ||
186 | unsigned char BaseType; /* See pnp.h for bit definitions */ | ||
187 | unsigned char SubType; /* See pnp.h for bit definitions */ | ||
188 | unsigned char Interface; /* See pnp.h for bit definitions */ | ||
189 | unsigned char Spare; | ||
190 | } DEVICE_ID; | ||
191 | |||
192 | typedef union _BUS_ACCESS { | ||
193 | struct _PnPAccess{ | ||
194 | unsigned char CSN; | ||
195 | unsigned char LogicalDevNumber; | ||
196 | unsigned short ReadDataPort; | ||
197 | } PnPAccess; | ||
198 | struct _ISAAccess{ | ||
199 | unsigned char SlotNumber; /* ISA Slot Number generally not | ||
200 | available; 0 if unknown */ | ||
201 | unsigned char LogicalDevNumber; | ||
202 | unsigned short ISAReserved; | ||
203 | } ISAAccess; | ||
204 | struct _MCAAccess{ | ||
205 | unsigned char SlotNumber; | ||
206 | unsigned char LogicalDevNumber; | ||
207 | unsigned short MCAReserved; | ||
208 | } MCAAccess; | ||
209 | struct _PCMCIAAccess{ | ||
210 | unsigned char SlotNumber; | ||
211 | unsigned char LogicalDevNumber; | ||
212 | unsigned short PCMCIAReserved; | ||
213 | } PCMCIAAccess; | ||
214 | struct _EISAAccess{ | ||
215 | unsigned char SlotNumber; | ||
216 | unsigned char FunctionNumber; | ||
217 | unsigned short EISAReserved; | ||
218 | } EISAAccess; | ||
219 | struct _PCIAccess{ | ||
220 | unsigned char BusNumber; | ||
221 | unsigned char DevFuncNumber; | ||
222 | unsigned short PCIReserved; | ||
223 | } PCIAccess; | ||
224 | struct _ProcBusAccess{ | ||
225 | unsigned char BusNumber; | ||
226 | unsigned char BUID; | ||
227 | unsigned short ProcBusReserved; | ||
228 | } ProcBusAccess; | ||
229 | } BUS_ACCESS; | ||
230 | |||
231 | /* Per logical device information */ | ||
232 | typedef struct _PPC_DEVICE { | ||
233 | DEVICE_ID DeviceId; | ||
234 | BUS_ACCESS BusAccess; | ||
235 | |||
236 | /* The following three are offsets into the DevicePnPHeap */ | ||
237 | /* All are in PnP compressed format */ | ||
238 | unsigned long AllocatedOffset; /* Allocated resource description */ | ||
239 | unsigned long PossibleOffset; /* Possible resource description */ | ||
240 | unsigned long CompatibleOffset; /* Compatible device identifiers */ | ||
241 | } PPC_DEVICE; | ||
242 | |||
243 | typedef enum _CPU_STATE { | ||
244 | CPU_GOOD = 0, /* CPU is present, and active */ | ||
245 | CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ | ||
246 | CPU_OFF = 2, /* CPU is present, but inactive */ | ||
247 | CPU_FAILED = 3, /* CPU is present, but failed POST */ | ||
248 | CPU_NOT_PRESENT = 255 /* CPU not present */ | ||
249 | } CPU_STATE; | ||
250 | |||
251 | typedef struct _PPC_CPU { | ||
252 | unsigned long CpuType; /* Result of mfspr from Processor | ||
253 | Version Register (PVR). | ||
254 | PVR(0-15) = Version (e.g. 601) | ||
255 | PVR(16-31 = EC Level */ | ||
256 | unsigned char CpuNumber; /* CPU Number for this processor */ | ||
257 | unsigned char CpuState; /* CPU State, see CPU_STATE enum */ | ||
258 | unsigned short Reserved; | ||
259 | } PPC_CPU; | ||
260 | |||
261 | typedef struct _PPC_MEM { | ||
262 | unsigned long SIMMSize; /* 0 - absent or bad | ||
263 | 8M, 32M (in MB) */ | ||
264 | } PPC_MEM; | ||
265 | |||
266 | typedef enum _MEM_USAGE { | ||
267 | Other = 0x8000, | ||
268 | ResumeBlock = 0x4000, /* for use by power management */ | ||
269 | SystemROM = 0x2000, /* Flash memory (populated) */ | ||
270 | UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ | ||
271 | IOMemory = 0x0800, | ||
272 | SystemIO = 0x0400, | ||
273 | SystemRegs = 0x0200, | ||
274 | PCIAddr = 0x0100, | ||
275 | PCIConfig = 0x80, | ||
276 | ISAAddr = 0x40, | ||
277 | Unpopulated = 0x20, /* Unpopulated part of System Memory */ | ||
278 | Free = 0x10, /* Free part of System Memory */ | ||
279 | BootImage = 0x08, /* BootImage part of System Memory */ | ||
280 | FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ | ||
281 | FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ | ||
282 | FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ | ||
283 | } MEM_USAGE; | ||
284 | |||
285 | typedef struct _MEM_MAP { | ||
286 | unsigned long Usage; /* See MEM_USAGE above */ | ||
287 | unsigned long BasePage; /* Page number measured in 4KB pages */ | ||
288 | unsigned long PageCount; /* Page count measured in 4KB pages */ | ||
289 | } MEM_MAP; | ||
290 | |||
291 | typedef struct _RESIDUAL { | ||
292 | unsigned long ResidualLength; /* Length of Residual */ | ||
293 | unsigned char Version; /* of this data structure */ | ||
294 | unsigned char Revision; /* of this data structure */ | ||
295 | unsigned short EC; /* of this data structure */ | ||
296 | /* VPD */ | ||
297 | VPD VitalProductData; | ||
298 | /* CPU */ | ||
299 | unsigned short MaxNumCpus; /* Max CPUs in this system */ | ||
300 | unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ | ||
301 | /* that there are unpopulated or */ | ||
302 | /* otherwise unusable cpu locations */ | ||
303 | PPC_CPU Cpus[MAX_CPUS]; | ||
304 | /* Memory */ | ||
305 | unsigned long TotalMemory; /* Total amount of memory installed */ | ||
306 | unsigned long GoodMemory; /* Total amount of good memory */ | ||
307 | unsigned long ActualNumMemSegs; | ||
308 | MEM_MAP Segs[MAX_MEM_SEGS]; | ||
309 | unsigned long ActualNumMemories; | ||
310 | PPC_MEM Memories[MAX_MEMS]; | ||
311 | /* Devices */ | ||
312 | unsigned long ActualNumDevices; | ||
313 | PPC_DEVICE Devices[MAX_DEVICES]; | ||
314 | unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; | ||
315 | } RESIDUAL; | ||
316 | |||
317 | |||
318 | /* | ||
319 | * Forward declaration - we can't include <linux/pci.h> because it | ||
320 | * breaks the boot loader | ||
321 | */ | ||
322 | struct pci_dev; | ||
323 | |||
324 | extern RESIDUAL *res; | ||
325 | extern void print_residual_device_info(void); | ||
326 | extern PPC_DEVICE *residual_find_device(unsigned long BusMask, | ||
327 | unsigned char * DevID, int BaseType, | ||
328 | int SubType, int Interface, int n); | ||
329 | extern int residual_pcidev_irq(struct pci_dev *dev); | ||
330 | extern void residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi); | ||
331 | extern unsigned int residual_isapic_addr(void); | ||
332 | extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, | ||
333 | int n); | ||
334 | extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, | ||
335 | unsigned packet_type, | ||
336 | int n); | ||
337 | extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, | ||
338 | unsigned packet_type, | ||
339 | int n); | ||
340 | |||
341 | #ifdef CONFIG_PREP_RESIDUAL | ||
342 | #define have_residual_data (res && res->ResidualLength) | ||
343 | #else | ||
344 | #define have_residual_data 0 | ||
345 | #endif | ||
346 | |||
347 | #endif /* __ASSEMBLY__ */ | ||
348 | #endif /* ndef _RESIDUAL_ */ | ||
349 | |||
350 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/resource.h b/include/asm-ppc/resource.h new file mode 100644 index 000000000000..86a1ea23a6ed --- /dev/null +++ b/include/asm-ppc/resource.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _PPC_RESOURCE_H | ||
2 | #define _PPC_RESOURCE_H | ||
3 | |||
4 | #include <asm-generic/resource.h> | ||
5 | |||
6 | #endif | ||
diff --git a/include/asm-ppc/rheap.h b/include/asm-ppc/rheap.h new file mode 100644 index 000000000000..e6ca1f67cedc --- /dev/null +++ b/include/asm-ppc/rheap.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/rheap.c | ||
3 | * | ||
4 | * Header file for the implementation of a remote heap. | ||
5 | * | ||
6 | * Author: Pantelis Antoniou <panto@intracom.gr> | ||
7 | * | ||
8 | * 2004 (c) INTRACOM S.A. Greece. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_PPC_RHEAP_H__ | ||
15 | #define __ASM_PPC_RHEAP_H__ | ||
16 | |||
17 | #include <linux/list.h> | ||
18 | |||
19 | typedef struct _rh_block { | ||
20 | struct list_head list; | ||
21 | void *start; | ||
22 | int size; | ||
23 | const char *owner; | ||
24 | } rh_block_t; | ||
25 | |||
26 | typedef struct _rh_info { | ||
27 | unsigned int alignment; | ||
28 | int max_blocks; | ||
29 | int empty_slots; | ||
30 | rh_block_t *block; | ||
31 | struct list_head empty_list; | ||
32 | struct list_head free_list; | ||
33 | struct list_head taken_list; | ||
34 | unsigned int flags; | ||
35 | } rh_info_t; | ||
36 | |||
37 | #define RHIF_STATIC_INFO 0x1 | ||
38 | #define RHIF_STATIC_BLOCK 0x2 | ||
39 | |||
40 | typedef struct rh_stats_t { | ||
41 | void *start; | ||
42 | int size; | ||
43 | const char *owner; | ||
44 | } rh_stats_t; | ||
45 | |||
46 | #define RHGS_FREE 0 | ||
47 | #define RHGS_TAKEN 1 | ||
48 | |||
49 | /* Create a remote heap dynamically */ | ||
50 | extern rh_info_t *rh_create(unsigned int alignment); | ||
51 | |||
52 | /* Destroy a remote heap, created by rh_create() */ | ||
53 | extern void rh_destroy(rh_info_t * info); | ||
54 | |||
55 | /* Initialize in place a remote info block */ | ||
56 | extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks, | ||
57 | rh_block_t * block); | ||
58 | |||
59 | /* Attach a free region to manage */ | ||
60 | extern int rh_attach_region(rh_info_t * info, void *start, int size); | ||
61 | |||
62 | /* Detach a free region */ | ||
63 | extern void *rh_detach_region(rh_info_t * info, void *start, int size); | ||
64 | |||
65 | /* Allocate the given size from the remote heap */ | ||
66 | extern void *rh_alloc(rh_info_t * info, int size, const char *owner); | ||
67 | |||
68 | /* Allocate the given size from the given address */ | ||
69 | extern void *rh_alloc_fixed(rh_info_t * info, void *start, int size, | ||
70 | const char *owner); | ||
71 | |||
72 | /* Free the allocated area */ | ||
73 | extern int rh_free(rh_info_t * info, void *start); | ||
74 | |||
75 | /* Get stats for debugging purposes */ | ||
76 | extern int rh_get_stats(rh_info_t * info, int what, int max_stats, | ||
77 | rh_stats_t * stats); | ||
78 | |||
79 | /* Simple dump of remote heap info */ | ||
80 | extern void rh_dump(rh_info_t * info); | ||
81 | |||
82 | /* Set owner of taken block */ | ||
83 | extern int rh_set_owner(rh_info_t * info, void *start, const char *owner); | ||
84 | |||
85 | #endif /* __ASM_PPC_RHEAP_H__ */ | ||
diff --git a/include/asm-ppc/rtc.h b/include/asm-ppc/rtc.h new file mode 100644 index 000000000000..05fbf912ab4d --- /dev/null +++ b/include/asm-ppc/rtc.h | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * inclue/asm-ppc/rtc.h | ||
3 | * | ||
4 | * Author: Tom Rini <trini@mvista.com> | ||
5 | * | ||
6 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | * | ||
11 | * Based on: | ||
12 | * include/asm-m68k/rtc.h | ||
13 | * | ||
14 | * Copyright Richard Zidlicky | ||
15 | * implementation details for genrtc/q40rtc driver | ||
16 | * | ||
17 | * And the old drivers/macintosh/rtc.c which was heavily based on: | ||
18 | * Linux/SPARC Real Time Clock Driver | ||
19 | * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) | ||
20 | * | ||
21 | * With additional work by Paul Mackerras and Franz Sirl. | ||
22 | */ | ||
23 | |||
24 | #ifndef __ASM_RTC_H__ | ||
25 | #define __ASM_RTC_H__ | ||
26 | |||
27 | #ifdef __KERNEL__ | ||
28 | |||
29 | #include <linux/rtc.h> | ||
30 | |||
31 | #include <asm/machdep.h> | ||
32 | #include <asm/time.h> | ||
33 | |||
34 | #define RTC_PIE 0x40 /* periodic interrupt enable */ | ||
35 | #define RTC_AIE 0x20 /* alarm interrupt enable */ | ||
36 | #define RTC_UIE 0x10 /* update-finished interrupt enable */ | ||
37 | |||
38 | /* some dummy definitions */ | ||
39 | #define RTC_BATT_BAD 0x100 /* battery bad */ | ||
40 | #define RTC_SQWE 0x08 /* enable square-wave output */ | ||
41 | #define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ | ||
42 | #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ | ||
43 | #define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ | ||
44 | |||
45 | static inline unsigned int get_rtc_time(struct rtc_time *time) | ||
46 | { | ||
47 | if (ppc_md.get_rtc_time) { | ||
48 | unsigned long nowtime; | ||
49 | |||
50 | nowtime = (ppc_md.get_rtc_time)(); | ||
51 | |||
52 | to_tm(nowtime, time); | ||
53 | |||
54 | time->tm_year -= 1900; | ||
55 | time->tm_mon -= 1; /* Make sure userland has a 0-based month */ | ||
56 | } | ||
57 | return RTC_24H; | ||
58 | } | ||
59 | |||
60 | /* Set the current date and time in the real time clock. */ | ||
61 | static inline int set_rtc_time(struct rtc_time *time) | ||
62 | { | ||
63 | if (ppc_md.get_rtc_time) { | ||
64 | unsigned long nowtime; | ||
65 | |||
66 | nowtime = mktime(time->tm_year+1900, time->tm_mon+1, | ||
67 | time->tm_mday, time->tm_hour, time->tm_min, | ||
68 | time->tm_sec); | ||
69 | |||
70 | (ppc_md.set_rtc_time)(nowtime); | ||
71 | |||
72 | return 0; | ||
73 | } else | ||
74 | return -EINVAL; | ||
75 | } | ||
76 | |||
77 | static inline unsigned int get_rtc_ss(void) | ||
78 | { | ||
79 | struct rtc_time h; | ||
80 | |||
81 | get_rtc_time(&h); | ||
82 | return h.tm_sec; | ||
83 | } | ||
84 | |||
85 | static inline int get_rtc_pll(struct rtc_pll_info *pll) | ||
86 | { | ||
87 | return -EINVAL; | ||
88 | } | ||
89 | static inline int set_rtc_pll(struct rtc_pll_info *pll) | ||
90 | { | ||
91 | return -EINVAL; | ||
92 | } | ||
93 | |||
94 | #endif /* __KERNEL__ */ | ||
95 | #endif /* __ASM_RTC_H__ */ | ||
diff --git a/include/asm-ppc/rwsem.h b/include/asm-ppc/rwsem.h new file mode 100644 index 000000000000..3e738f483c11 --- /dev/null +++ b/include/asm-ppc/rwsem.h | |||
@@ -0,0 +1,172 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/rwsem.h: R/W semaphores for PPC using the stuff | ||
3 | * in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h | ||
4 | * by Paul Mackerras <paulus@samba.org>. | ||
5 | */ | ||
6 | |||
7 | #ifndef _PPC_RWSEM_H | ||
8 | #define _PPC_RWSEM_H | ||
9 | |||
10 | #ifdef __KERNEL__ | ||
11 | #include <linux/list.h> | ||
12 | #include <linux/spinlock.h> | ||
13 | #include <asm/atomic.h> | ||
14 | #include <asm/system.h> | ||
15 | |||
16 | /* | ||
17 | * the semaphore definition | ||
18 | */ | ||
19 | struct rw_semaphore { | ||
20 | /* XXX this should be able to be an atomic_t -- paulus */ | ||
21 | signed long count; | ||
22 | #define RWSEM_UNLOCKED_VALUE 0x00000000 | ||
23 | #define RWSEM_ACTIVE_BIAS 0x00000001 | ||
24 | #define RWSEM_ACTIVE_MASK 0x0000ffff | ||
25 | #define RWSEM_WAITING_BIAS (-0x00010000) | ||
26 | #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS | ||
27 | #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) | ||
28 | spinlock_t wait_lock; | ||
29 | struct list_head wait_list; | ||
30 | #if RWSEM_DEBUG | ||
31 | int debug; | ||
32 | #endif | ||
33 | }; | ||
34 | |||
35 | /* | ||
36 | * initialisation | ||
37 | */ | ||
38 | #if RWSEM_DEBUG | ||
39 | #define __RWSEM_DEBUG_INIT , 0 | ||
40 | #else | ||
41 | #define __RWSEM_DEBUG_INIT /* */ | ||
42 | #endif | ||
43 | |||
44 | #define __RWSEM_INITIALIZER(name) \ | ||
45 | { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ | ||
46 | LIST_HEAD_INIT((name).wait_list) \ | ||
47 | __RWSEM_DEBUG_INIT } | ||
48 | |||
49 | #define DECLARE_RWSEM(name) \ | ||
50 | struct rw_semaphore name = __RWSEM_INITIALIZER(name) | ||
51 | |||
52 | extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); | ||
53 | extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); | ||
54 | extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); | ||
55 | extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); | ||
56 | |||
57 | static inline void init_rwsem(struct rw_semaphore *sem) | ||
58 | { | ||
59 | sem->count = RWSEM_UNLOCKED_VALUE; | ||
60 | spin_lock_init(&sem->wait_lock); | ||
61 | INIT_LIST_HEAD(&sem->wait_list); | ||
62 | #if RWSEM_DEBUG | ||
63 | sem->debug = 0; | ||
64 | #endif | ||
65 | } | ||
66 | |||
67 | /* | ||
68 | * lock for reading | ||
69 | */ | ||
70 | static inline void __down_read(struct rw_semaphore *sem) | ||
71 | { | ||
72 | if (atomic_inc_return((atomic_t *)(&sem->count)) > 0) | ||
73 | smp_wmb(); | ||
74 | else | ||
75 | rwsem_down_read_failed(sem); | ||
76 | } | ||
77 | |||
78 | static inline int __down_read_trylock(struct rw_semaphore *sem) | ||
79 | { | ||
80 | int tmp; | ||
81 | |||
82 | while ((tmp = sem->count) >= 0) { | ||
83 | if (tmp == cmpxchg(&sem->count, tmp, | ||
84 | tmp + RWSEM_ACTIVE_READ_BIAS)) { | ||
85 | smp_wmb(); | ||
86 | return 1; | ||
87 | } | ||
88 | } | ||
89 | return 0; | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | * lock for writing | ||
94 | */ | ||
95 | static inline void __down_write(struct rw_semaphore *sem) | ||
96 | { | ||
97 | int tmp; | ||
98 | |||
99 | tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS, | ||
100 | (atomic_t *)(&sem->count)); | ||
101 | if (tmp == RWSEM_ACTIVE_WRITE_BIAS) | ||
102 | smp_wmb(); | ||
103 | else | ||
104 | rwsem_down_write_failed(sem); | ||
105 | } | ||
106 | |||
107 | static inline int __down_write_trylock(struct rw_semaphore *sem) | ||
108 | { | ||
109 | int tmp; | ||
110 | |||
111 | tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, | ||
112 | RWSEM_ACTIVE_WRITE_BIAS); | ||
113 | smp_wmb(); | ||
114 | return tmp == RWSEM_UNLOCKED_VALUE; | ||
115 | } | ||
116 | |||
117 | /* | ||
118 | * unlock after reading | ||
119 | */ | ||
120 | static inline void __up_read(struct rw_semaphore *sem) | ||
121 | { | ||
122 | int tmp; | ||
123 | |||
124 | smp_wmb(); | ||
125 | tmp = atomic_dec_return((atomic_t *)(&sem->count)); | ||
126 | if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0) | ||
127 | rwsem_wake(sem); | ||
128 | } | ||
129 | |||
130 | /* | ||
131 | * unlock after writing | ||
132 | */ | ||
133 | static inline void __up_write(struct rw_semaphore *sem) | ||
134 | { | ||
135 | smp_wmb(); | ||
136 | if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS, | ||
137 | (atomic_t *)(&sem->count)) < 0) | ||
138 | rwsem_wake(sem); | ||
139 | } | ||
140 | |||
141 | /* | ||
142 | * implement atomic add functionality | ||
143 | */ | ||
144 | static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem) | ||
145 | { | ||
146 | atomic_add(delta, (atomic_t *)(&sem->count)); | ||
147 | } | ||
148 | |||
149 | /* | ||
150 | * downgrade write lock to read lock | ||
151 | */ | ||
152 | static inline void __downgrade_write(struct rw_semaphore *sem) | ||
153 | { | ||
154 | int tmp; | ||
155 | |||
156 | smp_wmb(); | ||
157 | tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count)); | ||
158 | if (tmp < 0) | ||
159 | rwsem_downgrade_wake(sem); | ||
160 | } | ||
161 | |||
162 | /* | ||
163 | * implement exchange and add functionality | ||
164 | */ | ||
165 | static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) | ||
166 | { | ||
167 | smp_mb(); | ||
168 | return atomic_add_return(delta, (atomic_t *)(&sem->count)); | ||
169 | } | ||
170 | |||
171 | #endif /* __KERNEL__ */ | ||
172 | #endif /* _PPC_RWSEM_XADD_H */ | ||
diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h new file mode 100644 index 000000000000..f21f18f56548 --- /dev/null +++ b/include/asm-ppc/scatterlist.h | |||
@@ -0,0 +1,25 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_SCATTERLIST_H | ||
3 | #define _PPC_SCATTERLIST_H | ||
4 | |||
5 | #include <asm/dma.h> | ||
6 | |||
7 | struct scatterlist { | ||
8 | struct page *page; | ||
9 | unsigned int offset; | ||
10 | dma_addr_t dma_address; | ||
11 | unsigned int length; | ||
12 | }; | ||
13 | |||
14 | /* | ||
15 | * These macros should be used after a pci_map_sg call has been done | ||
16 | * to get bus addresses of each of the SG entries and their lengths. | ||
17 | * You should only work with the number of sg entries pci_map_sg | ||
18 | * returns, or alternatively stop on the first sg_dma_len(sg) which | ||
19 | * is 0. | ||
20 | */ | ||
21 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
22 | #define sg_dma_len(sg) ((sg)->length) | ||
23 | |||
24 | #endif /* !(_PPC_SCATTERLIST_H) */ | ||
25 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/sections.h b/include/asm-ppc/sections.h new file mode 100644 index 000000000000..ba8f43ac9bf3 --- /dev/null +++ b/include/asm-ppc/sections.h | |||
@@ -0,0 +1,33 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_SECTIONS_H | ||
3 | #define _PPC_SECTIONS_H | ||
4 | |||
5 | #include <asm-generic/sections.h> | ||
6 | |||
7 | #define __pmac __attribute__ ((__section__ (".pmac.text"))) | ||
8 | #define __pmacdata __attribute__ ((__section__ (".pmac.data"))) | ||
9 | #define __pmacfunc(__argpmac) \ | ||
10 | __argpmac __pmac; \ | ||
11 | __argpmac | ||
12 | |||
13 | #define __prep __attribute__ ((__section__ (".prep.text"))) | ||
14 | #define __prepdata __attribute__ ((__section__ (".prep.data"))) | ||
15 | #define __prepfunc(__argprep) \ | ||
16 | __argprep __prep; \ | ||
17 | __argprep | ||
18 | |||
19 | #define __chrp __attribute__ ((__section__ (".chrp.text"))) | ||
20 | #define __chrpdata __attribute__ ((__section__ (".chrp.data"))) | ||
21 | #define __chrpfunc(__argchrp) \ | ||
22 | __argchrp __chrp; \ | ||
23 | __argchrp | ||
24 | |||
25 | /* this is actually just common chrp/pmac code, not OF code -- Cort */ | ||
26 | #define __openfirmware __attribute__ ((__section__ (".openfirmware.text"))) | ||
27 | #define __openfirmwaredata __attribute__ ((__section__ (".openfirmware.data"))) | ||
28 | #define __openfirmwarefunc(__argopenfirmware) \ | ||
29 | __argopenfirmware __openfirmware; \ | ||
30 | __argopenfirmware | ||
31 | |||
32 | #endif /* _PPC_SECTIONS_H */ | ||
33 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/segment.h b/include/asm-ppc/segment.h new file mode 100644 index 000000000000..0f2f7428d437 --- /dev/null +++ b/include/asm-ppc/segment.h | |||
@@ -0,0 +1 @@ | |||
#include <asm/uaccess.h> | |||
diff --git a/include/asm-ppc/semaphore.h b/include/asm-ppc/semaphore.h new file mode 100644 index 000000000000..89e6e73be08c --- /dev/null +++ b/include/asm-ppc/semaphore.h | |||
@@ -0,0 +1,111 @@ | |||
1 | #ifndef _PPC_SEMAPHORE_H | ||
2 | #define _PPC_SEMAPHORE_H | ||
3 | |||
4 | /* | ||
5 | * Swiped from asm-sparc/semaphore.h and modified | ||
6 | * -- Cort (cort@cs.nmt.edu) | ||
7 | * | ||
8 | * Stole some rw spinlock-based semaphore stuff from asm-alpha/semaphore.h | ||
9 | * -- Ani Joshi (ajoshi@unixbox.com) | ||
10 | * | ||
11 | * Remove spinlock-based RW semaphores; RW semaphore definitions are | ||
12 | * now in rwsem.h and we use the generic lib/rwsem.c implementation. | ||
13 | * Rework semaphores to use atomic_dec_if_positive. | ||
14 | * -- Paul Mackerras (paulus@samba.org) | ||
15 | */ | ||
16 | |||
17 | #ifdef __KERNEL__ | ||
18 | |||
19 | #include <asm/atomic.h> | ||
20 | #include <asm/system.h> | ||
21 | #include <linux/wait.h> | ||
22 | #include <linux/rwsem.h> | ||
23 | |||
24 | struct semaphore { | ||
25 | /* | ||
26 | * Note that any negative value of count is equivalent to 0, | ||
27 | * but additionally indicates that some process(es) might be | ||
28 | * sleeping on `wait'. | ||
29 | */ | ||
30 | atomic_t count; | ||
31 | wait_queue_head_t wait; | ||
32 | }; | ||
33 | |||
34 | #define __SEMAPHORE_INITIALIZER(name, n) \ | ||
35 | { \ | ||
36 | .count = ATOMIC_INIT(n), \ | ||
37 | .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ | ||
38 | } | ||
39 | |||
40 | #define __MUTEX_INITIALIZER(name) \ | ||
41 | __SEMAPHORE_INITIALIZER(name, 1) | ||
42 | |||
43 | #define __DECLARE_SEMAPHORE_GENERIC(name, count) \ | ||
44 | struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) | ||
45 | |||
46 | #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) | ||
47 | #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) | ||
48 | |||
49 | static inline void sema_init (struct semaphore *sem, int val) | ||
50 | { | ||
51 | atomic_set(&sem->count, val); | ||
52 | init_waitqueue_head(&sem->wait); | ||
53 | } | ||
54 | |||
55 | static inline void init_MUTEX (struct semaphore *sem) | ||
56 | { | ||
57 | sema_init(sem, 1); | ||
58 | } | ||
59 | |||
60 | static inline void init_MUTEX_LOCKED (struct semaphore *sem) | ||
61 | { | ||
62 | sema_init(sem, 0); | ||
63 | } | ||
64 | |||
65 | extern void __down(struct semaphore * sem); | ||
66 | extern int __down_interruptible(struct semaphore * sem); | ||
67 | extern void __up(struct semaphore * sem); | ||
68 | |||
69 | extern inline void down(struct semaphore * sem) | ||
70 | { | ||
71 | might_sleep(); | ||
72 | |||
73 | /* | ||
74 | * Try to get the semaphore, take the slow path if we fail. | ||
75 | */ | ||
76 | if (atomic_dec_return(&sem->count) < 0) | ||
77 | __down(sem); | ||
78 | smp_wmb(); | ||
79 | } | ||
80 | |||
81 | extern inline int down_interruptible(struct semaphore * sem) | ||
82 | { | ||
83 | int ret = 0; | ||
84 | |||
85 | might_sleep(); | ||
86 | |||
87 | if (atomic_dec_return(&sem->count) < 0) | ||
88 | ret = __down_interruptible(sem); | ||
89 | smp_wmb(); | ||
90 | return ret; | ||
91 | } | ||
92 | |||
93 | extern inline int down_trylock(struct semaphore * sem) | ||
94 | { | ||
95 | int ret; | ||
96 | |||
97 | ret = atomic_dec_if_positive(&sem->count) < 0; | ||
98 | smp_wmb(); | ||
99 | return ret; | ||
100 | } | ||
101 | |||
102 | extern inline void up(struct semaphore * sem) | ||
103 | { | ||
104 | smp_wmb(); | ||
105 | if (atomic_inc_return(&sem->count) <= 0) | ||
106 | __up(sem); | ||
107 | } | ||
108 | |||
109 | #endif /* __KERNEL__ */ | ||
110 | |||
111 | #endif /* !(_PPC_SEMAPHORE_H) */ | ||
diff --git a/include/asm-ppc/sembuf.h b/include/asm-ppc/sembuf.h new file mode 100644 index 000000000000..883f682f85b8 --- /dev/null +++ b/include/asm-ppc/sembuf.h | |||
@@ -0,0 +1,19 @@ | |||
1 | #ifndef _PPC_SEMBUF_H | ||
2 | #define _PPC_SEMBUF_H | ||
3 | |||
4 | /* | ||
5 | * The semid64_ds structure for PPC architecture. | ||
6 | */ | ||
7 | |||
8 | struct semid64_ds { | ||
9 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
10 | unsigned int __unused1; | ||
11 | __kernel_time_t sem_otime; /* last semop time */ | ||
12 | unsigned int __unused2; | ||
13 | __kernel_time_t sem_ctime; /* last change time */ | ||
14 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
15 | unsigned long __unused3; | ||
16 | unsigned long __unused4; | ||
17 | }; | ||
18 | |||
19 | #endif /* _PPC_SEMBUF_H */ | ||
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h new file mode 100644 index 000000000000..6d47438be58c --- /dev/null +++ b/include/asm-ppc/serial.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/serial.h | ||
3 | */ | ||
4 | |||
5 | #ifdef __KERNEL__ | ||
6 | #ifndef __ASM_SERIAL_H__ | ||
7 | #define __ASM_SERIAL_H__ | ||
8 | |||
9 | #include <linux/config.h> | ||
10 | |||
11 | #if defined(CONFIG_EV64260) | ||
12 | #include <platforms/ev64260.h> | ||
13 | #elif defined(CONFIG_CHESTNUT) | ||
14 | #include <platforms/chestnut.h> | ||
15 | #elif defined(CONFIG_GEMINI) | ||
16 | #include <platforms/gemini_serial.h> | ||
17 | #elif defined(CONFIG_POWERPMC250) | ||
18 | #include <platforms/powerpmc250.h> | ||
19 | #elif defined(CONFIG_LOPEC) | ||
20 | #include <platforms/lopec.h> | ||
21 | #elif defined(CONFIG_MCPN765) | ||
22 | #include <platforms/mcpn765.h> | ||
23 | #elif defined(CONFIG_MVME5100) | ||
24 | #include <platforms/mvme5100.h> | ||
25 | #elif defined(CONFIG_PAL4) | ||
26 | #include <platforms/pal4_serial.h> | ||
27 | #elif defined(CONFIG_PRPMC750) | ||
28 | #include <platforms/prpmc750.h> | ||
29 | #elif defined(CONFIG_PRPMC800) | ||
30 | #include <platforms/prpmc800.h> | ||
31 | #elif defined(CONFIG_SANDPOINT) | ||
32 | #include <platforms/sandpoint.h> | ||
33 | #elif defined(CONFIG_SPRUCE) | ||
34 | #include <platforms/spruce.h> | ||
35 | #elif defined(CONFIG_4xx) | ||
36 | #include <asm/ibm4xx.h> | ||
37 | #elif defined(CONFIG_83xx) | ||
38 | #include <asm/mpc83xx.h> | ||
39 | #elif defined(CONFIG_85xx) | ||
40 | #include <asm/mpc85xx.h> | ||
41 | #elif defined(CONFIG_RADSTONE_PPC7D) | ||
42 | #include <platforms/radstone_ppc7d.h> | ||
43 | #else | ||
44 | |||
45 | /* | ||
46 | * XXX Assume for now it has PC-style ISA serial ports. | ||
47 | * This is true for PReP and CHRP at least. | ||
48 | */ | ||
49 | #include <asm/pc_serial.h> | ||
50 | |||
51 | #if defined(CONFIG_MAC_SERIAL) | ||
52 | #define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2) | ||
53 | #endif | ||
54 | |||
55 | #endif /* !CONFIG_GEMINI and others */ | ||
56 | #endif /* __ASM_SERIAL_H__ */ | ||
57 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/setup.h b/include/asm-ppc/setup.h new file mode 100644 index 000000000000..d2d19ee103df --- /dev/null +++ b/include/asm-ppc/setup.h | |||
@@ -0,0 +1,14 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_SETUP_H | ||
3 | #define _PPC_SETUP_H | ||
4 | |||
5 | #define m68k_num_memory num_memory | ||
6 | #define m68k_memory memory | ||
7 | |||
8 | #include <asm-m68k/setup.h> | ||
9 | /* We have a bigger command line buffer. */ | ||
10 | #undef COMMAND_LINE_SIZE | ||
11 | #define COMMAND_LINE_SIZE 512 | ||
12 | |||
13 | #endif /* _PPC_SETUP_H */ | ||
14 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/shmbuf.h b/include/asm-ppc/shmbuf.h new file mode 100644 index 000000000000..7ac0bd38cbd8 --- /dev/null +++ b/include/asm-ppc/shmbuf.h | |||
@@ -0,0 +1,37 @@ | |||
1 | #ifndef _PPC_SHMBUF_H | ||
2 | #define _PPC_SHMBUF_H | ||
3 | |||
4 | /* | ||
5 | * The shmid64_ds structure for PPC architecture. | ||
6 | */ | ||
7 | |||
8 | struct shmid64_ds { | ||
9 | struct ipc64_perm shm_perm; /* operation perms */ | ||
10 | unsigned int __unused1; | ||
11 | __kernel_time_t shm_atime; /* last attach time */ | ||
12 | unsigned int __unused2; | ||
13 | __kernel_time_t shm_dtime; /* last detach time */ | ||
14 | unsigned int __unused3; | ||
15 | __kernel_time_t shm_ctime; /* last change time */ | ||
16 | unsigned int __unused4; | ||
17 | size_t shm_segsz; /* size of segment (bytes) */ | ||
18 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
19 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
20 | unsigned long shm_nattch; /* no. of current attaches */ | ||
21 | unsigned long __unused5; | ||
22 | unsigned long __unused6; | ||
23 | }; | ||
24 | |||
25 | struct shminfo64 { | ||
26 | unsigned long shmmax; | ||
27 | unsigned long shmmin; | ||
28 | unsigned long shmmni; | ||
29 | unsigned long shmseg; | ||
30 | unsigned long shmall; | ||
31 | unsigned long __unused1; | ||
32 | unsigned long __unused2; | ||
33 | unsigned long __unused3; | ||
34 | unsigned long __unused4; | ||
35 | }; | ||
36 | |||
37 | #endif /* _PPC_SHMBUF_H */ | ||
diff --git a/include/asm-ppc/shmparam.h b/include/asm-ppc/shmparam.h new file mode 100644 index 000000000000..d6250602ae64 --- /dev/null +++ b/include/asm-ppc/shmparam.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _PPC_SHMPARAM_H | ||
2 | #define _PPC_SHMPARAM_H | ||
3 | |||
4 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
5 | |||
6 | #endif /* _PPC_SHMPARAM_H */ | ||
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h new file mode 100644 index 000000000000..fc5e358c65f1 --- /dev/null +++ b/include/asm-ppc/sigcontext.h | |||
@@ -0,0 +1,15 @@ | |||
1 | #ifndef _ASM_PPC_SIGCONTEXT_H | ||
2 | #define _ASM_PPC_SIGCONTEXT_H | ||
3 | |||
4 | #include <asm/ptrace.h> | ||
5 | |||
6 | |||
7 | struct sigcontext { | ||
8 | unsigned long _unused[4]; | ||
9 | int signal; | ||
10 | unsigned long handler; | ||
11 | unsigned long oldmask; | ||
12 | struct pt_regs *regs; | ||
13 | }; | ||
14 | |||
15 | #endif | ||
diff --git a/include/asm-ppc/siginfo.h b/include/asm-ppc/siginfo.h new file mode 100644 index 000000000000..4b9435bb9049 --- /dev/null +++ b/include/asm-ppc/siginfo.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _PPC_SIGINFO_H | ||
2 | #define _PPC_SIGINFO_H | ||
3 | |||
4 | #include <asm-generic/siginfo.h> | ||
5 | |||
6 | #endif | ||
diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h new file mode 100644 index 000000000000..8cc8b88d4edd --- /dev/null +++ b/include/asm-ppc/signal.h | |||
@@ -0,0 +1,179 @@ | |||
1 | #ifndef _ASMPPC_SIGNAL_H | ||
2 | #define _ASMPPC_SIGNAL_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | #include <linux/types.h> | ||
6 | #endif /* __KERNEL__ */ | ||
7 | |||
8 | /* Avoid too many header ordering problems. */ | ||
9 | struct siginfo; | ||
10 | |||
11 | /* Most things should be clean enough to redefine this at will, if care | ||
12 | is taken to make libc match. */ | ||
13 | |||
14 | #define _NSIG 64 | ||
15 | #define _NSIG_BPW 32 | ||
16 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
17 | |||
18 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
19 | |||
20 | typedef struct { | ||
21 | unsigned long sig[_NSIG_WORDS]; | ||
22 | } sigset_t; | ||
23 | |||
24 | #define SIGHUP 1 | ||
25 | #define SIGINT 2 | ||
26 | #define SIGQUIT 3 | ||
27 | #define SIGILL 4 | ||
28 | #define SIGTRAP 5 | ||
29 | #define SIGABRT 6 | ||
30 | #define SIGIOT 6 | ||
31 | #define SIGBUS 7 | ||
32 | #define SIGFPE 8 | ||
33 | #define SIGKILL 9 | ||
34 | #define SIGUSR1 10 | ||
35 | #define SIGSEGV 11 | ||
36 | #define SIGUSR2 12 | ||
37 | #define SIGPIPE 13 | ||
38 | #define SIGALRM 14 | ||
39 | #define SIGTERM 15 | ||
40 | #define SIGSTKFLT 16 | ||
41 | #define SIGCHLD 17 | ||
42 | #define SIGCONT 18 | ||
43 | #define SIGSTOP 19 | ||
44 | #define SIGTSTP 20 | ||
45 | #define SIGTTIN 21 | ||
46 | #define SIGTTOU 22 | ||
47 | #define SIGURG 23 | ||
48 | #define SIGXCPU 24 | ||
49 | #define SIGXFSZ 25 | ||
50 | #define SIGVTALRM 26 | ||
51 | #define SIGPROF 27 | ||
52 | #define SIGWINCH 28 | ||
53 | #define SIGIO 29 | ||
54 | #define SIGPOLL SIGIO | ||
55 | /* | ||
56 | #define SIGLOST 29 | ||
57 | */ | ||
58 | #define SIGPWR 30 | ||
59 | #define SIGSYS 31 | ||
60 | #define SIGUNUSED 31 | ||
61 | |||
62 | /* These should not be considered constants from userland. */ | ||
63 | #define SIGRTMIN 32 | ||
64 | #define SIGRTMAX _NSIG | ||
65 | |||
66 | /* | ||
67 | * SA_FLAGS values: | ||
68 | * | ||
69 | * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). | ||
70 | * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the | ||
71 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
72 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
73 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
74 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
75 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
76 | * | ||
77 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
78 | * Unix names RESETHAND and NODEFER respectively. | ||
79 | */ | ||
80 | #define SA_NOCLDSTOP 0x00000001 | ||
81 | #define SA_NOCLDWAIT 0x00000002 | ||
82 | #define SA_SIGINFO 0x00000004 | ||
83 | #define SA_ONSTACK 0x08000000 | ||
84 | #define SA_RESTART 0x10000000 | ||
85 | #define SA_NODEFER 0x40000000 | ||
86 | #define SA_RESETHAND 0x80000000 | ||
87 | |||
88 | #define SA_NOMASK SA_NODEFER | ||
89 | #define SA_ONESHOT SA_RESETHAND | ||
90 | #define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ | ||
91 | |||
92 | #define SA_RESTORER 0x04000000 | ||
93 | |||
94 | /* | ||
95 | * sigaltstack controls | ||
96 | */ | ||
97 | #define SS_ONSTACK 1 | ||
98 | #define SS_DISABLE 2 | ||
99 | |||
100 | #define MINSIGSTKSZ 2048 | ||
101 | #define SIGSTKSZ 8192 | ||
102 | #ifdef __KERNEL__ | ||
103 | |||
104 | /* | ||
105 | * These values of sa_flags are used only by the kernel as part of the | ||
106 | * irq handling routines. | ||
107 | * | ||
108 | * SA_INTERRUPT is also used by the irq handling routines. | ||
109 | * SA_SHIRQ is for shared interrupt support on PCI and EISA. | ||
110 | */ | ||
111 | #define SA_PROBE SA_ONESHOT | ||
112 | #define SA_SAMPLE_RANDOM SA_RESTART | ||
113 | #define SA_SHIRQ 0x04000000 | ||
114 | #endif /* __KERNEL__ */ | ||
115 | |||
116 | #define SIG_BLOCK 0 /* for blocking signals */ | ||
117 | #define SIG_UNBLOCK 1 /* for unblocking signals */ | ||
118 | #define SIG_SETMASK 2 /* for setting the signal mask */ | ||
119 | |||
120 | /* Type of a signal handler. */ | ||
121 | typedef void __signalfn_t(int); | ||
122 | typedef __signalfn_t __user *__sighandler_t; | ||
123 | |||
124 | typedef void __restorefn_t(void); | ||
125 | typedef __restorefn_t __user *__sigrestore_t; | ||
126 | |||
127 | #define SIG_DFL ((__sighandler_t)0) /* default signal handling */ | ||
128 | #define SIG_IGN ((__sighandler_t)1) /* ignore signal */ | ||
129 | #define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ | ||
130 | |||
131 | struct old_sigaction { | ||
132 | __sighandler_t sa_handler; | ||
133 | old_sigset_t sa_mask; | ||
134 | unsigned long sa_flags; | ||
135 | __sigrestore_t sa_restorer; | ||
136 | }; | ||
137 | |||
138 | struct sigaction { | ||
139 | __sighandler_t sa_handler; | ||
140 | unsigned long sa_flags; | ||
141 | __sigrestore_t sa_restorer; | ||
142 | sigset_t sa_mask; /* mask last for extensibility */ | ||
143 | }; | ||
144 | |||
145 | struct k_sigaction { | ||
146 | struct sigaction sa; | ||
147 | }; | ||
148 | |||
149 | typedef struct sigaltstack { | ||
150 | void __user *ss_sp; | ||
151 | int ss_flags; | ||
152 | size_t ss_size; | ||
153 | } stack_t; | ||
154 | |||
155 | #ifdef __KERNEL__ | ||
156 | #include <asm/sigcontext.h> | ||
157 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
158 | #endif /* __KERNEL__ */ | ||
159 | |||
160 | /* | ||
161 | * These are parameters to dbg_sigreturn syscall. They enable or | ||
162 | * disable certain debugging things that can be done from signal | ||
163 | * handlers. The dbg_sigreturn syscall *must* be called from a | ||
164 | * SA_SIGINFO signal so the ucontext can be passed to it. It takes an | ||
165 | * array of struct sig_dbg_op, which has the debug operations to | ||
166 | * perform before returning from the signal. | ||
167 | */ | ||
168 | struct sig_dbg_op { | ||
169 | int dbg_type; | ||
170 | unsigned long dbg_value; | ||
171 | }; | ||
172 | |||
173 | /* Enable or disable single-stepping. The value sets the state. */ | ||
174 | #define SIG_DBG_SINGLE_STEPPING 1 | ||
175 | |||
176 | /* Enable or disable branch tracing. The value sets the state. */ | ||
177 | #define SIG_DBG_BRANCH_TRACING 2 | ||
178 | |||
179 | #endif | ||
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h new file mode 100644 index 000000000000..ebfb614f55f6 --- /dev/null +++ b/include/asm-ppc/smp.h | |||
@@ -0,0 +1,70 @@ | |||
1 | /* smp.h: PPC specific SMP stuff. | ||
2 | * | ||
3 | * Original was a copy of sparc smp.h. Now heavily modified | ||
4 | * for PPC. | ||
5 | * | ||
6 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | ||
7 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef _PPC_SMP_H | ||
11 | #define _PPC_SMP_H | ||
12 | |||
13 | #include <linux/config.h> | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/bitops.h> | ||
16 | #include <linux/errno.h> | ||
17 | #include <linux/cpumask.h> | ||
18 | #include <linux/threads.h> | ||
19 | |||
20 | #ifdef CONFIG_SMP | ||
21 | |||
22 | #ifndef __ASSEMBLY__ | ||
23 | |||
24 | struct cpuinfo_PPC { | ||
25 | unsigned long loops_per_jiffy; | ||
26 | unsigned long pvr; | ||
27 | unsigned long *pgd_cache; | ||
28 | unsigned long *pte_cache; | ||
29 | unsigned long pgtable_cache_sz; | ||
30 | }; | ||
31 | |||
32 | extern struct cpuinfo_PPC cpu_data[]; | ||
33 | extern cpumask_t cpu_online_map; | ||
34 | extern cpumask_t cpu_possible_map; | ||
35 | extern unsigned long smp_proc_in_lock[]; | ||
36 | extern volatile unsigned long cpu_callin_map[]; | ||
37 | extern int smp_tb_synchronized; | ||
38 | |||
39 | extern void smp_send_tlb_invalidate(int); | ||
40 | extern void smp_send_xmon_break(int cpu); | ||
41 | struct pt_regs; | ||
42 | extern void smp_message_recv(int, struct pt_regs *); | ||
43 | |||
44 | #define NO_PROC_ID 0xFF /* No processor magic marker */ | ||
45 | #define PROC_CHANGE_PENALTY 20 | ||
46 | |||
47 | #define smp_processor_id() (current_thread_info()->cpu) | ||
48 | |||
49 | extern int __cpu_up(unsigned int cpu); | ||
50 | |||
51 | extern int smp_hw_index[]; | ||
52 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) | ||
53 | |||
54 | struct klock_info_struct { | ||
55 | unsigned long kernel_flag; | ||
56 | unsigned char akp; | ||
57 | }; | ||
58 | |||
59 | extern struct klock_info_struct klock_info; | ||
60 | #define KLOCK_HELD 0xffffffff | ||
61 | #define KLOCK_CLEAR 0x0 | ||
62 | |||
63 | #endif /* __ASSEMBLY__ */ | ||
64 | |||
65 | #else /* !(CONFIG_SMP) */ | ||
66 | |||
67 | #endif /* !(CONFIG_SMP) */ | ||
68 | |||
69 | #endif /* !(_PPC_SMP_H) */ | ||
70 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/socket.h b/include/asm-ppc/socket.h new file mode 100644 index 000000000000..4134376b0f66 --- /dev/null +++ b/include/asm-ppc/socket.h | |||
@@ -0,0 +1,56 @@ | |||
1 | #ifndef _ASM_SOCKET_H | ||
2 | #define _ASM_SOCKET_H | ||
3 | |||
4 | /* Socket-level I/O control calls. */ | ||
5 | #define FIOSETOWN 0x8901 | ||
6 | #define SIOCSPGRP 0x8902 | ||
7 | #define FIOGETOWN 0x8903 | ||
8 | #define SIOCGPGRP 0x8904 | ||
9 | #define SIOCATMARK 0x8905 | ||
10 | #define SIOCGSTAMP 0x8906 /* Get stamp */ | ||
11 | |||
12 | /* For setsockopt(2) */ | ||
13 | #define SOL_SOCKET 1 | ||
14 | |||
15 | #define SO_DEBUG 1 | ||
16 | #define SO_REUSEADDR 2 | ||
17 | #define SO_TYPE 3 | ||
18 | #define SO_ERROR 4 | ||
19 | #define SO_DONTROUTE 5 | ||
20 | #define SO_BROADCAST 6 | ||
21 | #define SO_SNDBUF 7 | ||
22 | #define SO_RCVBUF 8 | ||
23 | #define SO_KEEPALIVE 9 | ||
24 | #define SO_OOBINLINE 10 | ||
25 | #define SO_NO_CHECK 11 | ||
26 | #define SO_PRIORITY 12 | ||
27 | #define SO_LINGER 13 | ||
28 | #define SO_BSDCOMPAT 14 | ||
29 | /* To add :#define SO_REUSEPORT 15 */ | ||
30 | #define SO_RCVLOWAT 16 | ||
31 | #define SO_SNDLOWAT 17 | ||
32 | #define SO_RCVTIMEO 18 | ||
33 | #define SO_SNDTIMEO 19 | ||
34 | #define SO_PASSCRED 20 | ||
35 | #define SO_PEERCRED 21 | ||
36 | |||
37 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
38 | #define SO_SECURITY_AUTHENTICATION 22 | ||
39 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
40 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
41 | |||
42 | #define SO_BINDTODEVICE 25 | ||
43 | |||
44 | /* Socket filtering */ | ||
45 | #define SO_ATTACH_FILTER 26 | ||
46 | #define SO_DETACH_FILTER 27 | ||
47 | |||
48 | #define SO_PEERNAME 28 | ||
49 | #define SO_TIMESTAMP 29 | ||
50 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
51 | |||
52 | #define SO_ACCEPTCONN 30 | ||
53 | |||
54 | #define SO_PEERSEC 31 | ||
55 | |||
56 | #endif /* _ASM_SOCKET_H */ | ||
diff --git a/include/asm-ppc/sockios.h b/include/asm-ppc/sockios.h new file mode 100644 index 000000000000..385aedc55ceb --- /dev/null +++ b/include/asm-ppc/sockios.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifndef _ASM_PPC_SOCKIOS_H | ||
2 | #define _ASM_PPC_SOCKIOS_H | ||
3 | |||
4 | #if 0 /* These are defined this way on Alpha - maybe later. */ | ||
5 | /* Socket-level I/O control calls. */ | ||
6 | |||
7 | #define FIOGETOWN _IOR('f', 123, int) | ||
8 | #define FIOSETOWN _IOW('f', 124, int) | ||
9 | |||
10 | #define SIOCATMARK _IOR('s', 7, int) | ||
11 | #define SIOCSPGRP _IOW('s', 8, pid_t) | ||
12 | #define SIOCGPGRP _IOR('s', 9, pid_t) | ||
13 | |||
14 | #define SIOCGSTAMP 0x8906 /* Get stamp - linux-specific */ | ||
15 | #endif | ||
16 | |||
17 | #endif /* _ASM_PPC_SOCKIOS_H */ | ||
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h new file mode 100644 index 000000000000..909199aae104 --- /dev/null +++ b/include/asm-ppc/spinlock.h | |||
@@ -0,0 +1,215 @@ | |||
1 | #ifndef __ASM_SPINLOCK_H | ||
2 | #define __ASM_SPINLOCK_H | ||
3 | |||
4 | #include <asm/system.h> | ||
5 | |||
6 | /* | ||
7 | * Simple spin lock operations. | ||
8 | */ | ||
9 | |||
10 | typedef struct { | ||
11 | volatile unsigned long lock; | ||
12 | #ifdef CONFIG_DEBUG_SPINLOCK | ||
13 | volatile unsigned long owner_pc; | ||
14 | volatile unsigned long owner_cpu; | ||
15 | #endif | ||
16 | #ifdef CONFIG_PREEMPT | ||
17 | unsigned int break_lock; | ||
18 | #endif | ||
19 | } spinlock_t; | ||
20 | |||
21 | #ifdef __KERNEL__ | ||
22 | #ifdef CONFIG_DEBUG_SPINLOCK | ||
23 | #define SPINLOCK_DEBUG_INIT , 0, 0 | ||
24 | #else | ||
25 | #define SPINLOCK_DEBUG_INIT /* */ | ||
26 | #endif | ||
27 | |||
28 | #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 SPINLOCK_DEBUG_INIT } | ||
29 | |||
30 | #define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) | ||
31 | #define spin_is_locked(x) ((x)->lock != 0) | ||
32 | #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) | ||
33 | #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) | ||
34 | |||
35 | #ifndef CONFIG_DEBUG_SPINLOCK | ||
36 | |||
37 | static inline void _raw_spin_lock(spinlock_t *lock) | ||
38 | { | ||
39 | unsigned long tmp; | ||
40 | |||
41 | __asm__ __volatile__( | ||
42 | "b 1f # spin_lock\n\ | ||
43 | 2: lwzx %0,0,%1\n\ | ||
44 | cmpwi 0,%0,0\n\ | ||
45 | bne+ 2b\n\ | ||
46 | 1: lwarx %0,0,%1\n\ | ||
47 | cmpwi 0,%0,0\n\ | ||
48 | bne- 2b\n" | ||
49 | PPC405_ERR77(0,%1) | ||
50 | " stwcx. %2,0,%1\n\ | ||
51 | bne- 2b\n\ | ||
52 | isync" | ||
53 | : "=&r"(tmp) | ||
54 | : "r"(&lock->lock), "r"(1) | ||
55 | : "cr0", "memory"); | ||
56 | } | ||
57 | |||
58 | static inline void _raw_spin_unlock(spinlock_t *lock) | ||
59 | { | ||
60 | __asm__ __volatile__("eieio # spin_unlock": : :"memory"); | ||
61 | lock->lock = 0; | ||
62 | } | ||
63 | |||
64 | #define _raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock)) | ||
65 | |||
66 | #else | ||
67 | |||
68 | extern void _raw_spin_lock(spinlock_t *lock); | ||
69 | extern void _raw_spin_unlock(spinlock_t *lock); | ||
70 | extern int _raw_spin_trylock(spinlock_t *lock); | ||
71 | |||
72 | #endif | ||
73 | |||
74 | /* | ||
75 | * Read-write spinlocks, allowing multiple readers | ||
76 | * but only one writer. | ||
77 | * | ||
78 | * NOTE! it is quite common to have readers in interrupts | ||
79 | * but no interrupt writers. For those circumstances we | ||
80 | * can "mix" irq-safe locks - any writer needs to get a | ||
81 | * irq-safe write-lock, but readers can get non-irqsafe | ||
82 | * read-locks. | ||
83 | */ | ||
84 | typedef struct { | ||
85 | volatile signed int lock; | ||
86 | #ifdef CONFIG_PREEMPT | ||
87 | unsigned int break_lock; | ||
88 | #endif | ||
89 | } rwlock_t; | ||
90 | |||
91 | #define RW_LOCK_UNLOCKED (rwlock_t) { 0 } | ||
92 | #define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while(0) | ||
93 | |||
94 | #define read_can_lock(rw) ((rw)->lock >= 0) | ||
95 | #define write_can_lock(rw) (!(rw)->lock) | ||
96 | |||
97 | #ifndef CONFIG_DEBUG_SPINLOCK | ||
98 | |||
99 | static __inline__ int _raw_read_trylock(rwlock_t *rw) | ||
100 | { | ||
101 | signed int tmp; | ||
102 | |||
103 | __asm__ __volatile__( | ||
104 | "2: lwarx %0,0,%1 # read_trylock\n\ | ||
105 | addic. %0,%0,1\n\ | ||
106 | ble- 1f\n" | ||
107 | PPC405_ERR77(0,%1) | ||
108 | " stwcx. %0,0,%1\n\ | ||
109 | bne- 2b\n\ | ||
110 | isync\n\ | ||
111 | 1:" | ||
112 | : "=&r"(tmp) | ||
113 | : "r"(&rw->lock) | ||
114 | : "cr0", "memory"); | ||
115 | |||
116 | return tmp > 0; | ||
117 | } | ||
118 | |||
119 | static __inline__ void _raw_read_lock(rwlock_t *rw) | ||
120 | { | ||
121 | signed int tmp; | ||
122 | |||
123 | __asm__ __volatile__( | ||
124 | "b 2f # read_lock\n\ | ||
125 | 1: lwzx %0,0,%1\n\ | ||
126 | cmpwi 0,%0,0\n\ | ||
127 | blt+ 1b\n\ | ||
128 | 2: lwarx %0,0,%1\n\ | ||
129 | addic. %0,%0,1\n\ | ||
130 | ble- 1b\n" | ||
131 | PPC405_ERR77(0,%1) | ||
132 | " stwcx. %0,0,%1\n\ | ||
133 | bne- 2b\n\ | ||
134 | isync" | ||
135 | : "=&r"(tmp) | ||
136 | : "r"(&rw->lock) | ||
137 | : "cr0", "memory"); | ||
138 | } | ||
139 | |||
140 | static __inline__ void _raw_read_unlock(rwlock_t *rw) | ||
141 | { | ||
142 | signed int tmp; | ||
143 | |||
144 | __asm__ __volatile__( | ||
145 | "eieio # read_unlock\n\ | ||
146 | 1: lwarx %0,0,%1\n\ | ||
147 | addic %0,%0,-1\n" | ||
148 | PPC405_ERR77(0,%1) | ||
149 | " stwcx. %0,0,%1\n\ | ||
150 | bne- 1b" | ||
151 | : "=&r"(tmp) | ||
152 | : "r"(&rw->lock) | ||
153 | : "cr0", "memory"); | ||
154 | } | ||
155 | |||
156 | static __inline__ int _raw_write_trylock(rwlock_t *rw) | ||
157 | { | ||
158 | signed int tmp; | ||
159 | |||
160 | __asm__ __volatile__( | ||
161 | "2: lwarx %0,0,%1 # write_trylock\n\ | ||
162 | cmpwi 0,%0,0\n\ | ||
163 | bne- 1f\n" | ||
164 | PPC405_ERR77(0,%1) | ||
165 | " stwcx. %2,0,%1\n\ | ||
166 | bne- 2b\n\ | ||
167 | isync\n\ | ||
168 | 1:" | ||
169 | : "=&r"(tmp) | ||
170 | : "r"(&rw->lock), "r"(-1) | ||
171 | : "cr0", "memory"); | ||
172 | |||
173 | return tmp == 0; | ||
174 | } | ||
175 | |||
176 | static __inline__ void _raw_write_lock(rwlock_t *rw) | ||
177 | { | ||
178 | signed int tmp; | ||
179 | |||
180 | __asm__ __volatile__( | ||
181 | "b 2f # write_lock\n\ | ||
182 | 1: lwzx %0,0,%1\n\ | ||
183 | cmpwi 0,%0,0\n\ | ||
184 | bne+ 1b\n\ | ||
185 | 2: lwarx %0,0,%1\n\ | ||
186 | cmpwi 0,%0,0\n\ | ||
187 | bne- 1b\n" | ||
188 | PPC405_ERR77(0,%1) | ||
189 | " stwcx. %2,0,%1\n\ | ||
190 | bne- 2b\n\ | ||
191 | isync" | ||
192 | : "=&r"(tmp) | ||
193 | : "r"(&rw->lock), "r"(-1) | ||
194 | : "cr0", "memory"); | ||
195 | } | ||
196 | |||
197 | static __inline__ void _raw_write_unlock(rwlock_t *rw) | ||
198 | { | ||
199 | __asm__ __volatile__("eieio # write_unlock": : :"memory"); | ||
200 | rw->lock = 0; | ||
201 | } | ||
202 | |||
203 | #else | ||
204 | |||
205 | extern void _raw_read_lock(rwlock_t *rw); | ||
206 | extern void _raw_read_unlock(rwlock_t *rw); | ||
207 | extern void _raw_write_lock(rwlock_t *rw); | ||
208 | extern void _raw_write_unlock(rwlock_t *rw); | ||
209 | extern int _raw_read_trylock(rwlock_t *rw); | ||
210 | extern int _raw_write_trylock(rwlock_t *rw); | ||
211 | |||
212 | #endif | ||
213 | |||
214 | #endif /* __ASM_SPINLOCK_H */ | ||
215 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/stat.h b/include/asm-ppc/stat.h new file mode 100644 index 000000000000..cadb34298496 --- /dev/null +++ b/include/asm-ppc/stat.h | |||
@@ -0,0 +1,69 @@ | |||
1 | #ifndef _PPC_STAT_H | ||
2 | #define _PPC_STAT_H | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | #include <linux/types.h> | ||
6 | #endif /* __KERNEL__ */ | ||
7 | |||
8 | struct __old_kernel_stat { | ||
9 | unsigned short st_dev; | ||
10 | unsigned short st_ino; | ||
11 | unsigned short st_mode; | ||
12 | unsigned short st_nlink; | ||
13 | unsigned short st_uid; | ||
14 | unsigned short st_gid; | ||
15 | unsigned short st_rdev; | ||
16 | unsigned long st_size; | ||
17 | unsigned long st_atime; | ||
18 | unsigned long st_mtime; | ||
19 | unsigned long st_ctime; | ||
20 | }; | ||
21 | |||
22 | #define STAT_HAVE_NSEC 1 | ||
23 | |||
24 | struct stat { | ||
25 | unsigned st_dev; | ||
26 | ino_t st_ino; | ||
27 | mode_t st_mode; | ||
28 | nlink_t st_nlink; | ||
29 | uid_t st_uid; | ||
30 | gid_t st_gid; | ||
31 | unsigned st_rdev; | ||
32 | off_t st_size; | ||
33 | unsigned long st_blksize; | ||
34 | unsigned long st_blocks; | ||
35 | unsigned long st_atime; | ||
36 | unsigned long st_atime_nsec; | ||
37 | unsigned long st_mtime; | ||
38 | unsigned long st_mtime_nsec; | ||
39 | unsigned long st_ctime; | ||
40 | unsigned long st_ctime_nsec; | ||
41 | unsigned long __unused4; | ||
42 | unsigned long __unused5; | ||
43 | }; | ||
44 | |||
45 | /* This matches struct stat64 in glibc2.1. | ||
46 | */ | ||
47 | struct stat64 { | ||
48 | unsigned long long st_dev; /* Device. */ | ||
49 | unsigned long long st_ino; /* File serial number. */ | ||
50 | unsigned int st_mode; /* File mode. */ | ||
51 | unsigned int st_nlink; /* Link count. */ | ||
52 | unsigned int st_uid; /* User ID of the file's owner. */ | ||
53 | unsigned int st_gid; /* Group ID of the file's group. */ | ||
54 | unsigned long long st_rdev; /* Device number, if device. */ | ||
55 | unsigned short int __pad2; | ||
56 | long long st_size; /* Size of file, in bytes. */ | ||
57 | long st_blksize; /* Optimal block size for I/O. */ | ||
58 | |||
59 | long long st_blocks; /* Number 512-byte blocks allocated. */ | ||
60 | long st_atime; /* Time of last access. */ | ||
61 | unsigned long st_atime_nsec; | ||
62 | long st_mtime; /* Time of last modification. */ | ||
63 | unsigned long int st_mtime_nsec; | ||
64 | long st_ctime; /* Time of last status change. */ | ||
65 | unsigned long int st_ctime_nsec; | ||
66 | unsigned long int __unused4; | ||
67 | unsigned long int __unused5; | ||
68 | }; | ||
69 | #endif | ||
diff --git a/include/asm-ppc/statfs.h b/include/asm-ppc/statfs.h new file mode 100644 index 000000000000..807c69954a1b --- /dev/null +++ b/include/asm-ppc/statfs.h | |||
@@ -0,0 +1,8 @@ | |||
1 | #ifndef _PPC_STATFS_H | ||
2 | #define _PPC_STATFS_H | ||
3 | |||
4 | #include <asm-generic/statfs.h> | ||
5 | #endif | ||
6 | |||
7 | |||
8 | |||
diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h new file mode 100644 index 000000000000..225575997392 --- /dev/null +++ b/include/asm-ppc/string.h | |||
@@ -0,0 +1,32 @@ | |||
1 | #ifndef _PPC_STRING_H_ | ||
2 | #define _PPC_STRING_H_ | ||
3 | |||
4 | #ifdef __KERNEL__ | ||
5 | |||
6 | #define __HAVE_ARCH_STRCPY | ||
7 | #define __HAVE_ARCH_STRNCPY | ||
8 | #define __HAVE_ARCH_STRLEN | ||
9 | #define __HAVE_ARCH_STRCMP | ||
10 | #define __HAVE_ARCH_STRCAT | ||
11 | #define __HAVE_ARCH_MEMSET | ||
12 | #define __HAVE_ARCH_MEMCPY | ||
13 | #define __HAVE_ARCH_MEMMOVE | ||
14 | #define __HAVE_ARCH_MEMCMP | ||
15 | #define __HAVE_ARCH_MEMCHR | ||
16 | |||
17 | extern int strcasecmp(const char *, const char *); | ||
18 | extern int strncasecmp(const char *, const char *, int); | ||
19 | extern char * strcpy(char *,const char *); | ||
20 | extern char * strncpy(char *,const char *, __kernel_size_t); | ||
21 | extern __kernel_size_t strlen(const char *); | ||
22 | extern int strcmp(const char *,const char *); | ||
23 | extern char * strcat(char *, const char *); | ||
24 | extern void * memset(void *,int,__kernel_size_t); | ||
25 | extern void * memcpy(void *,const void *,__kernel_size_t); | ||
26 | extern void * memmove(void *,const void *,__kernel_size_t); | ||
27 | extern int memcmp(const void *,const void *,__kernel_size_t); | ||
28 | extern void * memchr(const void *,int,__kernel_size_t); | ||
29 | |||
30 | #endif /* __KERNEL__ */ | ||
31 | |||
32 | #endif | ||
diff --git a/include/asm-ppc/suspend.h b/include/asm-ppc/suspend.h new file mode 100644 index 000000000000..3df9f32bd834 --- /dev/null +++ b/include/asm-ppc/suspend.h | |||
@@ -0,0 +1,12 @@ | |||
1 | static inline int arch_prepare_suspend(void) | ||
2 | { | ||
3 | return 0; | ||
4 | } | ||
5 | |||
6 | static inline void save_processor_state(void) | ||
7 | { | ||
8 | } | ||
9 | |||
10 | static inline void restore_processor_state(void) | ||
11 | { | ||
12 | } | ||
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h new file mode 100644 index 000000000000..82395f30004b --- /dev/null +++ b/include/asm-ppc/system.h | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | ||
3 | */ | ||
4 | #ifndef __PPC_SYSTEM_H | ||
5 | #define __PPC_SYSTEM_H | ||
6 | |||
7 | #include <linux/config.h> | ||
8 | #include <linux/kernel.h> | ||
9 | |||
10 | #include <asm/atomic.h> | ||
11 | #include <asm/hw_irq.h> | ||
12 | |||
13 | /* | ||
14 | * Memory barrier. | ||
15 | * The sync instruction guarantees that all memory accesses initiated | ||
16 | * by this processor have been performed (with respect to all other | ||
17 | * mechanisms that access memory). The eieio instruction is a barrier | ||
18 | * providing an ordering (separately) for (a) cacheable stores and (b) | ||
19 | * loads and stores to non-cacheable memory (e.g. I/O devices). | ||
20 | * | ||
21 | * mb() prevents loads and stores being reordered across this point. | ||
22 | * rmb() prevents loads being reordered across this point. | ||
23 | * wmb() prevents stores being reordered across this point. | ||
24 | * read_barrier_depends() prevents data-dependent loads being reordered | ||
25 | * across this point (nop on PPC). | ||
26 | * | ||
27 | * We can use the eieio instruction for wmb, but since it doesn't | ||
28 | * give any ordering guarantees about loads, we have to use the | ||
29 | * stronger but slower sync instruction for mb and rmb. | ||
30 | */ | ||
31 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | ||
32 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") | ||
33 | #define wmb() __asm__ __volatile__ ("eieio" : : : "memory") | ||
34 | #define read_barrier_depends() do { } while(0) | ||
35 | |||
36 | #define set_mb(var, value) do { var = value; mb(); } while (0) | ||
37 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | ||
38 | |||
39 | #ifdef CONFIG_SMP | ||
40 | #define smp_mb() mb() | ||
41 | #define smp_rmb() rmb() | ||
42 | #define smp_wmb() wmb() | ||
43 | #define smp_read_barrier_depends() read_barrier_depends() | ||
44 | #else | ||
45 | #define smp_mb() barrier() | ||
46 | #define smp_rmb() barrier() | ||
47 | #define smp_wmb() barrier() | ||
48 | #define smp_read_barrier_depends() do { } while(0) | ||
49 | #endif /* CONFIG_SMP */ | ||
50 | |||
51 | #ifdef __KERNEL__ | ||
52 | struct task_struct; | ||
53 | struct pt_regs; | ||
54 | |||
55 | extern void print_backtrace(unsigned long *); | ||
56 | extern void show_regs(struct pt_regs * regs); | ||
57 | extern void flush_instruction_cache(void); | ||
58 | extern void hard_reset_now(void); | ||
59 | extern void poweroff_now(void); | ||
60 | #ifdef CONFIG_6xx | ||
61 | extern long _get_L2CR(void); | ||
62 | extern long _get_L3CR(void); | ||
63 | extern void _set_L2CR(unsigned long); | ||
64 | extern void _set_L3CR(unsigned long); | ||
65 | #else | ||
66 | #define _get_L2CR() 0L | ||
67 | #define _get_L3CR() 0L | ||
68 | #define _set_L2CR(val) do { } while(0) | ||
69 | #define _set_L3CR(val) do { } while(0) | ||
70 | #endif | ||
71 | extern void via_cuda_init(void); | ||
72 | extern void pmac_nvram_init(void); | ||
73 | extern void read_rtc_time(void); | ||
74 | extern void pmac_find_display(void); | ||
75 | extern void giveup_fpu(struct task_struct *); | ||
76 | extern void enable_kernel_fp(void); | ||
77 | extern void enable_kernel_altivec(void); | ||
78 | extern void giveup_altivec(struct task_struct *); | ||
79 | extern void load_up_altivec(struct task_struct *); | ||
80 | extern void giveup_spe(struct task_struct *); | ||
81 | extern void load_up_spe(struct task_struct *); | ||
82 | extern int fix_alignment(struct pt_regs *); | ||
83 | extern void cvt_fd(float *from, double *to, unsigned long *fpscr); | ||
84 | extern void cvt_df(double *from, float *to, unsigned long *fpscr); | ||
85 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | ||
86 | extern void cacheable_memzero(void *p, unsigned int nb); | ||
87 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | ||
88 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | ||
89 | extern void die(const char *, struct pt_regs *, long); | ||
90 | |||
91 | struct device_node; | ||
92 | extern void note_scsi_host(struct device_node *, void *); | ||
93 | |||
94 | extern struct task_struct *__switch_to(struct task_struct *, | ||
95 | struct task_struct *); | ||
96 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | ||
97 | |||
98 | struct thread_struct; | ||
99 | extern struct task_struct *_switch(struct thread_struct *prev, | ||
100 | struct thread_struct *next); | ||
101 | |||
102 | extern unsigned int rtas_data; | ||
103 | |||
104 | static __inline__ unsigned long | ||
105 | xchg_u32(volatile void *p, unsigned long val) | ||
106 | { | ||
107 | unsigned long prev; | ||
108 | |||
109 | __asm__ __volatile__ ("\n\ | ||
110 | 1: lwarx %0,0,%2 \n" | ||
111 | PPC405_ERR77(0,%2) | ||
112 | " stwcx. %3,0,%2 \n\ | ||
113 | bne- 1b" | ||
114 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | ||
115 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | ||
116 | : "cc", "memory"); | ||
117 | |||
118 | return prev; | ||
119 | } | ||
120 | |||
121 | /* | ||
122 | * This function doesn't exist, so you'll get a linker error | ||
123 | * if something tries to do an invalid xchg(). | ||
124 | */ | ||
125 | extern void __xchg_called_with_bad_pointer(void); | ||
126 | |||
127 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
128 | #define tas(ptr) (xchg((ptr),1)) | ||
129 | |||
130 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | ||
131 | { | ||
132 | switch (size) { | ||
133 | case 4: | ||
134 | return (unsigned long) xchg_u32(ptr, x); | ||
135 | #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */ | ||
136 | case 8: | ||
137 | return (unsigned long) xchg_u64(ptr, x); | ||
138 | #endif /* 0 */ | ||
139 | } | ||
140 | __xchg_called_with_bad_pointer(); | ||
141 | return x; | ||
142 | |||
143 | |||
144 | } | ||
145 | |||
146 | extern inline void * xchg_ptr(void * m, void * val) | ||
147 | { | ||
148 | return (void *) xchg_u32(m, (unsigned long) val); | ||
149 | } | ||
150 | |||
151 | |||
152 | #define __HAVE_ARCH_CMPXCHG 1 | ||
153 | |||
154 | static __inline__ unsigned long | ||
155 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) | ||
156 | { | ||
157 | unsigned int prev; | ||
158 | |||
159 | __asm__ __volatile__ ("\n\ | ||
160 | 1: lwarx %0,0,%2 \n\ | ||
161 | cmpw 0,%0,%3 \n\ | ||
162 | bne 2f \n" | ||
163 | PPC405_ERR77(0,%2) | ||
164 | " stwcx. %4,0,%2 \n\ | ||
165 | bne- 1b\n" | ||
166 | #ifdef CONFIG_SMP | ||
167 | " sync\n" | ||
168 | #endif /* CONFIG_SMP */ | ||
169 | "2:" | ||
170 | : "=&r" (prev), "=m" (*p) | ||
171 | : "r" (p), "r" (old), "r" (new), "m" (*p) | ||
172 | : "cc", "memory"); | ||
173 | |||
174 | return prev; | ||
175 | } | ||
176 | |||
177 | /* This function doesn't exist, so you'll get a linker error | ||
178 | if something tries to do an invalid cmpxchg(). */ | ||
179 | extern void __cmpxchg_called_with_bad_pointer(void); | ||
180 | |||
181 | static __inline__ unsigned long | ||
182 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | ||
183 | { | ||
184 | switch (size) { | ||
185 | case 4: | ||
186 | return __cmpxchg_u32(ptr, old, new); | ||
187 | #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */ | ||
188 | case 8: | ||
189 | return __cmpxchg_u64(ptr, old, new); | ||
190 | #endif /* 0 */ | ||
191 | } | ||
192 | __cmpxchg_called_with_bad_pointer(); | ||
193 | return old; | ||
194 | } | ||
195 | |||
196 | #define cmpxchg(ptr,o,n) \ | ||
197 | ({ \ | ||
198 | __typeof__(*(ptr)) _o_ = (o); \ | ||
199 | __typeof__(*(ptr)) _n_ = (n); \ | ||
200 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | ||
201 | (unsigned long)_n_, sizeof(*(ptr))); \ | ||
202 | }) | ||
203 | |||
204 | #define arch_align_stack(x) (x) | ||
205 | |||
206 | #endif /* __KERNEL__ */ | ||
207 | #endif /* __PPC_SYSTEM_H */ | ||
diff --git a/include/asm-ppc/termbits.h b/include/asm-ppc/termbits.h new file mode 100644 index 000000000000..c343fb7bdfed --- /dev/null +++ b/include/asm-ppc/termbits.h | |||
@@ -0,0 +1,185 @@ | |||
1 | #ifndef _PPC_TERMBITS_H | ||
2 | #define _PPC_TERMBITS_H | ||
3 | |||
4 | typedef unsigned char cc_t; | ||
5 | typedef unsigned int speed_t; | ||
6 | typedef unsigned int tcflag_t; | ||
7 | |||
8 | /* | ||
9 | * termios type and macro definitions. Be careful about adding stuff | ||
10 | * to this file since it's used in GNU libc and there are strict rules | ||
11 | * concerning namespace pollution. | ||
12 | */ | ||
13 | |||
14 | #define NCCS 19 | ||
15 | struct termios { | ||
16 | tcflag_t c_iflag; /* input mode flags */ | ||
17 | tcflag_t c_oflag; /* output mode flags */ | ||
18 | tcflag_t c_cflag; /* control mode flags */ | ||
19 | tcflag_t c_lflag; /* local mode flags */ | ||
20 | cc_t c_cc[NCCS]; /* control characters */ | ||
21 | cc_t c_line; /* line discipline (== c_cc[19]) */ | ||
22 | speed_t c_ispeed; /* input speed */ | ||
23 | speed_t c_ospeed; /* output speed */ | ||
24 | }; | ||
25 | |||
26 | /* c_cc characters */ | ||
27 | #define VINTR 0 | ||
28 | #define VQUIT 1 | ||
29 | #define VERASE 2 | ||
30 | #define VKILL 3 | ||
31 | #define VEOF 4 | ||
32 | #define VMIN 5 | ||
33 | #define VEOL 6 | ||
34 | #define VTIME 7 | ||
35 | #define VEOL2 8 | ||
36 | #define VSWTC 9 | ||
37 | |||
38 | #define VWERASE 10 | ||
39 | #define VREPRINT 11 | ||
40 | #define VSUSP 12 | ||
41 | #define VSTART 13 | ||
42 | #define VSTOP 14 | ||
43 | #define VLNEXT 15 | ||
44 | #define VDISCARD 16 | ||
45 | |||
46 | /* c_iflag bits */ | ||
47 | #define IGNBRK 0000001 | ||
48 | #define BRKINT 0000002 | ||
49 | #define IGNPAR 0000004 | ||
50 | #define PARMRK 0000010 | ||
51 | #define INPCK 0000020 | ||
52 | #define ISTRIP 0000040 | ||
53 | #define INLCR 0000100 | ||
54 | #define IGNCR 0000200 | ||
55 | #define ICRNL 0000400 | ||
56 | #define IXON 0001000 | ||
57 | #define IXOFF 0002000 | ||
58 | #define IXANY 0004000 | ||
59 | #define IUCLC 0010000 | ||
60 | #define IMAXBEL 0020000 | ||
61 | #define IUTF8 0040000 | ||
62 | |||
63 | /* c_oflag bits */ | ||
64 | #define OPOST 0000001 | ||
65 | #define ONLCR 0000002 | ||
66 | #define OLCUC 0000004 | ||
67 | |||
68 | #define OCRNL 0000010 | ||
69 | #define ONOCR 0000020 | ||
70 | #define ONLRET 0000040 | ||
71 | |||
72 | #define OFILL 00000100 | ||
73 | #define OFDEL 00000200 | ||
74 | #define NLDLY 00001400 | ||
75 | #define NL0 00000000 | ||
76 | #define NL1 00000400 | ||
77 | #define NL2 00001000 | ||
78 | #define NL3 00001400 | ||
79 | #define TABDLY 00006000 | ||
80 | #define TAB0 00000000 | ||
81 | #define TAB1 00002000 | ||
82 | #define TAB2 00004000 | ||
83 | #define TAB3 00006000 | ||
84 | #define XTABS 00006000 /* required by POSIX to == TAB3 */ | ||
85 | #define CRDLY 00030000 | ||
86 | #define CR0 00000000 | ||
87 | #define CR1 00010000 | ||
88 | #define CR2 00020000 | ||
89 | #define CR3 00030000 | ||
90 | #define FFDLY 00040000 | ||
91 | #define FF0 00000000 | ||
92 | #define FF1 00040000 | ||
93 | #define BSDLY 00100000 | ||
94 | #define BS0 00000000 | ||
95 | #define BS1 00100000 | ||
96 | #define VTDLY 00200000 | ||
97 | #define VT0 00000000 | ||
98 | #define VT1 00200000 | ||
99 | |||
100 | /* c_cflag bit meaning */ | ||
101 | #define CBAUD 0000377 | ||
102 | #define B0 0000000 /* hang up */ | ||
103 | #define B50 0000001 | ||
104 | #define B75 0000002 | ||
105 | #define B110 0000003 | ||
106 | #define B134 0000004 | ||
107 | #define B150 0000005 | ||
108 | #define B200 0000006 | ||
109 | #define B300 0000007 | ||
110 | #define B600 0000010 | ||
111 | #define B1200 0000011 | ||
112 | #define B1800 0000012 | ||
113 | #define B2400 0000013 | ||
114 | #define B4800 0000014 | ||
115 | #define B9600 0000015 | ||
116 | #define B19200 0000016 | ||
117 | #define B38400 0000017 | ||
118 | #define EXTA B19200 | ||
119 | #define EXTB B38400 | ||
120 | #define CBAUDEX 0000000 | ||
121 | #define B57600 00020 | ||
122 | #define B115200 00021 | ||
123 | #define B230400 00022 | ||
124 | #define B460800 00023 | ||
125 | #define B500000 00024 | ||
126 | #define B576000 00025 | ||
127 | #define B921600 00026 | ||
128 | #define B1000000 00027 | ||
129 | #define B1152000 00030 | ||
130 | #define B1500000 00031 | ||
131 | #define B2000000 00032 | ||
132 | #define B2500000 00033 | ||
133 | #define B3000000 00034 | ||
134 | #define B3500000 00035 | ||
135 | #define B4000000 00036 | ||
136 | |||
137 | #define CSIZE 00001400 | ||
138 | #define CS5 00000000 | ||
139 | #define CS6 00000400 | ||
140 | #define CS7 00001000 | ||
141 | #define CS8 00001400 | ||
142 | |||
143 | #define CSTOPB 00002000 | ||
144 | #define CREAD 00004000 | ||
145 | #define PARENB 00010000 | ||
146 | #define PARODD 00020000 | ||
147 | #define HUPCL 00040000 | ||
148 | |||
149 | #define CLOCAL 00100000 | ||
150 | #define CRTSCTS 020000000000 /* flow control */ | ||
151 | |||
152 | /* c_lflag bits */ | ||
153 | #define ISIG 0x00000080 | ||
154 | #define ICANON 0x00000100 | ||
155 | #define XCASE 0x00004000 | ||
156 | #define ECHO 0x00000008 | ||
157 | #define ECHOE 0x00000002 | ||
158 | #define ECHOK 0x00000004 | ||
159 | #define ECHONL 0x00000010 | ||
160 | #define NOFLSH 0x80000000 | ||
161 | #define TOSTOP 0x00400000 | ||
162 | #define ECHOCTL 0x00000040 | ||
163 | #define ECHOPRT 0x00000020 | ||
164 | #define ECHOKE 0x00000001 | ||
165 | #define FLUSHO 0x00800000 | ||
166 | #define PENDIN 0x20000000 | ||
167 | #define IEXTEN 0x00000400 | ||
168 | |||
169 | /* Values for the ACTION argument to `tcflow'. */ | ||
170 | #define TCOOFF 0 | ||
171 | #define TCOON 1 | ||
172 | #define TCIOFF 2 | ||
173 | #define TCION 3 | ||
174 | |||
175 | /* Values for the QUEUE_SELECTOR argument to `tcflush'. */ | ||
176 | #define TCIFLUSH 0 | ||
177 | #define TCOFLUSH 1 | ||
178 | #define TCIOFLUSH 2 | ||
179 | |||
180 | /* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'. */ | ||
181 | #define TCSANOW 0 | ||
182 | #define TCSADRAIN 1 | ||
183 | #define TCSAFLUSH 2 | ||
184 | |||
185 | #endif /* _PPC_TERMBITS_H */ | ||
diff --git a/include/asm-ppc/termios.h b/include/asm-ppc/termios.h new file mode 100644 index 000000000000..97c6287a6cba --- /dev/null +++ b/include/asm-ppc/termios.h | |||
@@ -0,0 +1,232 @@ | |||
1 | #ifndef _PPC_TERMIOS_H | ||
2 | #define _PPC_TERMIOS_H | ||
3 | |||
4 | /* | ||
5 | * Liberally adapted from alpha/termios.h. In particular, the c_cc[] | ||
6 | * fields have been reordered so that termio & termios share the | ||
7 | * common subset in the same order (for brain dead programs that don't | ||
8 | * know or care about the differences). | ||
9 | */ | ||
10 | |||
11 | #include <asm/ioctls.h> | ||
12 | #include <asm/termbits.h> | ||
13 | |||
14 | struct sgttyb { | ||
15 | char sg_ispeed; | ||
16 | char sg_ospeed; | ||
17 | char sg_erase; | ||
18 | char sg_kill; | ||
19 | short sg_flags; | ||
20 | }; | ||
21 | |||
22 | struct tchars { | ||
23 | char t_intrc; | ||
24 | char t_quitc; | ||
25 | char t_startc; | ||
26 | char t_stopc; | ||
27 | char t_eofc; | ||
28 | char t_brkc; | ||
29 | }; | ||
30 | |||
31 | struct ltchars { | ||
32 | char t_suspc; | ||
33 | char t_dsuspc; | ||
34 | char t_rprntc; | ||
35 | char t_flushc; | ||
36 | char t_werasc; | ||
37 | char t_lnextc; | ||
38 | }; | ||
39 | |||
40 | #define FIOCLEX _IO('f', 1) | ||
41 | #define FIONCLEX _IO('f', 2) | ||
42 | #define FIOASYNC _IOW('f', 125, int) | ||
43 | #define FIONBIO _IOW('f', 126, int) | ||
44 | #define FIONREAD _IOR('f', 127, int) | ||
45 | #define TIOCINQ FIONREAD | ||
46 | #define FIOQSIZE _IOR('f', 128, loff_t) | ||
47 | |||
48 | #define TIOCGETP _IOR('t', 8, struct sgttyb) | ||
49 | #define TIOCSETP _IOW('t', 9, struct sgttyb) | ||
50 | #define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */ | ||
51 | |||
52 | #define TIOCSETC _IOW('t', 17, struct tchars) | ||
53 | #define TIOCGETC _IOR('t', 18, struct tchars) | ||
54 | #define TCGETS _IOR('t', 19, struct termios) | ||
55 | #define TCSETS _IOW('t', 20, struct termios) | ||
56 | #define TCSETSW _IOW('t', 21, struct termios) | ||
57 | #define TCSETSF _IOW('t', 22, struct termios) | ||
58 | |||
59 | #define TCGETA _IOR('t', 23, struct termio) | ||
60 | #define TCSETA _IOW('t', 24, struct termio) | ||
61 | #define TCSETAW _IOW('t', 25, struct termio) | ||
62 | #define TCSETAF _IOW('t', 28, struct termio) | ||
63 | |||
64 | #define TCSBRK _IO('t', 29) | ||
65 | #define TCXONC _IO('t', 30) | ||
66 | #define TCFLSH _IO('t', 31) | ||
67 | |||
68 | #define TIOCSWINSZ _IOW('t', 103, struct winsize) | ||
69 | #define TIOCGWINSZ _IOR('t', 104, struct winsize) | ||
70 | #define TIOCSTART _IO('t', 110) /* start output, like ^Q */ | ||
71 | #define TIOCSTOP _IO('t', 111) /* stop output, like ^S */ | ||
72 | #define TIOCOUTQ _IOR('t', 115, int) /* output queue size */ | ||
73 | |||
74 | #define TIOCGLTC _IOR('t', 116, struct ltchars) | ||
75 | #define TIOCSLTC _IOW('t', 117, struct ltchars) | ||
76 | #define TIOCSPGRP _IOW('t', 118, int) | ||
77 | #define TIOCGPGRP _IOR('t', 119, int) | ||
78 | |||
79 | #define TIOCEXCL 0x540C | ||
80 | #define TIOCNXCL 0x540D | ||
81 | #define TIOCSCTTY 0x540E | ||
82 | |||
83 | #define TIOCSTI 0x5412 | ||
84 | #define TIOCMGET 0x5415 | ||
85 | #define TIOCMBIS 0x5416 | ||
86 | #define TIOCMBIC 0x5417 | ||
87 | #define TIOCMSET 0x5418 | ||
88 | #define TIOCGSOFTCAR 0x5419 | ||
89 | #define TIOCSSOFTCAR 0x541A | ||
90 | #define TIOCLINUX 0x541C | ||
91 | #define TIOCCONS 0x541D | ||
92 | #define TIOCGSERIAL 0x541E | ||
93 | #define TIOCSSERIAL 0x541F | ||
94 | #define TIOCPKT 0x5420 | ||
95 | |||
96 | #define TIOCNOTTY 0x5422 | ||
97 | #define TIOCSETD 0x5423 | ||
98 | #define TIOCGETD 0x5424 | ||
99 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
100 | |||
101 | #define TIOCSERCONFIG 0x5453 | ||
102 | #define TIOCSERGWILD 0x5454 | ||
103 | #define TIOCSERSWILD 0x5455 | ||
104 | #define TIOCGLCKTRMIOS 0x5456 | ||
105 | #define TIOCSLCKTRMIOS 0x5457 | ||
106 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
107 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
108 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
109 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
110 | |||
111 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
112 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
113 | |||
114 | /* Used for packet mode */ | ||
115 | #define TIOCPKT_DATA 0 | ||
116 | #define TIOCPKT_FLUSHREAD 1 | ||
117 | #define TIOCPKT_FLUSHWRITE 2 | ||
118 | #define TIOCPKT_STOP 4 | ||
119 | #define TIOCPKT_START 8 | ||
120 | #define TIOCPKT_NOSTOP 16 | ||
121 | #define TIOCPKT_DOSTOP 32 | ||
122 | |||
123 | struct winsize { | ||
124 | unsigned short ws_row; | ||
125 | unsigned short ws_col; | ||
126 | unsigned short ws_xpixel; | ||
127 | unsigned short ws_ypixel; | ||
128 | }; | ||
129 | |||
130 | #define NCC 10 | ||
131 | struct termio { | ||
132 | unsigned short c_iflag; /* input mode flags */ | ||
133 | unsigned short c_oflag; /* output mode flags */ | ||
134 | unsigned short c_cflag; /* control mode flags */ | ||
135 | unsigned short c_lflag; /* local mode flags */ | ||
136 | unsigned char c_line; /* line discipline */ | ||
137 | unsigned char c_cc[NCC]; /* control characters */ | ||
138 | }; | ||
139 | |||
140 | /* c_cc characters */ | ||
141 | #define _VINTR 0 | ||
142 | #define _VQUIT 1 | ||
143 | #define _VERASE 2 | ||
144 | #define _VKILL 3 | ||
145 | #define _VEOF 4 | ||
146 | #define _VMIN 5 | ||
147 | #define _VEOL 6 | ||
148 | #define _VTIME 7 | ||
149 | #define _VEOL2 8 | ||
150 | #define _VSWTC 9 | ||
151 | |||
152 | #ifdef __KERNEL__ | ||
153 | /* ^C ^\ del ^U ^D 1 0 0 0 0 ^W ^R ^Z ^Q ^S ^V ^U */ | ||
154 | #define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025" | ||
155 | #endif /* __KERNEL__ */ | ||
156 | |||
157 | /* modem lines */ | ||
158 | #define TIOCM_LE 0x001 | ||
159 | #define TIOCM_DTR 0x002 | ||
160 | #define TIOCM_RTS 0x004 | ||
161 | #define TIOCM_ST 0x008 | ||
162 | #define TIOCM_SR 0x010 | ||
163 | #define TIOCM_CTS 0x020 | ||
164 | #define TIOCM_CAR 0x040 | ||
165 | #define TIOCM_RNG 0x080 | ||
166 | #define TIOCM_DSR 0x100 | ||
167 | #define TIOCM_CD TIOCM_CAR | ||
168 | #define TIOCM_RI TIOCM_RNG | ||
169 | #define TIOCM_OUT1 0x2000 | ||
170 | #define TIOCM_OUT2 0x4000 | ||
171 | #define TIOCM_LOOP 0x8000 | ||
172 | |||
173 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
174 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
175 | |||
176 | /* line disciplines */ | ||
177 | #define N_TTY 0 | ||
178 | #define N_SLIP 1 | ||
179 | #define N_MOUSE 2 | ||
180 | #define N_PPP 3 | ||
181 | #define N_STRIP 4 | ||
182 | #define N_AX25 5 | ||
183 | #define N_X25 6 /* X.25 async */ | ||
184 | #define N_6PACK 7 | ||
185 | #define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ | ||
186 | #define N_R3964 9 /* Reserved for Simatic R3964 module */ | ||
187 | #define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ | ||
188 | #define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ | ||
189 | #define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ | ||
190 | #define N_HDLC 13 /* synchronous HDLC */ | ||
191 | #define N_SYNC_PPP 14 | ||
192 | #define N_HCI 15 /* Bluetooth HCI UART */ | ||
193 | |||
194 | #ifdef __KERNEL__ | ||
195 | |||
196 | /* | ||
197 | * Translate a "termio" structure into a "termios". Ugh. | ||
198 | */ | ||
199 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
200 | unsigned short __tmp; \ | ||
201 | get_user(__tmp,&(termio)->x); \ | ||
202 | (termios)->x = (0xffff0000 & (termios)->x) | __tmp; \ | ||
203 | } | ||
204 | |||
205 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
206 | ({ \ | ||
207 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
208 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
209 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
210 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
211 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
212 | }) | ||
213 | |||
214 | /* | ||
215 | * Translate a "termios" structure into a "termio". Ugh. | ||
216 | */ | ||
217 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
218 | ({ \ | ||
219 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
220 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
221 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
222 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
223 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
224 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
225 | }) | ||
226 | |||
227 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) | ||
228 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) | ||
229 | |||
230 | #endif /* __KERNEL__ */ | ||
231 | |||
232 | #endif /* _PPC_TERMIOS_H */ | ||
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h new file mode 100644 index 000000000000..f7f01524e8a8 --- /dev/null +++ b/include/asm-ppc/thread_info.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* thread_info.h: PPC low-level thread information | ||
2 | * adapted from the i386 version by Paul Mackerras | ||
3 | * | ||
4 | * Copyright (C) 2002 David Howells (dhowells@redhat.com) | ||
5 | * - Incorporating suggestions made by Linus Torvalds and Dave Miller | ||
6 | */ | ||
7 | |||
8 | #ifndef _ASM_THREAD_INFO_H | ||
9 | #define _ASM_THREAD_INFO_H | ||
10 | |||
11 | #ifdef __KERNEL__ | ||
12 | #ifndef __ASSEMBLY__ | ||
13 | /* | ||
14 | * low level task data. | ||
15 | * If you change this, change the TI_* offsets below to match. | ||
16 | */ | ||
17 | struct thread_info { | ||
18 | struct task_struct *task; /* main task structure */ | ||
19 | struct exec_domain *exec_domain; /* execution domain */ | ||
20 | unsigned long flags; /* low level flags */ | ||
21 | unsigned long local_flags; /* non-racy flags */ | ||
22 | int cpu; /* cpu we're on */ | ||
23 | int preempt_count; | ||
24 | struct restart_block restart_block; | ||
25 | }; | ||
26 | |||
27 | #define INIT_THREAD_INFO(tsk) \ | ||
28 | { \ | ||
29 | .task = &tsk, \ | ||
30 | .exec_domain = &default_exec_domain, \ | ||
31 | .flags = 0, \ | ||
32 | .local_flags = 0, \ | ||
33 | .cpu = 0, \ | ||
34 | .preempt_count = 1, \ | ||
35 | .restart_block = { \ | ||
36 | .fn = do_no_restart_syscall, \ | ||
37 | }, \ | ||
38 | } | ||
39 | |||
40 | #define init_thread_info (init_thread_union.thread_info) | ||
41 | #define init_stack (init_thread_union.stack) | ||
42 | |||
43 | /* | ||
44 | * macros/functions for gaining access to the thread information structure | ||
45 | */ | ||
46 | |||
47 | /* how to get the thread information struct from C */ | ||
48 | static inline struct thread_info *current_thread_info(void) | ||
49 | { | ||
50 | struct thread_info *ti; | ||
51 | __asm__("rlwinm %0,1,0,0,18" : "=r"(ti)); | ||
52 | return ti; | ||
53 | } | ||
54 | |||
55 | /* thread information allocation */ | ||
56 | #define alloc_thread_info(tsk) ((struct thread_info *) \ | ||
57 | __get_free_pages(GFP_KERNEL, 1)) | ||
58 | #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) | ||
59 | #define get_thread_info(ti) get_task_struct((ti)->task) | ||
60 | #define put_thread_info(ti) put_task_struct((ti)->task) | ||
61 | #endif /* __ASSEMBLY__ */ | ||
62 | |||
63 | /* | ||
64 | * Size of kernel stack for each process. | ||
65 | */ | ||
66 | #define THREAD_SIZE 8192 /* 2 pages */ | ||
67 | |||
68 | #define PREEMPT_ACTIVE 0x10000000 | ||
69 | |||
70 | /* | ||
71 | * thread information flag bit numbers | ||
72 | */ | ||
73 | #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ | ||
74 | #define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ | ||
75 | #define TIF_SIGPENDING 2 /* signal pending */ | ||
76 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ | ||
77 | #define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling | ||
78 | TIF_NEED_RESCHED */ | ||
79 | #define TIF_MEMDIE 5 | ||
80 | /* as above, but as bit values */ | ||
81 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | ||
82 | #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) | ||
83 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | ||
84 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | ||
85 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | ||
86 | |||
87 | /* | ||
88 | * Non racy (local) flags bit numbers | ||
89 | */ | ||
90 | #define TIFL_FORCE_NOERROR 0 /* don't return error from current | ||
91 | syscall even if result < 0 */ | ||
92 | |||
93 | /* as above, but as bit values */ | ||
94 | #define _TIFL_FORCE_NOERROR (1<<TIFL_FORCE_NOERROR) | ||
95 | |||
96 | |||
97 | #endif /* __KERNEL__ */ | ||
98 | |||
99 | #endif /* _ASM_THREAD_INFO_H */ | ||
diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h new file mode 100644 index 000000000000..ce09b47fa819 --- /dev/null +++ b/include/asm-ppc/time.h | |||
@@ -0,0 +1,157 @@ | |||
1 | /* | ||
2 | * Common time prototypes and such for all ppc machines. | ||
3 | * | ||
4 | * Written by Cort Dougan (cort@fsmlabs.com) to merge | ||
5 | * Paul Mackerras' version and mine for PReP and Pmac. | ||
6 | */ | ||
7 | |||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef __ASM_TIME_H__ | ||
10 | #define __ASM_TIME_H__ | ||
11 | |||
12 | #include <linux/config.h> | ||
13 | #include <linux/types.h> | ||
14 | #include <linux/rtc.h> | ||
15 | #include <linux/threads.h> | ||
16 | |||
17 | #include <asm/reg.h> | ||
18 | |||
19 | /* time.c */ | ||
20 | extern unsigned tb_ticks_per_jiffy; | ||
21 | extern unsigned tb_to_us; | ||
22 | extern unsigned tb_last_stamp; | ||
23 | extern unsigned long disarm_decr[NR_CPUS]; | ||
24 | |||
25 | extern void to_tm(int tim, struct rtc_time * tm); | ||
26 | extern time_t last_rtc_update; | ||
27 | |||
28 | extern void set_dec_cpu6(unsigned int val); | ||
29 | |||
30 | int via_calibrate_decr(void); | ||
31 | |||
32 | /* Accessor functions for the decrementer register. | ||
33 | * The 4xx doesn't even have a decrementer. I tried to use the | ||
34 | * generic timer interrupt code, which seems OK, with the 4xx PIT | ||
35 | * in auto-reload mode. The problem is PIT stops counting when it | ||
36 | * hits zero. If it would wrap, we could use it just like a decrementer. | ||
37 | */ | ||
38 | static __inline__ unsigned int get_dec(void) | ||
39 | { | ||
40 | #if defined(CONFIG_40x) | ||
41 | return (mfspr(SPRN_PIT)); | ||
42 | #else | ||
43 | return (mfspr(SPRN_DEC)); | ||
44 | #endif | ||
45 | } | ||
46 | |||
47 | static __inline__ void set_dec(unsigned int val) | ||
48 | { | ||
49 | #if defined(CONFIG_40x) | ||
50 | return; /* Have to let it auto-reload */ | ||
51 | #elif defined(CONFIG_8xx_CPU6) | ||
52 | set_dec_cpu6(val); | ||
53 | #else | ||
54 | mtspr(SPRN_DEC, val); | ||
55 | #endif | ||
56 | } | ||
57 | |||
58 | /* Accessor functions for the timebase (RTC on 601) registers. */ | ||
59 | /* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ | ||
60 | #ifdef CONFIG_6xx | ||
61 | extern __inline__ int const __USE_RTC(void) { | ||
62 | return (mfspr(SPRN_PVR)>>16) == 1; | ||
63 | } | ||
64 | #else | ||
65 | #define __USE_RTC() 0 | ||
66 | #endif | ||
67 | |||
68 | extern __inline__ unsigned long get_tbl(void) { | ||
69 | unsigned long tbl; | ||
70 | #if defined(CONFIG_403GCX) | ||
71 | asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); | ||
72 | #else | ||
73 | asm volatile("mftb %0" : "=r" (tbl)); | ||
74 | #endif | ||
75 | return tbl; | ||
76 | } | ||
77 | |||
78 | extern __inline__ unsigned long get_tbu(void) { | ||
79 | unsigned long tbl; | ||
80 | #if defined(CONFIG_403GCX) | ||
81 | asm volatile("mfspr %0, 0x3dc" : "=r" (tbl)); | ||
82 | #else | ||
83 | asm volatile("mftbu %0" : "=r" (tbl)); | ||
84 | #endif | ||
85 | return tbl; | ||
86 | } | ||
87 | |||
88 | extern __inline__ void set_tb(unsigned int upper, unsigned int lower) | ||
89 | { | ||
90 | mtspr(SPRN_TBWL, 0); | ||
91 | mtspr(SPRN_TBWU, upper); | ||
92 | mtspr(SPRN_TBWL, lower); | ||
93 | } | ||
94 | |||
95 | extern __inline__ unsigned long get_rtcl(void) { | ||
96 | unsigned long rtcl; | ||
97 | asm volatile("mfrtcl %0" : "=r" (rtcl)); | ||
98 | return rtcl; | ||
99 | } | ||
100 | |||
101 | extern __inline__ unsigned long get_rtcu(void) | ||
102 | { | ||
103 | unsigned long rtcu; | ||
104 | asm volatile("mfrtcu %0" : "=r" (rtcu)); | ||
105 | return rtcu; | ||
106 | } | ||
107 | |||
108 | extern __inline__ unsigned get_native_tbl(void) { | ||
109 | if (__USE_RTC()) | ||
110 | return get_rtcl(); | ||
111 | else | ||
112 | return get_tbl(); | ||
113 | } | ||
114 | |||
115 | /* On machines with RTC, this function can only be used safely | ||
116 | * after the timestamp and for 1 second. It is only used by gettimeofday | ||
117 | * however so it should not matter. | ||
118 | */ | ||
119 | extern __inline__ unsigned tb_ticks_since(unsigned tstamp) { | ||
120 | if (__USE_RTC()) { | ||
121 | int delta = get_rtcl() - tstamp; | ||
122 | return delta<0 ? delta + 1000000000 : delta; | ||
123 | } else { | ||
124 | return get_tbl() - tstamp; | ||
125 | } | ||
126 | } | ||
127 | |||
128 | #if 0 | ||
129 | extern __inline__ unsigned long get_bin_rtcl(void) { | ||
130 | unsigned long rtcl, rtcu1, rtcu2; | ||
131 | asm volatile("\ | ||
132 | 1: mfrtcu %0\n\ | ||
133 | mfrtcl %1\n\ | ||
134 | mfrtcu %2\n\ | ||
135 | cmpw %0,%2\n\ | ||
136 | bne- 1b\n" | ||
137 | : "=r" (rtcu1), "=r" (rtcl), "=r" (rtcu2) | ||
138 | : : "cr0"); | ||
139 | return rtcu2*1000000000+rtcl; | ||
140 | } | ||
141 | |||
142 | extern __inline__ unsigned binary_tbl(void) { | ||
143 | if (__USE_RTC()) | ||
144 | return get_bin_rtcl(); | ||
145 | else | ||
146 | return get_tbl(); | ||
147 | } | ||
148 | #endif | ||
149 | |||
150 | /* Use mulhwu to scale processor timebase to timeval */ | ||
151 | /* Specifically, this computes (x * y) / 2^32. -- paulus */ | ||
152 | #define mulhwu(x,y) \ | ||
153 | ({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) | ||
154 | |||
155 | unsigned mulhwu_scale_factor(unsigned, unsigned); | ||
156 | #endif /* __ASM_TIME_H__ */ | ||
157 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/timex.h b/include/asm-ppc/timex.h new file mode 100644 index 000000000000..cffc8712077c --- /dev/null +++ b/include/asm-ppc/timex.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/timex.h | ||
3 | * | ||
4 | * ppc architecture timex specifications | ||
5 | */ | ||
6 | #ifdef __KERNEL__ | ||
7 | #ifndef _ASMppc_TIMEX_H | ||
8 | #define _ASMppc_TIMEX_H | ||
9 | |||
10 | #include <linux/config.h> | ||
11 | #include <asm/cputable.h> | ||
12 | |||
13 | #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ | ||
14 | |||
15 | typedef unsigned long cycles_t; | ||
16 | |||
17 | /* | ||
18 | * For the "cycle" counter we use the timebase lower half. | ||
19 | * Currently only used on SMP. | ||
20 | */ | ||
21 | |||
22 | static inline cycles_t get_cycles(void) | ||
23 | { | ||
24 | cycles_t ret = 0; | ||
25 | |||
26 | __asm__ __volatile__( | ||
27 | "98: mftb %0\n" | ||
28 | "99:\n" | ||
29 | ".section __ftr_fixup,\"a\"\n" | ||
30 | " .long %1\n" | ||
31 | " .long 0\n" | ||
32 | " .long 98b\n" | ||
33 | " .long 99b\n" | ||
34 | ".previous" | ||
35 | : "=r" (ret) : "i" (CPU_FTR_601)); | ||
36 | return ret; | ||
37 | } | ||
38 | |||
39 | #endif | ||
40 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/tlb.h b/include/asm-ppc/tlb.h new file mode 100644 index 000000000000..2c142c5d8584 --- /dev/null +++ b/include/asm-ppc/tlb.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * TLB shootdown specifics for PPC | ||
3 | * | ||
4 | * Copyright (C) 2002 Paul Mackerras, IBM Corp. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | */ | ||
11 | #ifndef _PPC_TLB_H | ||
12 | #define _PPC_TLB_H | ||
13 | |||
14 | #include <linux/config.h> | ||
15 | #include <asm/pgtable.h> | ||
16 | #include <asm/pgalloc.h> | ||
17 | #include <asm/tlbflush.h> | ||
18 | #include <asm/page.h> | ||
19 | #include <asm/mmu.h> | ||
20 | |||
21 | #ifdef CONFIG_PPC_STD_MMU | ||
22 | /* Classic PPC with hash-table based MMU... */ | ||
23 | |||
24 | struct mmu_gather; | ||
25 | extern void tlb_flush(struct mmu_gather *tlb); | ||
26 | |||
27 | /* Get the generic bits... */ | ||
28 | #include <asm-generic/tlb.h> | ||
29 | |||
30 | /* Nothing needed here in fact... */ | ||
31 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
32 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
33 | |||
34 | extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, | ||
35 | unsigned long address); | ||
36 | |||
37 | static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, | ||
38 | unsigned long address) | ||
39 | { | ||
40 | if (pte_val(*ptep) & _PAGE_HASHPTE) | ||
41 | flush_hash_entry(tlb->mm, ptep, address); | ||
42 | } | ||
43 | |||
44 | #else | ||
45 | /* Embedded PPC with software-loaded TLB, very simple... */ | ||
46 | |||
47 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
48 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
49 | #define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0) | ||
50 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | ||
51 | |||
52 | /* Get the generic bits... */ | ||
53 | #include <asm-generic/tlb.h> | ||
54 | |||
55 | #endif /* CONFIG_PPC_STD_MMU */ | ||
56 | |||
57 | #endif /* __PPC_TLB_H */ | ||
diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h new file mode 100644 index 000000000000..9850f53f54b0 --- /dev/null +++ b/include/asm-ppc/tlbflush.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/tlbflush.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation; either version | ||
7 | * 2 of the License, or (at your option) any later version. | ||
8 | */ | ||
9 | #ifdef __KERNEL__ | ||
10 | #ifndef _PPC_TLBFLUSH_H | ||
11 | #define _PPC_TLBFLUSH_H | ||
12 | |||
13 | #include <linux/config.h> | ||
14 | #include <linux/mm.h> | ||
15 | |||
16 | extern void _tlbie(unsigned long address); | ||
17 | extern void _tlbia(void); | ||
18 | |||
19 | #if defined(CONFIG_4xx) | ||
20 | |||
21 | #ifndef CONFIG_44x | ||
22 | #define __tlbia() asm volatile ("sync; tlbia; isync" : : : "memory") | ||
23 | #else | ||
24 | #define __tlbia _tlbia | ||
25 | #endif | ||
26 | |||
27 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
28 | { __tlbia(); } | ||
29 | static inline void flush_tlb_page(struct vm_area_struct *vma, | ||
30 | unsigned long vmaddr) | ||
31 | { _tlbie(vmaddr); } | ||
32 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | ||
33 | unsigned long vmaddr) | ||
34 | { _tlbie(vmaddr); } | ||
35 | static inline void flush_tlb_range(struct vm_area_struct *vma, | ||
36 | unsigned long start, unsigned long end) | ||
37 | { __tlbia(); } | ||
38 | static inline void flush_tlb_kernel_range(unsigned long start, | ||
39 | unsigned long end) | ||
40 | { __tlbia(); } | ||
41 | |||
42 | #elif defined(CONFIG_FSL_BOOKE) | ||
43 | |||
44 | /* TODO: determine if flush_tlb_range & flush_tlb_kernel_range | ||
45 | * are best implemented as tlbia vs specific tlbie's */ | ||
46 | |||
47 | #define __tlbia() _tlbia() | ||
48 | |||
49 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
50 | { __tlbia(); } | ||
51 | static inline void flush_tlb_page(struct vm_area_struct *vma, | ||
52 | unsigned long vmaddr) | ||
53 | { _tlbie(vmaddr); } | ||
54 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | ||
55 | unsigned long vmaddr) | ||
56 | { _tlbie(vmaddr); } | ||
57 | static inline void flush_tlb_range(struct vm_area_struct *vma, | ||
58 | unsigned long start, unsigned long end) | ||
59 | { __tlbia(); } | ||
60 | static inline void flush_tlb_kernel_range(unsigned long start, | ||
61 | unsigned long end) | ||
62 | { __tlbia(); } | ||
63 | |||
64 | #elif defined(CONFIG_8xx) | ||
65 | #define __tlbia() asm volatile ("tlbia; sync" : : : "memory") | ||
66 | |||
67 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
68 | { __tlbia(); } | ||
69 | static inline void flush_tlb_page(struct vm_area_struct *vma, | ||
70 | unsigned long vmaddr) | ||
71 | { _tlbie(vmaddr); } | ||
72 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | ||
73 | unsigned long vmaddr) | ||
74 | { _tlbie(vmaddr); } | ||
75 | static inline void flush_tlb_range(struct mm_struct *mm, | ||
76 | unsigned long start, unsigned long end) | ||
77 | { __tlbia(); } | ||
78 | static inline void flush_tlb_kernel_range(unsigned long start, | ||
79 | unsigned long end) | ||
80 | { __tlbia(); } | ||
81 | |||
82 | #else /* 6xx, 7xx, 7xxx cpus */ | ||
83 | struct mm_struct; | ||
84 | struct vm_area_struct; | ||
85 | extern void flush_tlb_mm(struct mm_struct *mm); | ||
86 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | ||
87 | extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr); | ||
88 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | ||
89 | unsigned long end); | ||
90 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | ||
91 | #endif | ||
92 | |||
93 | /* | ||
94 | * This is called in munmap when we have freed up some page-table | ||
95 | * pages. We don't need to do anything here, there's nothing special | ||
96 | * about our page-table pages. -- paulus | ||
97 | */ | ||
98 | static inline void flush_tlb_pgtables(struct mm_struct *mm, | ||
99 | unsigned long start, unsigned long end) | ||
100 | { | ||
101 | } | ||
102 | |||
103 | /* | ||
104 | * This gets called at the end of handling a page fault, when | ||
105 | * the kernel has put a new PTE into the page table for the process. | ||
106 | * We use it to ensure coherency between the i-cache and d-cache | ||
107 | * for the page which has just been mapped in. | ||
108 | * On machines which use an MMU hash table, we use this to put a | ||
109 | * corresponding HPTE into the hash table ahead of time, instead of | ||
110 | * waiting for the inevitable extra hash-table miss exception. | ||
111 | */ | ||
112 | extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); | ||
113 | |||
114 | #endif /* _PPC_TLBFLUSH_H */ | ||
115 | #endif /*__KERNEL__ */ | ||
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h new file mode 100644 index 000000000000..84bae7d76814 --- /dev/null +++ b/include/asm-ppc/todc.h | |||
@@ -0,0 +1,490 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/todc.h | ||
3 | * | ||
4 | * Definitions for the M48Txx and mc146818 series of Time of day/Real Time | ||
5 | * Clock chips. | ||
6 | * | ||
7 | * Author: Mark A. Greer | ||
8 | * mgreer@mvista.com | ||
9 | * | ||
10 | * 2001 (c) MontaVista, Software, Inc. This file is licensed under | ||
11 | * the terms of the GNU General Public License version 2. This program | ||
12 | * is licensed "as is" without any warranty of any kind, whether express | ||
13 | * or implied. | ||
14 | */ | ||
15 | |||
16 | /* | ||
17 | * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips. | ||
18 | * Purpose is to make one generic file that handles all of these chips instead | ||
19 | * of every platform implementing the same code over & over again. | ||
20 | */ | ||
21 | |||
22 | #ifndef __PPC_KERNEL_TODC_H | ||
23 | #define __PPC_KERNEL_TODC_H | ||
24 | |||
25 | typedef struct { | ||
26 | uint rtc_type; /* your particular chip */ | ||
27 | |||
28 | /* | ||
29 | * Following are the addresses of the AS0, AS1, and DATA registers | ||
30 | * of these chips. Note that these are board-specific. | ||
31 | */ | ||
32 | unsigned int nvram_as0; | ||
33 | unsigned int nvram_as1; | ||
34 | unsigned int nvram_data; | ||
35 | |||
36 | /* | ||
37 | * Define bits to stop external set of regs from changing so | ||
38 | * the chip can be read/written reliably. | ||
39 | */ | ||
40 | unsigned char enable_read; | ||
41 | unsigned char enable_write; | ||
42 | |||
43 | /* | ||
44 | * Following is the number of AS0 address bits. This is normally | ||
45 | * 8 but some bad hardware routes address lines incorrectly. | ||
46 | */ | ||
47 | int as0_bits; | ||
48 | |||
49 | int nvram_size; /* Size of NVRAM on chip */ | ||
50 | int sw_flags; /* Software control flags */ | ||
51 | |||
52 | /* Following are the register offsets for the particular chip */ | ||
53 | int year; | ||
54 | int month; | ||
55 | int day_of_month; | ||
56 | int day_of_week; | ||
57 | int hours; | ||
58 | int minutes; | ||
59 | int seconds; | ||
60 | int control_b; | ||
61 | int control_a; | ||
62 | int watchdog; | ||
63 | int interrupts; | ||
64 | int alarm_date; | ||
65 | int alarm_hour; | ||
66 | int alarm_minutes; | ||
67 | int alarm_seconds; | ||
68 | int century; | ||
69 | int flags; | ||
70 | |||
71 | /* | ||
72 | * Some RTC chips have their NVRAM buried behind a addr/data pair of | ||
73 | * regs on the first level/clock registers. The following fields | ||
74 | * are the addresses for those addr/data regs. | ||
75 | */ | ||
76 | int nvram_addr_reg; | ||
77 | int nvram_data_reg; | ||
78 | } todc_info_t; | ||
79 | |||
80 | /* | ||
81 | * Define the types of TODC/RTC variants that are supported in | ||
82 | * arch/ppc/kernel/todc_time.c | ||
83 | * Make a new one of these for any chip somehow differs from what's already | ||
84 | * defined. That way, if you ever need to put in code to touch those | ||
85 | * bits/registers in todc_time.c, you can put it inside an | ||
86 | * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break | ||
87 | * anyone else. | ||
88 | */ | ||
89 | #define TODC_TYPE_MK48T35 1 | ||
90 | #define TODC_TYPE_MK48T37 2 | ||
91 | #define TODC_TYPE_MK48T59 3 | ||
92 | #define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */ | ||
93 | #define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */ | ||
94 | #define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */ | ||
95 | #define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */ | ||
96 | #define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */ | ||
97 | #define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */ | ||
98 | #define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */ | ||
99 | #define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */ | ||
100 | #define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */ | ||
101 | #define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */ | ||
102 | #define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */ | ||
103 | |||
104 | /* | ||
105 | * Bit to clear/set to enable reads/writes to the chip | ||
106 | */ | ||
107 | #define TODC_MK48TXX_CNTL_A_R 0x40 | ||
108 | #define TODC_MK48TXX_CNTL_A_W 0x80 | ||
109 | #define TODC_MK48TXX_DAY_CB 0x80 | ||
110 | |||
111 | #define TODC_DS1501_CNTL_B_TE 0x80 | ||
112 | |||
113 | /* | ||
114 | * Define flag bits used by todc routines. | ||
115 | */ | ||
116 | #define TODC_FLAG_2_LEVEL_NVRAM 0x00000001 | ||
117 | |||
118 | /* | ||
119 | * Define the values for the various RTC's that should to into the todc_info | ||
120 | * table. | ||
121 | * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only | ||
122 | * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set. | ||
123 | */ | ||
124 | #define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8 | ||
125 | #define TODC_TYPE_MK48T35_SW_FLAGS 0 | ||
126 | #define TODC_TYPE_MK48T35_YEAR 0x7fff | ||
127 | #define TODC_TYPE_MK48T35_MONTH 0x7ffe | ||
128 | #define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */ | ||
129 | #define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */ | ||
130 | #define TODC_TYPE_MK48T35_HOURS 0x7ffb | ||
131 | #define TODC_TYPE_MK48T35_MINUTES 0x7ffa | ||
132 | #define TODC_TYPE_MK48T35_SECONDS 0x7ff9 | ||
133 | #define TODC_TYPE_MK48T35_CNTL_B 0x7ff9 | ||
134 | #define TODC_TYPE_MK48T35_CNTL_A 0x7ff8 | ||
135 | #define TODC_TYPE_MK48T35_WATCHDOG 0x0000 | ||
136 | #define TODC_TYPE_MK48T35_INTERRUPTS 0x0000 | ||
137 | #define TODC_TYPE_MK48T35_ALARM_DATE 0x0000 | ||
138 | #define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000 | ||
139 | #define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000 | ||
140 | #define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000 | ||
141 | #define TODC_TYPE_MK48T35_CENTURY 0x0000 | ||
142 | #define TODC_TYPE_MK48T35_FLAGS 0x0000 | ||
143 | #define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0 | ||
144 | #define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0 | ||
145 | |||
146 | #define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0 | ||
147 | #define TODC_TYPE_MK48T37_SW_FLAGS 0 | ||
148 | #define TODC_TYPE_MK48T37_YEAR 0x7fff | ||
149 | #define TODC_TYPE_MK48T37_MONTH 0x7ffe | ||
150 | #define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */ | ||
151 | #define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */ | ||
152 | #define TODC_TYPE_MK48T37_HOURS 0x7ffb | ||
153 | #define TODC_TYPE_MK48T37_MINUTES 0x7ffa | ||
154 | #define TODC_TYPE_MK48T37_SECONDS 0x7ff9 | ||
155 | #define TODC_TYPE_MK48T37_CNTL_B 0x7ff9 | ||
156 | #define TODC_TYPE_MK48T37_CNTL_A 0x7ff8 | ||
157 | #define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7 | ||
158 | #define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6 | ||
159 | #define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5 | ||
160 | #define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4 | ||
161 | #define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3 | ||
162 | #define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2 | ||
163 | #define TODC_TYPE_MK48T37_CENTURY 0x7ff1 | ||
164 | #define TODC_TYPE_MK48T37_FLAGS 0x7ff0 | ||
165 | #define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0 | ||
166 | #define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0 | ||
167 | |||
168 | #define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0 | ||
169 | #define TODC_TYPE_MK48T59_SW_FLAGS 0 | ||
170 | #define TODC_TYPE_MK48T59_YEAR 0x1fff | ||
171 | #define TODC_TYPE_MK48T59_MONTH 0x1ffe | ||
172 | #define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */ | ||
173 | #define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */ | ||
174 | #define TODC_TYPE_MK48T59_HOURS 0x1ffb | ||
175 | #define TODC_TYPE_MK48T59_MINUTES 0x1ffa | ||
176 | #define TODC_TYPE_MK48T59_SECONDS 0x1ff9 | ||
177 | #define TODC_TYPE_MK48T59_CNTL_B 0x1ff9 | ||
178 | #define TODC_TYPE_MK48T59_CNTL_A 0x1ff8 | ||
179 | #define TODC_TYPE_MK48T59_WATCHDOG 0x1fff | ||
180 | #define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff | ||
181 | #define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff | ||
182 | #define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff | ||
183 | #define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff | ||
184 | #define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff | ||
185 | #define TODC_TYPE_MK48T59_CENTURY 0x1fff | ||
186 | #define TODC_TYPE_MK48T59_FLAGS 0x1fff | ||
187 | #define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0 | ||
188 | #define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0 | ||
189 | |||
190 | #define TODC_TYPE_DS1501_NVRAM_SIZE 0x100 | ||
191 | #define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM | ||
192 | #define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06) | ||
193 | #define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05) | ||
194 | #define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04) | ||
195 | #define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03) | ||
196 | #define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02) | ||
197 | #define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01) | ||
198 | #define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00) | ||
199 | #define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) | ||
200 | #define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f) | ||
201 | #define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
202 | #define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
203 | #define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b) | ||
204 | #define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a) | ||
205 | #define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09) | ||
206 | #define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08) | ||
207 | #define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07) | ||
208 | #define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff) | ||
209 | #define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10 | ||
210 | #define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13 | ||
211 | |||
212 | #define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0 | ||
213 | #define TODC_TYPE_DS1553_SW_FLAGS 0 | ||
214 | #define TODC_TYPE_DS1553_YEAR 0x1fff | ||
215 | #define TODC_TYPE_DS1553_MONTH 0x1ffe | ||
216 | #define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */ | ||
217 | #define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */ | ||
218 | #define TODC_TYPE_DS1553_HOURS 0x1ffb | ||
219 | #define TODC_TYPE_DS1553_MINUTES 0x1ffa | ||
220 | #define TODC_TYPE_DS1553_SECONDS 0x1ff9 | ||
221 | #define TODC_TYPE_DS1553_CNTL_B 0x1ff9 | ||
222 | #define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
223 | #define TODC_TYPE_DS1553_WATCHDOG 0x1ff7 | ||
224 | #define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6 | ||
225 | #define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5 | ||
226 | #define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4 | ||
227 | #define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3 | ||
228 | #define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2 | ||
229 | #define TODC_TYPE_DS1553_CENTURY 0x1ff8 | ||
230 | #define TODC_TYPE_DS1553_FLAGS 0x1ff0 | ||
231 | #define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0 | ||
232 | #define TODC_TYPE_DS1553_NVRAM_DATA_REG 0 | ||
233 | |||
234 | #define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0 | ||
235 | #define TODC_TYPE_DS1557_SW_FLAGS 0 | ||
236 | #define TODC_TYPE_DS1557_YEAR 0x7ffff | ||
237 | #define TODC_TYPE_DS1557_MONTH 0x7fffe | ||
238 | #define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */ | ||
239 | #define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */ | ||
240 | #define TODC_TYPE_DS1557_HOURS 0x7fffb | ||
241 | #define TODC_TYPE_DS1557_MINUTES 0x7fffa | ||
242 | #define TODC_TYPE_DS1557_SECONDS 0x7fff9 | ||
243 | #define TODC_TYPE_DS1557_CNTL_B 0x7fff9 | ||
244 | #define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */ | ||
245 | #define TODC_TYPE_DS1557_WATCHDOG 0x7fff7 | ||
246 | #define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6 | ||
247 | #define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5 | ||
248 | #define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4 | ||
249 | #define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3 | ||
250 | #define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2 | ||
251 | #define TODC_TYPE_DS1557_CENTURY 0x7fff8 | ||
252 | #define TODC_TYPE_DS1557_FLAGS 0x7fff0 | ||
253 | #define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0 | ||
254 | #define TODC_TYPE_DS1557_NVRAM_DATA_REG 0 | ||
255 | |||
256 | #define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8 | ||
257 | #define TODC_TYPE_DS1643_SW_FLAGS 0 | ||
258 | #define TODC_TYPE_DS1643_YEAR 0x1fff | ||
259 | #define TODC_TYPE_DS1643_MONTH 0x1ffe | ||
260 | #define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */ | ||
261 | #define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */ | ||
262 | #define TODC_TYPE_DS1643_HOURS 0x1ffb | ||
263 | #define TODC_TYPE_DS1643_MINUTES 0x1ffa | ||
264 | #define TODC_TYPE_DS1643_SECONDS 0x1ff9 | ||
265 | #define TODC_TYPE_DS1643_CNTL_B 0x1ff9 | ||
266 | #define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
267 | #define TODC_TYPE_DS1643_WATCHDOG 0x1fff | ||
268 | #define TODC_TYPE_DS1643_INTERRUPTS 0x1fff | ||
269 | #define TODC_TYPE_DS1643_ALARM_DATE 0x1fff | ||
270 | #define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff | ||
271 | #define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff | ||
272 | #define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff | ||
273 | #define TODC_TYPE_DS1643_CENTURY 0x1ff8 | ||
274 | #define TODC_TYPE_DS1643_FLAGS 0x1fff | ||
275 | #define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0 | ||
276 | #define TODC_TYPE_DS1643_NVRAM_DATA_REG 0 | ||
277 | |||
278 | #define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */ | ||
279 | #define TODC_TYPE_DS1693_SW_FLAGS 0 | ||
280 | #define TODC_TYPE_DS1693_YEAR 0x09 | ||
281 | #define TODC_TYPE_DS1693_MONTH 0x08 | ||
282 | #define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */ | ||
283 | #define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */ | ||
284 | #define TODC_TYPE_DS1693_HOURS 0x04 | ||
285 | #define TODC_TYPE_DS1693_MINUTES 0x02 | ||
286 | #define TODC_TYPE_DS1693_SECONDS 0x00 | ||
287 | #define TODC_TYPE_DS1693_CNTL_B 0x0b | ||
288 | #define TODC_TYPE_DS1693_CNTL_A 0x0a | ||
289 | #define TODC_TYPE_DS1693_WATCHDOG 0xff | ||
290 | #define TODC_TYPE_DS1693_INTERRUPTS 0xff | ||
291 | #define TODC_TYPE_DS1693_ALARM_DATE 0x49 | ||
292 | #define TODC_TYPE_DS1693_ALARM_HOUR 0x05 | ||
293 | #define TODC_TYPE_DS1693_ALARM_MINUTES 0x03 | ||
294 | #define TODC_TYPE_DS1693_ALARM_SECONDS 0x01 | ||
295 | #define TODC_TYPE_DS1693_CENTURY 0x48 | ||
296 | #define TODC_TYPE_DS1693_FLAGS 0xff | ||
297 | #define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0 | ||
298 | #define TODC_TYPE_DS1693_NVRAM_DATA_REG 0 | ||
299 | |||
300 | #define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8 | ||
301 | #define TODC_TYPE_DS1743_SW_FLAGS 0 | ||
302 | #define TODC_TYPE_DS1743_YEAR 0x1fff | ||
303 | #define TODC_TYPE_DS1743_MONTH 0x1ffe | ||
304 | #define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */ | ||
305 | #define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */ | ||
306 | #define TODC_TYPE_DS1743_HOURS 0x1ffb | ||
307 | #define TODC_TYPE_DS1743_MINUTES 0x1ffa | ||
308 | #define TODC_TYPE_DS1743_SECONDS 0x1ff9 | ||
309 | #define TODC_TYPE_DS1743_CNTL_B 0x1ff9 | ||
310 | #define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */ | ||
311 | #define TODC_TYPE_DS1743_WATCHDOG 0x1fff | ||
312 | #define TODC_TYPE_DS1743_INTERRUPTS 0x1fff | ||
313 | #define TODC_TYPE_DS1743_ALARM_DATE 0x1fff | ||
314 | #define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff | ||
315 | #define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff | ||
316 | #define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff | ||
317 | #define TODC_TYPE_DS1743_CENTURY 0x1ff8 | ||
318 | #define TODC_TYPE_DS1743_FLAGS 0x1fff | ||
319 | #define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0 | ||
320 | #define TODC_TYPE_DS1743_NVRAM_DATA_REG 0 | ||
321 | |||
322 | #define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8 | ||
323 | #define TODC_TYPE_DS1746_SW_FLAGS 0 | ||
324 | #define TODC_TYPE_DS1746_YEAR 0x1ffff | ||
325 | #define TODC_TYPE_DS1746_MONTH 0x1fffe | ||
326 | #define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */ | ||
327 | #define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */ | ||
328 | #define TODC_TYPE_DS1746_HOURS 0x1fffb | ||
329 | #define TODC_TYPE_DS1746_MINUTES 0x1fffa | ||
330 | #define TODC_TYPE_DS1746_SECONDS 0x1fff9 | ||
331 | #define TODC_TYPE_DS1746_CNTL_B 0x1fff9 | ||
332 | #define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */ | ||
333 | #define TODC_TYPE_DS1746_WATCHDOG 0x00000 | ||
334 | #define TODC_TYPE_DS1746_INTERRUPTS 0x00000 | ||
335 | #define TODC_TYPE_DS1746_ALARM_DATE 0x00000 | ||
336 | #define TODC_TYPE_DS1746_ALARM_HOUR 0x00000 | ||
337 | #define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000 | ||
338 | #define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000 | ||
339 | #define TODC_TYPE_DS1746_CENTURY 0x00000 | ||
340 | #define TODC_TYPE_DS1746_FLAGS 0x00000 | ||
341 | #define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0 | ||
342 | #define TODC_TYPE_DS1746_NVRAM_DATA_REG 0 | ||
343 | |||
344 | #define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8 | ||
345 | #define TODC_TYPE_DS1747_SW_FLAGS 0 | ||
346 | #define TODC_TYPE_DS1747_YEAR 0x7ffff | ||
347 | #define TODC_TYPE_DS1747_MONTH 0x7fffe | ||
348 | #define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */ | ||
349 | #define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */ | ||
350 | #define TODC_TYPE_DS1747_HOURS 0x7fffb | ||
351 | #define TODC_TYPE_DS1747_MINUTES 0x7fffa | ||
352 | #define TODC_TYPE_DS1747_SECONDS 0x7fff9 | ||
353 | #define TODC_TYPE_DS1747_CNTL_B 0x7fff9 | ||
354 | #define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */ | ||
355 | #define TODC_TYPE_DS1747_WATCHDOG 0x00000 | ||
356 | #define TODC_TYPE_DS1747_INTERRUPTS 0x00000 | ||
357 | #define TODC_TYPE_DS1747_ALARM_DATE 0x00000 | ||
358 | #define TODC_TYPE_DS1747_ALARM_HOUR 0x00000 | ||
359 | #define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000 | ||
360 | #define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000 | ||
361 | #define TODC_TYPE_DS1747_CENTURY 0x00000 | ||
362 | #define TODC_TYPE_DS1747_FLAGS 0x00000 | ||
363 | #define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0 | ||
364 | #define TODC_TYPE_DS1747_NVRAM_DATA_REG 0 | ||
365 | |||
366 | #define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */ | ||
367 | #define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM | ||
368 | #define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00) | ||
369 | #define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01) | ||
370 | #define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02) | ||
371 | #define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03) | ||
372 | #define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04) | ||
373 | #define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05) | ||
374 | #define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06) | ||
375 | #define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07) | ||
376 | #define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08) | ||
377 | #define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09) | ||
378 | #define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A) | ||
379 | #define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B) | ||
380 | #define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C) | ||
381 | #define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D) | ||
382 | #define TODC_TYPE_DS17285_WATCHDOG 0 | ||
383 | #define TODC_TYPE_DS17285_INTERRUPTS 0 | ||
384 | #define TODC_TYPE_DS17285_ALARM_DATE 0 | ||
385 | #define TODC_TYPE_DS17285_CENTURY 0 | ||
386 | #define TODC_TYPE_DS17285_FLAGS 0 | ||
387 | #define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50 | ||
388 | #define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53 | ||
389 | |||
390 | #define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */ | ||
391 | #define TODC_TYPE_MC146818_SW_FLAGS 0 | ||
392 | #define TODC_TYPE_MC146818_YEAR 0x09 | ||
393 | #define TODC_TYPE_MC146818_MONTH 0x08 | ||
394 | #define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */ | ||
395 | #define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */ | ||
396 | #define TODC_TYPE_MC146818_HOURS 0x04 | ||
397 | #define TODC_TYPE_MC146818_MINUTES 0x02 | ||
398 | #define TODC_TYPE_MC146818_SECONDS 0x00 | ||
399 | #define TODC_TYPE_MC146818_CNTL_B 0x0a | ||
400 | #define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */ | ||
401 | #define TODC_TYPE_MC146818_WATCHDOG 0 | ||
402 | #define TODC_TYPE_MC146818_INTERRUPTS 0x0c | ||
403 | #define TODC_TYPE_MC146818_ALARM_DATE 0xff | ||
404 | #define TODC_TYPE_MC146818_ALARM_HOUR 0x05 | ||
405 | #define TODC_TYPE_MC146818_ALARM_MINUTES 0x03 | ||
406 | #define TODC_TYPE_MC146818_ALARM_SECONDS 0x01 | ||
407 | #define TODC_TYPE_MC146818_CENTURY 0xff | ||
408 | #define TODC_TYPE_MC146818_FLAGS 0xff | ||
409 | #define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0 | ||
410 | #define TODC_TYPE_MC146818_NVRAM_DATA_REG 0 | ||
411 | |||
412 | #define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */ | ||
413 | #define TODC_TYPE_PC97307_SW_FLAGS 0 | ||
414 | #define TODC_TYPE_PC97307_YEAR 0x09 | ||
415 | #define TODC_TYPE_PC97307_MONTH 0x08 | ||
416 | #define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */ | ||
417 | #define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */ | ||
418 | #define TODC_TYPE_PC97307_HOURS 0x04 | ||
419 | #define TODC_TYPE_PC97307_MINUTES 0x02 | ||
420 | #define TODC_TYPE_PC97307_SECONDS 0x00 | ||
421 | #define TODC_TYPE_PC97307_CNTL_B 0x0a | ||
422 | #define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */ | ||
423 | #define TODC_TYPE_PC97307_WATCHDOG 0x0c | ||
424 | #define TODC_TYPE_PC97307_INTERRUPTS 0x0d | ||
425 | #define TODC_TYPE_PC97307_ALARM_DATE 0xff | ||
426 | #define TODC_TYPE_PC97307_ALARM_HOUR 0x05 | ||
427 | #define TODC_TYPE_PC97307_ALARM_MINUTES 0x03 | ||
428 | #define TODC_TYPE_PC97307_ALARM_SECONDS 0x01 | ||
429 | #define TODC_TYPE_PC97307_CENTURY 0xff | ||
430 | #define TODC_TYPE_PC97307_FLAGS 0xff | ||
431 | #define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0 | ||
432 | #define TODC_TYPE_PC97307_NVRAM_DATA_REG 0 | ||
433 | |||
434 | /* | ||
435 | * Define macros to allocate and init the todc_info_t table that will | ||
436 | * be used by the todc_time.c routines. | ||
437 | */ | ||
438 | #define TODC_ALLOC() \ | ||
439 | static todc_info_t todc_info_alloc; \ | ||
440 | todc_info_t *todc_info = &todc_info_alloc; | ||
441 | |||
442 | #define TODC_INIT(clock_type, as0, as1, data, bits) { \ | ||
443 | todc_info->rtc_type = clock_type; \ | ||
444 | \ | ||
445 | todc_info->nvram_as0 = (unsigned int)(as0); \ | ||
446 | todc_info->nvram_as1 = (unsigned int)(as1); \ | ||
447 | todc_info->nvram_data = (unsigned int)(data); \ | ||
448 | \ | ||
449 | todc_info->as0_bits = (bits); \ | ||
450 | \ | ||
451 | todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \ | ||
452 | todc_info->sw_flags = clock_type ##_SW_FLAGS; \ | ||
453 | \ | ||
454 | todc_info->year = clock_type ##_YEAR; \ | ||
455 | todc_info->month = clock_type ##_MONTH; \ | ||
456 | todc_info->day_of_month = clock_type ##_DOM; \ | ||
457 | todc_info->day_of_week = clock_type ##_DOW; \ | ||
458 | todc_info->hours = clock_type ##_HOURS; \ | ||
459 | todc_info->minutes = clock_type ##_MINUTES; \ | ||
460 | todc_info->seconds = clock_type ##_SECONDS; \ | ||
461 | todc_info->control_b = clock_type ##_CNTL_B; \ | ||
462 | todc_info->control_a = clock_type ##_CNTL_A; \ | ||
463 | todc_info->watchdog = clock_type ##_WATCHDOG; \ | ||
464 | todc_info->interrupts = clock_type ##_INTERRUPTS; \ | ||
465 | todc_info->alarm_date = clock_type ##_ALARM_DATE; \ | ||
466 | todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \ | ||
467 | todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \ | ||
468 | todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \ | ||
469 | todc_info->century = clock_type ##_CENTURY; \ | ||
470 | todc_info->flags = clock_type ##_FLAGS; \ | ||
471 | \ | ||
472 | todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \ | ||
473 | todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \ | ||
474 | } | ||
475 | |||
476 | extern todc_info_t *todc_info; | ||
477 | |||
478 | unsigned char todc_direct_read_val(int addr); | ||
479 | void todc_direct_write_val(int addr, unsigned char val); | ||
480 | unsigned char todc_m48txx_read_val(int addr); | ||
481 | void todc_m48txx_write_val(int addr, unsigned char val); | ||
482 | unsigned char todc_mc146818_read_val(int addr); | ||
483 | void todc_mc146818_write_val(int addr, unsigned char val); | ||
484 | |||
485 | long todc_time_init(void); | ||
486 | unsigned long todc_get_rtc_time(void); | ||
487 | int todc_set_rtc_time(unsigned long nowtime); | ||
488 | void todc_calibrate_decr(void); | ||
489 | |||
490 | #endif /* __PPC_KERNEL_TODC_H */ | ||
diff --git a/include/asm-ppc/topology.h b/include/asm-ppc/topology.h new file mode 100644 index 000000000000..6a029bbba6e1 --- /dev/null +++ b/include/asm-ppc/topology.h | |||
@@ -0,0 +1,6 @@ | |||
1 | #ifndef _ASM_PPC_TOPOLOGY_H | ||
2 | #define _ASM_PPC_TOPOLOGY_H | ||
3 | |||
4 | #include <asm-generic/topology.h> | ||
5 | |||
6 | #endif /* _ASM_PPC_TOPOLOGY_H */ | ||
diff --git a/include/asm-ppc/traps.h b/include/asm-ppc/traps.h new file mode 100644 index 000000000000..68e7326b56f1 --- /dev/null +++ b/include/asm-ppc/traps.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-m68k/traps.h> | |||
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h new file mode 100644 index 000000000000..a787bc032587 --- /dev/null +++ b/include/asm-ppc/types.h | |||
@@ -0,0 +1,71 @@ | |||
1 | #ifndef _PPC_TYPES_H | ||
2 | #define _PPC_TYPES_H | ||
3 | |||
4 | #ifndef __ASSEMBLY__ | ||
5 | |||
6 | typedef __signed__ char __s8; | ||
7 | typedef unsigned char __u8; | ||
8 | |||
9 | typedef __signed__ short __s16; | ||
10 | typedef unsigned short __u16; | ||
11 | |||
12 | typedef __signed__ int __s32; | ||
13 | typedef unsigned int __u32; | ||
14 | |||
15 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | ||
16 | typedef __signed__ long long __s64; | ||
17 | typedef unsigned long long __u64; | ||
18 | #endif | ||
19 | |||
20 | typedef struct { | ||
21 | __u32 u[4]; | ||
22 | } __vector128; | ||
23 | |||
24 | /* | ||
25 | * XXX allowed outside of __KERNEL__ for now, until glibc gets | ||
26 | * a proper set of asm headers of its own. -- paulus | ||
27 | */ | ||
28 | typedef unsigned short umode_t; | ||
29 | |||
30 | #endif /* __ASSEMBLY__ */ | ||
31 | |||
32 | #ifdef __KERNEL__ | ||
33 | /* | ||
34 | * These aren't exported outside the kernel to avoid name space clashes | ||
35 | */ | ||
36 | #define BITS_PER_LONG 32 | ||
37 | |||
38 | #ifndef __ASSEMBLY__ | ||
39 | |||
40 | #include <linux/config.h> | ||
41 | |||
42 | typedef signed char s8; | ||
43 | typedef unsigned char u8; | ||
44 | |||
45 | typedef signed short s16; | ||
46 | typedef unsigned short u16; | ||
47 | |||
48 | typedef signed int s32; | ||
49 | typedef unsigned int u32; | ||
50 | |||
51 | typedef signed long long s64; | ||
52 | typedef unsigned long long u64; | ||
53 | |||
54 | typedef __vector128 vector128; | ||
55 | |||
56 | /* DMA addresses are 32-bits wide */ | ||
57 | typedef u32 dma_addr_t; | ||
58 | typedef u64 dma64_addr_t; | ||
59 | |||
60 | #ifdef CONFIG_LBD | ||
61 | typedef u64 sector_t; | ||
62 | #define HAVE_SECTOR_T | ||
63 | #endif | ||
64 | |||
65 | typedef unsigned int kmem_bufctl_t; | ||
66 | |||
67 | #endif /* __ASSEMBLY__ */ | ||
68 | |||
69 | #endif /* __KERNEL__ */ | ||
70 | |||
71 | #endif | ||
diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h new file mode 100644 index 000000000000..b044ae03ac56 --- /dev/null +++ b/include/asm-ppc/uaccess.h | |||
@@ -0,0 +1,400 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_UACCESS_H | ||
3 | #define _PPC_UACCESS_H | ||
4 | |||
5 | #ifndef __ASSEMBLY__ | ||
6 | #include <linux/sched.h> | ||
7 | #include <linux/errno.h> | ||
8 | #include <asm/processor.h> | ||
9 | |||
10 | #define VERIFY_READ 0 | ||
11 | #define VERIFY_WRITE 1 | ||
12 | |||
13 | /* | ||
14 | * The fs value determines whether argument validity checking should be | ||
15 | * performed or not. If get_fs() == USER_DS, checking is performed, with | ||
16 | * get_fs() == KERNEL_DS, checking is bypassed. | ||
17 | * | ||
18 | * For historical reasons, these macros are grossly misnamed. | ||
19 | * | ||
20 | * The fs/ds values are now the highest legal address in the "segment". | ||
21 | * This simplifies the checking in the routines below. | ||
22 | */ | ||
23 | |||
24 | #define KERNEL_DS ((mm_segment_t) { ~0UL }) | ||
25 | #define USER_DS ((mm_segment_t) { TASK_SIZE - 1 }) | ||
26 | |||
27 | #define get_ds() (KERNEL_DS) | ||
28 | #define get_fs() (current->thread.fs) | ||
29 | #define set_fs(val) (current->thread.fs = (val)) | ||
30 | |||
31 | #define segment_eq(a,b) ((a).seg == (b).seg) | ||
32 | |||
33 | #define __access_ok(addr,size) \ | ||
34 | ((addr) <= current->thread.fs.seg \ | ||
35 | && ((size) == 0 || (size) - 1 <= current->thread.fs.seg - (addr))) | ||
36 | |||
37 | #define access_ok(type, addr, size) \ | ||
38 | (__chk_user_ptr(addr),__access_ok((unsigned long)(addr),(size))) | ||
39 | |||
40 | /* this function will go away soon - use access_ok() instead */ | ||
41 | extern inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size) | ||
42 | { | ||
43 | return access_ok(type, addr, size) ? 0 : -EFAULT; | ||
44 | } | ||
45 | |||
46 | |||
47 | /* | ||
48 | * The exception table consists of pairs of addresses: the first is the | ||
49 | * address of an instruction that is allowed to fault, and the second is | ||
50 | * the address at which the program should continue. No registers are | ||
51 | * modified, so it is entirely up to the continuation code to figure out | ||
52 | * what to do. | ||
53 | * | ||
54 | * All the routines below use bits of fixup code that are out of line | ||
55 | * with the main instruction path. This means when everything is well, | ||
56 | * we don't even have to jump over them. Further, they do not intrude | ||
57 | * on our cache or tlb entries. | ||
58 | */ | ||
59 | |||
60 | struct exception_table_entry | ||
61 | { | ||
62 | unsigned long insn, fixup; | ||
63 | }; | ||
64 | |||
65 | /* | ||
66 | * These are the main single-value transfer routines. They automatically | ||
67 | * use the right size if we just have the right pointer type. | ||
68 | * | ||
69 | * This gets kind of ugly. We want to return _two_ values in "get_user()" | ||
70 | * and yet we don't want to do any pointers, because that is too much | ||
71 | * of a performance impact. Thus we have a few rather ugly macros here, | ||
72 | * and hide all the ugliness from the user. | ||
73 | * | ||
74 | * The "__xxx" versions of the user access functions are versions that | ||
75 | * do not verify the address space, that must have been done previously | ||
76 | * with a separate "access_ok()" call (this is used when we do multiple | ||
77 | * accesses to the same area of user memory). | ||
78 | * | ||
79 | * As we use the same address space for kernel and user data on the | ||
80 | * PowerPC, we can just do these as direct assignments. (Of course, the | ||
81 | * exception handling means that it's no longer "just"...) | ||
82 | * | ||
83 | * The "user64" versions of the user access functions are versions that | ||
84 | * allow access of 64-bit data. The "get_user" functions do not | ||
85 | * properly handle 64-bit data because the value gets down cast to a long. | ||
86 | * The "put_user" functions already handle 64-bit data properly but we add | ||
87 | * "user64" versions for completeness | ||
88 | */ | ||
89 | #define get_user(x,ptr) \ | ||
90 | __get_user_check((x),(ptr),sizeof(*(ptr))) | ||
91 | #define get_user64(x,ptr) \ | ||
92 | __get_user64_check((x),(ptr),sizeof(*(ptr))) | ||
93 | #define put_user(x,ptr) \ | ||
94 | __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
95 | #define put_user64(x,ptr) put_user(x,ptr) | ||
96 | |||
97 | #define __get_user(x,ptr) \ | ||
98 | __get_user_nocheck((x),(ptr),sizeof(*(ptr))) | ||
99 | #define __get_user64(x,ptr) \ | ||
100 | __get_user64_nocheck((x),(ptr),sizeof(*(ptr))) | ||
101 | #define __put_user(x,ptr) \ | ||
102 | __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) | ||
103 | #define __put_user64(x,ptr) __put_user(x,ptr) | ||
104 | |||
105 | extern long __put_user_bad(void); | ||
106 | |||
107 | #define __put_user_nocheck(x,ptr,size) \ | ||
108 | ({ \ | ||
109 | long __pu_err; \ | ||
110 | __chk_user_ptr(ptr); \ | ||
111 | __put_user_size((x),(ptr),(size),__pu_err); \ | ||
112 | __pu_err; \ | ||
113 | }) | ||
114 | |||
115 | #define __put_user_check(x,ptr,size) \ | ||
116 | ({ \ | ||
117 | long __pu_err = -EFAULT; \ | ||
118 | __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ | ||
119 | if (access_ok(VERIFY_WRITE,__pu_addr,size)) \ | ||
120 | __put_user_size((x),__pu_addr,(size),__pu_err); \ | ||
121 | __pu_err; \ | ||
122 | }) | ||
123 | |||
124 | #define __put_user_size(x,ptr,size,retval) \ | ||
125 | do { \ | ||
126 | retval = 0; \ | ||
127 | switch (size) { \ | ||
128 | case 1: \ | ||
129 | __put_user_asm(x, ptr, retval, "stb"); \ | ||
130 | break; \ | ||
131 | case 2: \ | ||
132 | __put_user_asm(x, ptr, retval, "sth"); \ | ||
133 | break; \ | ||
134 | case 4: \ | ||
135 | __put_user_asm(x, ptr, retval, "stw"); \ | ||
136 | break; \ | ||
137 | case 8: \ | ||
138 | __put_user_asm2(x, ptr, retval); \ | ||
139 | break; \ | ||
140 | default: \ | ||
141 | __put_user_bad(); \ | ||
142 | } \ | ||
143 | } while (0) | ||
144 | |||
145 | /* | ||
146 | * We don't tell gcc that we are accessing memory, but this is OK | ||
147 | * because we do not write to any memory gcc knows about, so there | ||
148 | * are no aliasing issues. | ||
149 | */ | ||
150 | #define __put_user_asm(x, addr, err, op) \ | ||
151 | __asm__ __volatile__( \ | ||
152 | "1: "op" %1,0(%2)\n" \ | ||
153 | "2:\n" \ | ||
154 | ".section .fixup,\"ax\"\n" \ | ||
155 | "3: li %0,%3\n" \ | ||
156 | " b 2b\n" \ | ||
157 | ".previous\n" \ | ||
158 | ".section __ex_table,\"a\"\n" \ | ||
159 | " .align 2\n" \ | ||
160 | " .long 1b,3b\n" \ | ||
161 | ".previous" \ | ||
162 | : "=r" (err) \ | ||
163 | : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) | ||
164 | |||
165 | #define __put_user_asm2(x, addr, err) \ | ||
166 | __asm__ __volatile__( \ | ||
167 | "1: stw %1,0(%2)\n" \ | ||
168 | "2: stw %1+1,4(%2)\n" \ | ||
169 | "3:\n" \ | ||
170 | ".section .fixup,\"ax\"\n" \ | ||
171 | "4: li %0,%3\n" \ | ||
172 | " b 3b\n" \ | ||
173 | ".previous\n" \ | ||
174 | ".section __ex_table,\"a\"\n" \ | ||
175 | " .align 2\n" \ | ||
176 | " .long 1b,4b\n" \ | ||
177 | " .long 2b,4b\n" \ | ||
178 | ".previous" \ | ||
179 | : "=r" (err) \ | ||
180 | : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) | ||
181 | |||
182 | #define __get_user_nocheck(x, ptr, size) \ | ||
183 | ({ \ | ||
184 | long __gu_err; \ | ||
185 | unsigned long __gu_val; \ | ||
186 | __chk_user_ptr(ptr); \ | ||
187 | __get_user_size(__gu_val, (ptr), (size), __gu_err); \ | ||
188 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
189 | __gu_err; \ | ||
190 | }) | ||
191 | |||
192 | #define __get_user64_nocheck(x, ptr, size) \ | ||
193 | ({ \ | ||
194 | long __gu_err; \ | ||
195 | long long __gu_val; \ | ||
196 | __chk_user_ptr(ptr); \ | ||
197 | __get_user_size64(__gu_val, (ptr), (size), __gu_err); \ | ||
198 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
199 | __gu_err; \ | ||
200 | }) | ||
201 | |||
202 | #define __get_user_check(x, ptr, size) \ | ||
203 | ({ \ | ||
204 | long __gu_err = -EFAULT; \ | ||
205 | unsigned long __gu_val = 0; \ | ||
206 | const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ | ||
207 | if (access_ok(VERIFY_READ, __gu_addr, (size))) \ | ||
208 | __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ | ||
209 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
210 | __gu_err; \ | ||
211 | }) | ||
212 | |||
213 | #define __get_user64_check(x, ptr, size) \ | ||
214 | ({ \ | ||
215 | long __gu_err = -EFAULT; \ | ||
216 | long long __gu_val = 0; \ | ||
217 | const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ | ||
218 | if (access_ok(VERIFY_READ, __gu_addr, (size))) \ | ||
219 | __get_user_size64(__gu_val, __gu_addr, (size), __gu_err); \ | ||
220 | (x) = (__typeof__(*(ptr)))__gu_val; \ | ||
221 | __gu_err; \ | ||
222 | }) | ||
223 | |||
224 | extern long __get_user_bad(void); | ||
225 | |||
226 | #define __get_user_size(x, ptr, size, retval) \ | ||
227 | do { \ | ||
228 | retval = 0; \ | ||
229 | switch (size) { \ | ||
230 | case 1: \ | ||
231 | __get_user_asm(x, ptr, retval, "lbz"); \ | ||
232 | break; \ | ||
233 | case 2: \ | ||
234 | __get_user_asm(x, ptr, retval, "lhz"); \ | ||
235 | break; \ | ||
236 | case 4: \ | ||
237 | __get_user_asm(x, ptr, retval, "lwz"); \ | ||
238 | break; \ | ||
239 | default: \ | ||
240 | x = __get_user_bad(); \ | ||
241 | } \ | ||
242 | } while (0) | ||
243 | |||
244 | #define __get_user_size64(x, ptr, size, retval) \ | ||
245 | do { \ | ||
246 | retval = 0; \ | ||
247 | switch (size) { \ | ||
248 | case 1: \ | ||
249 | __get_user_asm(x, ptr, retval, "lbz"); \ | ||
250 | break; \ | ||
251 | case 2: \ | ||
252 | __get_user_asm(x, ptr, retval, "lhz"); \ | ||
253 | break; \ | ||
254 | case 4: \ | ||
255 | __get_user_asm(x, ptr, retval, "lwz"); \ | ||
256 | break; \ | ||
257 | case 8: \ | ||
258 | __get_user_asm2(x, ptr, retval); \ | ||
259 | break; \ | ||
260 | default: \ | ||
261 | x = __get_user_bad(); \ | ||
262 | } \ | ||
263 | } while (0) | ||
264 | |||
265 | #define __get_user_asm(x, addr, err, op) \ | ||
266 | __asm__ __volatile__( \ | ||
267 | "1: "op" %1,0(%2)\n" \ | ||
268 | "2:\n" \ | ||
269 | ".section .fixup,\"ax\"\n" \ | ||
270 | "3: li %0,%3\n" \ | ||
271 | " li %1,0\n" \ | ||
272 | " b 2b\n" \ | ||
273 | ".previous\n" \ | ||
274 | ".section __ex_table,\"a\"\n" \ | ||
275 | " .align 2\n" \ | ||
276 | " .long 1b,3b\n" \ | ||
277 | ".previous" \ | ||
278 | : "=r"(err), "=r"(x) \ | ||
279 | : "b"(addr), "i"(-EFAULT), "0"(err)) | ||
280 | |||
281 | #define __get_user_asm2(x, addr, err) \ | ||
282 | __asm__ __volatile__( \ | ||
283 | "1: lwz %1,0(%2)\n" \ | ||
284 | "2: lwz %1+1,4(%2)\n" \ | ||
285 | "3:\n" \ | ||
286 | ".section .fixup,\"ax\"\n" \ | ||
287 | "4: li %0,%3\n" \ | ||
288 | " li %1,0\n" \ | ||
289 | " li %1+1,0\n" \ | ||
290 | " b 3b\n" \ | ||
291 | ".previous\n" \ | ||
292 | ".section __ex_table,\"a\"\n" \ | ||
293 | " .align 2\n" \ | ||
294 | " .long 1b,4b\n" \ | ||
295 | " .long 2b,4b\n" \ | ||
296 | ".previous" \ | ||
297 | : "=r"(err), "=&r"(x) \ | ||
298 | : "b"(addr), "i"(-EFAULT), "0"(err)) | ||
299 | |||
300 | /* more complex routines */ | ||
301 | |||
302 | extern int __copy_tofrom_user(void __user *to, const void __user *from, | ||
303 | unsigned long size); | ||
304 | |||
305 | extern inline unsigned long | ||
306 | copy_from_user(void *to, const void __user *from, unsigned long n) | ||
307 | { | ||
308 | unsigned long over; | ||
309 | |||
310 | if (access_ok(VERIFY_READ, from, n)) | ||
311 | return __copy_tofrom_user((__force void __user *)to, from, n); | ||
312 | if ((unsigned long)from < TASK_SIZE) { | ||
313 | over = (unsigned long)from + n - TASK_SIZE; | ||
314 | return __copy_tofrom_user((__force void __user *)to, from, n - over) + over; | ||
315 | } | ||
316 | return n; | ||
317 | } | ||
318 | |||
319 | extern inline unsigned long | ||
320 | copy_to_user(void __user *to, const void *from, unsigned long n) | ||
321 | { | ||
322 | unsigned long over; | ||
323 | |||
324 | if (access_ok(VERIFY_WRITE, to, n)) | ||
325 | return __copy_tofrom_user(to, (__force void __user *) from, n); | ||
326 | if ((unsigned long)to < TASK_SIZE) { | ||
327 | over = (unsigned long)to + n - TASK_SIZE; | ||
328 | return __copy_tofrom_user(to, (__force void __user *) from, n - over) + over; | ||
329 | } | ||
330 | return n; | ||
331 | } | ||
332 | |||
333 | static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long size) | ||
334 | { | ||
335 | return __copy_tofrom_user((__force void __user *)to, from, size); | ||
336 | } | ||
337 | |||
338 | static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long size) | ||
339 | { | ||
340 | return __copy_tofrom_user(to, (__force void __user *)from, size); | ||
341 | } | ||
342 | |||
343 | #define __copy_to_user_inatomic __copy_to_user | ||
344 | #define __copy_from_user_inatomic __copy_from_user | ||
345 | |||
346 | extern unsigned long __clear_user(void __user *addr, unsigned long size); | ||
347 | |||
348 | extern inline unsigned long | ||
349 | clear_user(void __user *addr, unsigned long size) | ||
350 | { | ||
351 | if (access_ok(VERIFY_WRITE, addr, size)) | ||
352 | return __clear_user(addr, size); | ||
353 | if ((unsigned long)addr < TASK_SIZE) { | ||
354 | unsigned long over = (unsigned long)addr + size - TASK_SIZE; | ||
355 | return __clear_user(addr, size - over) + over; | ||
356 | } | ||
357 | return size; | ||
358 | } | ||
359 | |||
360 | extern int __strncpy_from_user(char *dst, const char __user *src, long count); | ||
361 | |||
362 | extern inline long | ||
363 | strncpy_from_user(char *dst, const char __user *src, long count) | ||
364 | { | ||
365 | if (access_ok(VERIFY_READ, src, 1)) | ||
366 | return __strncpy_from_user(dst, src, count); | ||
367 | return -EFAULT; | ||
368 | } | ||
369 | |||
370 | /* | ||
371 | * Return the size of a string (including the ending 0) | ||
372 | * | ||
373 | * Return 0 for error | ||
374 | */ | ||
375 | |||
376 | extern int __strnlen_user(const char __user *str, long len, unsigned long top); | ||
377 | |||
378 | /* | ||
379 | * Returns the length of the string at str (including the null byte), | ||
380 | * or 0 if we hit a page we can't access, | ||
381 | * or something > len if we didn't find a null byte. | ||
382 | * | ||
383 | * The `top' parameter to __strnlen_user is to make sure that | ||
384 | * we can never overflow from the user area into kernel space. | ||
385 | */ | ||
386 | extern __inline__ int strnlen_user(const char __user *str, long len) | ||
387 | { | ||
388 | unsigned long top = current->thread.fs.seg; | ||
389 | |||
390 | if ((unsigned long)str > top) | ||
391 | return 0; | ||
392 | return __strnlen_user(str, len, top); | ||
393 | } | ||
394 | |||
395 | #define strlen_user(str) strnlen_user((str), 0x7ffffffe) | ||
396 | |||
397 | #endif /* __ASSEMBLY__ */ | ||
398 | |||
399 | #endif /* _PPC_UACCESS_H */ | ||
400 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ucontext.h b/include/asm-ppc/ucontext.h new file mode 100644 index 000000000000..664bc984d51f --- /dev/null +++ b/include/asm-ppc/ucontext.h | |||
@@ -0,0 +1,27 @@ | |||
1 | #ifndef _ASMPPC_UCONTEXT_H | ||
2 | #define _ASMPPC_UCONTEXT_H | ||
3 | |||
4 | #include <asm/elf.h> | ||
5 | #include <asm/signal.h> | ||
6 | |||
7 | struct mcontext { | ||
8 | elf_gregset_t mc_gregs; | ||
9 | elf_fpregset_t mc_fregs; | ||
10 | unsigned long mc_pad[2]; | ||
11 | elf_vrregset_t mc_vregs __attribute__((__aligned__(16))); | ||
12 | }; | ||
13 | |||
14 | struct ucontext { | ||
15 | unsigned long uc_flags; | ||
16 | struct ucontext __user *uc_link; | ||
17 | stack_t uc_stack; | ||
18 | int uc_pad[7]; | ||
19 | struct mcontext __user *uc_regs;/* points to uc_mcontext field */ | ||
20 | sigset_t uc_sigmask; | ||
21 | /* glibc has 1024-bit signal masks, ours are 64-bit */ | ||
22 | int uc_maskext[30]; | ||
23 | int uc_pad2[3]; | ||
24 | struct mcontext uc_mcontext; | ||
25 | }; | ||
26 | |||
27 | #endif /* !_ASMPPC_UCONTEXT_H */ | ||
diff --git a/include/asm-ppc/unaligned.h b/include/asm-ppc/unaligned.h new file mode 100644 index 000000000000..45520d9b85d1 --- /dev/null +++ b/include/asm-ppc/unaligned.h | |||
@@ -0,0 +1,18 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef __PPC_UNALIGNED_H | ||
3 | #define __PPC_UNALIGNED_H | ||
4 | |||
5 | /* | ||
6 | * The PowerPC can do unaligned accesses itself in big endian mode. | ||
7 | * | ||
8 | * The strange macros are there to make sure these can't | ||
9 | * be misused in a way that makes them not work on other | ||
10 | * architectures where unaligned accesses aren't as simple. | ||
11 | */ | ||
12 | |||
13 | #define get_unaligned(ptr) (*(ptr)) | ||
14 | |||
15 | #define put_unaligned(val, ptr) ((void)( *(ptr) = (val) )) | ||
16 | |||
17 | #endif | ||
18 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/uninorth.h b/include/asm-ppc/uninorth.h new file mode 100644 index 000000000000..f737732c3861 --- /dev/null +++ b/include/asm-ppc/uninorth.h | |||
@@ -0,0 +1,229 @@ | |||
1 | /* | ||
2 | * uninorth.h: definitions for using the "UniNorth" host bridge chip | ||
3 | * from Apple. This chip is used on "Core99" machines | ||
4 | * This also includes U2 used on more recent MacRISC2/3 | ||
5 | * machines and U3 (G5) | ||
6 | * | ||
7 | */ | ||
8 | #ifdef __KERNEL__ | ||
9 | #ifndef __ASM_UNINORTH_H__ | ||
10 | #define __ASM_UNINORTH_H__ | ||
11 | |||
12 | /* | ||
13 | * Uni-N and U3 config space reg. definitions | ||
14 | * | ||
15 | * (Little endian) | ||
16 | */ | ||
17 | |||
18 | /* Address ranges selection. This one should work with Bandit too */ | ||
19 | /* Not U3 */ | ||
20 | #define UNI_N_ADDR_SELECT 0x48 | ||
21 | #define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */ | ||
22 | #define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */ | ||
23 | |||
24 | /* AGP registers */ | ||
25 | /* Not U3 */ | ||
26 | #define UNI_N_CFG_GART_BASE 0x8c | ||
27 | #define UNI_N_CFG_AGP_BASE 0x90 | ||
28 | #define UNI_N_CFG_GART_CTRL 0x94 | ||
29 | #define UNI_N_CFG_INTERNAL_STATUS 0x98 | ||
30 | #define UNI_N_CFG_GART_DUMMY_PAGE 0xa4 | ||
31 | |||
32 | /* UNI_N_CFG_GART_CTRL bits definitions */ | ||
33 | #define UNI_N_CFG_GART_INVAL 0x00000001 | ||
34 | #define UNI_N_CFG_GART_ENABLE 0x00000100 | ||
35 | #define UNI_N_CFG_GART_2xRESET 0x00010000 | ||
36 | #define UNI_N_CFG_GART_DISSBADET 0x00020000 | ||
37 | /* The following seems to only be used only on U3 <j.glisse@gmail.com> */ | ||
38 | #define U3_N_CFG_GART_SYNCMODE 0x00040000 | ||
39 | #define U3_N_CFG_GART_PERFRD 0x00080000 | ||
40 | #define U3_N_CFG_GART_B2BGNT 0x00200000 | ||
41 | #define U3_N_CFG_GART_FASTDDR 0x00400000 | ||
42 | |||
43 | /* My understanding of UniNorth AGP as of UniNorth rev 1.0x, | ||
44 | * revision 1.5 (x4 AGP) may need further changes. | ||
45 | * | ||
46 | * AGP_BASE register contains the base address of the AGP aperture on | ||
47 | * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x, | ||
48 | * even if decoding of this address range is enabled in the address select | ||
49 | * register. Apparently, the only supported bases are 256Mb multiples | ||
50 | * (high 4 bits of that register). | ||
51 | * | ||
52 | * GART_BASE register appear to contain the physical address of the GART | ||
53 | * in system memory in the high address bits (page aligned), and the | ||
54 | * GART size in the low order bits (number of GART pages) | ||
55 | * | ||
56 | * The GART format itself is one 32bits word per physical memory page. | ||
57 | * This word contains, in little-endian format (!!!), the physical address | ||
58 | * of the page in the high bits, and what appears to be an "enable" bit | ||
59 | * in the LSB bit (0) that must be set to 1 when the entry is valid. | ||
60 | * | ||
61 | * Obviously, the GART is not cache coherent and so any change to it | ||
62 | * must be flushed to memory (or maybe just make the GART space non | ||
63 | * cachable). AGP memory itself doens't seem to be cache coherent neither. | ||
64 | * | ||
65 | * In order to invalidate the GART (which is probably necessary to inval | ||
66 | * the bridge internal TLBs), the following sequence has to be written, | ||
67 | * in order, to the GART_CTRL register: | ||
68 | * | ||
69 | * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL | ||
70 | * UNI_N_CFG_GART_ENABLE | ||
71 | * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET | ||
72 | * UNI_N_CFG_GART_ENABLE | ||
73 | * | ||
74 | * As far as AGP "features" are concerned, it looks like fast write may | ||
75 | * not be supported but this has to be confirmed. | ||
76 | * | ||
77 | * Turning on AGP seem to require a double invalidate operation, one before | ||
78 | * setting the AGP command register, on after. | ||
79 | * | ||
80 | * Turning off AGP seems to require the following sequence: first wait | ||
81 | * for the AGP to be idle by reading the internal status register, then | ||
82 | * write in that order to the GART_CTRL register: | ||
83 | * | ||
84 | * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL | ||
85 | * 0 | ||
86 | * UNI_N_CFG_GART_2xRESET | ||
87 | * 0 | ||
88 | */ | ||
89 | |||
90 | /* | ||
91 | * Uni-N memory mapped reg. definitions | ||
92 | * | ||
93 | * Those registers are Big-Endian !! | ||
94 | * | ||
95 | * Their meaning come from either Darwin and/or from experiments I made with | ||
96 | * the bootrom, I'm not sure about their exact meaning yet | ||
97 | * | ||
98 | */ | ||
99 | |||
100 | /* Version of the UniNorth chip */ | ||
101 | #define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */ | ||
102 | |||
103 | #define UNI_N_VERSION_107 0x0003 /* 1.0.7 */ | ||
104 | #define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */ | ||
105 | #define UNI_N_VERSION_150 0x0011 /* 1.5 */ | ||
106 | #define UNI_N_VERSION_200 0x0024 /* 2.0 */ | ||
107 | #define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */ | ||
108 | #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */ | ||
109 | #define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */ | ||
110 | |||
111 | /* This register is used to enable/disable various clocks */ | ||
112 | #define UNI_N_CLOCK_CNTL 0x0020 | ||
113 | #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */ | ||
114 | #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */ | ||
115 | #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */ | ||
116 | #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */ | ||
117 | |||
118 | /* Power Management control */ | ||
119 | #define UNI_N_POWER_MGT 0x0030 | ||
120 | #define UNI_N_POWER_MGT_NORMAL 0x00 | ||
121 | #define UNI_N_POWER_MGT_IDLE2 0x01 | ||
122 | #define UNI_N_POWER_MGT_SLEEP 0x02 | ||
123 | |||
124 | /* This register is configured by Darwin depending on the UniN | ||
125 | * revision | ||
126 | */ | ||
127 | #define UNI_N_ARB_CTRL 0x0040 | ||
128 | #define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15 | ||
129 | #define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000 | ||
130 | #define UNI_N_ARB_CTRL_QACK_DELAY 0x30 | ||
131 | #define UNI_N_ARB_CTRL_QACK_DELAY105 0x00 | ||
132 | |||
133 | /* This one _might_ return the CPU number of the CPU reading it; | ||
134 | * the bootROM decides whether to boot or to sleep/spinloop depending | ||
135 | * on this register beeing 0 or not | ||
136 | */ | ||
137 | #define UNI_N_CPU_NUMBER 0x0050 | ||
138 | |||
139 | /* This register appear to be read by the bootROM to decide what | ||
140 | * to do on a non-recoverable reset (powerup or wakeup) | ||
141 | */ | ||
142 | #define UNI_N_HWINIT_STATE 0x0070 | ||
143 | #define UNI_N_HWINIT_STATE_SLEEPING 0x01 | ||
144 | #define UNI_N_HWINIT_STATE_RUNNING 0x02 | ||
145 | /* This last bit appear to be used by the bootROM to know the second | ||
146 | * CPU has started and will enter it's sleep loop with IP=0 | ||
147 | */ | ||
148 | #define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000 | ||
149 | |||
150 | /* This register controls AACK delay, which is set when 2004 iBook/PowerBook | ||
151 | * is in low speed mode. | ||
152 | */ | ||
153 | #define UNI_N_AACK_DELAY 0x0100 | ||
154 | #define UNI_N_AACK_DELAY_ENABLE 0x00000001 | ||
155 | |||
156 | /* Clock status for Intrepid */ | ||
157 | #define UNI_N_CLOCK_STOP_STATUS0 0x0150 | ||
158 | #define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000 | ||
159 | #define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000 | ||
160 | #define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000 | ||
161 | #define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000 | ||
162 | #define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000 | ||
163 | #define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000 | ||
164 | #define UNI_N_CLOCK_STOPPED_TIMER 0x00008000 | ||
165 | #define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000 | ||
166 | #define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000 | ||
167 | #define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000 | ||
168 | #define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800 | ||
169 | #define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400 | ||
170 | #define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200 | ||
171 | #define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100 | ||
172 | #define UNI_N_CLOCK_STOPPED_VEO0 0x00000080 | ||
173 | #define UNI_N_CLOCK_STOPPED_VEO1 0x00000040 | ||
174 | #define UNI_N_CLOCK_STOPPED_USB0 0x00000020 | ||
175 | #define UNI_N_CLOCK_STOPPED_USB1 0x00000010 | ||
176 | #define UNI_N_CLOCK_STOPPED_USB2 0x00000008 | ||
177 | #define UNI_N_CLOCK_STOPPED_32 0x00000004 | ||
178 | #define UNI_N_CLOCK_STOPPED_45 0x00000002 | ||
179 | #define UNI_N_CLOCK_STOPPED_49 0x00000001 | ||
180 | |||
181 | #define UNI_N_CLOCK_STOP_STATUS1 0x0160 | ||
182 | #define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000 | ||
183 | #define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000 | ||
184 | #define UNI_N_CLOCK_STOPPED_CPU 0x00020000 | ||
185 | #define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000 | ||
186 | #define UNI_N_CLOCK_STOPPED_PCI2 0x00008000 | ||
187 | #define UNI_N_CLOCK_STOPPED_FW 0x00004000 | ||
188 | #define UNI_N_CLOCK_STOPPED_GB 0x00002000 | ||
189 | #define UNI_N_CLOCK_STOPPED_ATA66 0x00001000 | ||
190 | #define UNI_N_CLOCK_STOPPED_ATA100 0x00000800 | ||
191 | #define UNI_N_CLOCK_STOPPED_MAX 0x00000400 | ||
192 | #define UNI_N_CLOCK_STOPPED_PCI1 0x00000200 | ||
193 | #define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100 | ||
194 | #define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080 | ||
195 | #define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040 | ||
196 | #define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020 | ||
197 | #define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008 | ||
198 | #define UNI_N_CLOCK_STOPPED_AGP 0x00000004 | ||
199 | #define UNI_N_CLOCK_STOPPED_PCI0 0x00000002 | ||
200 | #define UNI_N_CLOCK_STOPPED_18 0x00000001 | ||
201 | |||
202 | /* Intrepid registe to OF do-platform-clockspreading */ | ||
203 | #define UNI_N_CLOCK_SPREADING 0x190 | ||
204 | |||
205 | /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */ | ||
206 | |||
207 | |||
208 | /* | ||
209 | * U3 specific registers | ||
210 | */ | ||
211 | |||
212 | |||
213 | /* U3 Toggle */ | ||
214 | #define U3_TOGGLE_REG 0x00e0 | ||
215 | #define U3_PMC_START_STOP 0x0001 | ||
216 | #define U3_MPIC_RESET 0x0002 | ||
217 | #define U3_MPIC_OUTPUT_ENABLE 0x0004 | ||
218 | |||
219 | /* U3 API PHY Config 1 */ | ||
220 | #define U3_API_PHY_CONFIG_1 0x23030 | ||
221 | |||
222 | /* U3 HyperTransport registers */ | ||
223 | #define U3_HT_CONFIG_BASE 0x70000 | ||
224 | #define U3_HT_LINK_COMMAND 0x100 | ||
225 | #define U3_HT_LINK_CONFIG 0x110 | ||
226 | #define U3_HT_LINK_FREQ 0x120 | ||
227 | |||
228 | #endif /* __ASM_UNINORTH_H__ */ | ||
229 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h new file mode 100644 index 000000000000..cc51e5c9acc2 --- /dev/null +++ b/include/asm-ppc/unistd.h | |||
@@ -0,0 +1,488 @@ | |||
1 | #ifndef _ASM_PPC_UNISTD_H_ | ||
2 | #define _ASM_PPC_UNISTD_H_ | ||
3 | |||
4 | /* | ||
5 | * This file contains the system call numbers. | ||
6 | */ | ||
7 | #define __NR_restart_syscall 0 | ||
8 | #define __NR_exit 1 | ||
9 | #define __NR_fork 2 | ||
10 | #define __NR_read 3 | ||
11 | #define __NR_write 4 | ||
12 | #define __NR_open 5 | ||
13 | #define __NR_close 6 | ||
14 | #define __NR_waitpid 7 | ||
15 | #define __NR_creat 8 | ||
16 | #define __NR_link 9 | ||
17 | #define __NR_unlink 10 | ||
18 | #define __NR_execve 11 | ||
19 | #define __NR_chdir 12 | ||
20 | #define __NR_time 13 | ||
21 | #define __NR_mknod 14 | ||
22 | #define __NR_chmod 15 | ||
23 | #define __NR_lchown 16 | ||
24 | #define __NR_break 17 | ||
25 | #define __NR_oldstat 18 | ||
26 | #define __NR_lseek 19 | ||
27 | #define __NR_getpid 20 | ||
28 | #define __NR_mount 21 | ||
29 | #define __NR_umount 22 | ||
30 | #define __NR_setuid 23 | ||
31 | #define __NR_getuid 24 | ||
32 | #define __NR_stime 25 | ||
33 | #define __NR_ptrace 26 | ||
34 | #define __NR_alarm 27 | ||
35 | #define __NR_oldfstat 28 | ||
36 | #define __NR_pause 29 | ||
37 | #define __NR_utime 30 | ||
38 | #define __NR_stty 31 | ||
39 | #define __NR_gtty 32 | ||
40 | #define __NR_access 33 | ||
41 | #define __NR_nice 34 | ||
42 | #define __NR_ftime 35 | ||
43 | #define __NR_sync 36 | ||
44 | #define __NR_kill 37 | ||
45 | #define __NR_rename 38 | ||
46 | #define __NR_mkdir 39 | ||
47 | #define __NR_rmdir 40 | ||
48 | #define __NR_dup 41 | ||
49 | #define __NR_pipe 42 | ||
50 | #define __NR_times 43 | ||
51 | #define __NR_prof 44 | ||
52 | #define __NR_brk 45 | ||
53 | #define __NR_setgid 46 | ||
54 | #define __NR_getgid 47 | ||
55 | #define __NR_signal 48 | ||
56 | #define __NR_geteuid 49 | ||
57 | #define __NR_getegid 50 | ||
58 | #define __NR_acct 51 | ||
59 | #define __NR_umount2 52 | ||
60 | #define __NR_lock 53 | ||
61 | #define __NR_ioctl 54 | ||
62 | #define __NR_fcntl 55 | ||
63 | #define __NR_mpx 56 | ||
64 | #define __NR_setpgid 57 | ||
65 | #define __NR_ulimit 58 | ||
66 | #define __NR_oldolduname 59 | ||
67 | #define __NR_umask 60 | ||
68 | #define __NR_chroot 61 | ||
69 | #define __NR_ustat 62 | ||
70 | #define __NR_dup2 63 | ||
71 | #define __NR_getppid 64 | ||
72 | #define __NR_getpgrp 65 | ||
73 | #define __NR_setsid 66 | ||
74 | #define __NR_sigaction 67 | ||
75 | #define __NR_sgetmask 68 | ||
76 | #define __NR_ssetmask 69 | ||
77 | #define __NR_setreuid 70 | ||
78 | #define __NR_setregid 71 | ||
79 | #define __NR_sigsuspend 72 | ||
80 | #define __NR_sigpending 73 | ||
81 | #define __NR_sethostname 74 | ||
82 | #define __NR_setrlimit 75 | ||
83 | #define __NR_getrlimit 76 | ||
84 | #define __NR_getrusage 77 | ||
85 | #define __NR_gettimeofday 78 | ||
86 | #define __NR_settimeofday 79 | ||
87 | #define __NR_getgroups 80 | ||
88 | #define __NR_setgroups 81 | ||
89 | #define __NR_select 82 | ||
90 | #define __NR_symlink 83 | ||
91 | #define __NR_oldlstat 84 | ||
92 | #define __NR_readlink 85 | ||
93 | #define __NR_uselib 86 | ||
94 | #define __NR_swapon 87 | ||
95 | #define __NR_reboot 88 | ||
96 | #define __NR_readdir 89 | ||
97 | #define __NR_mmap 90 | ||
98 | #define __NR_munmap 91 | ||
99 | #define __NR_truncate 92 | ||
100 | #define __NR_ftruncate 93 | ||
101 | #define __NR_fchmod 94 | ||
102 | #define __NR_fchown 95 | ||
103 | #define __NR_getpriority 96 | ||
104 | #define __NR_setpriority 97 | ||
105 | #define __NR_profil 98 | ||
106 | #define __NR_statfs 99 | ||
107 | #define __NR_fstatfs 100 | ||
108 | #define __NR_ioperm 101 | ||
109 | #define __NR_socketcall 102 | ||
110 | #define __NR_syslog 103 | ||
111 | #define __NR_setitimer 104 | ||
112 | #define __NR_getitimer 105 | ||
113 | #define __NR_stat 106 | ||
114 | #define __NR_lstat 107 | ||
115 | #define __NR_fstat 108 | ||
116 | #define __NR_olduname 109 | ||
117 | #define __NR_iopl 110 | ||
118 | #define __NR_vhangup 111 | ||
119 | #define __NR_idle 112 | ||
120 | #define __NR_vm86 113 | ||
121 | #define __NR_wait4 114 | ||
122 | #define __NR_swapoff 115 | ||
123 | #define __NR_sysinfo 116 | ||
124 | #define __NR_ipc 117 | ||
125 | #define __NR_fsync 118 | ||
126 | #define __NR_sigreturn 119 | ||
127 | #define __NR_clone 120 | ||
128 | #define __NR_setdomainname 121 | ||
129 | #define __NR_uname 122 | ||
130 | #define __NR_modify_ldt 123 | ||
131 | #define __NR_adjtimex 124 | ||
132 | #define __NR_mprotect 125 | ||
133 | #define __NR_sigprocmask 126 | ||
134 | #define __NR_create_module 127 | ||
135 | #define __NR_init_module 128 | ||
136 | #define __NR_delete_module 129 | ||
137 | #define __NR_get_kernel_syms 130 | ||
138 | #define __NR_quotactl 131 | ||
139 | #define __NR_getpgid 132 | ||
140 | #define __NR_fchdir 133 | ||
141 | #define __NR_bdflush 134 | ||
142 | #define __NR_sysfs 135 | ||
143 | #define __NR_personality 136 | ||
144 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
145 | #define __NR_setfsuid 138 | ||
146 | #define __NR_setfsgid 139 | ||
147 | #define __NR__llseek 140 | ||
148 | #define __NR_getdents 141 | ||
149 | #define __NR__newselect 142 | ||
150 | #define __NR_flock 143 | ||
151 | #define __NR_msync 144 | ||
152 | #define __NR_readv 145 | ||
153 | #define __NR_writev 146 | ||
154 | #define __NR_getsid 147 | ||
155 | #define __NR_fdatasync 148 | ||
156 | #define __NR__sysctl 149 | ||
157 | #define __NR_mlock 150 | ||
158 | #define __NR_munlock 151 | ||
159 | #define __NR_mlockall 152 | ||
160 | #define __NR_munlockall 153 | ||
161 | #define __NR_sched_setparam 154 | ||
162 | #define __NR_sched_getparam 155 | ||
163 | #define __NR_sched_setscheduler 156 | ||
164 | #define __NR_sched_getscheduler 157 | ||
165 | #define __NR_sched_yield 158 | ||
166 | #define __NR_sched_get_priority_max 159 | ||
167 | #define __NR_sched_get_priority_min 160 | ||
168 | #define __NR_sched_rr_get_interval 161 | ||
169 | #define __NR_nanosleep 162 | ||
170 | #define __NR_mremap 163 | ||
171 | #define __NR_setresuid 164 | ||
172 | #define __NR_getresuid 165 | ||
173 | #define __NR_query_module 166 | ||
174 | #define __NR_poll 167 | ||
175 | #define __NR_nfsservctl 168 | ||
176 | #define __NR_setresgid 169 | ||
177 | #define __NR_getresgid 170 | ||
178 | #define __NR_prctl 171 | ||
179 | #define __NR_rt_sigreturn 172 | ||
180 | #define __NR_rt_sigaction 173 | ||
181 | #define __NR_rt_sigprocmask 174 | ||
182 | #define __NR_rt_sigpending 175 | ||
183 | #define __NR_rt_sigtimedwait 176 | ||
184 | #define __NR_rt_sigqueueinfo 177 | ||
185 | #define __NR_rt_sigsuspend 178 | ||
186 | #define __NR_pread64 179 | ||
187 | #define __NR_pwrite64 180 | ||
188 | #define __NR_chown 181 | ||
189 | #define __NR_getcwd 182 | ||
190 | #define __NR_capget 183 | ||
191 | #define __NR_capset 184 | ||
192 | #define __NR_sigaltstack 185 | ||
193 | #define __NR_sendfile 186 | ||
194 | #define __NR_getpmsg 187 /* some people actually want streams */ | ||
195 | #define __NR_putpmsg 188 /* some people actually want streams */ | ||
196 | #define __NR_vfork 189 | ||
197 | #define __NR_ugetrlimit 190 /* SuS compliant getrlimit */ | ||
198 | #define __NR_readahead 191 | ||
199 | #define __NR_mmap2 192 | ||
200 | #define __NR_truncate64 193 | ||
201 | #define __NR_ftruncate64 194 | ||
202 | #define __NR_stat64 195 | ||
203 | #define __NR_lstat64 196 | ||
204 | #define __NR_fstat64 197 | ||
205 | #define __NR_pciconfig_read 198 | ||
206 | #define __NR_pciconfig_write 199 | ||
207 | #define __NR_pciconfig_iobase 200 | ||
208 | #define __NR_multiplexer 201 | ||
209 | #define __NR_getdents64 202 | ||
210 | #define __NR_pivot_root 203 | ||
211 | #define __NR_fcntl64 204 | ||
212 | #define __NR_madvise 205 | ||
213 | #define __NR_mincore 206 | ||
214 | #define __NR_gettid 207 | ||
215 | #define __NR_tkill 208 | ||
216 | #define __NR_setxattr 209 | ||
217 | #define __NR_lsetxattr 210 | ||
218 | #define __NR_fsetxattr 211 | ||
219 | #define __NR_getxattr 212 | ||
220 | #define __NR_lgetxattr 213 | ||
221 | #define __NR_fgetxattr 214 | ||
222 | #define __NR_listxattr 215 | ||
223 | #define __NR_llistxattr 216 | ||
224 | #define __NR_flistxattr 217 | ||
225 | #define __NR_removexattr 218 | ||
226 | #define __NR_lremovexattr 219 | ||
227 | #define __NR_fremovexattr 220 | ||
228 | #define __NR_futex 221 | ||
229 | #define __NR_sched_setaffinity 222 | ||
230 | #define __NR_sched_getaffinity 223 | ||
231 | /* 224 currently unused */ | ||
232 | #define __NR_tuxcall 225 | ||
233 | #define __NR_sendfile64 226 | ||
234 | #define __NR_io_setup 227 | ||
235 | #define __NR_io_destroy 228 | ||
236 | #define __NR_io_getevents 229 | ||
237 | #define __NR_io_submit 230 | ||
238 | #define __NR_io_cancel 231 | ||
239 | #define __NR_set_tid_address 232 | ||
240 | #define __NR_fadvise64 233 | ||
241 | #define __NR_exit_group 234 | ||
242 | #define __NR_lookup_dcookie 235 | ||
243 | #define __NR_epoll_create 236 | ||
244 | #define __NR_epoll_ctl 237 | ||
245 | #define __NR_epoll_wait 238 | ||
246 | #define __NR_remap_file_pages 239 | ||
247 | #define __NR_timer_create 240 | ||
248 | #define __NR_timer_settime 241 | ||
249 | #define __NR_timer_gettime 242 | ||
250 | #define __NR_timer_getoverrun 243 | ||
251 | #define __NR_timer_delete 244 | ||
252 | #define __NR_clock_settime 245 | ||
253 | #define __NR_clock_gettime 246 | ||
254 | #define __NR_clock_getres 247 | ||
255 | #define __NR_clock_nanosleep 248 | ||
256 | #define __NR_swapcontext 249 | ||
257 | #define __NR_tgkill 250 | ||
258 | #define __NR_utimes 251 | ||
259 | #define __NR_statfs64 252 | ||
260 | #define __NR_fstatfs64 253 | ||
261 | #define __NR_fadvise64_64 254 | ||
262 | #define __NR_rtas 255 | ||
263 | #define __NR_sys_debug_setcontext 256 | ||
264 | /* Number 257 is reserved for vserver */ | ||
265 | /* Number 258 is reserved for new sys_remap_file_pages */ | ||
266 | /* Number 259 is reserved for new sys_mbind */ | ||
267 | /* Number 260 is reserved for new sys_get_mempolicy */ | ||
268 | /* Number 261 is reserved for new sys_set_mempolicy */ | ||
269 | #define __NR_mq_open 262 | ||
270 | #define __NR_mq_unlink 263 | ||
271 | #define __NR_mq_timedsend 264 | ||
272 | #define __NR_mq_timedreceive 265 | ||
273 | #define __NR_mq_notify 266 | ||
274 | #define __NR_mq_getsetattr 267 | ||
275 | #define __NR_kexec_load 268 | ||
276 | #define __NR_add_key 269 | ||
277 | #define __NR_request_key 270 | ||
278 | #define __NR_keyctl 271 | ||
279 | #define __NR_waitid 272 | ||
280 | |||
281 | #define __NR_syscalls 273 | ||
282 | |||
283 | #define __NR(n) #n | ||
284 | |||
285 | /* On powerpc a system call basically clobbers the same registers like a | ||
286 | * function call, with the exception of LR (which is needed for the | ||
287 | * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal | ||
288 | * an error return status). | ||
289 | */ | ||
290 | |||
291 | #define __syscall_nr(nr, type, name, args...) \ | ||
292 | unsigned long __sc_ret, __sc_err; \ | ||
293 | { \ | ||
294 | register unsigned long __sc_0 __asm__ ("r0"); \ | ||
295 | register unsigned long __sc_3 __asm__ ("r3"); \ | ||
296 | register unsigned long __sc_4 __asm__ ("r4"); \ | ||
297 | register unsigned long __sc_5 __asm__ ("r5"); \ | ||
298 | register unsigned long __sc_6 __asm__ ("r6"); \ | ||
299 | register unsigned long __sc_7 __asm__ ("r7"); \ | ||
300 | register unsigned long __sc_8 __asm__ ("r8"); \ | ||
301 | \ | ||
302 | __sc_loadargs_##nr(name, args); \ | ||
303 | __asm__ __volatile__ \ | ||
304 | ("sc \n\t" \ | ||
305 | "mfcr %0 " \ | ||
306 | : "=&r" (__sc_0), \ | ||
307 | "=&r" (__sc_3), "=&r" (__sc_4), \ | ||
308 | "=&r" (__sc_5), "=&r" (__sc_6), \ | ||
309 | "=&r" (__sc_7), "=&r" (__sc_8) \ | ||
310 | : __sc_asm_input_##nr \ | ||
311 | : "cr0", "ctr", "memory", \ | ||
312 | "r9", "r10","r11", "r12"); \ | ||
313 | __sc_ret = __sc_3; \ | ||
314 | __sc_err = __sc_0; \ | ||
315 | } \ | ||
316 | if (__sc_err & 0x10000000) \ | ||
317 | { \ | ||
318 | errno = __sc_ret; \ | ||
319 | __sc_ret = -1; \ | ||
320 | } \ | ||
321 | return (type) __sc_ret | ||
322 | |||
323 | #define __sc_loadargs_0(name, dummy...) \ | ||
324 | __sc_0 = __NR_##name | ||
325 | #define __sc_loadargs_1(name, arg1) \ | ||
326 | __sc_loadargs_0(name); \ | ||
327 | __sc_3 = (unsigned long) (arg1) | ||
328 | #define __sc_loadargs_2(name, arg1, arg2) \ | ||
329 | __sc_loadargs_1(name, arg1); \ | ||
330 | __sc_4 = (unsigned long) (arg2) | ||
331 | #define __sc_loadargs_3(name, arg1, arg2, arg3) \ | ||
332 | __sc_loadargs_2(name, arg1, arg2); \ | ||
333 | __sc_5 = (unsigned long) (arg3) | ||
334 | #define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \ | ||
335 | __sc_loadargs_3(name, arg1, arg2, arg3); \ | ||
336 | __sc_6 = (unsigned long) (arg4) | ||
337 | #define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \ | ||
338 | __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \ | ||
339 | __sc_7 = (unsigned long) (arg5) | ||
340 | #define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6) \ | ||
341 | __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5); \ | ||
342 | __sc_8 = (unsigned long) (arg6) | ||
343 | |||
344 | #define __sc_asm_input_0 "0" (__sc_0) | ||
345 | #define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3) | ||
346 | #define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4) | ||
347 | #define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5) | ||
348 | #define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6) | ||
349 | #define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7) | ||
350 | #define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8) | ||
351 | |||
352 | #define _syscall0(type,name) \ | ||
353 | type name(void) \ | ||
354 | { \ | ||
355 | __syscall_nr(0, type, name); \ | ||
356 | } | ||
357 | |||
358 | #define _syscall1(type,name,type1,arg1) \ | ||
359 | type name(type1 arg1) \ | ||
360 | { \ | ||
361 | __syscall_nr(1, type, name, arg1); \ | ||
362 | } | ||
363 | |||
364 | #define _syscall2(type,name,type1,arg1,type2,arg2) \ | ||
365 | type name(type1 arg1, type2 arg2) \ | ||
366 | { \ | ||
367 | __syscall_nr(2, type, name, arg1, arg2); \ | ||
368 | } | ||
369 | |||
370 | #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ | ||
371 | type name(type1 arg1, type2 arg2, type3 arg3) \ | ||
372 | { \ | ||
373 | __syscall_nr(3, type, name, arg1, arg2, arg3); \ | ||
374 | } | ||
375 | |||
376 | #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
377 | type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
378 | { \ | ||
379 | __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \ | ||
380 | } | ||
381 | |||
382 | #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ | ||
383 | type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ | ||
384 | { \ | ||
385 | __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \ | ||
386 | } | ||
387 | |||
388 | #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \ | ||
389 | type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \ | ||
390 | { \ | ||
391 | __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6); \ | ||
392 | } | ||
393 | |||
394 | #ifdef __KERNEL__ | ||
395 | |||
396 | #define __NR__exit __NR_exit | ||
397 | #define NR_syscalls __NR_syscalls | ||
398 | |||
399 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
400 | #define __ARCH_WANT_OLD_READDIR | ||
401 | #define __ARCH_WANT_OLD_STAT | ||
402 | #define __ARCH_WANT_STAT64 | ||
403 | #define __ARCH_WANT_SYS_ALARM | ||
404 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
405 | #define __ARCH_WANT_SYS_PAUSE | ||
406 | #define __ARCH_WANT_SYS_SGETMASK | ||
407 | #define __ARCH_WANT_SYS_SIGNAL | ||
408 | #define __ARCH_WANT_SYS_TIME | ||
409 | #define __ARCH_WANT_SYS_UTIME | ||
410 | #define __ARCH_WANT_SYS_WAITPID | ||
411 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
412 | #define __ARCH_WANT_SYS_FADVISE64 | ||
413 | #define __ARCH_WANT_SYS_GETPGRP | ||
414 | #define __ARCH_WANT_SYS_LLSEEK | ||
415 | #define __ARCH_WANT_SYS_NICE | ||
416 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
417 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
418 | #define __ARCH_WANT_SYS_SIGPENDING | ||
419 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
420 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
421 | |||
422 | /* | ||
423 | * Forking from kernel space will result in the child getting a new, | ||
424 | * empty kernel stack area. Thus the child cannot access automatic | ||
425 | * variables set in the parent unless they are in registers, and the | ||
426 | * procedure where the fork was done cannot return to its caller in | ||
427 | * the child. | ||
428 | */ | ||
429 | |||
430 | #ifdef __KERNEL_SYSCALLS__ | ||
431 | |||
432 | #include <linux/compiler.h> | ||
433 | #include <linux/types.h> | ||
434 | |||
435 | /* | ||
436 | * System call prototypes. | ||
437 | */ | ||
438 | extern pid_t setsid(void); | ||
439 | extern int write(int fd, const char *buf, off_t count); | ||
440 | extern int read(int fd, char *buf, off_t count); | ||
441 | extern off_t lseek(int fd, off_t offset, int count); | ||
442 | extern int dup(int fd); | ||
443 | extern int execve(const char *file, char **argv, char **envp); | ||
444 | extern int open(const char *file, int flag, int mode); | ||
445 | extern int close(int fd); | ||
446 | extern pid_t waitpid(pid_t pid, int *wait_stat, int options); | ||
447 | |||
448 | unsigned long sys_mmap(unsigned long addr, size_t len, | ||
449 | unsigned long prot, unsigned long flags, | ||
450 | unsigned long fd, off_t offset); | ||
451 | unsigned long sys_mmap2(unsigned long addr, size_t len, | ||
452 | unsigned long prot, unsigned long flags, | ||
453 | unsigned long fd, unsigned long pgoff); | ||
454 | struct pt_regs; | ||
455 | int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2, | ||
456 | unsigned long a3, unsigned long a4, unsigned long a5, | ||
457 | struct pt_regs *regs); | ||
458 | int sys_clone(unsigned long clone_flags, unsigned long usp, | ||
459 | int __user *parent_tidp, void __user *child_threadptr, | ||
460 | int __user *child_tidp, int p6, | ||
461 | struct pt_regs *regs); | ||
462 | int sys_fork(int p1, int p2, int p3, int p4, int p5, int p6, | ||
463 | struct pt_regs *regs); | ||
464 | int sys_vfork(int p1, int p2, int p3, int p4, int p5, int p6, | ||
465 | struct pt_regs *regs); | ||
466 | int sys_pipe(int __user *fildes); | ||
467 | int sys_ptrace(long request, long pid, long addr, long data); | ||
468 | struct sigaction; | ||
469 | long sys_rt_sigaction(int sig, | ||
470 | const struct sigaction __user *act, | ||
471 | struct sigaction __user *oact, | ||
472 | size_t sigsetsize); | ||
473 | |||
474 | #endif /* __KERNEL_SYSCALLS__ */ | ||
475 | |||
476 | /* | ||
477 | * "Conditional" syscalls | ||
478 | * | ||
479 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
480 | * but it doesn't work on all toolchains, so we just do it by hand | ||
481 | */ | ||
482 | #ifndef cond_syscall | ||
483 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
484 | #endif | ||
485 | |||
486 | #endif /* __KERNEL__ */ | ||
487 | |||
488 | #endif /* _ASM_PPC_UNISTD_H_ */ | ||
diff --git a/include/asm-ppc/user.h b/include/asm-ppc/user.h new file mode 100644 index 000000000000..d662b2151370 --- /dev/null +++ b/include/asm-ppc/user.h | |||
@@ -0,0 +1,54 @@ | |||
1 | #ifdef __KERNEL__ | ||
2 | #ifndef _PPC_USER_H | ||
3 | #define _PPC_USER_H | ||
4 | |||
5 | /* Adapted from <asm-alpha/user.h> */ | ||
6 | |||
7 | #include <linux/ptrace.h> | ||
8 | #include <asm/page.h> | ||
9 | |||
10 | /* | ||
11 | * Core file format: The core file is written in such a way that gdb | ||
12 | * can understand it and provide useful information to the user (under | ||
13 | * linux we use the `trad-core' bfd, NOT the osf-core). The file contents | ||
14 | * are as follows: | ||
15 | * | ||
16 | * upage: 1 page consisting of a user struct that tells gdb | ||
17 | * what is present in the file. Directly after this is a | ||
18 | * copy of the task_struct, which is currently not used by gdb, | ||
19 | * but it may come in handy at some point. All of the registers | ||
20 | * are stored as part of the upage. The upage should always be | ||
21 | * only one page long. | ||
22 | * data: The data segment follows next. We use current->end_text to | ||
23 | * current->brk to pick up all of the user variables, plus any memory | ||
24 | * that may have been sbrk'ed. No attempt is made to determine if a | ||
25 | * page is demand-zero or if a page is totally unused, we just cover | ||
26 | * the entire range. All of the addresses are rounded in such a way | ||
27 | * that an integral number of pages is written. | ||
28 | * stack: We need the stack information in order to get a meaningful | ||
29 | * backtrace. We need to write the data from usp to | ||
30 | * current->start_stack, so we round each of these in order to be able | ||
31 | * to write an integer number of pages. | ||
32 | */ | ||
33 | struct user { | ||
34 | struct pt_regs regs; /* entire machine state */ | ||
35 | size_t u_tsize; /* text size (pages) */ | ||
36 | size_t u_dsize; /* data size (pages) */ | ||
37 | size_t u_ssize; /* stack size (pages) */ | ||
38 | unsigned long start_code; /* text starting address */ | ||
39 | unsigned long start_data; /* data starting address */ | ||
40 | unsigned long start_stack; /* stack starting address */ | ||
41 | long int signal; /* signal causing core dump */ | ||
42 | struct regs * u_ar0; /* help gdb find registers */ | ||
43 | unsigned long magic; /* identifies a core file */ | ||
44 | char u_comm[32]; /* user command name */ | ||
45 | }; | ||
46 | |||
47 | #define NBPG PAGE_SIZE | ||
48 | #define UPAGES 1 | ||
49 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
50 | #define HOST_DATA_START_ADDR (u.start_data) | ||
51 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
52 | |||
53 | #endif /* _PPC_USER_H */ | ||
54 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h new file mode 100644 index 000000000000..c5864734e3e1 --- /dev/null +++ b/include/asm-ppc/vga.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * Access to VGA videoram | ||
3 | * | ||
4 | * (c) 1998 Martin Mares <mj@ucw.cz> | ||
5 | */ | ||
6 | |||
7 | #ifdef __KERNEL__ | ||
8 | #ifndef _LINUX_ASM_VGA_H_ | ||
9 | #define _LINUX_ASM_VGA_H_ | ||
10 | |||
11 | #include <asm/io.h> | ||
12 | |||
13 | #include <linux/config.h> | ||
14 | |||
15 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE) | ||
16 | |||
17 | #define VT_BUF_HAVE_RW | ||
18 | /* | ||
19 | * These are only needed for supporting VGA or MDA text mode, which use little | ||
20 | * endian byte ordering. | ||
21 | * In other cases, we can optimize by using native byte ordering and | ||
22 | * <linux/vt_buffer.h> has already done the right job for us. | ||
23 | */ | ||
24 | |||
25 | extern inline void scr_writew(u16 val, volatile u16 *addr) | ||
26 | { | ||
27 | st_le16(addr, val); | ||
28 | } | ||
29 | |||
30 | extern inline u16 scr_readw(volatile const u16 *addr) | ||
31 | { | ||
32 | return ld_le16(addr); | ||
33 | } | ||
34 | |||
35 | #define VT_BUF_HAVE_MEMCPYW | ||
36 | #define scr_memcpyw memcpy | ||
37 | |||
38 | #endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */ | ||
39 | |||
40 | extern unsigned long vgacon_remap_base; | ||
41 | #define VGA_MAP_MEM(x) (x + vgacon_remap_base) | ||
42 | #define vga_readb(x) (*(x)) | ||
43 | #define vga_writeb(x,y) (*(y) = (x)) | ||
44 | |||
45 | #endif | ||
46 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/xmon.h b/include/asm-ppc/xmon.h new file mode 100644 index 000000000000..042b83e6680d --- /dev/null +++ b/include/asm-ppc/xmon.h | |||
@@ -0,0 +1,17 @@ | |||
1 | #ifndef __PPC_XMON_H | ||
2 | #define __PPC_XMON_H | ||
3 | #ifdef __KERNEL__ | ||
4 | |||
5 | struct pt_regs; | ||
6 | |||
7 | extern void xmon(struct pt_regs *excp); | ||
8 | extern void xmon_printf(const char *fmt, ...); | ||
9 | extern void xmon_map_scc(void); | ||
10 | extern int xmon_bpt(struct pt_regs *regs); | ||
11 | extern int xmon_sstep(struct pt_regs *regs); | ||
12 | extern int xmon_iabr_match(struct pt_regs *regs); | ||
13 | extern int xmon_dabr_match(struct pt_regs *regs); | ||
14 | extern void (*xmon_fault_handler)(struct pt_regs *regs); | ||
15 | |||
16 | #endif | ||
17 | #endif | ||
diff --git a/include/asm-ppc/xor.h b/include/asm-ppc/xor.h new file mode 100644 index 000000000000..c82eb12a5b18 --- /dev/null +++ b/include/asm-ppc/xor.h | |||
@@ -0,0 +1 @@ | |||
#include <asm-generic/xor.h> | |||
diff --git a/include/asm-ppc/xparameters.h b/include/asm-ppc/xparameters.h new file mode 100644 index 000000000000..fe4eac629139 --- /dev/null +++ b/include/asm-ppc/xparameters.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/xparameters.h | ||
3 | * | ||
4 | * This file includes the correct xparameters.h for the CONFIG'ed board | ||
5 | * | ||
6 | * Author: MontaVista Software, Inc. | ||
7 | * source@mvista.com | ||
8 | * | ||
9 | * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms | ||
10 | * of the GNU General Public License version 2. This program is licensed | ||
11 | * "as is" without any warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <linux/config.h> | ||
15 | |||
16 | #if defined(CONFIG_XILINX_ML300) | ||
17 | #include <platforms/4xx/xparameters/xparameters_ml300.h> | ||
18 | #endif | ||
diff --git a/include/asm-ppc/zorro.h b/include/asm-ppc/zorro.h new file mode 100644 index 000000000000..1e5fbc65e77b --- /dev/null +++ b/include/asm-ppc/zorro.h | |||
@@ -0,0 +1,30 @@ | |||
1 | #ifndef _ASM_PPC_ZORRO_H | ||
2 | #define _ASM_PPC_ZORRO_H | ||
3 | |||
4 | #include <asm/io.h> | ||
5 | |||
6 | #define z_readb in_8 | ||
7 | #define z_readw in_be16 | ||
8 | #define z_readl in_be32 | ||
9 | |||
10 | #define z_writeb(val, port) out_8((port), (val)) | ||
11 | #define z_writew(val, port) out_be16((port), (val)) | ||
12 | #define z_writel(val, port) out_be32((port), (val)) | ||
13 | |||
14 | #define z_memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
15 | #define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
16 | #define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
17 | |||
18 | extern void *__ioremap(unsigned long address, unsigned long size, | ||
19 | unsigned long flags); | ||
20 | |||
21 | extern void *ioremap(unsigned long address, unsigned long size); | ||
22 | extern void iounmap(void *addr); | ||
23 | |||
24 | extern void *__ioremap(unsigned long address, unsigned long size, | ||
25 | unsigned long flags); | ||
26 | |||
27 | #define z_ioremap ioremap | ||
28 | #define z_iounmap iounmap | ||
29 | |||
30 | #endif /* _ASM_PPC_ZORRO_H */ | ||