aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ppc
diff options
context:
space:
mode:
authorVitaly Bordug <vbordug@ru.mvista.com>2005-05-28 18:52:09 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-05-28 19:46:15 -0400
commita6dbba77a9d4b47c60d60c4f07fa79b3ca93a1d5 (patch)
tree3eb846b21a4353b1c17edeebc9db4bdd586c2ea3 /include/asm-ppc
parented36959621451da7195be83b87878b060ce64724 (diff)
[PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge
This patch adds on-chip PCI bridge support for the PQ2 family. The incomplete existent code is updated with interrupt handling stuff and board-specific bits for 8272ADS and PQ2FADS; the related files were renamed (from m8260_pci to m82xx_pci) to be of more generic fashion. This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/cpm2.h46
-rw-r--r--include/asm-ppc/m8260_pci.h1
-rw-r--r--include/asm-ppc/mpc8260.h2
3 files changed, 48 insertions, 1 deletions
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 42fd1068cf2a..c5883dbed63f 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1039,6 +1039,52 @@ typedef struct im_idma {
1039#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 1039#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1040#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 1040#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1041 1041
1042/*-----------------------------------------------------------------------
1043 * SIUMCR - SIU Module Configuration Register 4-31
1044 */
1045#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1046#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1047#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1048#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1049#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1050#define SIUMCR_DPPC01 0x04000000 /* - " - */
1051#define SIUMCR_DPPC10 0x08000000 /* - " - */
1052#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1053#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1054#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1055#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1056#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1057#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1058#define SIUMCR_LBPC01 0x00400000 /* - " - */
1059#define SIUMCR_LBPC10 0x00800000 /* - " - */
1060#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1061#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1062#define SIUMCR_APPC01 0x00100000 /* - " - */
1063#define SIUMCR_APPC10 0x00200000 /* - " - */
1064#define SIUMCR_APPC11 0x00300000 /* - " - */
1065#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1066#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1067#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1068#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1069#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1070#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1071#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1072#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1073#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1074#define SIUMCR_MMR01 0x00004000 /* - " - */
1075#define SIUMCR_MMR10 0x00008000 /* - " - */
1076#define SIUMCR_MMR11 0x0000c000 /* - " - */
1077#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1078
1079/*-----------------------------------------------------------------------
1080 * SCCR - System Clock Control Register 9-8
1081*/
1082#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1083#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1084#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1085#define SCCR_PCIDF_SHIFT 3
1086
1087
1042#endif /* __CPM2__ */ 1088#endif /* __CPM2__ */
1043#endif /* __KERNEL__ */ 1089#endif /* __KERNEL__ */
1044 1090
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
index 163a6b91d5b2..bf9e05dd54b5 100644
--- a/include/asm-ppc/m8260_pci.h
+++ b/include/asm-ppc/m8260_pci.h
@@ -19,6 +19,7 @@
19 * Define the vendor/device ID for the MPC8265. 19 * Define the vendor/device ID for the MPC8265.
20 */ 20 */
21#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) 21#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
22#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
22 23
23#define M8265_PCIBR0 0x101ac 24#define M8265_PCIBR0 0x101ac
24#define M8265_PCIBR1 0x101b0 25#define M8265_PCIBR1 0x101b0
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index d820894e5991..89eb8a2ac693 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -41,7 +41,7 @@
41#endif 41#endif
42 42
43#ifdef CONFIG_PCI_8260 43#ifdef CONFIG_PCI_8260
44#include <syslib/m8260_pci.h> 44#include <syslib/m82xx_pci.h>
45#endif 45#endif
46 46
47/* Make sure the memory translation stuff is there if PCI not used. 47/* Make sure the memory translation stuff is there if PCI not used.