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authorStephen Rothwell <sfr@canb.auug.org.au>2005-06-21 20:15:34 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-06-21 21:46:27 -0400
commitfcee38952609fccb2bdfe166b3b96bd75a292aa6 (patch)
tree8abe11ef9b03ba56ea0882433b7439d7bd576fff /include/asm-ppc64/iSeries/ItLpQueue.h
parent45dc76aaf63fc336527da80337d3e3684f50f387 (diff)
[PATCH] ppc64 iSeries: more header file white space cleanups
This patch just contains white space and comment cleanups in the iSeries headers files. There are no semantic changes. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc64/iSeries/ItLpQueue.h')
-rw-r--r--include/asm-ppc64/iSeries/ItLpQueue.h74
1 files changed, 37 insertions, 37 deletions
diff --git a/include/asm-ppc64/iSeries/ItLpQueue.h b/include/asm-ppc64/iSeries/ItLpQueue.h
index 4f4dde2a638d..b2bdef429591 100644
--- a/include/asm-ppc64/iSeries/ItLpQueue.h
+++ b/include/asm-ppc64/iSeries/ItLpQueue.h
@@ -1,17 +1,17 @@
1/* 1/*
2 * ItLpQueue.h 2 * ItLpQueue.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation 3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or 7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version. 8 * (at your option) any later version.
9 * 9 *
10 * This program is distributed in the hope that it will be useful, 10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 * You should have received a copy of the GNU General Public License 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
@@ -19,47 +19,47 @@
19#ifndef _ITLPQUEUE_H 19#ifndef _ITLPQUEUE_H
20#define _ITLPQUEUE_H 20#define _ITLPQUEUE_H
21 21
22//============================================================================= 22/*
23// 23 * This control block defines the simple LP queue structure that is
24// This control block defines the simple LP queue structure that is 24 * shared between the hypervisor (PLIC) and the OS in order to send
25// shared between the hypervisor (PLIC) and the OS in order to send 25 * events to an LP.
26// events to an LP. 26 */
27//
28 27
29#include <asm/types.h> 28#include <asm/types.h>
30#include <asm/ptrace.h> 29#include <asm/ptrace.h>
31 30
32struct HvLpEvent; 31struct HvLpEvent;
33 32
34#define ITMaxLpQueues 8 33#define ITMaxLpQueues 8
35 34
36#define NotUsed 0 // Queue will not be used by PLIC 35#define NotUsed 0 // Queue will not be used by PLIC
37#define DedicatedIo 1 // Queue dedicated to IO processor specified 36#define DedicatedIo 1 // Queue dedicated to IO processor specified
38#define DedicatedLp 2 // Queue dedicated to LP specified 37#define DedicatedLp 2 // Queue dedicated to LP specified
39#define Shared 3 // Queue shared for both IO and LP 38#define Shared 3 // Queue shared for both IO and LP
40 39
41#define LpEventStackSize 4096 40#define LpEventStackSize 4096
42#define LpEventMaxSize 256 41#define LpEventMaxSize 256
43#define LpEventAlign 64 42#define LpEventAlign 64
44 43
45struct ItLpQueue 44struct ItLpQueue {
46{ 45/*
47// 46 * The xSlicCurEventPtr is the pointer to the next event stack entry
48// The xSlicCurEventPtr is the pointer to the next event stack entry that will 47 * that will become valid. The OS must peek at this entry to determine
49// become valid. The OS must peek at this entry to determine if it is valid. 48 * if it is valid. PLIC will set the valid indicator as the very last
50// PLIC will set the valid indicator as the very last store into that entry. 49 * store into that entry.
51// 50 *
52// When the OS has completed processing of the event then it will mark the event 51 * When the OS has completed processing of the event then it will mark
53// as invalid so that PLIC knows it can store into that event location again. 52 * the event as invalid so that PLIC knows it can store into that event
54// 53 * location again.
55// If the event stack fills and there are overflow events, then PLIC will set 54 *
56// the xPlicOverflowIntPending flag in which case the OS will have to fetch the 55 * If the event stack fills and there are overflow events, then PLIC
57// additional LP events once they have drained the event stack. 56 * will set the xPlicOverflowIntPending flag in which case the OS will
58// 57 * have to fetch the additional LP events once they have drained the
59// The first 16-bytes are known by both the OS and PLIC. The remainder of the 58 * event stack.
60// cache line is for use by the OS. 59 *
61// 60 * The first 16-bytes are known by both the OS and PLIC. The remainder
62//============================================================================= 61 * of the cache line is for use by the OS.
62 */
63 u8 xPlicOverflowIntPending;// 0x00 Overflow events are pending 63 u8 xPlicOverflowIntPending;// 0x00 Overflow events are pending
64 u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed 64 u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed
65 u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation 65 u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation
@@ -76,17 +76,17 @@ struct ItLpQueue
76 76
77extern struct ItLpQueue xItLpQueue; 77extern struct ItLpQueue xItLpQueue;
78 78
79extern struct HvLpEvent * ItLpQueue_getNextLpEvent( struct ItLpQueue * ); 79extern struct HvLpEvent * ItLpQueue_getNextLpEvent(struct ItLpQueue *);
80extern int ItLpQueue_isLpIntPending( struct ItLpQueue * ); 80extern int ItLpQueue_isLpIntPending(struct ItLpQueue *);
81extern unsigned ItLpQueue_process( struct ItLpQueue *, struct pt_regs * ); 81extern unsigned ItLpQueue_process(struct ItLpQueue *, struct pt_regs *);
82extern void ItLpQueue_clearValid( struct HvLpEvent * ); 82extern void ItLpQueue_clearValid(struct HvLpEvent *);
83 83
84static __inline__ void process_iSeries_events( void ) 84static __inline__ void process_iSeries_events(void)
85{ 85{
86 __asm__ __volatile__ ( 86 __asm__ __volatile__ (
87 " li 0,0x5555 \n\ 87 " li 0,0x5555 \n\
88 sc" 88 sc"
89 : : : "r0", "r3" ); 89 : : : "r0", "r3");
90} 90}
91 91
92#endif /* _ITLPQUEUE_H */ 92#endif /* _ITLPQUEUE_H */