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authorKumar Gala <galak@freescale.com>2005-04-16 18:24:22 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:24:22 -0400
commitf50b153b1966230e78034d5ab1641ca4bb5db56d (patch)
tree9f3f0971789ca2cbb59efbd694c172804f4547cd /include/asm-ppc/reg_booke.h
parentb464fce5edc08a825907e9d48a2d2f1af0393fef (diff)
[PATCH] ppc32: Support 36-bit physical addressing on e500
To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc/reg_booke.h')
-rw-r--r--include/asm-ppc/reg_booke.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 4b03f8e26b72..e70c25f3c339 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -172,6 +172,7 @@ do { \
172#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 172#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
173#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 173#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
174#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 174#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
175#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
175#define SPRN_PID1 0x279 /* Process ID Register 1 */ 176#define SPRN_PID1 0x279 /* Process ID Register 1 */
176#define SPRN_PID2 0x27A /* Process ID Register 2 */ 177#define SPRN_PID2 0x27A /* Process ID Register 2 */
177#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 178#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */