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authorEugene Surovegin <ebs@ebshome.net>2006-04-25 04:22:44 -0400
committerPaul Mackerras <paulus@samba.org>2006-04-28 07:04:56 -0400
commit30aacebed0f0619f23ce84df7c59ad033ca08d77 (patch)
treefb32292e6804fdab515227a0b7d9722e9595d532 /include/asm-ppc/reg_booke.h
parent1269277a5e7c6d7ae1852e648a8bcdb78035e9fa (diff)
[PATCH] ppc32: add 440GX erratum 440_43 workaround
This patch adds workaround for PPC 440GX erratum 440_43. According to this erratum spurious MachineChecks (caused by L1 cache parity) can happen during DataTLB miss processing. We disable L1 cache parity checking for 440GX rev.C and rev.F Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-ppc/reg_booke.h')
-rw-r--r--include/asm-ppc/reg_booke.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 00ad9c754c78..4944c0fb8bea 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -237,6 +237,7 @@ do { \
237#endif 237#endif
238 238
239/* Bit definitions for CCR1. */ 239/* Bit definitions for CCR1. */
240#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
240#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 241#define CCR1_TCS 0x00000080 /* Timer Clock Select */
241 242
242/* Bit definitions for the MCSR. */ 243/* Bit definitions for the MCSR. */