[PPC] Remove 85xx from arch/ppc

85xx exists in arch/powerpc as well as cuImage support to boot from
a u-boot that doesn't support device trees.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 0 insertions, 26 deletions

diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 2f1a2afcfc28..91e96af88bd8 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -218,32 +218,6 @@
 #define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
 #define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
 #endif
-#ifdef CONFIG_E500
-#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
-#define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
-#define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
-#define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI      0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
-#define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
-#define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
-#define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
-#define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
-#define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
-#define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
-#define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
-#define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
-#endif
-#ifdef CONFIG_E200
-#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
-#define MCSR_CP_PERR    0x20000000UL /* Cache Push Parity Error */
-#define MCSR_CPERR      0x10000000UL /* Cache Parity Error */
-#define MCSR_EXCP_ERR   0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
-                                        fetch for an exception handler */
-#define MCSR_BUS_IRERR  0x00000010UL /* Read Bus Error on instruction fetch*/
-#define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
-#define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
-                                        store or cache line push */
-#endif
 
 /* Bit definitions for the DBSR. */
 /*