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| author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 14:47:26 -0400 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 14:47:26 -0400 |
| commit | f0cd91a68acdc9b49d7f6738b514a426da627649 (patch) | |
| tree | 8ad73564015794197583b094217ae0a71e71e753 /include/asm-ppc/reg_booke.h | |
| parent | 60eef25701d25e99c991dd0f4a9f3832a0c3ad3e (diff) | |
| parent | 128e6ced247cda88f96fa9f2e4ba8b2c4a681560 (diff) | |
Merge ../linux-2.6
Diffstat (limited to 'include/asm-ppc/reg_booke.h')
| -rw-r--r-- | include/asm-ppc/reg_booke.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index 00ad9c754c78..4944c0fb8bea 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h | |||
| @@ -237,6 +237,7 @@ do { \ | |||
| 237 | #endif | 237 | #endif |
| 238 | 238 | ||
| 239 | /* Bit definitions for CCR1. */ | 239 | /* Bit definitions for CCR1. */ |
| 240 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | ||
| 240 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | 241 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ |
| 241 | 242 | ||
| 242 | /* Bit definitions for the MCSR. */ | 243 | /* Bit definitions for the MCSR. */ |