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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ppc/mv64x60_defs.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-ppc/mv64x60_defs.h')
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diff --git a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
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1/*
2 * include/asm-ppc/gt64260_defs.h
3 *
4 * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
5 * host bridges.
6 *
7 * Author: Mark A. Greer <mgreer@mvista.com>
8 *
9 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#ifndef __ASMPPC_MV64x60_DEFS_H
15#define __ASMPPC_MV64x60_DEFS_H
16
17/*
18 * Define the Marvell bridges that are supported
19 */
20#define MV64x60_TYPE_INVALID 0
21#define MV64x60_TYPE_GT64260A 1
22#define MV64x60_TYPE_GT64260B 2
23#define MV64x60_TYPE_MV64360 3
24#define MV64x60_TYPE_MV64361 4
25#define MV64x60_TYPE_MV64362 5
26#define MV64x60_TYPE_MV64460 6
27
28
29/* Revisions of each supported chip */
30#define GT64260_REV_A 0x10
31#define GT64260_REV_B 0x20
32#define MV64360 0x01
33#define MV64460 0x01
34
35/* Minimum window size supported by 64260 is 1MB */
36#define GT64260_WINDOW_SIZE_MIN 0x00100000
37#define MV64360_WINDOW_SIZE_MIN 0x00010000
38
39#define MV64x60_TCLK_FREQ_MAX 133333333U
40
41/* IRQ's for embedded controllers */
42#define MV64x60_IRQ_DEV 1
43#define MV64x60_IRQ_CPU_ERR 3
44#define MV64x60_IRQ_TIMER_0_1 8
45#define MV64x60_IRQ_TIMER_2_3 9
46#define MV64x60_IRQ_TIMER_4_5 10
47#define MV64x60_IRQ_TIMER_6_7 11
48#define MV64x60_IRQ_P1_GPP_0_7 24
49#define MV64x60_IRQ_P1_GPP_8_15 25
50#define MV64x60_IRQ_P1_GPP_16_23 26
51#define MV64x60_IRQ_P1_GPP_24_31 27
52#define MV64x60_IRQ_DOORBELL 28
53#define MV64x60_IRQ_ETH_0 32
54#define MV64x60_IRQ_ETH_1 33
55#define MV64x60_IRQ_ETH_2 34
56#define MV64x60_IRQ_SDMA_0 36
57#define MV64x60_IRQ_I2C 37
58#define MV64x60_IRQ_BRG 39
59#define MV64x60_IRQ_MPSC_0 40
60#define MV64x60_IRQ_MPSC_1 42
61#define MV64x60_IRQ_COMM 43
62#define MV64x60_IRQ_P0_GPP_0_7 56
63#define MV64x60_IRQ_P0_GPP_8_15 57
64#define MV64x60_IRQ_P0_GPP_16_23 58
65#define MV64x60_IRQ_P0_GPP_24_31 59
66
67#define MV64360_IRQ_PCI0 12
68#define MV64360_IRQ_SRAM_PAR_ERR 13
69#define MV64360_IRQ_PCI1 16
70#define MV64360_IRQ_SDMA_1 38
71
72#define MV64x60_IRQ_GPP0 64
73#define MV64x60_IRQ_GPP1 65
74#define MV64x60_IRQ_GPP2 66
75#define MV64x60_IRQ_GPP3 67
76#define MV64x60_IRQ_GPP4 68
77#define MV64x60_IRQ_GPP5 69
78#define MV64x60_IRQ_GPP6 70
79#define MV64x60_IRQ_GPP7 71
80#define MV64x60_IRQ_GPP8 72
81#define MV64x60_IRQ_GPP9 73
82#define MV64x60_IRQ_GPP10 74
83#define MV64x60_IRQ_GPP11 75
84#define MV64x60_IRQ_GPP12 76
85#define MV64x60_IRQ_GPP13 77
86#define MV64x60_IRQ_GPP14 78
87#define MV64x60_IRQ_GPP15 79
88#define MV64x60_IRQ_GPP16 80
89#define MV64x60_IRQ_GPP17 81
90#define MV64x60_IRQ_GPP18 82
91#define MV64x60_IRQ_GPP19 83
92#define MV64x60_IRQ_GPP20 84
93#define MV64x60_IRQ_GPP21 85
94#define MV64x60_IRQ_GPP22 86
95#define MV64x60_IRQ_GPP23 87
96#define MV64x60_IRQ_GPP24 88
97#define MV64x60_IRQ_GPP25 89
98#define MV64x60_IRQ_GPP26 90
99#define MV64x60_IRQ_GPP27 91
100#define MV64x60_IRQ_GPP28 92
101#define MV64x60_IRQ_GPP29 93
102#define MV64x60_IRQ_GPP30 94
103#define MV64x60_IRQ_GPP31 95
104
105/* Offsets for register blocks */
106#define GT64260_ENET_PHY_ADDR 0x2000
107#define GT64260_ENET_ESMIR 0x2010
108#define GT64260_ENET_0_OFFSET 0x2400
109#define GT64260_ENET_1_OFFSET 0x2800
110#define GT64260_ENET_2_OFFSET 0x2c00
111#define MV64x60_SDMA_0_OFFSET 0x4000
112#define MV64x60_SDMA_1_OFFSET 0x6000
113#define MV64x60_MPSC_0_OFFSET 0x8000
114#define MV64x60_MPSC_1_OFFSET 0x9000
115#define MV64x60_MPSC_ROUTING_OFFSET 0xb400
116#define MV64x60_SDMA_INTR_OFFSET 0xb800
117#define MV64x60_BRG_0_OFFSET 0xb200
118#define MV64x60_BRG_1_OFFSET 0xb208
119
120/*
121 *****************************************************************************
122 *
123 * CPU Interface Registers
124 *
125 *****************************************************************************
126 */
127
128/* CPU physical address of bridge's registers */
129#define MV64x60_INTERNAL_SPACE_DECODE 0x0068
130#define MV64x60_INTERNAL_SPACE_SIZE 0x10000
131#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000
132
133#define MV64360_CPU_BAR_ENABLE 0x0278
134
135/* CPU Memory Controller Window Registers (4 windows) */
136#define MV64x60_CPU2MEM_WINDOWS 4
137
138#define MV64x60_CPU2MEM_0_BASE 0x0008
139#define MV64x60_CPU2MEM_0_SIZE 0x0010
140#define MV64x60_CPU2MEM_1_BASE 0x0208
141#define MV64x60_CPU2MEM_1_SIZE 0x0210
142#define MV64x60_CPU2MEM_2_BASE 0x0018
143#define MV64x60_CPU2MEM_2_SIZE 0x0020
144#define MV64x60_CPU2MEM_3_BASE 0x0218
145#define MV64x60_CPU2MEM_3_SIZE 0x0220
146
147/* CPU Device Controller Window Registers (4 windows) */
148#define MV64x60_CPU2DEV_WINDOWS 4
149
150#define MV64x60_CPU2DEV_0_BASE 0x0028
151#define MV64x60_CPU2DEV_0_SIZE 0x0030
152#define MV64x60_CPU2DEV_1_BASE 0x0228
153#define MV64x60_CPU2DEV_1_SIZE 0x0230
154#define MV64x60_CPU2DEV_2_BASE 0x0248
155#define MV64x60_CPU2DEV_2_SIZE 0x0250
156#define MV64x60_CPU2DEV_3_BASE 0x0038
157#define MV64x60_CPU2DEV_3_SIZE 0x0040
158
159#define MV64x60_CPU2BOOT_0_BASE 0x0238
160#define MV64x60_CPU2BOOT_0_SIZE 0x0240
161
162#define MV64360_CPU2SRAM_BASE 0x0268
163
164/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
165#define MV64x60_PCI_BUSES 2
166#define MV64x60_PCI_IO_WINDOWS_PER_BUS 1
167#define MV64x60_PCI_MEM_WINDOWS_PER_BUS 4
168
169#define MV64x60_CPU2PCI_SWAP_BYTE 0x00000000
170#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
171#define MV64x60_CPU2PCI_SWAP_BYTE_WORD 0x02000000
172#define MV64x60_CPU2PCI_SWAP_WORD 0x03000000
173
174#define MV64x60_CPU2PCI_MEM_REQ64 (1<<27)
175
176#define MV64x60_CPU2PCI0_IO_BASE 0x0048
177#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
178#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
179#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
180#define MV64x60_CPU2PCI0_MEM_1_BASE 0x0080
181#define MV64x60_CPU2PCI0_MEM_1_SIZE 0x0088
182#define MV64x60_CPU2PCI0_MEM_2_BASE 0x0258
183#define MV64x60_CPU2PCI0_MEM_2_SIZE 0x0260
184#define MV64x60_CPU2PCI0_MEM_3_BASE 0x0280
185#define MV64x60_CPU2PCI0_MEM_3_SIZE 0x0288
186
187#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
188#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
189#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
190#define MV64x60_CPU2PCI0_MEM_1_REMAP_LO 0x0100
191#define MV64x60_CPU2PCI0_MEM_1_REMAP_HI 0x0328
192#define MV64x60_CPU2PCI0_MEM_2_REMAP_LO 0x02f8
193#define MV64x60_CPU2PCI0_MEM_2_REMAP_HI 0x0330
194#define MV64x60_CPU2PCI0_MEM_3_REMAP_LO 0x0300
195#define MV64x60_CPU2PCI0_MEM_3_REMAP_HI 0x0338
196
197#define MV64x60_CPU2PCI1_IO_BASE 0x0090
198#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
199#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
200#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
201#define MV64x60_CPU2PCI1_MEM_1_BASE 0x00b0
202#define MV64x60_CPU2PCI1_MEM_1_SIZE 0x00b8
203#define MV64x60_CPU2PCI1_MEM_2_BASE 0x02a0
204#define MV64x60_CPU2PCI1_MEM_2_SIZE 0x02a8
205#define MV64x60_CPU2PCI1_MEM_3_BASE 0x02b0
206#define MV64x60_CPU2PCI1_MEM_3_SIZE 0x02b8
207
208#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
209#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
210#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
211#define MV64x60_CPU2PCI1_MEM_1_REMAP_LO 0x0118
212#define MV64x60_CPU2PCI1_MEM_1_REMAP_HI 0x0348
213#define MV64x60_CPU2PCI1_MEM_2_REMAP_LO 0x0310
214#define MV64x60_CPU2PCI1_MEM_2_REMAP_HI 0x0350
215#define MV64x60_CPU2PCI1_MEM_3_REMAP_LO 0x0318
216#define MV64x60_CPU2PCI1_MEM_3_REMAP_HI 0x0358
217
218/* CPU Control Registers */
219#define MV64x60_CPU_CONFIG 0x0000
220#define MV64x60_CPU_MODE 0x0120
221#define MV64x60_CPU_MASTER_CNTL 0x0160
222#define MV64x60_CPU_XBAR_CNTL_LO 0x0150
223#define MV64x60_CPU_XBAR_CNTL_HI 0x0158
224#define MV64x60_CPU_XBAR_TO 0x0168
225
226#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170
227#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178
228
229#define MV64360_CPU_PADS_CALIBRATION 0x03b4
230#define MV64360_CPU_RESET_SAMPLE_LO 0x03c4
231#define MV64360_CPU_RESET_SAMPLE_HI 0x03d4
232
233/* SMP Register Map */
234#define MV64360_WHO_AM_I 0x0200
235#define MV64360_CPU0_DOORBELL 0x0214
236#define MV64360_CPU0_DOORBELL_CLR 0x021c
237#define MV64360_CPU0_DOORBELL_MASK 0x0234
238#define MV64360_CPU1_DOORBELL 0x0224
239#define MV64360_CPU1_DOORBELL_CLR 0x022c
240#define MV64360_CPU1_DOORBELL_MASK 0x023c
241#define MV64360_CPUx_DOORBELL(x) (0x0214 + ((x)*0x10))
242#define MV64360_CPUx_DOORBELL_CLR(x) (0x021c + ((x)*0x10))
243#define MV64360_CPUx_DOORBELL_MASK(x) (0x0234 + ((x)*0x08))
244#define MV64360_SEMAPHORE_0 0x0244
245#define MV64360_SEMAPHORE_1 0x024c
246#define MV64360_SEMAPHORE_2 0x0254
247#define MV64360_SEMAPHORE_3 0x025c
248#define MV64360_SEMAPHORE_4 0x0264
249#define MV64360_SEMAPHORE_5 0x026c
250#define MV64360_SEMAPHORE_6 0x0274
251#define MV64360_SEMAPHORE_7 0x027c
252
253/* CPU Sync Barrier Registers */
254#define GT64260_CPU_SYNC_BARRIER_PCI0 0x00c0
255#define GT64260_CPU_SYNC_BARRIER_PCI1 0x00c8
256
257#define MV64360_CPU0_SYNC_BARRIER_TRIG 0x00c0
258#define MV64360_CPU0_SYNC_BARRIER_VIRT 0x00c8
259#define MV64360_CPU1_SYNC_BARRIER_TRIG 0x00d0
260#define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8
261
262/* CPU Deadlock and Ordering registers (Rev B part only) */
263#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
264#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
265#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
266
267/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
268#define MV64x260_CPU_PROT_WINDOWS 4
269
270#define GT64260_CPU_PROT_ACCPROTECT (1<<16)
271#define GT64260_CPU_PROT_WRPROTECT (1<<17)
272#define GT64260_CPU_PROT_CACHEPROTECT (1<<18)
273
274#define MV64360_CPU_PROT_ACCPROTECT (1<<20)
275#define MV64360_CPU_PROT_WRPROTECT (1<<21)
276#define MV64360_CPU_PROT_CACHEPROTECT (1<<22)
277#define MV64360_CPU_PROT_WIN_ENABLE (1<<31)
278
279#define MV64x60_CPU_PROT_BASE_0 0x0180
280#define MV64x60_CPU_PROT_SIZE_0 0x0188
281#define MV64x60_CPU_PROT_BASE_1 0x0190
282#define MV64x60_CPU_PROT_SIZE_1 0x0198
283#define MV64x60_CPU_PROT_BASE_2 0x01a0
284#define MV64x60_CPU_PROT_SIZE_2 0x01a8
285#define MV64x60_CPU_PROT_BASE_3 0x01b0
286#define MV64x60_CPU_PROT_SIZE_3 0x01b8
287
288#define GT64260_CPU_PROT_BASE_4 0x01c0
289#define GT64260_CPU_PROT_SIZE_4 0x01c8
290#define GT64260_CPU_PROT_BASE_5 0x01d0
291#define GT64260_CPU_PROT_SIZE_5 0x01d8
292#define GT64260_CPU_PROT_BASE_6 0x01e0
293#define GT64260_CPU_PROT_SIZE_6 0x01e8
294#define GT64260_CPU_PROT_BASE_7 0x01f0
295#define GT64260_CPU_PROT_SIZE_7 0x01f8
296
297/* CPU Snoop Control Registers (64260 only) */
298#define GT64260_CPU_SNOOP_WINDOWS 4
299
300#define GT64260_CPU_SNOOP_NONE 0x00000000
301#define GT64260_CPU_SNOOP_WT 0x00010000
302#define GT64260_CPU_SNOOP_WB 0x00020000
303#define GT64260_CPU_SNOOP_MASK 0x00030000
304#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK
305
306#define GT64260_CPU_SNOOP_BASE_0 0x0380
307#define GT64260_CPU_SNOOP_SIZE_0 0x0388
308#define GT64260_CPU_SNOOP_BASE_1 0x0390
309#define GT64260_CPU_SNOOP_SIZE_1 0x0398
310#define GT64260_CPU_SNOOP_BASE_2 0x03a0
311#define GT64260_CPU_SNOOP_SIZE_2 0x03a8
312#define GT64260_CPU_SNOOP_BASE_3 0x03b0
313#define GT64260_CPU_SNOOP_SIZE_3 0x03b8
314
315/* CPU Snoop Control Registers (64360 only) */
316#define MV64360_CPU_SNOOP_WINDOWS 4
317#define MV64360_CPU_SNOOP_NONE 0x00000000
318#define MV64360_CPU_SNOOP_WT 0x00010000
319#define MV64360_CPU_SNOOP_WB 0x00020000
320#define MV64360_CPU_SNOOP_MASK 0x00030000
321#define MV64360_CPU_SNOOP_ALL_BITS MV64360_CPU_SNOOP_MASK
322
323
324/* CPU Error Report Registers */
325#define MV64x60_CPU_ERR_ADDR_LO 0x0070
326#define MV64x60_CPU_ERR_ADDR_HI 0x0078
327#define MV64x60_CPU_ERR_DATA_LO 0x0128
328#define MV64x60_CPU_ERR_DATA_HI 0x0130
329#define MV64x60_CPU_ERR_PARITY 0x0138
330#define MV64x60_CPU_ERR_CAUSE 0x0140
331#define MV64x60_CPU_ERR_MASK 0x0148
332
333/*
334 *****************************************************************************
335 *
336 * SRAM Cotnroller Registers
337 *
338 *****************************************************************************
339 */
340
341#define MV64360_SRAM_CONFIG 0x0380
342#define MV64360_SRAM_TEST_MODE 0x03f4
343#define MV64360_SRAM_ERR_CAUSE 0x0388
344#define MV64360_SRAM_ERR_ADDR_LO 0x0390
345#define MV64360_SRAM_ERR_ADDR_HI 0x03f8
346#define MV64360_SRAM_ERR_DATA_LO 0x0398
347#define MV64360_SRAM_ERR_DATA_HI 0x03a0
348#define MV64360_SRAM_ERR_PARITY 0x03a8
349
350#define MV64360_SRAM_SIZE 0x00040000 /* 2Mb/256KB SRAM */
351
352/*
353 *****************************************************************************
354 *
355 * SDRAM/MEM Cotnroller Registers
356 *
357 *****************************************************************************
358 */
359
360/* SDRAM Config Registers (64260) */
361#define GT64260_SDRAM_CONFIG 0x0448
362
363/* SDRAM Error Report Registers (64260) */
364#define GT64260_SDRAM_ERR_DATA_LO 0x0484
365#define GT64260_SDRAM_ERR_DATA_HI 0x0480
366#define GT64260_SDRAM_ERR_ADDR 0x0490
367#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488
368#define GT64260_SDRAM_ERR_ECC_CALC 0x048c
369#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494
370#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498
371
372/* SDRAM Config Registers (64360) */
373#define MV64360_SDRAM_CONFIG 0x1400
374
375/* SDRAM Control Registers */
376#define MV64360_D_UNIT_CONTROL_LOW 0x1404
377#define MV64360_D_UNIT_CONTROL_HIGH 0x1424
378
379/* SDRAM Error Report Registers (64360) */
380#define MV64360_SDRAM_ERR_DATA_LO 0x1444
381#define MV64360_SDRAM_ERR_DATA_HI 0x1440
382#define MV64360_SDRAM_ERR_ADDR 0x1450
383#define MV64360_SDRAM_ERR_ECC_RCVD 0x1448
384#define MV64360_SDRAM_ERR_ECC_CALC 0x144c
385#define MV64360_SDRAM_ERR_ECC_CNTL 0x1454
386#define MV64360_SDRAM_ERR_ECC_ERR_CNT 0x1458
387
388/*
389 *****************************************************************************
390 *
391 * Device/BOOT Cotnroller Registers
392 *
393 *****************************************************************************
394 */
395
396/* Device Control Registers */
397#define MV64x60_DEV_BANK_PARAMS_0 0x045c
398#define MV64x60_DEV_BANK_PARAMS_1 0x0460
399#define MV64x60_DEV_BANK_PARAMS_2 0x0464
400#define MV64x60_DEV_BANK_PARAMS_3 0x0468
401#define MV64x60_DEV_BOOT_PARAMS 0x046c
402#define MV64x60_DEV_IF_CNTL 0x04c0
403#define MV64x60_DEV_IF_XBAR_CNTL_LO 0x04c8
404#define MV64x60_DEV_IF_XBAR_CNTL_HI 0x04cc
405#define MV64x60_DEV_IF_XBAR_CNTL_TO 0x04c4
406
407/* Device Interrupt Registers */
408#define MV64x60_DEV_INTR_CAUSE 0x04d0
409#define MV64x60_DEV_INTR_MASK 0x04d4
410#define MV64x60_DEV_INTR_ERR_ADDR 0x04d8
411
412#define MV64360_DEV_INTR_ERR_DATA 0x04dc
413#define MV64360_DEV_INTR_ERR_PAR 0x04e0
414
415/*
416 *****************************************************************************
417 *
418 * PCI Bridge Interface Registers
419 *
420 *****************************************************************************
421 */
422
423/* PCI Configuration Access Registers */
424#define MV64x60_PCI0_CONFIG_ADDR 0x0cf8
425#define MV64x60_PCI0_CONFIG_DATA 0x0cfc
426#define MV64x60_PCI0_IACK 0x0c34
427
428#define MV64x60_PCI1_CONFIG_ADDR 0x0c78
429#define MV64x60_PCI1_CONFIG_DATA 0x0c7c
430#define MV64x60_PCI1_IACK 0x0cb4
431
432/* PCI Control Registers */
433#define MV64x60_PCI0_CMD 0x0c00
434#define MV64x60_PCI0_MODE 0x0d00
435#define MV64x60_PCI0_TO_RETRY 0x0c04
436#define MV64x60_PCI0_RD_BUF_DISCARD_TIMER 0x0d04
437#define MV64x60_PCI0_MSI_TRIGGER_TIMER 0x0c38
438#define MV64x60_PCI0_ARBITER_CNTL 0x1d00
439#define MV64x60_PCI0_XBAR_CNTL_LO 0x1d08
440#define MV64x60_PCI0_XBAR_CNTL_HI 0x1d0c
441#define MV64x60_PCI0_XBAR_CNTL_TO 0x1d04
442#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_LO 0x1d18
443#define MV64x60_PCI0_RD_RESP_XBAR_CNTL_HI 0x1d1c
444#define MV64x60_PCI0_SYNC_BARRIER 0x1d10
445#define MV64x60_PCI0_P2P_CONFIG 0x1d14
446#define MV64x60_PCI0_INTR_MASK
447
448#define GT64260_PCI0_P2P_SWAP_CNTL 0x1d54
449
450#define MV64x60_PCI1_CMD 0x0c80
451#define MV64x60_PCI1_MODE 0x0d80
452#define MV64x60_PCI1_TO_RETRY 0x0c84
453#define MV64x60_PCI1_RD_BUF_DISCARD_TIMER 0x0d84
454#define MV64x60_PCI1_MSI_TRIGGER_TIMER 0x0cb8
455#define MV64x60_PCI1_ARBITER_CNTL 0x1d80
456#define MV64x60_PCI1_XBAR_CNTL_LO 0x1d88
457#define MV64x60_PCI1_XBAR_CNTL_HI 0x1d8c
458#define MV64x60_PCI1_XBAR_CNTL_TO 0x1d84
459#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_LO 0x1d98
460#define MV64x60_PCI1_RD_RESP_XBAR_CNTL_HI 0x1d9c
461#define MV64x60_PCI1_SYNC_BARRIER 0x1d90
462#define MV64x60_PCI1_P2P_CONFIG 0x1d94
463
464#define GT64260_PCI1_P2P_SWAP_CNTL 0x1dd4
465
466/* Different modes that the pci hoses can be in (bits 5:4 in PCI Mode reg) */
467#define MV64x60_PCIMODE_CONVENTIONAL 0
468#define MV64x60_PCIMODE_PCIX_66 (1 << 4)
469#define MV64x60_PCIMODE_PCIX_100 (2 << 4)
470#define MV64x60_PCIMODE_PCIX_133 (3 << 4)
471#define MV64x60_PCIMODE_MASK (0x3 << 4)
472
473/* PCI Access Control Regions Registers */
474#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12)
475#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13)
476#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16)
477#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17)
478#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18)
479#define GT64260_PCI_ACC_CNTL_MBURST_32_BTYES 0x00000000
480#define GT64260_PCI_ACC_CNTL_MBURST_64_BYTES 0x00100000
481#define GT64260_PCI_ACC_CNTL_MBURST_128_BYTES 0x00200000
482#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000
483#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
484#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000
485#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000
486#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000
487#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000
488#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28)
489#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29)
490
491#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \
492 GT64260_PCI_ACC_CNTL_DREADEN | \
493 GT64260_PCI_ACC_CNTL_RDPREFETCH | \
494 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
495 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
496 GT64260_PCI_ACC_CNTL_MBURST_MASK | \
497 GT64260_PCI_ACC_CNTL_SWAP_MASK | \
498 GT64260_PCI_ACC_CNTL_ACCPROT| \
499 GT64260_PCI_ACC_CNTL_WRPROT)
500
501#define MV64360_PCI_ACC_CNTL_ENABLE (1<<0)
502#define MV64360_PCI_ACC_CNTL_REQ64 (1<<1)
503#define MV64360_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
504#define MV64360_PCI_ACC_CNTL_SNOOP_WT 0x00000004
505#define MV64360_PCI_ACC_CNTL_SNOOP_WB 0x00000008
506#define MV64360_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
507#define MV64360_PCI_ACC_CNTL_ACCPROT (1<<4)
508#define MV64360_PCI_ACC_CNTL_WRPROT (1<<5)
509#define MV64360_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
510#define MV64360_PCI_ACC_CNTL_SWAP_NONE 0x00000040
511#define MV64360_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
512#define MV64360_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
513#define MV64360_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
514#define MV64360_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
515#define MV64360_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
516#define MV64360_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
517#define MV64360_PCI_ACC_CNTL_MBURST_MASK 0x00000300
518#define MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
519#define MV64360_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
520#define MV64360_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
521#define MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
522#define MV64360_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
523
524#define MV64360_PCI_ACC_CNTL_ALL_BITS (MV64360_PCI_ACC_CNTL_ENABLE | \
525 MV64360_PCI_ACC_CNTL_REQ64 | \
526 MV64360_PCI_ACC_CNTL_SNOOP_MASK | \
527 MV64360_PCI_ACC_CNTL_ACCPROT | \
528 MV64360_PCI_ACC_CNTL_WRPROT | \
529 MV64360_PCI_ACC_CNTL_SWAP_MASK | \
530 MV64360_PCI_ACC_CNTL_MBURST_MASK | \
531 MV64360_PCI_ACC_CNTL_RDSIZE_MASK)
532
533#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
534#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
535#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
536#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
537#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
538#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
539#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
540#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
541#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
542#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
543#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
544#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
545#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
546#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
547#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
548#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
549#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
550#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
551
552#define GT64260_PCI0_ACC_CNTL_6_BASE_LO 0x1e60
553#define GT64260_PCI0_ACC_CNTL_6_BASE_HI 0x1e64
554#define GT64260_PCI0_ACC_CNTL_6_SIZE 0x1e68
555#define GT64260_PCI0_ACC_CNTL_7_BASE_LO 0x1e70
556#define GT64260_PCI0_ACC_CNTL_7_BASE_HI 0x1e74
557#define GT64260_PCI0_ACC_CNTL_7_SIZE 0x1e78
558
559#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
560#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
561#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
562#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
563#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
564#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
565#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
566#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
567#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
568#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
569#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
570#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
571#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
572#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
573#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
574#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
575#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
576#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
577
578#define GT64260_PCI1_ACC_CNTL_6_BASE_LO 0x1ee0
579#define GT64260_PCI1_ACC_CNTL_6_BASE_HI 0x1ee4
580#define GT64260_PCI1_ACC_CNTL_6_SIZE 0x1ee8
581#define GT64260_PCI1_ACC_CNTL_7_BASE_LO 0x1ef0
582#define GT64260_PCI1_ACC_CNTL_7_BASE_HI 0x1ef4
583#define GT64260_PCI1_ACC_CNTL_7_SIZE 0x1ef8
584
585/* PCI Snoop Control Registers (64260 only) */
586#define GT64260_PCI_SNOOP_NONE 0x00000000
587#define GT64260_PCI_SNOOP_WT 0x00001000
588#define GT64260_PCI_SNOOP_WB 0x00002000
589
590#define GT64260_PCI0_SNOOP_0_BASE_LO 0x1f00
591#define GT64260_PCI0_SNOOP_0_BASE_HI 0x1f04
592#define GT64260_PCI0_SNOOP_0_SIZE 0x1f08
593#define GT64260_PCI0_SNOOP_1_BASE_LO 0x1f10
594#define GT64260_PCI0_SNOOP_1_BASE_HI 0x1f14
595#define GT64260_PCI0_SNOOP_1_SIZE 0x1f18
596#define GT64260_PCI0_SNOOP_2_BASE_LO 0x1f20
597#define GT64260_PCI0_SNOOP_2_BASE_HI 0x1f24
598#define GT64260_PCI0_SNOOP_2_SIZE 0x1f28
599#define GT64260_PCI0_SNOOP_3_BASE_LO 0x1f30
600#define GT64260_PCI0_SNOOP_3_BASE_HI 0x1f34
601#define GT64260_PCI0_SNOOP_3_SIZE 0x1f38
602
603#define GT64260_PCI1_SNOOP_0_BASE_LO 0x1f80
604#define GT64260_PCI1_SNOOP_0_BASE_HI 0x1f84
605#define GT64260_PCI1_SNOOP_0_SIZE 0x1f88
606#define GT64260_PCI1_SNOOP_1_BASE_LO 0x1f90
607#define GT64260_PCI1_SNOOP_1_BASE_HI 0x1f94
608#define GT64260_PCI1_SNOOP_1_SIZE 0x1f98
609#define GT64260_PCI1_SNOOP_2_BASE_LO 0x1fa0
610#define GT64260_PCI1_SNOOP_2_BASE_HI 0x1fa4
611#define GT64260_PCI1_SNOOP_2_SIZE 0x1fa8
612#define GT64260_PCI1_SNOOP_3_BASE_LO 0x1fb0
613#define GT64260_PCI1_SNOOP_3_BASE_HI 0x1fb4
614#define GT64260_PCI1_SNOOP_3_SIZE 0x1fb8
615
616/* PCI Error Report Registers */
617#define MV64x60_PCI0_ERR_SERR_MASK 0x0c28
618#define MV64x60_PCI0_ERR_ADDR_LO 0x1d40
619#define MV64x60_PCI0_ERR_ADDR_HI 0x1d44
620#define MV64x60_PCI0_ERR_DATA_LO 0x1d48
621#define MV64x60_PCI0_ERR_DATA_HI 0x1d4c
622#define MV64x60_PCI0_ERR_CMD 0x1d50
623#define MV64x60_PCI0_ERR_CAUSE 0x1d58
624#define MV64x60_PCI0_ERR_MASK 0x1d5c
625
626#define MV64x60_PCI1_ERR_SERR_MASK 0x0ca8
627#define MV64x60_PCI1_ERR_ADDR_LO 0x1dc0
628#define MV64x60_PCI1_ERR_ADDR_HI 0x1dc4
629#define MV64x60_PCI1_ERR_DATA_LO 0x1dc8
630#define MV64x60_PCI1_ERR_DATA_HI 0x1dcc
631#define MV64x60_PCI1_ERR_CMD 0x1dd0
632#define MV64x60_PCI1_ERR_CAUSE 0x1dd8
633#define MV64x60_PCI1_ERR_MASK 0x1ddc
634
635/* PCI Slave Address Decoding Registers */
636#define MV64x60_PCI0_MEM_0_SIZE 0x0c08
637#define MV64x60_PCI0_MEM_1_SIZE 0x0d08
638#define MV64x60_PCI0_MEM_2_SIZE 0x0c0c
639#define MV64x60_PCI0_MEM_3_SIZE 0x0d0c
640#define MV64x60_PCI1_MEM_0_SIZE 0x0c88
641#define MV64x60_PCI1_MEM_1_SIZE 0x0d88
642#define MV64x60_PCI1_MEM_2_SIZE 0x0c8c
643#define MV64x60_PCI1_MEM_3_SIZE 0x0d8c
644
645#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
646#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
647
648#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
649#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
650
651#define MV64x60_PCI0_SLAVE_MEM_0_REMAP 0x0c48
652#define MV64x60_PCI0_SLAVE_MEM_1_REMAP 0x0d48
653#define MV64x60_PCI0_SLAVE_MEM_2_REMAP 0x0c4c
654#define MV64x60_PCI0_SLAVE_MEM_3_REMAP 0x0d4c
655#define MV64x60_PCI0_SLAVE_DEV_0_REMAP 0x0c50
656#define MV64x60_PCI0_SLAVE_DEV_1_REMAP 0x0d50
657#define MV64x60_PCI0_SLAVE_DEV_2_REMAP 0x0d58
658#define MV64x60_PCI0_SLAVE_DEV_3_REMAP 0x0c54
659#define MV64x60_PCI0_SLAVE_BOOT_REMAP 0x0d54
660#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c
661#define MV64x60_PCI0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60
662#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64
663#define MV64x60_PCI0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68
664#define MV64x60_PCI0_SLAVE_P2P_IO_REMAP 0x0d6c
665#define MV64x60_PCI0_SLAVE_CPU_REMAP 0x0d70
666
667#define MV64x60_PCI1_SLAVE_MEM_0_REMAP 0x0cc8
668#define MV64x60_PCI1_SLAVE_MEM_1_REMAP 0x0dc8
669#define MV64x60_PCI1_SLAVE_MEM_2_REMAP 0x0ccc
670#define MV64x60_PCI1_SLAVE_MEM_3_REMAP 0x0dcc
671#define MV64x60_PCI1_SLAVE_DEV_0_REMAP 0x0cd0
672#define MV64x60_PCI1_SLAVE_DEV_1_REMAP 0x0dd0
673#define MV64x60_PCI1_SLAVE_DEV_2_REMAP 0x0dd8
674#define MV64x60_PCI1_SLAVE_DEV_3_REMAP 0x0cd4
675#define MV64x60_PCI1_SLAVE_BOOT_REMAP 0x0dd4
676#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc
677#define MV64x60_PCI1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0
678#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4
679#define MV64x60_PCI1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8
680#define MV64x60_PCI1_SLAVE_P2P_IO_REMAP 0x0dec
681#define MV64x60_PCI1_SLAVE_CPU_REMAP 0x0df0
682
683/*
684 *****************************************************************************
685 *
686 * ENET Controller Interface Registers
687 *
688 *****************************************************************************
689 */
690
691/* ENET Controller Window Registers (6 windows) */
692#define MV64360_ENET2MEM_WINDOWS 6
693
694#define MV64360_ENET2MEM_0_BASE 0x2200
695#define MV64360_ENET2MEM_0_SIZE 0x2204
696#define MV64360_ENET2MEM_1_BASE 0x2208
697#define MV64360_ENET2MEM_1_SIZE 0x220c
698#define MV64360_ENET2MEM_2_BASE 0x2210
699#define MV64360_ENET2MEM_2_SIZE 0x2214
700#define MV64360_ENET2MEM_3_BASE 0x2218
701#define MV64360_ENET2MEM_3_SIZE 0x221c
702#define MV64360_ENET2MEM_4_BASE 0x2220
703#define MV64360_ENET2MEM_4_SIZE 0x2224
704#define MV64360_ENET2MEM_5_BASE 0x2228
705#define MV64360_ENET2MEM_5_SIZE 0x222c
706
707#define MV64360_ENET2MEM_SNOOP_NONE 0x00000000
708#define MV64360_ENET2MEM_SNOOP_WT 0x00001000
709#define MV64360_ENET2MEM_SNOOP_WB 0x00002000
710
711#define MV64360_ENET2MEM_BAR_ENABLE 0x2290
712
713#define MV64360_ENET2MEM_ACC_PROT_0 0x2294
714#define MV64360_ENET2MEM_ACC_PROT_1 0x2298
715#define MV64360_ENET2MEM_ACC_PROT_2 0x229c
716
717/*
718 *****************************************************************************
719 *
720 * MPSC Controller Interface Registers
721 *
722 *****************************************************************************
723 */
724
725/* MPSC Controller Window Registers (4 windows) */
726#define MV64360_MPSC2MEM_WINDOWS 4
727
728#define MV64360_MPSC2MEM_0_BASE 0xf200
729#define MV64360_MPSC2MEM_0_SIZE 0xf204
730#define MV64360_MPSC2MEM_1_BASE 0xf208
731#define MV64360_MPSC2MEM_1_SIZE 0xf20c
732#define MV64360_MPSC2MEM_2_BASE 0xf210
733#define MV64360_MPSC2MEM_2_SIZE 0xf214
734#define MV64360_MPSC2MEM_3_BASE 0xf218
735#define MV64360_MPSC2MEM_3_SIZE 0xf21c
736
737#define MV64360_MPSC_0_REMAP 0xf240
738#define MV64360_MPSC_1_REMAP 0xf244
739
740#define MV64360_MPSC2MEM_SNOOP_NONE 0x00000000
741#define MV64360_MPSC2MEM_SNOOP_WT 0x00001000
742#define MV64360_MPSC2MEM_SNOOP_WB 0x00002000
743
744#define MV64360_MPSC2MEM_BAR_ENABLE 0xf250
745
746#define MV64360_MPSC2MEM_ACC_PROT_0 0xf254
747#define MV64360_MPSC2MEM_ACC_PROT_1 0xf258
748
749#define MV64360_MPSC2REGS_BASE 0xf25c
750
751/*
752 *****************************************************************************
753 *
754 * Timer/Counter Interface Registers
755 *
756 *****************************************************************************
757 */
758
759#define MV64x60_TIMR_CNTR_0 0x0850
760#define MV64x60_TIMR_CNTR_1 0x0854
761#define MV64x60_TIMR_CNTR_2 0x0858
762#define MV64x60_TIMR_CNTR_3 0x085c
763#define MV64x60_TIMR_CNTR_0_3_CNTL 0x0864
764#define MV64x60_TIMR_CNTR_0_3_INTR_CAUSE 0x0868
765#define MV64x60_TIMR_CNTR_0_3_INTR_MASK 0x086c
766
767#define GT64260_TIMR_CNTR_4 0x0950
768#define GT64260_TIMR_CNTR_5 0x0954
769#define GT64260_TIMR_CNTR_6 0x0958
770#define GT64260_TIMR_CNTR_7 0x095c
771#define GT64260_TIMR_CNTR_4_7_CNTL 0x0964
772#define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968
773#define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c
774
775/*
776 *****************************************************************************
777 *
778 * Communications Controller
779 *
780 *****************************************************************************
781 */
782
783#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320
784#define GT64260_SER_INIT_LAST_DATA 0xf324
785#define GT64260_SER_INIT_CONTROL 0xf328
786#define GT64260_SER_INIT_STATUS 0xf32c
787
788#define MV64x60_COMM_ARBITER_CNTL 0xf300
789#define MV64x60_COMM_CONFIG 0xb40c
790#define MV64x60_COMM_XBAR_TO 0xf304
791#define MV64x60_COMM_INTR_CAUSE 0xf310
792#define MV64x60_COMM_INTR_MASK 0xf314
793#define MV64x60_COMM_ERR_ADDR 0xf318
794
795#define MV64360_COMM_ARBITER_CNTL 0xf300
796
797/*
798 *****************************************************************************
799 *
800 * IDMA Controller Interface Registers
801 *
802 *****************************************************************************
803 */
804
805/* IDMA Controller Window Registers (8 windows) */
806#define MV64360_IDMA2MEM_WINDOWS 8
807
808#define MV64360_IDMA2MEM_0_BASE 0x0a00
809#define MV64360_IDMA2MEM_0_SIZE 0x0a04
810#define MV64360_IDMA2MEM_1_BASE 0x0a08
811#define MV64360_IDMA2MEM_1_SIZE 0x0a0c
812#define MV64360_IDMA2MEM_2_BASE 0x0a10
813#define MV64360_IDMA2MEM_2_SIZE 0x0a14
814#define MV64360_IDMA2MEM_3_BASE 0x0a18
815#define MV64360_IDMA2MEM_3_SIZE 0x0a1c
816#define MV64360_IDMA2MEM_4_BASE 0x0a20
817#define MV64360_IDMA2MEM_4_SIZE 0x0a24
818#define MV64360_IDMA2MEM_5_BASE 0x0a28
819#define MV64360_IDMA2MEM_5_SIZE 0x0a2c
820#define MV64360_IDMA2MEM_6_BASE 0x0a30
821#define MV64360_IDMA2MEM_6_SIZE 0x0a34
822#define MV64360_IDMA2MEM_7_BASE 0x0a38
823#define MV64360_IDMA2MEM_7_SIZE 0x0a3c
824
825#define MV64360_IDMA2MEM_SNOOP_NONE 0x00000000
826#define MV64360_IDMA2MEM_SNOOP_WT 0x00001000
827#define MV64360_IDMA2MEM_SNOOP_WB 0x00002000
828
829#define MV64360_IDMA2MEM_BAR_ENABLE 0x0a80
830
831#define MV64360_IDMA2MEM_ACC_PROT_0 0x0a70
832#define MV64360_IDMA2MEM_ACC_PROT_1 0x0a74
833#define MV64360_IDMA2MEM_ACC_PROT_2 0x0a78
834#define MV64360_IDMA2MEM_ACC_PROT_3 0x0a7c
835
836#define MV64x60_IDMA_0_OFFSET 0x0800
837#define MV64x60_IDMA_1_OFFSET 0x0804
838#define MV64x60_IDMA_2_OFFSET 0x0808
839#define MV64x60_IDMA_3_OFFSET 0x080c
840#define MV64x60_IDMA_4_OFFSET 0x0900
841#define MV64x60_IDMA_5_OFFSET 0x0904
842#define MV64x60_IDMA_6_OFFSET 0x0908
843#define MV64x60_IDMA_7_OFFSET 0x090c
844
845#define MV64x60_IDMA_BYTE_COUNT (0x0800 - MV64x60_IDMA_0_OFFSET)
846#define MV64x60_IDMA_SRC_ADDR (0x0810 - MV64x60_IDMA_0_OFFSET)
847#define MV64x60_IDMA_DST_ADDR (0x0820 - MV64x60_IDMA_0_OFFSET)
848#define MV64x60_IDMA_NEXT_DESC (0x0830 - MV64x60_IDMA_0_OFFSET)
849#define MV64x60_IDMA_CUR_DESC (0x0870 - MV64x60_IDMA_0_OFFSET)
850#define MV64x60_IDMA_SRC_PCI_ADDR_HI (0x0890 - MV64x60_IDMA_0_OFFSET)
851#define MV64x60_IDMA_DST_PCI_ADDR_HI (0x08a0 - MV64x60_IDMA_0_OFFSET)
852#define MV64x60_IDMA_NEXT_DESC_PCI_ADDR_HI (0x08b0 - MV64x60_IDMA_0_OFFSET)
853#define MV64x60_IDMA_CONTROL_LO (0x0840 - MV64x60_IDMA_0_OFFSET)
854#define MV64x60_IDMA_CONTROL_HI (0x0880 - MV64x60_IDMA_0_OFFSET)
855
856#define MV64x60_IDMA_0_3_ARBITER_CNTL 0x0860
857#define MV64x60_IDMA_4_7_ARBITER_CNTL 0x0960
858
859#define MV64x60_IDMA_0_3_XBAR_TO 0x08d0
860#define MV64x60_IDMA_4_7_XBAR_TO 0x09d0
861
862#define MV64x60_IDMA_0_3_INTR_CAUSE 0x08c0
863#define MV64x60_IDMA_0_3_INTR_MASK 0x08c4
864#define MV64x60_IDMA_0_3_ERROR_ADDR 0x08c8
865#define MV64x60_IDMA_0_3_ERROR_SELECT 0x08cc
866#define MV64x60_IDMA_4_7_INTR_CAUSE 0x09c0
867#define MV64x60_IDMA_4_7_INTR_MASK 0x09c4
868#define MV64x60_IDMA_4_7_ERROR_ADDR 0x09c8
869#define MV64x60_IDMA_4_7_ERROR_SELECT 0x09cc
870
871/*
872 *****************************************************************************
873 *
874 * Watchdog Timer Interface Registers
875 *
876 *****************************************************************************
877 */
878
879#define MV64x60_WDT_WDC 0xb410
880#define MV64x60_WDT_WDV 0xb414
881
882
883/*
884 *****************************************************************************
885 *
886 * General Purpose Pins Controller Interface Registers
887 *
888 *****************************************************************************
889 */
890
891#define MV64x60_GPP_IO_CNTL 0xf100
892#define MV64x60_GPP_LEVEL_CNTL 0xf110
893#define MV64x60_GPP_VALUE 0xf104
894#define MV64x60_GPP_INTR_CAUSE 0xf108
895#define MV64x60_GPP_INTR_MASK 0xf10c
896#define MV64x60_GPP_VALUE_SET 0xf118
897#define MV64x60_GPP_VALUE_CLR 0xf11c
898
899
900/*
901 *****************************************************************************
902 *
903 * Multi-Purpose Pins Controller Interface Registers
904 *
905 *****************************************************************************
906 */
907
908#define MV64x60_MPP_CNTL_0 0xf000
909#define MV64x60_MPP_CNTL_1 0xf004
910#define MV64x60_MPP_CNTL_2 0xf008
911#define MV64x60_MPP_CNTL_3 0xf00c
912#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010
913
914#define MV64x60_ETH_BAR_GAP 0x8
915#define MV64x60_ETH_SIZE_REG_GAP 0x8
916#define MV64x60_ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
917#define MV64x60_ETH_PORT_ACCESS_CTRL_GAP 0x4
918
919#define MV64x60_EBAR_ATTR_DRAM_CS0 0x00000E00
920#define MV64x60_EBAR_ATTR_DRAM_CS1 0x00000D00
921#define MV64x60_EBAR_ATTR_DRAM_CS2 0x00000B00
922#define MV64x60_EBAR_ATTR_DRAM_CS3 0x00000700
923
924#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
925#define MV64x60_EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
926#define MV64x60_EBAR_ATTR_CBS_SRAM 0x00000000
927#define MV64x60_EBAR_ATTR_CBS_CPU_BUS 0x00000800
928
929
930/*
931 *****************************************************************************
932 *
933 * Interrupt Controller Interface Registers
934 *
935 *****************************************************************************
936 */
937
938#define GT64260_IC_OFFSET 0x0c18
939
940#define GT64260_IC_MAIN_CAUSE_LO 0x0c18
941#define GT64260_IC_MAIN_CAUSE_HI 0x0c68
942#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c
943#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c
944#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70
945#define GT64260_IC_PCI0_INTR_MASK_LO 0x0c24
946#define GT64260_IC_PCI0_INTR_MASK_HI 0x0c64
947#define GT64260_IC_PCI0_SELECT_CAUSE 0x0c74
948#define GT64260_IC_PCI1_INTR_MASK_LO 0x0ca4
949#define GT64260_IC_PCI1_INTR_MASK_HI 0x0ce4
950#define GT64260_IC_PCI1_SELECT_CAUSE 0x0cf4
951#define GT64260_IC_CPU_INT_0_MASK 0x0e60
952#define GT64260_IC_CPU_INT_1_MASK 0x0e64
953#define GT64260_IC_CPU_INT_2_MASK 0x0e68
954#define GT64260_IC_CPU_INT_3_MASK 0x0e6c
955
956#define MV64360_IC_OFFSET 0x0000
957
958#define MV64360_IC_MAIN_CAUSE_LO 0x0004
959#define MV64360_IC_MAIN_CAUSE_HI 0x000c
960#define MV64360_IC_CPU0_INTR_MASK_LO 0x0014
961#define MV64360_IC_CPU0_INTR_MASK_HI 0x001c
962#define MV64360_IC_CPU0_SELECT_CAUSE 0x0024
963#define MV64360_IC_CPU1_INTR_MASK_LO 0x0034
964#define MV64360_IC_CPU1_INTR_MASK_HI 0x003c
965#define MV64360_IC_CPU1_SELECT_CAUSE 0x0044
966#define MV64360_IC_INT0_MASK_LO 0x0054
967#define MV64360_IC_INT0_MASK_HI 0x005c
968#define MV64360_IC_INT0_SELECT_CAUSE 0x0064
969#define MV64360_IC_INT1_MASK_LO 0x0074
970#define MV64360_IC_INT1_MASK_HI 0x007c
971#define MV64360_IC_INT1_SELECT_CAUSE 0x0084
972
973#endif /* __ASMPPC_MV64x60_DEFS_H */