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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ppc/m8260_pci.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-ppc/m8260_pci.h')
-rw-r--r--include/asm-ppc/m8260_pci.h186
1 files changed, 186 insertions, 0 deletions
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
new file mode 100644
index 000000000000..163a6b91d5b2
--- /dev/null
+++ b/include/asm-ppc/m8260_pci.h
@@ -0,0 +1,186 @@
1/*
2 * include/asm-ppc/m8260_pci.h
3 *
4 * Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifdef __KERNEL__
13#ifndef __M8260_PCI_H
14#define __M8260_PCI_H
15
16#include <linux/pci_ids.h>
17
18/*
19 * Define the vendor/device ID for the MPC8265.
20 */
21#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
22
23#define M8265_PCIBR0 0x101ac
24#define M8265_PCIBR1 0x101b0
25#define M8265_PCIMSK0 0x101c4
26#define M8265_PCIMSK1 0x101c8
27
28/* Bit definitions for PCIBR registers */
29
30#define PCIBR_ENABLE 0x00000001
31
32/* Bit definitions for PCIMSK registers */
33
34#define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */
35#define PCIMSK_64KiB 0xFFFF0000
36#define PCIMSK_128KiB 0xFFFE0000
37#define PCIMSK_256KiB 0xFFFC0000
38#define PCIMSK_512KiB 0xFFF80000
39#define PCIMSK_1MiB 0xFFF00000
40#define PCIMSK_2MiB 0xFFE00000
41#define PCIMSK_4MiB 0xFFC00000
42#define PCIMSK_8MiB 0xFF800000
43#define PCIMSK_16MiB 0xFF000000
44#define PCIMSK_32MiB 0xFE000000
45#define PCIMSK_64MiB 0xFC000000
46#define PCIMSK_128MiB 0xF8000000
47#define PCIMSK_256MiB 0xF0000000
48#define PCIMSK_512MiB 0xE0000000
49#define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */
50
51
52#define M826X_SCCR_PCI_MODE_EN 0x100
53
54
55/*
56 * Outbound ATU registers (3 sets). These registers control how 60x bus (local)
57 * addresses are translated to PCI addresses when the MPC826x is a PCI bus
58 * master (initiator).
59 */
60
61#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
62#define POTAR_REG1 0x10818
63#define POTAR_REG2 0x10830
64
65#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
66#define POBAR_REG1 0x10820
67#define POBAR_REG2 0x10838
68
69#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
70#define POCMR_REG1 0x10828
71#define POCMR_REG2 0x10840
72
73/* Bit definitions for POMCR registers */
74
75#define POCMR_MASK_4KiB 0x000FFFFF
76#define POCMR_MASK_8KiB 0x000FFFFE
77#define POCMR_MASK_16KiB 0x000FFFFC
78#define POCMR_MASK_32KiB 0x000FFFF8
79#define POCMR_MASK_64KiB 0x000FFFF0
80#define POCMR_MASK_128KiB 0x000FFFE0
81#define POCMR_MASK_256KiB 0x000FFFC0
82#define POCMR_MASK_512KiB 0x000FFF80
83#define POCMR_MASK_1MiB 0x000FFF00
84#define POCMR_MASK_2MiB 0x000FFE00
85#define POCMR_MASK_4MiB 0x000FFC00
86#define POCMR_MASK_8MiB 0x000FF800
87#define POCMR_MASK_16MiB 0x000FF000
88#define POCMR_MASK_32MiB 0x000FE000
89#define POCMR_MASK_64MiB 0x000FC000
90#define POCMR_MASK_128MiB 0x000F8000
91#define POCMR_MASK_256MiB 0x000F0000
92#define POCMR_MASK_512MiB 0x000E0000
93#define POCMR_MASK_1GiB 0x000C0000
94
95#define POCMR_ENABLE 0x80000000
96#define POCMR_PCI_IO 0x40000000
97#define POCMR_PREFETCH_EN 0x20000000
98
99/* Soft PCI reset */
100
101#define PCI_GCR_REG 0x10880
102
103/* Bit definitions for PCI_GCR registers */
104
105#define PCIGCR_PCI_BUS_EN 0x1
106
107#define PCI_EMR_REG 0x10888
108/*
109 * Inbound ATU registers (2 sets). These registers control how PCI addresses
110 * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
111 */
112
113#define PITAR_REG1 0x108D0
114#define PIBAR_REG1 0x108D8
115#define PICMR_REG1 0x108E0
116#define PITAR_REG0 0x108E8
117#define PIBAR_REG0 0x108F0
118#define PICMR_REG0 0x108F8
119
120/* Bit definitions for PCI Inbound Comparison Mask registers */
121
122#define PICMR_MASK_4KiB 0x000FFFFF
123#define PICMR_MASK_8KiB 0x000FFFFE
124#define PICMR_MASK_16KiB 0x000FFFFC
125#define PICMR_MASK_32KiB 0x000FFFF8
126#define PICMR_MASK_64KiB 0x000FFFF0
127#define PICMR_MASK_128KiB 0x000FFFE0
128#define PICMR_MASK_256KiB 0x000FFFC0
129#define PICMR_MASK_512KiB 0x000FFF80
130#define PICMR_MASK_1MiB 0x000FFF00
131#define PICMR_MASK_2MiB 0x000FFE00
132#define PICMR_MASK_4MiB 0x000FFC00
133#define PICMR_MASK_8MiB 0x000FF800
134#define PICMR_MASK_16MiB 0x000FF000
135#define PICMR_MASK_32MiB 0x000FE000
136#define PICMR_MASK_64MiB 0x000FC000
137#define PICMR_MASK_128MiB 0x000F8000
138#define PICMR_MASK_256MiB 0x000F0000
139#define PICMR_MASK_512MiB 0x000E0000
140#define PICMR_MASK_1GiB 0x000C0000
141
142#define PICMR_ENABLE 0x80000000
143#define PICMR_NO_SNOOP_EN 0x40000000
144#define PICMR_PREFETCH_EN 0x20000000
145
146/* PCI error Registers */
147
148#define PCI_ERROR_STATUS_REG 0x10884
149#define PCI_ERROR_MASK_REG 0x10888
150#define PCI_ERROR_CONTROL_REG 0x1088C
151#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
152#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
153#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
154
155/* PCI error Register bit defines */
156
157#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
158#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
159#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
160#define PCI_ERROR_PCI_NO_RSP 0x00000008
161#define PCI_ERROR_PCI_TAR_ABT 0x00000010
162#define PCI_ERROR_PCI_SERR 0x00000020
163#define PCI_ERROR_PCI_PERR_RD 0x00000040
164#define PCI_ERROR_PCI_PERR_WR 0x00000080
165#define PCI_ERROR_I2O_OFQO 0x00000100
166#define PCI_ERROR_I2O_IPQO 0x00000200
167#define PCI_ERROR_IRA 0x00000400
168#define PCI_ERROR_NMI 0x00000800
169#define PCI_ERROR_I2O_DBMC 0x00001000
170
171/*
172 * Register pair used to generate configuration cycles on the PCI bus
173 * and access the MPC826x's own PCI configuration registers.
174 */
175
176#define PCI_CFG_ADDR_REG 0x10900
177#define PCI_CFG_DATA_REG 0x10904
178
179/* Bus parking decides where the bus control sits when idle */
180/* If modifying memory controllers for PCI park on the core */
181
182#define PPC_ACR_BUS_PARK_CORE 0x6
183#define PPC_ACR_BUS_PARK_PCI 0x3
184
185#endif /* __M8260_PCI_H */
186#endif /* __KERNEL__ */