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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-ppc/io.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-ppc/io.h')
-rw-r--r--include/asm-ppc/io.h566
1 files changed, 566 insertions, 0 deletions
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
new file mode 100644
index 000000000000..7eb7cf6360bd
--- /dev/null
+++ b/include/asm-ppc/io.h
@@ -0,0 +1,566 @@
1#ifdef __KERNEL__
2#ifndef _PPC_IO_H
3#define _PPC_IO_H
4
5#include <linux/config.h>
6#include <linux/string.h>
7#include <linux/types.h>
8
9#include <asm/page.h>
10#include <asm/byteorder.h>
11#include <asm/mmu.h>
12
13#define SIO_CONFIG_RA 0x398
14#define SIO_CONFIG_RD 0x399
15
16#define SLOW_DOWN_IO
17
18#define PMAC_ISA_MEM_BASE 0
19#define PMAC_PCI_DRAM_OFFSET 0
20#define CHRP_ISA_IO_BASE 0xf8000000
21#define CHRP_ISA_MEM_BASE 0xf7000000
22#define CHRP_PCI_DRAM_OFFSET 0
23#define PREP_ISA_IO_BASE 0x80000000
24#define PREP_ISA_MEM_BASE 0xc0000000
25#define PREP_PCI_DRAM_OFFSET 0x80000000
26
27#if defined(CONFIG_4xx)
28#include <asm/ibm4xx.h>
29#elif defined(CONFIG_8xx)
30#include <asm/mpc8xx.h>
31#elif defined(CONFIG_8260)
32#include <asm/mpc8260.h>
33#elif defined(CONFIG_83xx)
34#include <asm/mpc83xx.h>
35#elif defined(CONFIG_85xx)
36#include <asm/mpc85xx.h>
37#elif defined(CONFIG_APUS)
38#define _IO_BASE 0
39#define _ISA_MEM_BASE 0
40#define PCI_DRAM_OFFSET 0
41#else /* Everyone else */
42#define _IO_BASE isa_io_base
43#define _ISA_MEM_BASE isa_mem_base
44#define PCI_DRAM_OFFSET pci_dram_offset
45#endif /* Platform-dependent I/O */
46
47#define ___IO_BASE ((void __iomem *)_IO_BASE)
48extern unsigned long isa_io_base;
49extern unsigned long isa_mem_base;
50extern unsigned long pci_dram_offset;
51
52/*
53 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
54 *
55 * Read operations have additional twi & isync to make sure the read
56 * is actually performed (i.e. the data has come back) before we start
57 * executing any following instructions.
58 */
59extern inline int in_8(volatile unsigned char __iomem *addr)
60{
61 int ret;
62
63 __asm__ __volatile__(
64 "lbz%U1%X1 %0,%1;\n"
65 "twi 0,%0,0;\n"
66 "isync" : "=r" (ret) : "m" (*addr));
67 return ret;
68}
69
70extern inline void out_8(volatile unsigned char __iomem *addr, int val)
71{
72 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
73}
74
75extern inline int in_le16(volatile unsigned short __iomem *addr)
76{
77 int ret;
78
79 __asm__ __volatile__("lhbrx %0,0,%1;\n"
80 "twi 0,%0,0;\n"
81 "isync" : "=r" (ret) :
82 "r" (addr), "m" (*addr));
83 return ret;
84}
85
86extern inline int in_be16(volatile unsigned short __iomem *addr)
87{
88 int ret;
89
90 __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
91 "twi 0,%0,0;\n"
92 "isync" : "=r" (ret) : "m" (*addr));
93 return ret;
94}
95
96extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
97{
98 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
99 "r" (val), "r" (addr));
100}
101
102extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
103{
104 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
105}
106
107extern inline unsigned in_le32(volatile unsigned __iomem *addr)
108{
109 unsigned ret;
110
111 __asm__ __volatile__("lwbrx %0,0,%1;\n"
112 "twi 0,%0,0;\n"
113 "isync" : "=r" (ret) :
114 "r" (addr), "m" (*addr));
115 return ret;
116}
117
118extern inline unsigned in_be32(volatile unsigned __iomem *addr)
119{
120 unsigned ret;
121
122 __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
123 "twi 0,%0,0;\n"
124 "isync" : "=r" (ret) : "m" (*addr));
125 return ret;
126}
127
128extern inline void out_le32(volatile unsigned __iomem *addr, int val)
129{
130 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
131 "r" (val), "r" (addr));
132}
133
134extern inline void out_be32(volatile unsigned __iomem *addr, int val)
135{
136 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
137}
138#if defined (CONFIG_8260_PCI9)
139#define readb(addr) in_8((volatile u8 *)(addr))
140#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
141#else
142static inline __u8 readb(volatile void __iomem *addr)
143{
144 return in_8(addr);
145}
146static inline void writeb(__u8 b, volatile void __iomem *addr)
147{
148 out_8(addr, b);
149}
150#endif
151
152#if defined(CONFIG_APUS)
153static inline __u16 readw(volatile void __iomem *addr)
154{
155 return *(__force volatile __u16 *)(addr);
156}
157static inline __u32 readl(volatile void __iomem *addr)
158{
159 return *(__force volatile __u32 *)(addr);
160}
161static inline void writew(__u16 b, volatile void __iomem *addr)
162{
163 *(__force volatile __u16 *)(addr) = b;
164}
165static inline void writel(__u32 b, volatile void __iomem *addr)
166{
167 *(__force volatile __u32 *)(addr) = b;
168}
169#elif defined (CONFIG_8260_PCI9)
170/* Use macros if PCI9 workaround enabled */
171#define readw(addr) in_le16((volatile u16 *)(addr))
172#define readl(addr) in_le32((volatile u32 *)(addr))
173#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
174#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
175#else
176static inline __u16 readw(volatile void __iomem *addr)
177{
178 return in_le16(addr);
179}
180static inline __u32 readl(volatile void __iomem *addr)
181{
182 return in_le32(addr);
183}
184static inline void writew(__u16 b, volatile void __iomem *addr)
185{
186 out_le16(addr, b);
187}
188static inline void writel(__u32 b, volatile void __iomem *addr)
189{
190 out_le32(addr, b);
191}
192#endif /* CONFIG_APUS */
193
194#define readb_relaxed(addr) readb(addr)
195#define readw_relaxed(addr) readw(addr)
196#define readl_relaxed(addr) readl(addr)
197
198static inline __u8 __raw_readb(const volatile void __iomem *addr)
199{
200 return *(__force volatile __u8 *)(addr);
201}
202static inline __u16 __raw_readw(const volatile void __iomem *addr)
203{
204 return *(__force volatile __u16 *)(addr);
205}
206static inline __u32 __raw_readl(const volatile void __iomem *addr)
207{
208 return *(__force volatile __u32 *)(addr);
209}
210static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
211{
212 *(__force volatile __u8 *)(addr) = b;
213}
214static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
215{
216 *(__force volatile __u16 *)(addr) = b;
217}
218static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
219{
220 *(__force volatile __u32 *)(addr) = b;
221}
222
223#define mmiowb()
224
225/*
226 * The insw/outsw/insl/outsl macros don't do byte-swapping.
227 * They are only used in practice for transferring buffers which
228 * are arrays of bytes, and byte-swapping is not appropriate in
229 * that case. - paulus
230 */
231#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
232#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
233#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
234#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
235#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
236#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
237
238/*
239 * On powermacs, we will get a machine check exception if we
240 * try to read data from a non-existent I/O port. Because the
241 * machine check is an asynchronous exception, it isn't
242 * well-defined which instruction SRR0 will point to when the
243 * exception occurs.
244 * With the sequence below (twi; isync; nop), we have found that
245 * the machine check occurs on one of the three instructions on
246 * all PPC implementations tested so far. The twi and isync are
247 * needed on the 601 (in fact twi; sync works too), the isync and
248 * nop are needed on 604[e|r], and any of twi, sync or isync will
249 * work on 603[e], 750, 74xx.
250 * The twi creates an explicit data dependency on the returned
251 * value which seems to be needed to make the 601 wait for the
252 * load to finish.
253 */
254
255#define __do_in_asm(name, op) \
256extern __inline__ unsigned int name(unsigned int port) \
257{ \
258 unsigned int x; \
259 __asm__ __volatile__( \
260 op " %0,0,%1\n" \
261 "1: twi 0,%0,0\n" \
262 "2: isync\n" \
263 "3: nop\n" \
264 "4:\n" \
265 ".section .fixup,\"ax\"\n" \
266 "5: li %0,-1\n" \
267 " b 4b\n" \
268 ".previous\n" \
269 ".section __ex_table,\"a\"\n" \
270 " .align 2\n" \
271 " .long 1b,5b\n" \
272 " .long 2b,5b\n" \
273 " .long 3b,5b\n" \
274 ".previous" \
275 : "=&r" (x) \
276 : "r" (port + ___IO_BASE)); \
277 return x; \
278}
279
280#define __do_out_asm(name, op) \
281extern __inline__ void name(unsigned int val, unsigned int port) \
282{ \
283 __asm__ __volatile__( \
284 op " %0,0,%1\n" \
285 "1: sync\n" \
286 "2:\n" \
287 ".section __ex_table,\"a\"\n" \
288 " .align 2\n" \
289 " .long 1b,2b\n" \
290 ".previous" \
291 : : "r" (val), "r" (port + ___IO_BASE)); \
292}
293
294__do_out_asm(outb, "stbx")
295#ifdef CONFIG_APUS
296__do_in_asm(inb, "lbzx")
297__do_in_asm(inw, "lhz%U1%X1")
298__do_in_asm(inl, "lwz%U1%X1")
299__do_out_asm(outl,"stw%U0%X0")
300__do_out_asm(outw, "sth%U0%X0")
301#elif defined (CONFIG_8260_PCI9)
302/* in asm cannot be defined if PCI9 workaround is used */
303#define inb(port) in_8((port)+___IO_BASE)
304#define inw(port) in_le16((port)+___IO_BASE)
305#define inl(port) in_le32((port)+___IO_BASE)
306__do_out_asm(outw, "sthbrx")
307__do_out_asm(outl, "stwbrx")
308#else
309__do_in_asm(inb, "lbzx")
310__do_in_asm(inw, "lhbrx")
311__do_in_asm(inl, "lwbrx")
312__do_out_asm(outw, "sthbrx")
313__do_out_asm(outl, "stwbrx")
314
315#endif
316
317#define inb_p(port) inb((port))
318#define outb_p(val, port) outb((val), (port))
319#define inw_p(port) inw((port))
320#define outw_p(val, port) outw((val), (port))
321#define inl_p(port) inl((port))
322#define outl_p(val, port) outl((val), (port))
323
324extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
325extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
326extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
327extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
328extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
329extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
330extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
331extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
332extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
333extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
334
335/*
336 * The *_ns versions below don't do byte-swapping.
337 * Neither do the standard versions now, these are just here
338 * for older code.
339 */
340#define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
341#define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
342#define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
343#define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
344
345
346#define IO_SPACE_LIMIT ~0
347
348#if defined (CONFIG_8260_PCI9)
349#define memset_io(a,b,c) memset((void *)(a),(b),(c))
350#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
351#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
352#else
353static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
354{
355 memset((void __force *)addr, val, count);
356}
357static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
358{
359 memcpy(dst, (void __force *) src, count);
360}
361static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
362{
363 memcpy((void __force *) dst, src, count);
364}
365#endif
366
367#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
368
369/*
370 * Map in an area of physical address space, for accessing
371 * I/O devices etc.
372 */
373extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
374 unsigned long flags);
375extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
376#ifdef CONFIG_44x
377extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
378#endif
379#define ioremap_nocache(addr, size) ioremap((addr), (size))
380extern void iounmap(volatile void __iomem *addr);
381extern unsigned long iopa(unsigned long addr);
382extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
383extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
384 unsigned int size, int flags);
385
386/*
387 * The PCI bus is inherently Little-Endian. The PowerPC is being
388 * run Big-Endian. Thus all values which cross the [PCI] barrier
389 * must be endian-adjusted. Also, the local DRAM has a different
390 * address from the PCI point of view, thus buffer addresses also
391 * have to be modified [mapped] appropriately.
392 */
393extern inline unsigned long virt_to_bus(volatile void * address)
394{
395#ifndef CONFIG_APUS
396 if (address == (void *)0)
397 return 0;
398 return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
399#else
400 return iopa ((unsigned long) address);
401#endif
402}
403
404extern inline void * bus_to_virt(unsigned long address)
405{
406#ifndef CONFIG_APUS
407 if (address == 0)
408 return NULL;
409 return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
410#else
411 return (void*) mm_ptov (address);
412#endif
413}
414
415/*
416 * Change virtual addresses to physical addresses and vv, for
417 * addresses in the area where the kernel has the RAM mapped.
418 */
419extern inline unsigned long virt_to_phys(volatile void * address)
420{
421#ifndef CONFIG_APUS
422 return (unsigned long) address - KERNELBASE;
423#else
424 return iopa ((unsigned long) address);
425#endif
426}
427
428extern inline void * phys_to_virt(unsigned long address)
429{
430#ifndef CONFIG_APUS
431 return (void *) (address + KERNELBASE);
432#else
433 return (void*) mm_ptov (address);
434#endif
435}
436
437/*
438 * Change "struct page" to physical address.
439 */
440#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
441#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
442
443/*
444 * Enforce In-order Execution of I/O:
445 * Acts as a barrier to ensure all previous I/O accesses have
446 * completed before any further ones are issued.
447 */
448extern inline void eieio(void)
449{
450 __asm__ __volatile__ ("eieio" : : : "memory");
451}
452
453/* Enforce in-order execution of data I/O.
454 * No distinction between read/write on PPC; use eieio for all three.
455 */
456#define iobarrier_rw() eieio()
457#define iobarrier_r() eieio()
458#define iobarrier_w() eieio()
459
460static inline int check_signature(volatile void __iomem * io_addr,
461 const unsigned char *signature, int length)
462{
463 int retval = 0;
464 do {
465 if (readb(io_addr) != *signature)
466 goto out;
467 io_addr++;
468 signature++;
469 length--;
470 } while (length);
471 retval = 1;
472out:
473 return retval;
474}
475
476/*
477 * Here comes the ppc implementation of the IOMAP
478 * interfaces.
479 */
480static inline unsigned int ioread8(void __iomem *addr)
481{
482 return readb(addr);
483}
484
485static inline unsigned int ioread16(void __iomem *addr)
486{
487 return readw(addr);
488}
489
490static inline unsigned int ioread32(void __iomem *addr)
491{
492 return readl(addr);
493}
494
495static inline void iowrite8(u8 val, void __iomem *addr)
496{
497 writeb(val, addr);
498}
499
500static inline void iowrite16(u16 val, void __iomem *addr)
501{
502 writew(val, addr);
503}
504
505static inline void iowrite32(u32 val, void __iomem *addr)
506{
507 writel(val, addr);
508}
509
510static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
511{
512 _insb(addr, dst, count);
513}
514
515static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
516{
517 _insw_ns(addr, dst, count);
518}
519
520static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
521{
522 _insl_ns(addr, dst, count);
523}
524
525static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
526{
527 _outsb(addr, src, count);
528}
529
530static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
531{
532 _outsw_ns(addr, src, count);
533}
534
535static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
536{
537 _outsl_ns(addr, src, count);
538}
539
540/* Create a virtual mapping cookie for an IO port range */
541extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
542extern void ioport_unmap(void __iomem *);
543
544/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
545struct pci_dev;
546extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
547extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
548
549#endif /* _PPC_IO_H */
550
551#ifdef CONFIG_8260_PCI9
552#include <asm/mpc8260_pci9.h>
553#endif
554
555/*
556 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
557 * access
558 */
559#define xlate_dev_mem_ptr(p) __va(p)
560
561/*
562 * Convert a virtual cached pointer to an uncached pointer
563 */
564#define xlate_dev_kmem_ptr(p) p
565
566#endif /* __KERNEL__ */