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authorPaul Mackerras <paulus@samba.org>2006-09-13 08:08:26 -0400
committerPaul Mackerras <paulus@samba.org>2006-09-13 08:08:26 -0400
commitf007cacffc8870702a1473d83ba5e4922d54e17c (patch)
tree7faa1dbd7ccd2c4536f29852e0fedf7499d90508 /include/asm-ppc/io.h
parent2e8e8dacc566cc91cd8707cb092e76c7bbfab178 (diff)
[POWERPC] Fix MMIO ops to provide expected barrier behaviour
This changes the writeX family of functions to have a sync instruction before the MMIO store rather than after, because the generally expected behaviour is that the device receiving the MMIO store can be guaranteed to see the effects of any preceding writes to normal memory. To preserve ordering between writeX and readX, and to preserve ordering between preceding stores and the readX, the readX family of functions have had an sync added before the load. Although writeX followed by spin_unlock is not officially guaranteed to keep the writeX inside the spin-locked region unless an mmiowb() is used, there are currently drivers that depend on the previous behaviour on powerpc, which was that the mmiowb wasn't actually required. Therefore we have a per-cpu flag that is set by writeX, cleared by __raw_spin_lock and mmiowb, and tested by __raw_spin_unlock. If it is set, __raw_spin_unlock does a sync and clears it. This changes both 32-bit and 64-bit readX/writeX. 32-bit already has a sync in __raw_spin_unlock (since lwsync doesn't exist on 32-bit), and thus doesn't need the per-cpu flag. Tested on G5 (PPC970) and POWER5. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-ppc/io.h')
-rw-r--r--include/asm-ppc/io.h20
1 files changed, 11 insertions, 9 deletions
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 89c6f1bc3aab..680555be22ec 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -63,7 +63,7 @@ extern inline int in_8(const volatile unsigned char __iomem *addr)
63 int ret; 63 int ret;
64 64
65 __asm__ __volatile__( 65 __asm__ __volatile__(
66 "lbz%U1%X1 %0,%1;\n" 66 "sync; lbz%U1%X1 %0,%1;\n"
67 "twi 0,%0,0;\n" 67 "twi 0,%0,0;\n"
68 "isync" : "=r" (ret) : "m" (*addr)); 68 "isync" : "=r" (ret) : "m" (*addr));
69 return ret; 69 return ret;
@@ -78,7 +78,7 @@ extern inline int in_le16(const volatile unsigned short __iomem *addr)
78{ 78{
79 int ret; 79 int ret;
80 80
81 __asm__ __volatile__("lhbrx %0,0,%1;\n" 81 __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
82 "twi 0,%0,0;\n" 82 "twi 0,%0,0;\n"
83 "isync" : "=r" (ret) : 83 "isync" : "=r" (ret) :
84 "r" (addr), "m" (*addr)); 84 "r" (addr), "m" (*addr));
@@ -89,7 +89,7 @@ extern inline int in_be16(const volatile unsigned short __iomem *addr)
89{ 89{
90 int ret; 90 int ret;
91 91
92 __asm__ __volatile__("lhz%U1%X1 %0,%1;\n" 92 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
93 "twi 0,%0,0;\n" 93 "twi 0,%0,0;\n"
94 "isync" : "=r" (ret) : "m" (*addr)); 94 "isync" : "=r" (ret) : "m" (*addr));
95 return ret; 95 return ret;
@@ -97,20 +97,20 @@ extern inline int in_be16(const volatile unsigned short __iomem *addr)
97 97
98extern inline void out_le16(volatile unsigned short __iomem *addr, int val) 98extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
99{ 99{
100 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : 100 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
101 "r" (val), "r" (addr)); 101 "r" (val), "r" (addr));
102} 102}
103 103
104extern inline void out_be16(volatile unsigned short __iomem *addr, int val) 104extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
105{ 105{
106 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); 106 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
107} 107}
108 108
109extern inline unsigned in_le32(const volatile unsigned __iomem *addr) 109extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
110{ 110{
111 unsigned ret; 111 unsigned ret;
112 112
113 __asm__ __volatile__("lwbrx %0,0,%1;\n" 113 __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
114 "twi 0,%0,0;\n" 114 "twi 0,%0,0;\n"
115 "isync" : "=r" (ret) : 115 "isync" : "=r" (ret) :
116 "r" (addr), "m" (*addr)); 116 "r" (addr), "m" (*addr));
@@ -121,7 +121,7 @@ extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
121{ 121{
122 unsigned ret; 122 unsigned ret;
123 123
124 __asm__ __volatile__("lwz%U1%X1 %0,%1;\n" 124 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
125 "twi 0,%0,0;\n" 125 "twi 0,%0,0;\n"
126 "isync" : "=r" (ret) : "m" (*addr)); 126 "isync" : "=r" (ret) : "m" (*addr));
127 return ret; 127 return ret;
@@ -129,13 +129,13 @@ extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
129 129
130extern inline void out_le32(volatile unsigned __iomem *addr, int val) 130extern inline void out_le32(volatile unsigned __iomem *addr, int val)
131{ 131{
132 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : 132 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
133 "r" (val), "r" (addr)); 133 "r" (val), "r" (addr));
134} 134}
135 135
136extern inline void out_be32(volatile unsigned __iomem *addr, int val) 136extern inline void out_be32(volatile unsigned __iomem *addr, int val)
137{ 137{
138 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); 138 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
139} 139}
140#if defined (CONFIG_8260_PCI9) 140#if defined (CONFIG_8260_PCI9)
141#define readb(addr) in_8((volatile u8 *)(addr)) 141#define readb(addr) in_8((volatile u8 *)(addr))
@@ -259,6 +259,7 @@ extern __inline__ unsigned int name(unsigned int port) \
259{ \ 259{ \
260 unsigned int x; \ 260 unsigned int x; \
261 __asm__ __volatile__( \ 261 __asm__ __volatile__( \
262 "sync\n" \
262 "0:" op " %0,0,%1\n" \ 263 "0:" op " %0,0,%1\n" \
263 "1: twi 0,%0,0\n" \ 264 "1: twi 0,%0,0\n" \
264 "2: isync\n" \ 265 "2: isync\n" \
@@ -284,6 +285,7 @@ extern __inline__ unsigned int name(unsigned int port) \
284extern __inline__ void name(unsigned int val, unsigned int port) \ 285extern __inline__ void name(unsigned int val, unsigned int port) \
285{ \ 286{ \
286 __asm__ __volatile__( \ 287 __asm__ __volatile__( \
288 "sync\n" \
287 "0:" op " %0,0,%1\n" \ 289 "0:" op " %0,0,%1\n" \
288 "1: sync\n" \ 290 "1: sync\n" \
289 "2:\n" \ 291 "2:\n" \