[PATCH] ppc32: Support 36-bit physical addressing on e500

To add support for 36-bit physical addressing on e500 the following changes
have been made.  The changes are generalized to support any physical address
size larger than 32-bits:

* Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits
  of flags.

* Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of
  updating hardware register (SPRN_MAS7) which holds the upper 32-bits of
  physical address that will be written into the TLB.  This is useful since
  not all e500 cores support 36-bit physical addressing.

* Currently have a pass through implementation of fixup_bigphys_addr

* Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional
  storage attributes that may exist in future FSL Book-E cores and updated
  fault handler to copy these bits into the hardware TLBs.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 2 insertions, 1 deletions

diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
index 22de04fe1b4c..41d8f8425c04 100644
--- a/include/asm-ppc/cputable.h
+++ b/include/asm-ppc/cputable.h
@@ -86,8 +86,9 @@ static inline unsigned int cpu_has_feature(unsigned int feature)
 #define CPU_FTR_DUAL_PLL_750FX          0x00004000
 #define CPU_FTR_NO_DPM                  0x00008000
 #define CPU_FTR_HAS_HIGH_BATS           0x00010000
-#define CPU_FTR_NEED_COHERENT           0x00020000
+#define CPU_FTR_NEED_COHERENT           0x00020000
 #define CPU_FTR_NO_BTIC                 0x00040000
+#define CPU_FTR_BIG_PHYS                0x00080000
 
 #ifdef __ASSEMBLY__