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authorDavid Howells <dhowells@redhat.com>2006-12-05 12:01:28 -0500
committerDavid Howells <dhowells@warthog.cambridge.redhat.com>2006-12-05 12:01:28 -0500
commit9db73724453a9350e1c22dbe732d427e2939a5c9 (patch)
tree15e3ead6413ae97398a54292acc199bee0864d42 /include/asm-powerpc
parent4c1ac1b49122b805adfa4efc620592f68dccf5db (diff)
parente62438630ca37539c8cc1553710bbfaa3cf960a7 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/ata/libata-scsi.c include/linux/libata.h Futher merge of Linus's head and compilation fixups. Signed-Off-By: David Howells <dhowells@redhat.com>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/Kbuild1
-rw-r--r--include/asm-powerpc/cell-pmu.h113
-rw-r--r--include/asm-powerpc/cputable.h31
-rw-r--r--include/asm-powerpc/dbdma.h8
-rw-r--r--include/asm-powerpc/dcr-mmio.h51
-rw-r--r--include/asm-powerpc/dcr-native.h39
-rw-r--r--include/asm-powerpc/dcr.h42
-rw-r--r--include/asm-powerpc/device.h19
-rw-r--r--include/asm-powerpc/dma-mapping.h182
-rw-r--r--include/asm-powerpc/eeh.h213
-rw-r--r--include/asm-powerpc/elf.h13
-rw-r--r--include/asm-powerpc/firmware.h17
-rw-r--r--include/asm-powerpc/hw_irq.h44
-rw-r--r--include/asm-powerpc/ibmebus.h1
-rw-r--r--include/asm-powerpc/ide.h8
-rw-r--r--include/asm-powerpc/immap_qe.h17
-rw-r--r--include/asm-powerpc/io-defs.h59
-rw-r--r--include/asm-powerpc/io.h845
-rw-r--r--include/asm-powerpc/iommu.h34
-rw-r--r--include/asm-powerpc/irq.h4
-rw-r--r--include/asm-powerpc/iseries/iommu.h4
-rw-r--r--include/asm-powerpc/lv1call.h345
-rw-r--r--include/asm-powerpc/machdep.h18
-rw-r--r--include/asm-powerpc/mmu.h15
-rw-r--r--include/asm-powerpc/mpc52xx.h254
-rw-r--r--include/asm-powerpc/mpc85xx.h8
-rw-r--r--include/asm-powerpc/mpic.h39
-rw-r--r--include/asm-powerpc/of_device.h36
-rw-r--r--include/asm-powerpc/of_platform.h60
-rw-r--r--include/asm-powerpc/oprofile_impl.h3
-rw-r--r--include/asm-powerpc/paca.h3
-rw-r--r--include/asm-powerpc/pci-bridge.h1
-rw-r--r--include/asm-powerpc/pci.h10
-rw-r--r--include/asm-powerpc/ppc-pci.h13
-rw-r--r--include/asm-powerpc/processor.h4
-rw-r--r--include/asm-powerpc/prom.h15
-rw-r--r--include/asm-powerpc/ps3.h462
-rw-r--r--include/asm-powerpc/rtas.h2
-rw-r--r--include/asm-powerpc/sparsemem.h6
-rw-r--r--include/asm-powerpc/spu.h30
-rw-r--r--include/asm-powerpc/spu_csa.h1
-rw-r--r--include/asm-powerpc/spu_info.h54
-rw-r--r--include/asm-powerpc/spu_priv1.h46
-rw-r--r--include/asm-powerpc/todc.h487
-rw-r--r--include/asm-powerpc/topology.h7
-rw-r--r--include/asm-powerpc/tsi108.h4
-rw-r--r--include/asm-powerpc/types.h10
-rw-r--r--include/asm-powerpc/uaccess.h4
-rw-r--r--include/asm-powerpc/unistd.h12
-rw-r--r--include/asm-powerpc/vio.h1
-rw-r--r--include/asm-powerpc/xmon.h2
51 files changed, 2524 insertions, 1173 deletions
diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index 9827849953a3..1e637381c118 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -17,6 +17,7 @@ header-y += ipc.h
17header-y += poll.h 17header-y += poll.h
18header-y += shmparam.h 18header-y += shmparam.h
19header-y += sockios.h 19header-y += sockios.h
20header-y += spu_info.h
20header-y += ucontext.h 21header-y += ucontext.h
21header-y += ioctl.h 22header-y += ioctl.h
22header-y += linkage.h 23header-y += linkage.h
diff --git a/include/asm-powerpc/cell-pmu.h b/include/asm-powerpc/cell-pmu.h
new file mode 100644
index 000000000000..e8c2ebd3ddda
--- /dev/null
+++ b/include/asm-powerpc/cell-pmu.h
@@ -0,0 +1,113 @@
1/*
2 * Cell Broadband Engine Performance Monitor
3 *
4 * (C) Copyright IBM Corporation 2006
5 *
6 * Author:
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ASM_CELL_PMU_H__
26#define __ASM_CELL_PMU_H__
27
28/* The Cell PMU has four hardware performance counters, which can be
29 * configured as four 32-bit counters or eight 16-bit counters.
30 */
31#define NR_PHYS_CTRS 4
32#define NR_CTRS (NR_PHYS_CTRS * 2)
33
34/* Macros for the pm_control register. */
35#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
36#define CBE_PM_ENABLE_PERF_MON 0x80000000
37#define CBE_PM_STOP_AT_MAX 0x40000000
38#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
39#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
40#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
41#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
42#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
43
44/* Macros for the trace_address register. */
45#define CBE_PM_TRACE_BUF_FULL 0x00000800
46#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
47#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
48#define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
49
50/* Macros for the pm07_control registers. */
51#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
52#define CBE_PM_CTR_INPUT_CONTROL 0x02000000
53#define CBE_PM_CTR_POLARITY 0x01000000
54#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
55#define CBE_PM_CTR_ENABLE 0x00400000
56
57/* Macros for the pm_status register. */
58#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
59
60enum pm_reg_name {
61 group_control,
62 debug_bus_control,
63 trace_address,
64 ext_tr_timer,
65 pm_status,
66 pm_control,
67 pm_interval,
68 pm_start_stop,
69};
70
71/* Routines for reading/writing the PMU registers. */
72extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
73extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
74extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
75extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
76
77extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
78extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
79extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
80extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
81
82extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
83extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
84
85extern void cbe_enable_pm(u32 cpu);
86extern void cbe_disable_pm(u32 cpu);
87
88extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
89
90extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
91extern void cbe_disable_pm_interrupts(u32 cpu);
92extern u32 cbe_query_pm_interrupts(u32 cpu);
93extern u32 cbe_clear_pm_interrupts(u32 cpu);
94extern void cbe_sync_irq(int node);
95
96/* Utility functions, macros */
97extern u32 cbe_get_hw_thread_id(int cpu);
98
99#define cbe_cpu_to_node(cpu) ((cpu) >> 1)
100
101#define CBE_COUNT_SUPERVISOR_MODE 0
102#define CBE_COUNT_HYPERVISOR_MODE 1
103#define CBE_COUNT_PROBLEM_MODE 2
104#define CBE_COUNT_ALL_MODES 3
105
106/* Macros for the pm07_control registers. */
107#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
108#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
109#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
110#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
111#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
112
113#endif /* __ASM_CELL_PMU_H__ */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index a9a40149a7c0..6fe5c9d4ca3b 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -24,6 +24,8 @@
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25#define PPC_FEATURE_ARCH_2_05 0x00001000 25#define PPC_FEATURE_ARCH_2_05 0x00001000
26#define PPC_FEATURE_PA6T 0x00000800 26#define PPC_FEATURE_PA6T 0x00000800
27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
27 29
28#define PPC_FEATURE_TRUE_LE 0x00000002 30#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001 31#define PPC_FEATURE_PPC_LE 0x00000001
@@ -45,6 +47,7 @@ enum powerpc_oprofile_type {
45 PPC_OPROFILE_POWER4 = 2, 47 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_G4 = 3, 48 PPC_OPROFILE_G4 = 3,
47 PPC_OPROFILE_BOOKE = 4, 49 PPC_OPROFILE_BOOKE = 4,
50 PPC_OPROFILE_CELL = 5,
48}; 51};
49 52
50struct cpu_spec { 53struct cpu_spec {
@@ -91,7 +94,7 @@ extern struct cpu_spec *cur_cpu_spec;
91 94
92extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 95extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
93 96
94extern struct cpu_spec *identify_cpu(unsigned long offset); 97extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
95extern void do_feature_fixups(unsigned long value, void *fixup_start, 98extern void do_feature_fixups(unsigned long value, void *fixup_start,
96 void *fixup_end); 99 void *fixup_end);
97 100
@@ -148,19 +151,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
148#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 151#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
149#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 152#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
150#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 153#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
154#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
151 155
152#ifndef __ASSEMBLY__ 156#ifndef __ASSEMBLY__
153 157
154#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ 158#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
155 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ 159 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
156 CPU_FTR_NODSISRALIGN) 160 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
157
158/* iSeries doesn't support large pages */
159#ifdef CONFIG_PPC_ISERIES
160#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
161#else
162#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
163#endif /* CONFIG_PPC_ISERIES */
164 161
165/* We only set the altivec features if the kernel was compiled with altivec 162/* We only set the altivec features if the kernel was compiled with altivec
166 * support 163 * support
@@ -311,7 +308,8 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
311#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 308#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
312 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) 309 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
313#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 310#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
314#ifdef __powerpc64__ 311
312/* 64-bit CPUs */
315#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 313#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
316 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) 314 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
317#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 315#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
@@ -332,7 +330,13 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
332 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
333 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 331 CPU_FTR_MMCRA | CPU_FTR_SMT | \
334 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 332 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
335 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) 333 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
334#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
336 CPU_FTR_MMCRA | CPU_FTR_SMT | \
337 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
338 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
339 CPU_FTR_SPURR | CPU_FTR_REAL_LE)
336#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 340#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
337 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
338 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 342 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -343,7 +347,6 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
343 CPU_FTR_PURR | CPU_FTR_REAL_LE) 347 CPU_FTR_PURR | CPU_FTR_REAL_LE)
344#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ 348#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) 349 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
346#endif
347 350
348#ifdef __powerpc64__ 351#ifdef __powerpc64__
349#define CPU_FTRS_POSSIBLE \ 352#define CPU_FTRS_POSSIBLE \
diff --git a/include/asm-powerpc/dbdma.h b/include/asm-powerpc/dbdma.h
index 8973565f95d3..e23f07e73cb3 100644
--- a/include/asm-powerpc/dbdma.h
+++ b/include/asm-powerpc/dbdma.h
@@ -95,7 +95,13 @@ struct dbdma_cmd {
95#define DBDMA_DO_STOP(regs) do { \ 95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ 96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \ 97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \ 98 ; \
99} while(0)
100
101#define DBDMA_DO_RESET(regs) do { \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
103 while(in_le32(&((regs)->status)) & (RUN)) \
104 ; \
99} while(0) 105} while(0)
100 106
101#endif /* _ASM_DBDMA_H_ */ 107#endif /* _ASM_DBDMA_H_ */
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h
new file mode 100644
index 000000000000..5dbfca8dde36
--- /dev/null
+++ b/include/asm-powerpc/dcr-mmio.h
@@ -0,0 +1,51 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_MMIO_H
21#define _ASM_POWERPC_DCR_MMIO_H
22#ifdef __KERNEL__
23
24#include <asm/io.h>
25
26typedef struct { void __iomem *token; unsigned int stride; } dcr_host_t;
27
28#define DCR_MAP_OK(host) ((host).token != NULL)
29
30extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
31 unsigned int dcr_c);
32extern void dcr_unmap(dcr_host_t host, unsigned int dcr_n, unsigned int dcr_c);
33
34static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
35{
36 return in_be32(host.token + dcr_n * host.stride);
37}
38
39static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
40{
41 out_be32(host.token + dcr_n * host.stride, value);
42}
43
44extern u64 of_translate_dcr_address(struct device_node *dev,
45 unsigned int dcr_n,
46 unsigned int *stride);
47
48#endif /* __KERNEL__ */
49#endif /* _ASM_POWERPC_DCR_MMIO_H */
50
51
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
new file mode 100644
index 000000000000..fd4a5f5e33d1
--- /dev/null
+++ b/include/asm-powerpc/dcr-native.h
@@ -0,0 +1,39 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_NATIVE_H
21#define _ASM_POWERPC_DCR_NATIVE_H
22#ifdef __KERNEL__
23
24#include <asm/reg.h>
25
26typedef struct {} dcr_host_t;
27
28#define DCR_MAP_OK(host) (1)
29
30#define dcr_map(dev, dcr_n, dcr_c) {}
31#define dcr_unmap(host, dcr_n, dcr_c) {}
32#define dcr_read(host, dcr_n) mfdcr(dcr_n)
33#define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value)
34
35
36#endif /* __KERNEL__ */
37#endif /* _ASM_POWERPC_DCR_NATIVE_H */
38
39
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
new file mode 100644
index 000000000000..473f2c7fd892
--- /dev/null
+++ b/include/asm-powerpc/dcr.h
@@ -0,0 +1,42 @@
1/*
2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13 * the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_POWERPC_DCR_H
21#define _ASM_POWERPC_DCR_H
22#ifdef __KERNEL__
23
24#ifdef CONFIG_PPC_DCR_NATIVE
25#include <asm/dcr-native.h>
26#else
27#include <asm/dcr-mmio.h>
28#endif
29
30/*
31 * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
32 * base from the device-tree
33 */
34#ifdef CONFIG_PPC_MERGE
35extern unsigned int dcr_resource_start(struct device_node *np,
36 unsigned int index);
37extern unsigned int dcr_resource_len(struct device_node *np,
38 unsigned int index);
39#endif /* CONFIG_PPC_MERGE */
40
41#endif /* __KERNEL__ */
42#endif /* _ASM_POWERPC_DCR_H */
diff --git a/include/asm-powerpc/device.h b/include/asm-powerpc/device.h
index d8f9872b0e2d..228ab2a315b9 100644
--- a/include/asm-powerpc/device.h
+++ b/include/asm-powerpc/device.h
@@ -3,5 +3,22 @@
3 * 3 *
4 * This file is released under the GPLv2 4 * This file is released under the GPLv2
5 */ 5 */
6#include <asm-generic/device.h> 6#ifndef _ASM_POWERPC_DEVICE_H
7#define _ASM_POWERPC_DEVICE_H
7 8
9struct dma_mapping_ops;
10struct device_node;
11
12struct dev_archdata {
13 /* Optional pointer to an OF device node */
14 struct device_node *of_node;
15
16 /* DMA operations on that device */
17 struct dma_mapping_ops *dma_ops;
18 void *dma_data;
19
20 /* NUMA node if applicable */
21 int numa_node;
22};
23
24#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index 2ab9baf78bb4..7e38b5fddada 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -44,26 +44,150 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
44#endif /* ! CONFIG_NOT_COHERENT_CACHE */ 44#endif /* ! CONFIG_NOT_COHERENT_CACHE */
45 45
46#ifdef CONFIG_PPC64 46#ifdef CONFIG_PPC64
47/*
48 * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
49 */
50struct dma_mapping_ops {
51 void * (*alloc_coherent)(struct device *dev, size_t size,
52 dma_addr_t *dma_handle, gfp_t flag);
53 void (*free_coherent)(struct device *dev, size_t size,
54 void *vaddr, dma_addr_t dma_handle);
55 dma_addr_t (*map_single)(struct device *dev, void *ptr,
56 size_t size, enum dma_data_direction direction);
57 void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
58 size_t size, enum dma_data_direction direction);
59 int (*map_sg)(struct device *dev, struct scatterlist *sg,
60 int nents, enum dma_data_direction direction);
61 void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
62 int nents, enum dma_data_direction direction);
63 int (*dma_supported)(struct device *dev, u64 mask);
64 int (*dac_dma_supported)(struct device *dev, u64 mask);
65 int (*set_dma_mask)(struct device *dev, u64 dma_mask);
66};
67
68static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
69{
70 /* We don't handle the NULL dev case for ISA for now. We could
71 * do it via an out of line call but it is not needed for now. The
72 * only ISA DMA device we support is the floppy and we have a hack
73 * in the floppy driver directly to get a device for us.
74 */
75 if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
76 return NULL;
77 return dev->archdata.dma_ops;
78}
47 79
48extern int dma_supported(struct device *dev, u64 mask); 80static inline int dma_supported(struct device *dev, u64 mask)
49extern int dma_set_mask(struct device *dev, u64 dma_mask); 81{
50extern void *dma_alloc_coherent(struct device *dev, size_t size, 82 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
51 dma_addr_t *dma_handle, gfp_t flag); 83
52extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, 84 if (unlikely(dma_ops == NULL))
53 dma_addr_t dma_handle); 85 return 0;
54extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, 86 if (dma_ops->dma_supported == NULL)
55 size_t size, enum dma_data_direction direction); 87 return 1;
56extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, 88 return dma_ops->dma_supported(dev, mask);
57 size_t size, enum dma_data_direction direction); 89}
58extern dma_addr_t dma_map_page(struct device *dev, struct page *page, 90
59 unsigned long offset, size_t size, 91static inline int dma_set_mask(struct device *dev, u64 dma_mask)
60 enum dma_data_direction direction); 92{
61extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, 93 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
62 size_t size, enum dma_data_direction direction); 94
63extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, 95 if (unlikely(dma_ops == NULL))
64 enum dma_data_direction direction); 96 return -EIO;
65extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 97 if (dma_ops->set_dma_mask != NULL)
66 int nhwentries, enum dma_data_direction direction); 98 return dma_ops->set_dma_mask(dev, dma_mask);
99 if (!dev->dma_mask || !dma_supported(dev, *dev->dma_mask))
100 return -EIO;
101 *dev->dma_mask = dma_mask;
102 return 0;
103}
104
105static inline void *dma_alloc_coherent(struct device *dev, size_t size,
106 dma_addr_t *dma_handle, gfp_t flag)
107{
108 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
109
110 BUG_ON(!dma_ops);
111 return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
112}
113
114static inline void dma_free_coherent(struct device *dev, size_t size,
115 void *cpu_addr, dma_addr_t dma_handle)
116{
117 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
118
119 BUG_ON(!dma_ops);
120 dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
121}
122
123static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
124 size_t size,
125 enum dma_data_direction direction)
126{
127 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
128
129 BUG_ON(!dma_ops);
130 return dma_ops->map_single(dev, cpu_addr, size, direction);
131}
132
133static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
134 size_t size,
135 enum dma_data_direction direction)
136{
137 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
138
139 BUG_ON(!dma_ops);
140 dma_ops->unmap_single(dev, dma_addr, size, direction);
141}
142
143static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
144 unsigned long offset, size_t size,
145 enum dma_data_direction direction)
146{
147 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
148
149 BUG_ON(!dma_ops);
150 return dma_ops->map_single(dev, page_address(page) + offset, size,
151 direction);
152}
153
154static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
155 size_t size,
156 enum dma_data_direction direction)
157{
158 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
159
160 BUG_ON(!dma_ops);
161 dma_ops->unmap_single(dev, dma_address, size, direction);
162}
163
164static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
165 int nents, enum dma_data_direction direction)
166{
167 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
168
169 BUG_ON(!dma_ops);
170 return dma_ops->map_sg(dev, sg, nents, direction);
171}
172
173static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
174 int nhwentries,
175 enum dma_data_direction direction)
176{
177 struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
178
179 BUG_ON(!dma_ops);
180 dma_ops->unmap_sg(dev, sg, nhwentries, direction);
181}
182
183
184/*
185 * Available generic sets of operations
186 */
187extern struct dma_mapping_ops dma_iommu_ops;
188extern struct dma_mapping_ops dma_direct_ops;
189
190extern unsigned long dma_direct_offset;
67 191
68#else /* CONFIG_PPC64 */ 192#else /* CONFIG_PPC64 */
69 193
@@ -261,25 +385,5 @@ static inline void dma_cache_sync(void *vaddr, size_t size,
261 __dma_sync(vaddr, size, (int)direction); 385 __dma_sync(vaddr, size, (int)direction);
262} 386}
263 387
264/*
265 * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
266 */
267struct dma_mapping_ops {
268 void * (*alloc_coherent)(struct device *dev, size_t size,
269 dma_addr_t *dma_handle, gfp_t flag);
270 void (*free_coherent)(struct device *dev, size_t size,
271 void *vaddr, dma_addr_t dma_handle);
272 dma_addr_t (*map_single)(struct device *dev, void *ptr,
273 size_t size, enum dma_data_direction direction);
274 void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
275 size_t size, enum dma_data_direction direction);
276 int (*map_sg)(struct device *dev, struct scatterlist *sg,
277 int nents, enum dma_data_direction direction);
278 void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
279 int nents, enum dma_data_direction direction);
280 int (*dma_supported)(struct device *dev, u64 mask);
281 int (*dac_dma_supported)(struct device *dev, u64 mask);
282};
283
284#endif /* __KERNEL__ */ 388#endif /* __KERNEL__ */
285#endif /* _ASM_DMA_MAPPING_H */ 389#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-powerpc/eeh.h b/include/asm-powerpc/eeh.h
index 6a784396660b..b886bec67016 100644
--- a/include/asm-powerpc/eeh.h
+++ b/include/asm-powerpc/eeh.h
@@ -120,10 +120,6 @@ static inline u8 eeh_readb(const volatile void __iomem *addr)
120 return eeh_check_failure(addr, val); 120 return eeh_check_failure(addr, val);
121 return val; 121 return val;
122} 122}
123static inline void eeh_writeb(u8 val, volatile void __iomem *addr)
124{
125 out_8(addr, val);
126}
127 123
128static inline u16 eeh_readw(const volatile void __iomem *addr) 124static inline u16 eeh_readw(const volatile void __iomem *addr)
129{ 125{
@@ -132,21 +128,6 @@ static inline u16 eeh_readw(const volatile void __iomem *addr)
132 return eeh_check_failure(addr, val); 128 return eeh_check_failure(addr, val);
133 return val; 129 return val;
134} 130}
135static inline void eeh_writew(u16 val, volatile void __iomem *addr)
136{
137 out_le16(addr, val);
138}
139static inline u16 eeh_raw_readw(const volatile void __iomem *addr)
140{
141 u16 val = in_be16(addr);
142 if (EEH_POSSIBLE_ERROR(val, u16))
143 return eeh_check_failure(addr, val);
144 return val;
145}
146static inline void eeh_raw_writew(u16 val, volatile void __iomem *addr) {
147 volatile u16 __iomem *vaddr = (volatile u16 __iomem *) addr;
148 out_be16(vaddr, val);
149}
150 131
151static inline u32 eeh_readl(const volatile void __iomem *addr) 132static inline u32 eeh_readl(const volatile void __iomem *addr)
152{ 133{
@@ -155,205 +136,75 @@ static inline u32 eeh_readl(const volatile void __iomem *addr)
155 return eeh_check_failure(addr, val); 136 return eeh_check_failure(addr, val);
156 return val; 137 return val;
157} 138}
158static inline void eeh_writel(u32 val, volatile void __iomem *addr) 139
159{ 140static inline u64 eeh_readq(const volatile void __iomem *addr)
160 out_le32(addr, val);
161}
162static inline u32 eeh_raw_readl(const volatile void __iomem *addr)
163{ 141{
164 u32 val = in_be32(addr); 142 u64 val = in_le64(addr);
165 if (EEH_POSSIBLE_ERROR(val, u32)) 143 if (EEH_POSSIBLE_ERROR(val, u64))
166 return eeh_check_failure(addr, val); 144 return eeh_check_failure(addr, val);
167 return val; 145 return val;
168} 146}
169static inline void eeh_raw_writel(u32 val, volatile void __iomem *addr)
170{
171 out_be32(addr, val);
172}
173 147
174static inline u64 eeh_readq(const volatile void __iomem *addr) 148static inline u16 eeh_readw_be(const volatile void __iomem *addr)
175{ 149{
176 u64 val = in_le64(addr); 150 u16 val = in_be16(addr);
177 if (EEH_POSSIBLE_ERROR(val, u64)) 151 if (EEH_POSSIBLE_ERROR(val, u16))
178 return eeh_check_failure(addr, val); 152 return eeh_check_failure(addr, val);
179 return val; 153 return val;
180} 154}
181static inline void eeh_writeq(u64 val, volatile void __iomem *addr) 155
156static inline u32 eeh_readl_be(const volatile void __iomem *addr)
182{ 157{
183 out_le64(addr, val); 158 u32 val = in_be32(addr);
159 if (EEH_POSSIBLE_ERROR(val, u32))
160 return eeh_check_failure(addr, val);
161 return val;
184} 162}
185static inline u64 eeh_raw_readq(const volatile void __iomem *addr) 163
164static inline u64 eeh_readq_be(const volatile void __iomem *addr)
186{ 165{
187 u64 val = in_be64(addr); 166 u64 val = in_be64(addr);
188 if (EEH_POSSIBLE_ERROR(val, u64)) 167 if (EEH_POSSIBLE_ERROR(val, u64))
189 return eeh_check_failure(addr, val); 168 return eeh_check_failure(addr, val);
190 return val; 169 return val;
191} 170}
192static inline void eeh_raw_writeq(u64 val, volatile void __iomem *addr)
193{
194 out_be64(addr, val);
195}
196
197#define EEH_CHECK_ALIGN(v,a) \
198 ((((unsigned long)(v)) & ((a) - 1)) == 0)
199 171
200static inline void eeh_memset_io(volatile void __iomem *addr, int c, 172static inline void eeh_memcpy_fromio(void *dest, const
201 unsigned long n) 173 volatile void __iomem *src,
202{
203 void *p = (void __force *)addr;
204 u32 lc = c;
205 lc |= lc << 8;
206 lc |= lc << 16;
207
208 __asm__ __volatile__ ("sync" : : : "memory");
209 while(n && !EEH_CHECK_ALIGN(p, 4)) {
210 *((volatile u8 *)p) = c;
211 p++;
212 n--;
213 }
214 while(n >= 4) {
215 *((volatile u32 *)p) = lc;
216 p += 4;
217 n -= 4;
218 }
219 while(n) {
220 *((volatile u8 *)p) = c;
221 p++;
222 n--;
223 }
224 __asm__ __volatile__ ("sync" : : : "memory");
225}
226static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *src,
227 unsigned long n) 174 unsigned long n)
228{ 175{
229 void *vsrc = (void __force *) src; 176 _memcpy_fromio(dest, src, n);
230 void *destsave = dest;
231 unsigned long nsave = n;
232
233 __asm__ __volatile__ ("sync" : : : "memory");
234 while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
235 *((u8 *)dest) = *((volatile u8 *)vsrc);
236 __asm__ __volatile__ ("eieio" : : : "memory");
237 vsrc++;
238 dest++;
239 n--;
240 }
241 while(n > 4) {
242 *((u32 *)dest) = *((volatile u32 *)vsrc);
243 __asm__ __volatile__ ("eieio" : : : "memory");
244 vsrc += 4;
245 dest += 4;
246 n -= 4;
247 }
248 while(n) {
249 *((u8 *)dest) = *((volatile u8 *)vsrc);
250 __asm__ __volatile__ ("eieio" : : : "memory");
251 vsrc++;
252 dest++;
253 n--;
254 }
255 __asm__ __volatile__ ("sync" : : : "memory");
256 177
257 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 178 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
258 * were copied. Check all four bytes. 179 * were copied. Check all four bytes.
259 */ 180 */
260 if ((nsave >= 4) && 181 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
261 (EEH_POSSIBLE_ERROR((*((u32 *) destsave+nsave-4)), u32))) { 182 eeh_check_failure(src, *((u32 *)(dest + n - 4)));
262 eeh_check_failure(src, (*((u32 *) destsave+nsave-4)));
263 }
264}
265
266static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
267 unsigned long n)
268{
269 void *vdest = (void __force *) dest;
270
271 __asm__ __volatile__ ("sync" : : : "memory");
272 while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
273 *((volatile u8 *)vdest) = *((u8 *)src);
274 src++;
275 vdest++;
276 n--;
277 }
278 while(n > 4) {
279 *((volatile u32 *)vdest) = *((volatile u32 *)src);
280 src += 4;
281 vdest += 4;
282 n-=4;
283 }
284 while(n) {
285 *((volatile u8 *)vdest) = *((u8 *)src);
286 src++;
287 vdest++;
288 n--;
289 }
290 __asm__ __volatile__ ("sync" : : : "memory");
291}
292
293#undef EEH_CHECK_ALIGN
294
295static inline u8 eeh_inb(unsigned long port)
296{
297 u8 val;
298 val = in_8((u8 __iomem *)(port+pci_io_base));
299 if (EEH_POSSIBLE_ERROR(val, u8))
300 return eeh_check_failure((void __iomem *)(port), val);
301 return val;
302}
303
304static inline void eeh_outb(u8 val, unsigned long port)
305{
306 out_8((u8 __iomem *)(port+pci_io_base), val);
307}
308
309static inline u16 eeh_inw(unsigned long port)
310{
311 u16 val;
312 val = in_le16((u16 __iomem *)(port+pci_io_base));
313 if (EEH_POSSIBLE_ERROR(val, u16))
314 return eeh_check_failure((void __iomem *)(port), val);
315 return val;
316}
317
318static inline void eeh_outw(u16 val, unsigned long port)
319{
320 out_le16((u16 __iomem *)(port+pci_io_base), val);
321}
322
323static inline u32 eeh_inl(unsigned long port)
324{
325 u32 val;
326 val = in_le32((u32 __iomem *)(port+pci_io_base));
327 if (EEH_POSSIBLE_ERROR(val, u32))
328 return eeh_check_failure((void __iomem *)(port), val);
329 return val;
330}
331
332static inline void eeh_outl(u32 val, unsigned long port)
333{
334 out_le32((u32 __iomem *)(port+pci_io_base), val);
335} 183}
336 184
337/* in-string eeh macros */ 185/* in-string eeh macros */
338static inline void eeh_insb(unsigned long port, void * buf, int ns) 186static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
187 int ns)
339{ 188{
340 _insb((u8 __iomem *)(port+pci_io_base), buf, ns); 189 _insb(addr, buf, ns);
341 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 190 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
342 eeh_check_failure((void __iomem *)(port), *(u8*)buf); 191 eeh_check_failure(addr, *(u8*)buf);
343} 192}
344 193
345static inline void eeh_insw_ns(unsigned long port, void * buf, int ns) 194static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
195 int ns)
346{ 196{
347 _insw_ns((u16 __iomem *)(port+pci_io_base), buf, ns); 197 _insw(addr, buf, ns);
348 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 198 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
349 eeh_check_failure((void __iomem *)(port), *(u16*)buf); 199 eeh_check_failure(addr, *(u16*)buf);
350} 200}
351 201
352static inline void eeh_insl_ns(unsigned long port, void * buf, int nl) 202static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
203 int nl)
353{ 204{
354 _insl_ns((u32 __iomem *)(port+pci_io_base), buf, nl); 205 _insl(addr, buf, nl);
355 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 206 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
356 eeh_check_failure((void __iomem *)(port), *(u32*)buf); 207 eeh_check_failure(addr, *(u32*)buf);
357} 208}
358 209
359#endif /* __KERNEL__ */ 210#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
index 9a83a987d396..b5436642a109 100644
--- a/include/asm-powerpc/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -411,4 +411,17 @@ do { \
411/* Keep this the last entry. */ 411/* Keep this the last entry. */
412#define R_PPC64_NUM 107 412#define R_PPC64_NUM 107
413 413
414#ifdef CONFIG_SPU_BASE
415/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
416#define NT_SPU 1
417
418extern int arch_notes_size(void);
419extern void arch_write_notes(struct file *file);
420
421#define ELF_CORE_EXTRA_NOTES_SIZE arch_notes_size()
422#define ELF_CORE_WRITE_EXTRA_NOTES arch_write_notes(file)
423
424#define ARCH_HAVE_EXTRA_ELF_NOTES
425#endif /* CONFIG_PPC_CELL */
426
414#endif /* _ASM_POWERPC_ELF_H */ 427#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index fdf9aff71150..98f7b62422c9 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -42,6 +42,7 @@
42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000) 42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
43#define FW_FEATURE_ISERIES ASM_CONST(0x0000000000200000) 43#define FW_FEATURE_ISERIES ASM_CONST(0x0000000000200000)
44#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000) 44#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
45#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
45 46
46#ifndef __ASSEMBLY__ 47#ifndef __ASSEMBLY__
47 48
@@ -58,6 +59,10 @@ enum {
58 FW_FEATURE_PSERIES_ALWAYS = 0, 59 FW_FEATURE_PSERIES_ALWAYS = 0,
59 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 60 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
60 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 61 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
62 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
63 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
64 FW_FEATURE_NATIVE_POSSIBLE = 0,
65 FW_FEATURE_NATIVE_ALWAYS = 0,
61 FW_FEATURE_POSSIBLE = 66 FW_FEATURE_POSSIBLE =
62#ifdef CONFIG_PPC_PSERIES 67#ifdef CONFIG_PPC_PSERIES
63 FW_FEATURE_PSERIES_POSSIBLE | 68 FW_FEATURE_PSERIES_POSSIBLE |
@@ -65,6 +70,12 @@ enum {
65#ifdef CONFIG_PPC_ISERIES 70#ifdef CONFIG_PPC_ISERIES
66 FW_FEATURE_ISERIES_POSSIBLE | 71 FW_FEATURE_ISERIES_POSSIBLE |
67#endif 72#endif
73#ifdef CONFIG_PPC_PS3
74 FW_FEATURE_PS3_POSSIBLE |
75#endif
76#ifdef CONFIG_PPC_NATIVE
77 FW_FEATURE_NATIVE_ALWAYS |
78#endif
68 0, 79 0,
69 FW_FEATURE_ALWAYS = 80 FW_FEATURE_ALWAYS =
70#ifdef CONFIG_PPC_PSERIES 81#ifdef CONFIG_PPC_PSERIES
@@ -73,6 +84,12 @@ enum {
73#ifdef CONFIG_PPC_ISERIES 84#ifdef CONFIG_PPC_ISERIES
74 FW_FEATURE_ISERIES_ALWAYS & 85 FW_FEATURE_ISERIES_ALWAYS &
75#endif 86#endif
87#ifdef CONFIG_PPC_PS3
88 FW_FEATURE_PS3_ALWAYS &
89#endif
90#ifdef CONFIG_PPC_NATIVE
91 FW_FEATURE_NATIVE_ALWAYS &
92#endif
76 FW_FEATURE_POSSIBLE, 93 FW_FEATURE_POSSIBLE,
77 94
78#else /* CONFIG_PPC64 */ 95#else /* CONFIG_PPC64 */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index d40359204aba..d604863d72fb 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -7,16 +7,40 @@
7#ifdef __KERNEL__ 7#ifdef __KERNEL__
8 8
9#include <linux/errno.h> 9#include <linux/errno.h>
10#include <linux/compiler.h>
10#include <asm/ptrace.h> 11#include <asm/ptrace.h>
11#include <asm/processor.h> 12#include <asm/processor.h>
12 13
13extern void timer_interrupt(struct pt_regs *); 14extern void timer_interrupt(struct pt_regs *);
14 15
15#ifdef CONFIG_PPC_ISERIES 16#ifdef CONFIG_PPC64
17#include <asm/paca.h>
18
19static inline unsigned long local_get_flags(void)
20{
21 unsigned long flags;
22
23 __asm__ __volatile__("lbz %0,%1(13)"
24 : "=r" (flags)
25 : "i" (offsetof(struct paca_struct, soft_enabled)));
26
27 return flags;
28}
29
30static inline unsigned long local_irq_disable(void)
31{
32 unsigned long flags, zero;
33
34 __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
35 : "=r" (flags), "=&r" (zero)
36 : "i" (offsetof(struct paca_struct, soft_enabled))
37 : "memory");
38
39 return flags;
40}
16 41
17extern unsigned long local_get_flags(void);
18extern unsigned long local_irq_disable(void);
19extern void local_irq_restore(unsigned long); 42extern void local_irq_restore(unsigned long);
43extern void iseries_handle_interrupts(void);
20 44
21#define local_irq_enable() local_irq_restore(1) 45#define local_irq_enable() local_irq_restore(1)
22#define local_save_flags(flags) ((flags) = local_get_flags()) 46#define local_save_flags(flags) ((flags) = local_get_flags())
@@ -24,17 +48,14 @@ extern void local_irq_restore(unsigned long);
24 48
25#define irqs_disabled() (local_get_flags() == 0) 49#define irqs_disabled() (local_get_flags() == 0)
26 50
51#define hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
52#define hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
53
27#else 54#else
28 55
29#if defined(CONFIG_BOOKE) 56#if defined(CONFIG_BOOKE)
30#define SET_MSR_EE(x) mtmsr(x) 57#define SET_MSR_EE(x) mtmsr(x)
31#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") 58#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
32#elif defined(__powerpc64__)
33#define SET_MSR_EE(x) __mtmsrd(x, 1)
34#define local_irq_restore(flags) do { \
35 __asm__ __volatile__("": : :"memory"); \
36 __mtmsrd((flags), 1); \
37} while(0)
38#else 59#else
39#define SET_MSR_EE(x) mtmsr(x) 60#define SET_MSR_EE(x) mtmsr(x)
40#define local_irq_restore(flags) mtmsr(flags) 61#define local_irq_restore(flags) mtmsr(flags)
@@ -81,7 +102,10 @@ static inline void local_irq_save_ptr(unsigned long *flags)
81#define local_irq_save(flags) local_irq_save_ptr(&flags) 102#define local_irq_save(flags) local_irq_save_ptr(&flags)
82#define irqs_disabled() ((mfmsr() & MSR_EE) == 0) 103#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
83 104
84#endif /* CONFIG_PPC_ISERIES */ 105#define hard_irq_enable() local_irq_enable()
106#define hard_irq_disable() local_irq_disable()
107
108#endif /* CONFIG_PPC64 */
85 109
86#define mask_irq(irq) \ 110#define mask_irq(irq) \
87 ({ \ 111 ({ \
diff --git a/include/asm-powerpc/ibmebus.h b/include/asm-powerpc/ibmebus.h
index 3493429b70f5..66112114b8c5 100644
--- a/include/asm-powerpc/ibmebus.h
+++ b/include/asm-powerpc/ibmebus.h
@@ -44,7 +44,6 @@
44#include <linux/mod_devicetable.h> 44#include <linux/mod_devicetable.h>
45#include <asm/of_device.h> 45#include <asm/of_device.h>
46 46
47extern struct dma_mapping_ops ibmebus_dma_ops;
48extern struct bus_type ibmebus_bus_type; 47extern struct bus_type ibmebus_bus_type;
49 48
50struct ibmebus_dev { 49struct ibmebus_dev {
diff --git a/include/asm-powerpc/ide.h b/include/asm-powerpc/ide.h
index c8390f9485de..0f66f0f82c32 100644
--- a/include/asm-powerpc/ide.h
+++ b/include/asm-powerpc/ide.h
@@ -22,10 +22,10 @@
22#endif 22#endif
23#endif 23#endif
24 24
25#define __ide_mm_insw(p, a, c) _insw_ns((volatile u16 __iomem *)(p), (a), (c)) 25#define __ide_mm_insw(p, a, c) readsw((void __iomem *)(p), (a), (c))
26#define __ide_mm_insl(p, a, c) _insl_ns((volatile u32 __iomem *)(p), (a), (c)) 26#define __ide_mm_insl(p, a, c) readsl((void __iomem *)(p), (a), (c))
27#define __ide_mm_outsw(p, a, c) _outsw_ns((volatile u16 __iomem *)(p), (a), (c)) 27#define __ide_mm_outsw(p, a, c) writesw((void __iomem *)(p), (a), (c))
28#define __ide_mm_outsl(p, a, c) _outsl_ns((volatile u32 __iomem *)(p), (a), (c)) 28#define __ide_mm_outsl(p, a, c) writesl((void __iomem *)(p), (a), (c))
29 29
30#ifndef __powerpc64__ 30#ifndef __powerpc64__
31#include <linux/hdreg.h> 31#include <linux/hdreg.h>
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index ce12f85fff9b..9fdd0491f6a3 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -136,22 +136,7 @@ struct qe_timers {
136 136
137/* BRG */ 137/* BRG */
138struct qe_brg { 138struct qe_brg {
139 __be32 brgc1; /* BRG1 configuration register */ 139 __be32 brgc[16]; /* BRG configuration registers */
140 __be32 brgc2; /* BRG2 configuration register */
141 __be32 brgc3; /* BRG3 configuration register */
142 __be32 brgc4; /* BRG4 configuration register */
143 __be32 brgc5; /* BRG5 configuration register */
144 __be32 brgc6; /* BRG6 configuration register */
145 __be32 brgc7; /* BRG7 configuration register */
146 __be32 brgc8; /* BRG8 configuration register */
147 __be32 brgc9; /* BRG9 configuration register */
148 __be32 brgc10; /* BRG10 configuration register */
149 __be32 brgc11; /* BRG11 configuration register */
150 __be32 brgc12; /* BRG12 configuration register */
151 __be32 brgc13; /* BRG13 configuration register */
152 __be32 brgc14; /* BRG14 configuration register */
153 __be32 brgc15; /* BRG15 configuration register */
154 __be32 brgc16; /* BRG16 configuration register */
155 u8 res0[0x40]; 140 u8 res0[0x40];
156} __attribute__ ((packed)); 141} __attribute__ ((packed));
157 142
diff --git a/include/asm-powerpc/io-defs.h b/include/asm-powerpc/io-defs.h
new file mode 100644
index 000000000000..03691ab69217
--- /dev/null
+++ b/include/asm-powerpc/io-defs.h
@@ -0,0 +1,59 @@
1/* This file is meant to be include multiple times by other headers */
2
3DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr))
4DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr))
5DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr))
6DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr))
7DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr))
8DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr))
9DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr))
10DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr))
11DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr))
12DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr))
13
14#ifdef __powerpc64__
15DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr))
16DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr))
17DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr))
18DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr))
19#endif /* __powerpc64__ */
20
21DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port))
22DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port))
23DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port))
24DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port))
25DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port))
26DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port))
27
28DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c), \
29 (a, b, c))
30DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c), \
31 (a, b, c))
32DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c), \
33 (a, b, c))
34DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c), \
35 (a, b, c))
36DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c), \
37 (a, b, c))
38DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c), \
39 (a, b, c))
40
41DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c), \
42 (p, b, c))
43DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c), \
44 (p, b, c))
45DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c), \
46 (p, b, c))
47DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c), \
48 (p, b, c))
49DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c), \
50 (p, b, c))
51DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c), \
52 (p, b, c))
53
54DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n), \
55 (a, c, n))
56DEF_PCI_AC_NORET(memcpy_fromio,(void *d,const PCI_IO_ADDR s,unsigned long n), \
57 (d, s, n))
58DEF_PCI_AC_NORET(memcpy_toio,(PCI_IO_ADDR d,const void *s,unsigned long n), \
59 (d, s, n))
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index c2c5f14b5f5f..1cd532379c30 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -13,154 +13,530 @@
13extern int check_legacy_ioport(unsigned long base_port); 13extern int check_legacy_ioport(unsigned long base_port);
14#define PNPBIOS_BASE 0xf000 /* only relevant for PReP */ 14#define PNPBIOS_BASE 0xf000 /* only relevant for PReP */
15 15
16#ifndef CONFIG_PPC64
17#include <asm-ppc/io.h>
18#else
19
20#include <linux/compiler.h> 16#include <linux/compiler.h>
21#include <asm/page.h> 17#include <asm/page.h>
22#include <asm/byteorder.h> 18#include <asm/byteorder.h>
23#include <asm/paca.h>
24#include <asm/synch.h> 19#include <asm/synch.h>
25#include <asm/delay.h> 20#include <asm/delay.h>
21#include <asm/mmu.h>
26 22
27#include <asm-generic/iomap.h> 23#include <asm-generic/iomap.h>
28 24
25#ifdef CONFIG_PPC64
26#include <asm/paca.h>
27#endif
28
29#define SIO_CONFIG_RA 0x398 29#define SIO_CONFIG_RA 0x398
30#define SIO_CONFIG_RD 0x399 30#define SIO_CONFIG_RD 0x399
31 31
32#define SLOW_DOWN_IO 32#define SLOW_DOWN_IO
33 33
34/* 32 bits uses slightly different variables for the various IO
35 * bases. Most of this file only uses _IO_BASE though which we
36 * define properly based on the platform
37 */
38#ifndef CONFIG_PCI
39#define _IO_BASE 0
40#define _ISA_MEM_BASE 0
41#define PCI_DRAM_OFFSET 0
42#elif defined(CONFIG_PPC32)
43#define _IO_BASE isa_io_base
44#define _ISA_MEM_BASE isa_mem_base
45#define PCI_DRAM_OFFSET pci_dram_offset
46#else
47#define _IO_BASE pci_io_base
48#define _ISA_MEM_BASE 0
49#define PCI_DRAM_OFFSET 0
50#endif
51
34extern unsigned long isa_io_base; 52extern unsigned long isa_io_base;
53extern unsigned long isa_mem_base;
35extern unsigned long pci_io_base; 54extern unsigned long pci_io_base;
55extern unsigned long pci_dram_offset;
56
57#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
58#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
59#endif
60
61/*
62 *
63 * Low level MMIO accessors
64 *
65 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
66 * specific and thus shouldn't be used in generic code. The accessors
67 * provided here are:
68 *
69 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
70 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
71 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
72 *
73 * Those operate directly on a kernel virtual address. Note that the prototype
74 * for the out_* accessors has the arguments in opposite order from the usual
75 * linux PCI accessors. Unlike those, they take the address first and the value
76 * next.
77 *
78 * Note: I might drop the _ns suffix on the stream operations soon as it is
79 * simply normal for stream operations to not swap in the first place.
80 *
81 */
82
83#ifdef CONFIG_PPC64
84#define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0)
85#else
86#define IO_SET_SYNC_FLAG()
87#endif
88
89#define DEF_MMIO_IN(name, type, insn) \
90static inline type name(const volatile type __iomem *addr) \
91{ \
92 type ret; \
93 __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \
94 : "=r" (ret) : "r" (addr), "m" (*addr)); \
95 return ret; \
96}
97
98#define DEF_MMIO_OUT(name, type, insn) \
99static inline void name(volatile type __iomem *addr, type val) \
100{ \
101 __asm__ __volatile__("sync;" insn \
102 : "=m" (*addr) : "r" (val), "r" (addr)); \
103 IO_SET_SYNC_FLAG(); \
104}
105
106
107#define DEF_MMIO_IN_BE(name, size, insn) \
108 DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
109#define DEF_MMIO_IN_LE(name, size, insn) \
110 DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
111
112#define DEF_MMIO_OUT_BE(name, size, insn) \
113 DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
114#define DEF_MMIO_OUT_LE(name, size, insn) \
115 DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
116
117DEF_MMIO_IN_BE(in_8, 8, lbz);
118DEF_MMIO_IN_BE(in_be16, 16, lhz);
119DEF_MMIO_IN_BE(in_be32, 32, lwz);
120DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
121DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
122
123DEF_MMIO_OUT_BE(out_8, 8, stb);
124DEF_MMIO_OUT_BE(out_be16, 16, sth);
125DEF_MMIO_OUT_BE(out_be32, 32, stw);
126DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
127DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
128
129#ifdef __powerpc64__
130DEF_MMIO_OUT_BE(out_be64, 64, std);
131DEF_MMIO_IN_BE(in_be64, 64, ld);
132
133/* There is no asm instructions for 64 bits reverse loads and stores */
134static inline u64 in_le64(const volatile u64 __iomem *addr)
135{
136 return le64_to_cpu(in_be64(addr));
137}
138
139static inline void out_le64(volatile u64 __iomem *addr, u64 val)
140{
141 out_be64(addr, cpu_to_le64(val));
142}
143#endif /* __powerpc64__ */
144
145/*
146 * Low level IO stream instructions are defined out of line for now
147 */
148extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
149extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
150extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
151extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
152extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
153extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
154
155/* The _ns naming is historical and will be removed. For now, just #define
156 * the non _ns equivalent names
157 */
158#define _insw _insw_ns
159#define _insl _insl_ns
160#define _outsw _outsw_ns
161#define _outsl _outsl_ns
162
163
164/*
165 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
166 */
167
168extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
169extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
170 unsigned long n);
171extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
172 unsigned long n);
173
174/*
175 *
176 * PCI and standard ISA accessors
177 *
178 * Those are globally defined linux accessors for devices on PCI or ISA
179 * busses. They follow the Linux defined semantics. The current implementation
180 * for PowerPC is as close as possible to the x86 version of these, and thus
181 * provides fairly heavy weight barriers for the non-raw versions
182 *
183 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
184 * allowing the platform to provide its own implementation of some or all
185 * of the accessors.
186 */
187
188/*
189 * Include the EEH definitions when EEH is enabled only so they don't get
190 * in the way when building for 32 bits
191 */
192#ifdef CONFIG_EEH
193#include <asm/eeh.h>
194#endif
195
196/* Shortcut to the MMIO argument pointer */
197#define PCI_IO_ADDR volatile void __iomem *
198
199/* Indirect IO address tokens:
200 *
201 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
202 * on all IOs. (Note that this is all 64 bits only for now)
203 *
204 * To help platforms who may need to differenciate MMIO addresses in
205 * their hooks, a bitfield is reserved for use by the platform near the
206 * top of MMIO addresses (not PIO, those have to cope the hard way).
207 *
208 * This bit field is 12 bits and is at the top of the IO virtual
209 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
210 *
211 * The kernel virtual space is thus:
212 *
213 * 0xD000000000000000 : vmalloc
214 * 0xD000080000000000 : PCI PHB IO space
215 * 0xD000080080000000 : ioremap
216 * 0xD0000fffffffffff : end of ioremap region
217 *
218 * Since the top 4 bits are reserved as the region ID, we use thus
219 * the next 12 bits and keep 4 bits available for the future if the
220 * virtual address space is ever to be extended.
221 *
222 * The direct IO mapping operations will then mask off those bits
223 * before doing the actual access, though that only happen when
224 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
225 * mechanism
226 */
227
228#ifdef CONFIG_PPC_INDIRECT_IO
229#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
230#define PCI_IO_IND_TOKEN_SHIFT 48
231#define PCI_FIX_ADDR(addr) \
232 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
233#define PCI_GET_ADDR_TOKEN(addr) \
234 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
235 PCI_IO_IND_TOKEN_SHIFT)
236#define PCI_SET_ADDR_TOKEN(addr, token) \
237do { \
238 unsigned long __a = (unsigned long)(addr); \
239 __a &= ~PCI_IO_IND_TOKEN_MASK; \
240 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
241 (addr) = (void __iomem *)__a; \
242} while(0)
243#else
244#define PCI_FIX_ADDR(addr) (addr)
245#endif
36 246
37#ifdef CONFIG_PPC_ISERIES 247
38 248/*
39extern int in_8(const volatile unsigned char __iomem *addr); 249 * Non ordered and non-swapping "raw" accessors
40extern void out_8(volatile unsigned char __iomem *addr, int val); 250 */
41extern int in_le16(const volatile unsigned short __iomem *addr);
42extern int in_be16(const volatile unsigned short __iomem *addr);
43extern void out_le16(volatile unsigned short __iomem *addr, int val);
44extern void out_be16(volatile unsigned short __iomem *addr, int val);
45extern unsigned in_le32(const volatile unsigned __iomem *addr);
46extern unsigned in_be32(const volatile unsigned __iomem *addr);
47extern void out_le32(volatile unsigned __iomem *addr, int val);
48extern void out_be32(volatile unsigned __iomem *addr, int val);
49extern unsigned long in_le64(const volatile unsigned long __iomem *addr);
50extern unsigned long in_be64(const volatile unsigned long __iomem *addr);
51extern void out_le64(volatile unsigned long __iomem *addr, unsigned long val);
52extern void out_be64(volatile unsigned long __iomem *addr, unsigned long val);
53
54extern unsigned char __raw_readb(const volatile void __iomem *addr);
55extern unsigned short __raw_readw(const volatile void __iomem *addr);
56extern unsigned int __raw_readl(const volatile void __iomem *addr);
57extern unsigned long __raw_readq(const volatile void __iomem *addr);
58extern void __raw_writeb(unsigned char v, volatile void __iomem *addr);
59extern void __raw_writew(unsigned short v, volatile void __iomem *addr);
60extern void __raw_writel(unsigned int v, volatile void __iomem *addr);
61extern void __raw_writeq(unsigned long v, volatile void __iomem *addr);
62
63extern void memset_io(volatile void __iomem *addr, int c, unsigned long n);
64extern void memcpy_fromio(void *dest, const volatile void __iomem *src,
65 unsigned long n);
66extern void memcpy_toio(volatile void __iomem *dest, const void *src,
67 unsigned long n);
68
69#else /* CONFIG_PPC_ISERIES */
70
71#define in_8(addr) __in_8((addr))
72#define out_8(addr, val) __out_8((addr), (val))
73#define in_le16(addr) __in_le16((addr))
74#define in_be16(addr) __in_be16((addr))
75#define out_le16(addr, val) __out_le16((addr), (val))
76#define out_be16(addr, val) __out_be16((addr), (val))
77#define in_le32(addr) __in_le32((addr))
78#define in_be32(addr) __in_be32((addr))
79#define out_le32(addr, val) __out_le32((addr), (val))
80#define out_be32(addr, val) __out_be32((addr), (val))
81#define in_le64(addr) __in_le64((addr))
82#define in_be64(addr) __in_be64((addr))
83#define out_le64(addr, val) __out_le64((addr), (val))
84#define out_be64(addr, val) __out_be64((addr), (val))
85 251
86static inline unsigned char __raw_readb(const volatile void __iomem *addr) 252static inline unsigned char __raw_readb(const volatile void __iomem *addr)
87{ 253{
88 return *(volatile unsigned char __force *)addr; 254 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
89} 255}
90static inline unsigned short __raw_readw(const volatile void __iomem *addr) 256static inline unsigned short __raw_readw(const volatile void __iomem *addr)
91{ 257{
92 return *(volatile unsigned short __force *)addr; 258 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
93} 259}
94static inline unsigned int __raw_readl(const volatile void __iomem *addr) 260static inline unsigned int __raw_readl(const volatile void __iomem *addr)
95{ 261{
96 return *(volatile unsigned int __force *)addr; 262 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
97}
98static inline unsigned long __raw_readq(const volatile void __iomem *addr)
99{
100 return *(volatile unsigned long __force *)addr;
101} 263}
102static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 264static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
103{ 265{
104 *(volatile unsigned char __force *)addr = v; 266 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
105} 267}
106static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 268static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
107{ 269{
108 *(volatile unsigned short __force *)addr = v; 270 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
109} 271}
110static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 272static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
111{ 273{
112 *(volatile unsigned int __force *)addr = v; 274 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
275}
276
277#ifdef __powerpc64__
278static inline unsigned long __raw_readq(const volatile void __iomem *addr)
279{
280 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
113} 281}
114static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 282static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
115{ 283{
116 *(volatile unsigned long __force *)addr = v; 284 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
285}
286#endif /* __powerpc64__ */
287
288/*
289 *
290 * PCI PIO and MMIO accessors.
291 *
292 *
293 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
294 * machine checks (which they occasionally do when probing non existing
295 * IO ports on some platforms, like PowerMac and 8xx).
296 * I always found it to be of dubious reliability and I am tempted to get
297 * rid of it one of these days. So if you think it's important to keep it,
298 * please voice up asap. We never had it for 64 bits and I do not intend
299 * to port it over
300 */
301
302#ifdef CONFIG_PPC32
303
304#define __do_in_asm(name, op) \
305static inline unsigned int name(unsigned int port) \
306{ \
307 unsigned int x; \
308 __asm__ __volatile__( \
309 "sync\n" \
310 "0:" op " %0,0,%1\n" \
311 "1: twi 0,%0,0\n" \
312 "2: isync\n" \
313 "3: nop\n" \
314 "4:\n" \
315 ".section .fixup,\"ax\"\n" \
316 "5: li %0,-1\n" \
317 " b 4b\n" \
318 ".previous\n" \
319 ".section __ex_table,\"a\"\n" \
320 " .align 2\n" \
321 " .long 0b,5b\n" \
322 " .long 1b,5b\n" \
323 " .long 2b,5b\n" \
324 " .long 3b,5b\n" \
325 ".previous" \
326 : "=&r" (x) \
327 : "r" (port + _IO_BASE)); \
328 return x; \
329}
330
331#define __do_out_asm(name, op) \
332static inline void name(unsigned int val, unsigned int port) \
333{ \
334 __asm__ __volatile__( \
335 "sync\n" \
336 "0:" op " %0,0,%1\n" \
337 "1: sync\n" \
338 "2:\n" \
339 ".section __ex_table,\"a\"\n" \
340 " .align 2\n" \
341 " .long 0b,2b\n" \
342 " .long 1b,2b\n" \
343 ".previous" \
344 : : "r" (val), "r" (port + _IO_BASE)); \
345}
346
347__do_in_asm(_rec_inb, "lbzx")
348__do_in_asm(_rec_inw, "lhbrx")
349__do_in_asm(_rec_inl, "lwbrx")
350__do_out_asm(_rec_outb, "stbx")
351__do_out_asm(_rec_outw, "sthbrx")
352__do_out_asm(_rec_outl, "stwbrx")
353
354#endif /* CONFIG_PPC32 */
355
356/* The "__do_*" operations below provide the actual "base" implementation
357 * for each of the defined acccessor. Some of them use the out_* functions
358 * directly, some of them still use EEH, though we might change that in the
359 * future. Those macros below provide the necessary argument swapping and
360 * handling of the IO base for PIO.
361 *
362 * They are themselves used by the macros that define the actual accessors
363 * and can be used by the hooks if any.
364 *
365 * Note that PIO operations are always defined in terms of their corresonding
366 * MMIO operations. That allows platforms like iSeries who want to modify the
367 * behaviour of both to only hook on the MMIO version and get both. It's also
368 * possible to hook directly at the toplevel PIO operation if they have to
369 * be handled differently
370 */
371#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
372#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
373#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
374#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
375#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
376#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
377#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
378
379#ifdef CONFIG_EEH
380#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
381#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
382#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
383#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
384#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
385#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
386#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
387#else /* CONFIG_EEH */
388#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
389#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
390#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
391#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
392#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
393#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
394#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
395#endif /* !defined(CONFIG_EEH) */
396
397#ifdef CONFIG_PPC32
398#define __do_outb(val, port) _rec_outb(val, port)
399#define __do_outw(val, port) _rec_outw(val, port)
400#define __do_outl(val, port) _rec_outl(val, port)
401#define __do_inb(port) _rec_inb(port)
402#define __do_inw(port) _rec_inw(port)
403#define __do_inl(port) _rec_inl(port)
404#else /* CONFIG_PPC32 */
405#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
406#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
407#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
408#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
409#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
410#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
411#endif /* !CONFIG_PPC32 */
412
413#ifdef CONFIG_EEH
414#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
415#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
416#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
417#else /* CONFIG_EEH */
418#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
419#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
420#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
421#endif /* !CONFIG_EEH */
422#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
423#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
424#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
425
426#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
427#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
428#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
429#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
430#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
431#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
432
433#define __do_memset_io(addr, c, n) \
434 _memset_io(PCI_FIX_ADDR(addr), c, n)
435#define __do_memcpy_toio(dst, src, n) \
436 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
437
438#ifdef CONFIG_EEH
439#define __do_memcpy_fromio(dst, src, n) \
440 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
441#else /* CONFIG_EEH */
442#define __do_memcpy_fromio(dst, src, n) \
443 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
444#endif /* !CONFIG_EEH */
445
446#ifdef CONFIG_PPC_INDIRECT_IO
447#define DEF_PCI_HOOK(x) x
448#else
449#define DEF_PCI_HOOK(x) NULL
450#endif
451
452/* Structure containing all the hooks */
453extern struct ppc_pci_io {
454
455#define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at;
456#define DEF_PCI_AC_NORET(name, at, al) void (*name) at;
457
458#include <asm/io-defs.h>
459
460#undef DEF_PCI_AC_RET
461#undef DEF_PCI_AC_NORET
462
463} ppc_pci_io;
464
465/* The inline wrappers */
466#define DEF_PCI_AC_RET(name, ret, at, al) \
467static inline ret name at \
468{ \
469 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
470 return ppc_pci_io.name al; \
471 return __do_##name al; \
472}
473
474#define DEF_PCI_AC_NORET(name, at, al) \
475static inline void name at \
476{ \
477 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
478 ppc_pci_io.name al; \
479 else \
480 __do_##name al; \
117} 481}
118#define memset_io(a,b,c) eeh_memset_io((a),(b),(c))
119#define memcpy_fromio(a,b,c) eeh_memcpy_fromio((a),(b),(c))
120#define memcpy_toio(a,b,c) eeh_memcpy_toio((a),(b),(c))
121 482
122#endif /* CONFIG_PPC_ISERIES */ 483#include <asm/io-defs.h>
484
485#undef DEF_PCI_AC_RET
486#undef DEF_PCI_AC_NORET
487
488/* Some drivers check for the presence of readq & writeq with
489 * a #ifdef, so we make them happy here.
490 */
491#ifdef __powerpc64__
492#define readq readq
493#define writeq writeq
494#endif
495
496#ifdef CONFIG_NOT_COHERENT_CACHE
497
498#define dma_cache_inv(_start,_size) \
499 invalidate_dcache_range(_start, (_start + _size))
500#define dma_cache_wback(_start,_size) \
501 clean_dcache_range(_start, (_start + _size))
502#define dma_cache_wback_inv(_start,_size) \
503 flush_dcache_range(_start, (_start + _size))
504
505#else /* CONFIG_NOT_COHERENT_CACHE */
506
507#define dma_cache_inv(_start,_size) do { } while (0)
508#define dma_cache_wback(_start,_size) do { } while (0)
509#define dma_cache_wback_inv(_start,_size) do { } while (0)
510
511#endif /* !CONFIG_NOT_COHERENT_CACHE */
123 512
124/* 513/*
125 * The insw/outsw/insl/outsl macros don't do byte-swapping. 514 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
126 * They are only used in practice for transferring buffers which 515 * access
127 * are arrays of bytes, and byte-swapping is not appropriate in 516 */
128 * that case. - paulus */ 517#define xlate_dev_mem_ptr(p) __va(p)
129#define insb(port, buf, ns) eeh_insb((port), (buf), (ns)) 518
130#define insw(port, buf, ns) eeh_insw_ns((port), (buf), (ns)) 519/*
131#define insl(port, buf, nl) eeh_insl_ns((port), (buf), (nl)) 520 * Convert a virtual cached pointer to an uncached pointer
132 521 */
133#define outsb(port, buf, ns) _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns)) 522#define xlate_dev_kmem_ptr(p) p
134#define outsw(port, buf, ns) _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
135#define outsl(port, buf, nl) _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
136
137#define readb(addr) eeh_readb(addr)
138#define readw(addr) eeh_readw(addr)
139#define readl(addr) eeh_readl(addr)
140#define readq(addr) eeh_readq(addr)
141#define writeb(data, addr) eeh_writeb((data), (addr))
142#define writew(data, addr) eeh_writew((data), (addr))
143#define writel(data, addr) eeh_writel((data), (addr))
144#define writeq(data, addr) eeh_writeq((data), (addr))
145#define inb(port) eeh_inb((unsigned long)port)
146#define outb(val, port) eeh_outb(val, (unsigned long)port)
147#define inw(port) eeh_inw((unsigned long)port)
148#define outw(val, port) eeh_outw(val, (unsigned long)port)
149#define inl(port) eeh_inl((unsigned long)port)
150#define outl(val, port) eeh_outl(val, (unsigned long)port)
151 523
524/*
525 * We don't do relaxed operations yet, at least not with this semantic
526 */
152#define readb_relaxed(addr) readb(addr) 527#define readb_relaxed(addr) readb(addr)
153#define readw_relaxed(addr) readw(addr) 528#define readw_relaxed(addr) readw(addr)
154#define readl_relaxed(addr) readl(addr) 529#define readl_relaxed(addr) readl(addr)
155#define readq_relaxed(addr) readq(addr) 530#define readq_relaxed(addr) readq(addr)
156 531
157extern void _insb(volatile u8 __iomem *port, void *buf, long count); 532#ifdef CONFIG_PPC32
158extern void _outsb(volatile u8 __iomem *port, const void *buf, long count); 533#define mmiowb()
159extern void _insw_ns(volatile u16 __iomem *port, void *buf, long count); 534#else
160extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, long count); 535/*
161extern void _insl_ns(volatile u32 __iomem *port, void *buf, long count); 536 * Enforce synchronisation of stores vs. spin_unlock
162extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, long count); 537 * (this does it explicitely, though our implementation of spin_unlock
163 538 * does it implicitely too)
539 */
164static inline void mmiowb(void) 540static inline void mmiowb(void)
165{ 541{
166 unsigned long tmp; 542 unsigned long tmp;
@@ -169,6 +545,24 @@ static inline void mmiowb(void)
169 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 545 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
170 : "memory"); 546 : "memory");
171} 547}
548#endif /* !CONFIG_PPC32 */
549
550static inline void iosync(void)
551{
552 __asm__ __volatile__ ("sync" : : : "memory");
553}
554
555/* Enforce in-order execution of data I/O.
556 * No distinction between read/write on PPC; use eieio for all three.
557 * Those are fairly week though. They don't provide a barrier between
558 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
559 * they only provide barriers between 2 __raw MMIO operations and
560 * possibly break write combining.
561 */
562#define iobarrier_rw() eieio()
563#define iobarrier_r() eieio()
564#define iobarrier_w() eieio()
565
172 566
173/* 567/*
174 * output pause versions need a delay at least for the 568 * output pause versions need a delay at least for the
@@ -185,11 +579,6 @@ static inline void mmiowb(void)
185#define IO_SPACE_LIMIT ~(0UL) 579#define IO_SPACE_LIMIT ~(0UL)
186 580
187 581
188extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
189 unsigned long size, unsigned long flags);
190extern void __iomem *__ioremap(unsigned long address, unsigned long size,
191 unsigned long flags);
192
193/** 582/**
194 * ioremap - map bus memory into CPU space 583 * ioremap - map bus memory into CPU space
195 * @address: bus address of the memory 584 * @address: bus address of the memory
@@ -200,14 +589,77 @@ extern void __iomem *__ioremap(unsigned long address, unsigned long size,
200 * writew/writel functions and the other mmio helpers. The returned 589 * writew/writel functions and the other mmio helpers. The returned
201 * address is not guaranteed to be usable directly as a virtual 590 * address is not guaranteed to be usable directly as a virtual
202 * address. 591 * address.
592 *
593 * We provide a few variations of it:
594 *
595 * * ioremap is the standard one and provides non-cacheable guarded mappings
596 * and can be hooked by the platform via ppc_md
597 *
598 * * ioremap_flags allows to specify the page flags as an argument and can
599 * also be hooked by the platform via ppc_md
600 *
601 * * ioremap_nocache is identical to ioremap
602 *
603 * * iounmap undoes such a mapping and can be hooked
604 *
605 * * __ioremap_explicit (and the pending __iounmap_explicit) are low level
606 * functions to create hand-made mappings for use only by the PCI code
607 * and cannot currently be hooked.
608 *
609 * * __ioremap is the low level implementation used by ioremap and
610 * ioremap_flags and cannot be hooked (but can be used by a hook on one
611 * of the previous ones)
612 *
613 * * __iounmap, is the low level implementation used by iounmap and cannot
614 * be hooked (but can be used by a hook on iounmap)
615 *
203 */ 616 */
204extern void __iomem *ioremap(unsigned long address, unsigned long size); 617extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
205 618extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
619 unsigned long flags);
206#define ioremap_nocache(addr, size) ioremap((addr), (size)) 620#define ioremap_nocache(addr, size) ioremap((addr), (size))
207extern int iounmap_explicit(volatile void __iomem *addr, unsigned long size);
208extern void iounmap(volatile void __iomem *addr); 621extern void iounmap(volatile void __iomem *addr);
622
623extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
624 unsigned long flags);
625extern void __iounmap(volatile void __iomem *addr);
626
627extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr,
628 unsigned long size, unsigned long flags);
629extern int __iounmap_explicit(volatile void __iomem *start,
630 unsigned long size);
631
209extern void __iomem * reserve_phb_iospace(unsigned long size); 632extern void __iomem * reserve_phb_iospace(unsigned long size);
210 633
634/* Those are more 32 bits only functions */
635extern unsigned long iopa(unsigned long addr);
636extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
637extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
638 unsigned int size, int flags);
639
640
641/*
642 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
643 * which needs some additional definitions here. They basically allow PIO
644 * space overall to be 1GB. This will work as long as we never try to use
645 * iomap to map MMIO below 1GB which should be fine on ppc64
646 */
647#define HAVE_ARCH_PIO_SIZE 1
648#define PIO_OFFSET 0x00000000UL
649#define PIO_MASK 0x3fffffffUL
650#define PIO_RESERVED 0x40000000UL
651
652#define mmio_read16be(addr) readw_be(addr)
653#define mmio_read32be(addr) readl_be(addr)
654#define mmio_write16be(val, addr) writew_be(val, addr)
655#define mmio_write32be(val, addr) writel_be(val, addr)
656#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
657#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
658#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
659#define mmio_outsb(addr, src, count) writesb(addr, src, count)
660#define mmio_outsw(addr, src, count) writesw(addr, src, count)
661#define mmio_outsl(addr, src, count) writesl(addr, src, count)
662
211/** 663/**
212 * virt_to_phys - map virtual addresses to physical 664 * virt_to_phys - map virtual addresses to physical
213 * @address: address to remap 665 * @address: address to remap
@@ -254,178 +706,33 @@ static inline void * phys_to_virt(unsigned long address)
254 */ 706 */
255#define BIO_VMERGE_BOUNDARY 0 707#define BIO_VMERGE_BOUNDARY 0
256 708
257static inline void iosync(void)
258{
259 __asm__ __volatile__ ("sync" : : : "memory");
260}
261
262/* Enforce in-order execution of data I/O.
263 * No distinction between read/write on PPC; use eieio for all three.
264 */
265#define iobarrier_rw() eieio()
266#define iobarrier_r() eieio()
267#define iobarrier_w() eieio()
268
269/* 709/*
270 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. 710 * 32 bits still uses virt_to_bus() for it's implementation of DMA
271 * These routines do not perform EEH-related I/O address translation, 711 * mappings se we have to keep it defined here. We also have some old
272 * and should not be used directly by device drivers. Use inb/readb 712 * drivers (shame shame shame) that use bus_to_virt() and haven't been
273 * instead. 713 * fixed yet so I need to define it here.
274 */ 714 */
275static inline int __in_8(const volatile unsigned char __iomem *addr) 715#ifdef CONFIG_PPC32
276{
277 int ret;
278 716
279 __asm__ __volatile__("sync; lbz%U1%X1 %0,%1; twi 0,%0,0; isync" 717static inline unsigned long virt_to_bus(volatile void * address)
280 : "=r" (ret) : "m" (*addr));
281 return ret;
282}
283
284static inline void __out_8(volatile unsigned char __iomem *addr, int val)
285{
286 __asm__ __volatile__("sync; stb%U0%X0 %1,%0"
287 : "=m" (*addr) : "r" (val));
288 get_paca()->io_sync = 1;
289}
290
291static inline int __in_le16(const volatile unsigned short __iomem *addr)
292{ 718{
293 int ret; 719 if (address == NULL)
294 720 return 0;
295 __asm__ __volatile__("sync; lhbrx %0,0,%1; twi 0,%0,0; isync" 721 return __pa(address) + PCI_DRAM_OFFSET;
296 : "=r" (ret) : "r" (addr), "m" (*addr));
297 return ret;
298} 722}
299 723
300static inline int __in_be16(const volatile unsigned short __iomem *addr) 724static inline void * bus_to_virt(unsigned long address)
301{ 725{
302 int ret; 726 if (address == 0)
303 727 return NULL;
304 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1; twi 0,%0,0; isync" 728 return __va(address - PCI_DRAM_OFFSET);
305 : "=r" (ret) : "m" (*addr));
306 return ret;
307} 729}
308 730
309static inline void __out_le16(volatile unsigned short __iomem *addr, int val) 731#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
310{
311 __asm__ __volatile__("sync; sthbrx %1,0,%2"
312 : "=m" (*addr) : "r" (val), "r" (addr));
313 get_paca()->io_sync = 1;
314}
315
316static inline void __out_be16(volatile unsigned short __iomem *addr, int val)
317{
318 __asm__ __volatile__("sync; sth%U0%X0 %1,%0"
319 : "=m" (*addr) : "r" (val));
320 get_paca()->io_sync = 1;
321}
322
323static inline unsigned __in_le32(const volatile unsigned __iomem *addr)
324{
325 unsigned ret;
326
327 __asm__ __volatile__("sync; lwbrx %0,0,%1; twi 0,%0,0; isync"
328 : "=r" (ret) : "r" (addr), "m" (*addr));
329 return ret;
330}
331 732
332static inline unsigned __in_be32(const volatile unsigned __iomem *addr) 733#endif /* CONFIG_PPC32 */
333{
334 unsigned ret;
335
336 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
337 : "=r" (ret) : "m" (*addr));
338 return ret;
339}
340
341static inline void __out_le32(volatile unsigned __iomem *addr, int val)
342{
343 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
344 : "r" (val), "r" (addr));
345 get_paca()->io_sync = 1;
346}
347
348static inline void __out_be32(volatile unsigned __iomem *addr, int val)
349{
350 __asm__ __volatile__("sync; stw%U0%X0 %1,%0"
351 : "=m" (*addr) : "r" (val));
352 get_paca()->io_sync = 1;
353}
354
355static inline unsigned long __in_le64(const volatile unsigned long __iomem *addr)
356{
357 unsigned long tmp, ret;
358
359 __asm__ __volatile__(
360 "sync\n"
361 "ld %1,0(%2)\n"
362 "twi 0,%1,0\n"
363 "isync\n"
364 "rldimi %0,%1,5*8,1*8\n"
365 "rldimi %0,%1,3*8,2*8\n"
366 "rldimi %0,%1,1*8,3*8\n"
367 "rldimi %0,%1,7*8,4*8\n"
368 "rldicl %1,%1,32,0\n"
369 "rlwimi %0,%1,8,8,31\n"
370 "rlwimi %0,%1,24,16,23\n"
371 : "=r" (ret) , "=r" (tmp) : "b" (addr) , "m" (*addr));
372 return ret;
373}
374
375static inline unsigned long __in_be64(const volatile unsigned long __iomem *addr)
376{
377 unsigned long ret;
378 734
379 __asm__ __volatile__("sync; ld%U1%X1 %0,%1; twi 0,%0,0; isync"
380 : "=r" (ret) : "m" (*addr));
381 return ret;
382}
383
384static inline void __out_le64(volatile unsigned long __iomem *addr, unsigned long val)
385{
386 unsigned long tmp;
387
388 __asm__ __volatile__(
389 "rldimi %0,%1,5*8,1*8\n"
390 "rldimi %0,%1,3*8,2*8\n"
391 "rldimi %0,%1,1*8,3*8\n"
392 "rldimi %0,%1,7*8,4*8\n"
393 "rldicl %1,%1,32,0\n"
394 "rlwimi %0,%1,8,8,31\n"
395 "rlwimi %0,%1,24,16,23\n"
396 "sync\n"
397 "std %0,0(%3)"
398 : "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
399 get_paca()->io_sync = 1;
400}
401
402static inline void __out_be64(volatile unsigned long __iomem *addr, unsigned long val)
403{
404 __asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
405 get_paca()->io_sync = 1;
406}
407
408#include <asm/eeh.h>
409
410/* Nothing to do */
411
412#define dma_cache_inv(_start,_size) do { } while (0)
413#define dma_cache_wback(_start,_size) do { } while (0)
414#define dma_cache_wback_inv(_start,_size) do { } while (0)
415
416
417/*
418 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
419 * access
420 */
421#define xlate_dev_mem_ptr(p) __va(p)
422
423/*
424 * Convert a virtual cached pointer to an uncached pointer
425 */
426#define xlate_dev_kmem_ptr(p) p
427 735
428#endif /* __KERNEL__ */ 736#endif /* __KERNEL__ */
429 737
430#endif /* CONFIG_PPC64 */
431#endif /* _ASM_POWERPC_IO_H */ 738#endif /* _ASM_POWERPC_IO_H */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 39fad685ffab..f85dbd305558 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -34,7 +34,9 @@
34#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1)) 34#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
35#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE) 35#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
36 36
37#ifndef __ASSEMBLY__ 37/* Boot time flags */
38extern int iommu_is_off;
39extern int iommu_force_on;
38 40
39/* Pure 2^n version of get_order */ 41/* Pure 2^n version of get_order */
40static __inline__ __attribute_const__ int get_iommu_order(unsigned long size) 42static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
@@ -42,8 +44,6 @@ static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
42 return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1; 44 return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
43} 45}
44 46
45#endif /* __ASSEMBLY__ */
46
47 47
48/* 48/*
49 * IOMAP_MAX_ORDER defines the largest contiguous block 49 * IOMAP_MAX_ORDER defines the largest contiguous block
@@ -70,39 +70,31 @@ struct iommu_table {
70struct scatterlist; 70struct scatterlist;
71struct device_node; 71struct device_node;
72 72
73#ifdef CONFIG_PPC_MULTIPLATFORM
74
75/* Walks all buses and creates iommu tables */
76extern void iommu_setup_pSeries(void);
77extern void iommu_setup_dart(void);
78
79/* Frees table for an individual device node */ 73/* Frees table for an individual device node */
80extern void iommu_free_table(struct device_node *dn); 74extern void iommu_free_table(struct device_node *dn);
81 75
82#endif /* CONFIG_PPC_MULTIPLATFORM */
83
84/* Initializes an iommu_table based in values set in the passed-in 76/* Initializes an iommu_table based in values set in the passed-in
85 * structure 77 * structure
86 */ 78 */
87extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, 79extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
88 int nid); 80 int nid);
89 81
90extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl, 82extern int iommu_map_sg(struct iommu_table *tbl, struct scatterlist *sglist,
91 struct scatterlist *sglist, int nelems, unsigned long mask, 83 int nelems, unsigned long mask,
92 enum dma_data_direction direction); 84 enum dma_data_direction direction);
93extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, 85extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
94 int nelems, enum dma_data_direction direction); 86 int nelems, enum dma_data_direction direction);
95 87
96extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size, 88extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
97 dma_addr_t *dma_handle, unsigned long mask, 89 dma_addr_t *dma_handle, unsigned long mask,
98 gfp_t flag, int node); 90 gfp_t flag, int node);
99extern void iommu_free_coherent(struct iommu_table *tbl, size_t size, 91extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
100 void *vaddr, dma_addr_t dma_handle); 92 void *vaddr, dma_addr_t dma_handle);
101extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr, 93extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
102 size_t size, unsigned long mask, 94 size_t size, unsigned long mask,
103 enum dma_data_direction direction); 95 enum dma_data_direction direction);
104extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, 96extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
105 size_t size, enum dma_data_direction direction); 97 size_t size, enum dma_data_direction direction);
106 98
107extern void iommu_init_early_pSeries(void); 99extern void iommu_init_early_pSeries(void);
108extern void iommu_init_early_iSeries(void); 100extern void iommu_init_early_iSeries(void);
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index f960f5346f40..46476e9a494a 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -135,6 +135,10 @@ struct irq_map_entry {
135 135
136extern struct irq_map_entry irq_map[NR_IRQS]; 136extern struct irq_map_entry irq_map[NR_IRQS];
137 137
138static inline irq_hw_number_t virq_to_hw(unsigned int virq)
139{
140 return irq_map[virq].hwirq;
141}
138 142
139/** 143/**
140 * irq_alloc_host - Allocate a new irq_host data structure 144 * irq_alloc_host - Allocate a new irq_host data structure
diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h
index 0edbfe10cb37..6e323a13ac30 100644
--- a/include/asm-powerpc/iseries/iommu.h
+++ b/include/asm-powerpc/iseries/iommu.h
@@ -21,11 +21,13 @@
21 * Boston, MA 02111-1307 USA 21 * Boston, MA 02111-1307 USA
22 */ 22 */
23 23
24struct pci_dev;
24struct device_node; 25struct device_node;
25struct iommu_table; 26struct iommu_table;
26 27
27/* Creates table for an individual device node */ 28/* Creates table for an individual device node */
28extern void iommu_devnode_init_iSeries(struct device_node *dn); 29extern void iommu_devnode_init_iSeries(struct pci_dev *pdev,
30 struct device_node *dn);
29 31
30/* Get table parameters from HV */ 32/* Get table parameters from HV */
31extern void iommu_table_getparms_iSeries(unsigned long busno, 33extern void iommu_table_getparms_iSeries(unsigned long busno,
diff --git a/include/asm-powerpc/lv1call.h b/include/asm-powerpc/lv1call.h
new file mode 100644
index 000000000000..f733beeea63a
--- /dev/null
+++ b/include/asm-powerpc/lv1call.h
@@ -0,0 +1,345 @@
1/*
2 * PS3 hvcall interface.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 * Copyright 2003, 2004 (c) MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#if !defined(_ASM_POWERPC_LV1CALL_H)
23#define _ASM_POWERPC_LV1CALL_H
24
25#if !defined(__ASSEMBLY__)
26
27#include <linux/types.h>
28
29/* lv1 call declaration macros */
30
31#define LV1_1_IN_ARG_DECL u64 in_1
32#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
33#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
34#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
35#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
36#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
37#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
38#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
39#define LV1_1_OUT_ARG_DECL u64 *out_1
40#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
41#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
42#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
43#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
44#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
45#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
46
47#define LV1_0_IN_0_OUT_ARG_DECL void
48#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
49#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
50#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
51#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
52#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
53#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
54#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
55
56#define LV1_0_IN_1_OUT_ARG_DECL LV1_1_OUT_ARG_DECL
57#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
58#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
59#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
60#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
61#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
62#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
63#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
64#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
65
66#define LV1_0_IN_2_OUT_ARG_DECL LV1_2_OUT_ARG_DECL
67#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
68#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
69#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
70#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
71#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
72#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
73#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
74
75#define LV1_0_IN_3_OUT_ARG_DECL LV1_3_OUT_ARG_DECL
76#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
77#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
78#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
79#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
80#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
81#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
82#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
83
84#define LV1_0_IN_4_OUT_ARG_DECL LV1_4_OUT_ARG_DECL
85#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
86#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
87#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
88#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
89#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
90#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
91#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
92
93#define LV1_0_IN_5_OUT_ARG_DECL LV1_5_OUT_ARG_DECL
94#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
95#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
96#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
97#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
98#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
99#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
100#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
101
102#define LV1_0_IN_6_OUT_ARG_DECL LV1_6_OUT_ARG_DECL
103#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
104#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
105#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
106#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
107#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
108#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
109#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
110
111#define LV1_0_IN_7_OUT_ARG_DECL LV1_7_OUT_ARG_DECL
112#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
113#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
114#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
115#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
116#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
117#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
118#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
119
120#define LV1_1_IN_ARGS in_1
121#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
122#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
123#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
124#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
125#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
126#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
127#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
128
129#define LV1_1_OUT_ARGS out_1
130#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
131#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
132#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
133#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
134#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
135#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
136
137#define LV1_0_IN_0_OUT_ARGS
138#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
139#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
140#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
141#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
142#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
143#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
144#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
145
146#define LV1_0_IN_1_OUT_ARGS LV1_1_OUT_ARGS
147#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
148#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
149#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
150#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
151#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
152#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
153#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
154#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
155
156#define LV1_0_IN_2_OUT_ARGS LV1_2_OUT_ARGS
157#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
158#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
159#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
160#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
161#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
162#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
163#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
164
165#define LV1_0_IN_3_OUT_ARGS LV1_3_OUT_ARGS
166#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
167#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
168#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
169#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
170#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
171#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
172#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
173
174#define LV1_0_IN_4_OUT_ARGS LV1_4_OUT_ARGS
175#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
176#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
177#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
178#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
179#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
180#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
181#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
182
183#define LV1_0_IN_5_OUT_ARGS LV1_5_OUT_ARGS
184#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
185#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
186#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
187#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
188#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
189#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
190#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
191
192#define LV1_0_IN_6_OUT_ARGS LV1_6_OUT_ARGS
193#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
194#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
195#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
196#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
197#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
198#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
199#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
200
201#define LV1_0_IN_7_OUT_ARGS LV1_7_OUT_ARGS
202#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
203#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
204#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
205#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
206#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
207#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
208#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
209
210/*
211 * This LV1_CALL() macro is for use by callers. It expands into an
212 * inline call wrapper and an underscored HV call declaration. The
213 * wrapper can be used to instrument the lv1 call interface. The
214 * file lv1call.S defines its own LV1_CALL() macro to expand into
215 * the actual underscored call definition.
216 */
217
218#if !defined(LV1_CALL)
219#define LV1_CALL(name, in, out, num) \
220 extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL); \
221 static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
222 {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
223#endif
224
225#endif /* !defined(__ASSEMBLY__) */
226
227/* lv1 call table */
228
229LV1_CALL(allocate_memory, 4, 2, 0 )
230LV1_CALL(write_htab_entry, 4, 0, 1 )
231LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
232LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
233LV1_CALL(get_virtual_address_space_id_of_ppe, 1, 1, 4 )
234LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
235LV1_CALL(select_virtual_address_space, 1, 0, 7 )
236LV1_CALL(pause, 1, 0, 9 )
237LV1_CALL(destruct_virtual_address_space, 1, 0, 10 )
238LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 )
239LV1_CALL(connect_irq_plug_ext, 5, 0, 12 )
240LV1_CALL(release_memory, 1, 0, 13 )
241LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 )
242LV1_CALL(construct_event_receive_port, 0, 1, 18 )
243LV1_CALL(destruct_event_receive_port, 1, 0, 19 )
244LV1_CALL(send_event_locally, 1, 0, 24 )
245LV1_CALL(end_of_interrupt, 1, 0, 27 )
246LV1_CALL(connect_irq_plug, 2, 0, 28 )
247LV1_CALL(disconnect_irq_plug, 1, 0, 29 )
248LV1_CALL(end_of_interrupt_ext, 3, 0, 30 )
249LV1_CALL(did_update_interrupt_mask, 2, 0, 31 )
250LV1_CALL(shutdown_logical_partition, 1, 0, 44 )
251LV1_CALL(destruct_logical_spe, 1, 0, 54 )
252LV1_CALL(construct_logical_spe, 7, 6, 57 )
253LV1_CALL(set_spe_interrupt_mask, 3, 0, 61 )
254LV1_CALL(set_spe_transition_notifier, 3, 0, 64 )
255LV1_CALL(disable_logical_spe, 2, 0, 65 )
256LV1_CALL(clear_spe_interrupt_status, 4, 0, 66 )
257LV1_CALL(get_spe_interrupt_status, 2, 1, 67 )
258LV1_CALL(get_logical_ppe_id, 0, 1, 69 )
259LV1_CALL(set_interrupt_mask, 5, 0, 73 )
260LV1_CALL(get_logical_partition_id, 0, 1, 74 )
261LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
262LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
263LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
264LV1_CALL(create_repository_node, 6, 0, 90 )
265LV1_CALL(get_repository_node_value, 5, 2, 91 )
266LV1_CALL(modify_repository_node_value, 6, 0, 92 )
267LV1_CALL(remove_repository_node, 4, 0, 93 )
268LV1_CALL(read_htab_entries, 2, 5, 95 )
269LV1_CALL(set_dabr, 2, 0, 96 )
270LV1_CALL(get_total_execution_time, 2, 1, 103 )
271LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
272LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
273LV1_CALL(map_htab, 1, 1, 122 )
274LV1_CALL(unmap_htab, 1, 0, 123 )
275LV1_CALL(get_version_info, 0, 1, 127 )
276LV1_CALL(insert_htab_entry, 6, 3, 158 )
277LV1_CALL(read_virtual_uart, 3, 1, 162 )
278LV1_CALL(write_virtual_uart, 3, 1, 163 )
279LV1_CALL(set_virtual_uart_param, 3, 0, 164 )
280LV1_CALL(get_virtual_uart_param, 2, 1, 165 )
281LV1_CALL(configure_virtual_uart_irq, 1, 1, 166 )
282LV1_CALL(open_device, 3, 0, 170 )
283LV1_CALL(close_device, 2, 0, 171 )
284LV1_CALL(map_device_mmio_region, 5, 1, 172 )
285LV1_CALL(unmap_device_mmio_region, 3, 0, 173 )
286LV1_CALL(allocate_device_dma_region, 5, 1, 174 )
287LV1_CALL(free_device_dma_region, 3, 0, 175 )
288LV1_CALL(map_device_dma_region, 6, 0, 176 )
289LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
290LV1_CALL(net_add_multicast_address, 4, 0, 185 )
291LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
292LV1_CALL(net_start_tx_dma, 4, 0, 187 )
293LV1_CALL(net_stop_tx_dma, 3, 0, 188 )
294LV1_CALL(net_start_rx_dma, 4, 0, 189 )
295LV1_CALL(net_stop_rx_dma, 3, 0, 190 )
296LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
297LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
298LV1_CALL(net_control, 6, 2, 194 )
299LV1_CALL(connect_interrupt_event_receive_port, 4, 0, 197 )
300LV1_CALL(disconnect_interrupt_event_receive_port, 4, 0, 198 )
301LV1_CALL(get_spe_all_interrupt_statuses, 1, 1, 199 )
302LV1_CALL(deconfigure_virtual_uart_irq, 0, 0, 202 )
303LV1_CALL(enable_logical_spe, 2, 0, 207 )
304LV1_CALL(gpu_open, 1, 0, 210 )
305LV1_CALL(gpu_close, 0, 0, 211 )
306LV1_CALL(gpu_device_map, 1, 2, 212 )
307LV1_CALL(gpu_device_unmap, 1, 0, 213 )
308LV1_CALL(gpu_memory_allocate, 5, 2, 214 )
309LV1_CALL(gpu_memory_free, 1, 0, 216 )
310LV1_CALL(gpu_context_allocate, 2, 5, 217 )
311LV1_CALL(gpu_context_free, 1, 0, 218 )
312LV1_CALL(gpu_context_iomap, 5, 0, 221 )
313LV1_CALL(gpu_context_attribute, 6, 0, 225 )
314LV1_CALL(gpu_context_intr, 1, 1, 227 )
315LV1_CALL(gpu_attribute, 5, 0, 228 )
316LV1_CALL(get_rtc, 0, 2, 232 )
317LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 )
318LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 )
319LV1_CALL(stop_ppe_periodic_tracer, 1, 1, 242 )
320LV1_CALL(storage_read, 6, 1, 245 )
321LV1_CALL(storage_write, 6, 1, 246 )
322LV1_CALL(storage_send_device_command, 6, 1, 248 )
323LV1_CALL(storage_get_async_status, 1, 2, 249 )
324LV1_CALL(storage_check_async_status, 2, 1, 254 )
325LV1_CALL(panic, 1, 0, 255 )
326LV1_CALL(construct_lpm, 6, 3, 140 )
327LV1_CALL(destruct_lpm, 1, 0, 141 )
328LV1_CALL(start_lpm, 1, 0, 142 )
329LV1_CALL(stop_lpm, 1, 1, 143 )
330LV1_CALL(copy_lpm_trace_buffer, 3, 1, 144 )
331LV1_CALL(add_lpm_event_bookmark, 5, 0, 145 )
332LV1_CALL(delete_lpm_event_bookmark, 3, 0, 146 )
333LV1_CALL(set_lpm_interrupt_mask, 3, 1, 147 )
334LV1_CALL(get_lpm_interrupt_status, 1, 1, 148 )
335LV1_CALL(set_lpm_general_control, 5, 2, 149 )
336LV1_CALL(set_lpm_interval, 3, 1, 150 )
337LV1_CALL(set_lpm_trigger_control, 3, 1, 151 )
338LV1_CALL(set_lpm_counter_control, 4, 1, 152 )
339LV1_CALL(set_lpm_group_control, 3, 1, 153 )
340LV1_CALL(set_lpm_debug_bus_control, 3, 1, 154 )
341LV1_CALL(set_lpm_counter, 5, 2, 155 )
342LV1_CALL(set_lpm_signal, 7, 0, 156 )
343LV1_CALL(set_lpm_spr_trigger, 2, 0, 157 )
344
345#endif
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index dac90dc341cb..1b04e5723548 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -26,6 +26,7 @@ struct device_node;
26struct iommu_table; 26struct iommu_table;
27struct rtc_time; 27struct rtc_time;
28struct file; 28struct file;
29struct pci_controller;
29#ifdef CONFIG_KEXEC 30#ifdef CONFIG_KEXEC
30struct kimage; 31struct kimage;
31#endif 32#endif
@@ -84,9 +85,12 @@ struct machdep_calls {
84 unsigned long (*tce_get)(struct iommu_table *tbl, 85 unsigned long (*tce_get)(struct iommu_table *tbl,
85 long index); 86 long index);
86 void (*tce_flush)(struct iommu_table *tbl); 87 void (*tce_flush)(struct iommu_table *tbl);
87 void (*iommu_dev_setup)(struct pci_dev *dev); 88 void (*pci_dma_dev_setup)(struct pci_dev *dev);
88 void (*iommu_bus_setup)(struct pci_bus *bus); 89 void (*pci_dma_bus_setup)(struct pci_bus *bus);
89 void (*irq_bus_setup)(struct pci_bus *bus); 90
91 void __iomem * (*ioremap)(phys_addr_t addr, unsigned long size,
92 unsigned long flags);
93 void (*iounmap)(volatile void __iomem *token);
90#endif /* CONFIG_PPC64 */ 94#endif /* CONFIG_PPC64 */
91 95
92 int (*probe)(void); 96 int (*probe)(void);
@@ -106,6 +110,10 @@ struct machdep_calls {
106 /* Called after scanning the bus, before allocating resources */ 110 /* Called after scanning the bus, before allocating resources */
107 void (*pcibios_fixup)(void); 111 void (*pcibios_fixup)(void);
108 int (*pci_probe_mode)(struct pci_bus *); 112 int (*pci_probe_mode)(struct pci_bus *);
113 void (*pci_irq_fixup)(struct pci_dev *dev);
114
115 /* To setup PHBs when using automatic OF platform driver for PCI */
116 int (*pci_setup_phb)(struct pci_controller *host);
109 117
110 void (*restart)(char *cmd); 118 void (*restart)(char *cmd);
111 void (*power_off)(void); 119 void (*power_off)(void);
@@ -199,10 +207,6 @@ struct machdep_calls {
199 * Returns 0 to allow assignment/enabling of the device. */ 207 * Returns 0 to allow assignment/enabling of the device. */
200 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); 208 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
201 209
202 /* For interrupt routing */
203 unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
204 int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
205
206 /* Called in indirect_* to avoid touching devices */ 210 /* Called in indirect_* to avoid touching devices */
207 int (*pci_exclude_device)(unsigned char, unsigned char); 211 int (*pci_exclude_device)(unsigned char, unsigned char);
208 212
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index c3fc7a28e3cd..41c8c9c5a254 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -248,21 +248,6 @@ extern void hpte_init_native(void);
248extern void hpte_init_lpar(void); 248extern void hpte_init_lpar(void);
249extern void hpte_init_iSeries(void); 249extern void hpte_init_iSeries(void);
250 250
251extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
252 unsigned long va, unsigned long prpn,
253 unsigned long rflags,
254 unsigned long vflags, int psize);
255
256extern long native_hpte_insert(unsigned long hpte_group,
257 unsigned long va, unsigned long prpn,
258 unsigned long rflags,
259 unsigned long vflags, int psize);
260
261extern long iSeries_hpte_insert(unsigned long hpte_group,
262 unsigned long va, unsigned long prpn,
263 unsigned long rflags,
264 unsigned long vflags, int psize);
265
266extern void stabs_alloc(void); 251extern void stabs_alloc(void);
267extern void slb_initialize(void); 252extern void slb_initialize(void);
268extern void slb_flush_and_rebolt(void); 253extern void slb_flush_and_rebolt(void);
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
new file mode 100644
index 000000000000..4a28a850998c
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx.h
@@ -0,0 +1,254 @@
1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21
22/* ======================================================================== */
23/* Structures mapping of some unit register set */
24/* ======================================================================== */
25
26#ifndef __ASSEMBLY__
27
28/* Memory Mapping Control */
29struct mpc52xx_mmap_ctl {
30 u32 mbar; /* MMAP_CTRL + 0x00 */
31
32 u32 cs0_start; /* MMAP_CTRL + 0x04 */
33 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
34 u32 cs1_start; /* MMAP_CTRL + 0x0c */
35 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
36 u32 cs2_start; /* MMAP_CTRL + 0x14 */
37 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
38 u32 cs3_start; /* MMAP_CTRL + 0x1c */
39 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
40 u32 cs4_start; /* MMAP_CTRL + 0x24 */
41 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
42 u32 cs5_start; /* MMAP_CTRL + 0x2c */
43 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
44
45 u32 sdram0; /* MMAP_CTRL + 0x34 */
46 u32 sdram1; /* MMAP_CTRL + 0X38 */
47
48 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
49
50 u32 boot_start; /* MMAP_CTRL + 0x4c */
51 u32 boot_stop; /* MMAP_CTRL + 0x50 */
52
53 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
54
55 u32 cs6_start; /* MMAP_CTRL + 0x58 */
56 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
57 u32 cs7_start; /* MMAP_CTRL + 0x60 */
58 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
59};
60
61/* SDRAM control */
62struct mpc52xx_sdram {
63 u32 mode; /* SDRAM + 0x00 */
64 u32 ctrl; /* SDRAM + 0x04 */
65 u32 config1; /* SDRAM + 0x08 */
66 u32 config2; /* SDRAM + 0x0c */
67};
68
69/* SDMA */
70struct mpc52xx_sdma {
71 u32 taskBar; /* SDMA + 0x00 */
72 u32 currentPointer; /* SDMA + 0x04 */
73 u32 endPointer; /* SDMA + 0x08 */
74 u32 variablePointer; /* SDMA + 0x0c */
75
76 u8 IntVect1; /* SDMA + 0x10 */
77 u8 IntVect2; /* SDMA + 0x11 */
78 u16 PtdCntrl; /* SDMA + 0x12 */
79
80 u32 IntPend; /* SDMA + 0x14 */
81 u32 IntMask; /* SDMA + 0x18 */
82
83 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
84
85 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
86
87 u32 cReqSelect; /* SDMA + 0x5c */
88 u32 task_size0; /* SDMA + 0x60 */
89 u32 task_size1; /* SDMA + 0x64 */
90 u32 MDEDebug; /* SDMA + 0x68 */
91 u32 ADSDebug; /* SDMA + 0x6c */
92 u32 Value1; /* SDMA + 0x70 */
93 u32 Value2; /* SDMA + 0x74 */
94 u32 Control; /* SDMA + 0x78 */
95 u32 Status; /* SDMA + 0x7c */
96 u32 PTDDebug; /* SDMA + 0x80 */
97};
98
99/* GPT */
100struct mpc52xx_gpt {
101 u32 mode; /* GPTx + 0x00 */
102 u32 count; /* GPTx + 0x04 */
103 u32 pwm; /* GPTx + 0x08 */
104 u32 status; /* GPTx + 0X0c */
105};
106
107/* GPIO */
108struct mpc52xx_gpio {
109 u32 port_config; /* GPIO + 0x00 */
110 u32 simple_gpioe; /* GPIO + 0x04 */
111 u32 simple_ode; /* GPIO + 0x08 */
112 u32 simple_ddr; /* GPIO + 0x0c */
113 u32 simple_dvo; /* GPIO + 0x10 */
114 u32 simple_ival; /* GPIO + 0x14 */
115 u8 outo_gpioe; /* GPIO + 0x18 */
116 u8 reserved1[3]; /* GPIO + 0x19 */
117 u8 outo_dvo; /* GPIO + 0x1c */
118 u8 reserved2[3]; /* GPIO + 0x1d */
119 u8 sint_gpioe; /* GPIO + 0x20 */
120 u8 reserved3[3]; /* GPIO + 0x21 */
121 u8 sint_ode; /* GPIO + 0x24 */
122 u8 reserved4[3]; /* GPIO + 0x25 */
123 u8 sint_ddr; /* GPIO + 0x28 */
124 u8 reserved5[3]; /* GPIO + 0x29 */
125 u8 sint_dvo; /* GPIO + 0x2c */
126 u8 reserved6[3]; /* GPIO + 0x2d */
127 u8 sint_inten; /* GPIO + 0x30 */
128 u8 reserved7[3]; /* GPIO + 0x31 */
129 u16 sint_itype; /* GPIO + 0x34 */
130 u16 reserved8; /* GPIO + 0x36 */
131 u8 gpio_control; /* GPIO + 0x38 */
132 u8 reserved9[3]; /* GPIO + 0x39 */
133 u8 sint_istat; /* GPIO + 0x3c */
134 u8 sint_ival; /* GPIO + 0x3d */
135 u8 bus_errs; /* GPIO + 0x3e */
136 u8 reserved10; /* GPIO + 0x3f */
137};
138
139#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
140#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
141#define MPC52xx_GPIO_PCI_DIS (1<<15)
142
143/* GPIO with WakeUp*/
144struct mpc52xx_gpio_wkup {
145 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
146 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
147 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
148 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
149 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
150 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
151 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
152 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
153 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
154 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
155 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
156 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
157 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
158 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
159 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
160 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
161 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
162 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
163 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
164 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
165};
166
167/* XLB Bus control */
168struct mpc52xx_xlb {
169 u8 reserved[0x40];
170 u32 config; /* XLB + 0x40 */
171 u32 version; /* XLB + 0x44 */
172 u32 status; /* XLB + 0x48 */
173 u32 int_enable; /* XLB + 0x4c */
174 u32 addr_capture; /* XLB + 0x50 */
175 u32 bus_sig_capture; /* XLB + 0x54 */
176 u32 addr_timeout; /* XLB + 0x58 */
177 u32 data_timeout; /* XLB + 0x5c */
178 u32 bus_act_timeout; /* XLB + 0x60 */
179 u32 master_pri_enable; /* XLB + 0x64 */
180 u32 master_priority; /* XLB + 0x68 */
181 u32 base_address; /* XLB + 0x6c */
182 u32 snoop_window; /* XLB + 0x70 */
183};
184
185#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
186#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
187
188/* Clock Distribution control */
189struct mpc52xx_cdm {
190 u32 jtag_id; /* CDM + 0x00 reg0 read only */
191 u32 rstcfg; /* CDM + 0x04 reg1 read only */
192 u32 breadcrumb; /* CDM + 0x08 reg2 */
193
194 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
195 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
196 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
197 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
198
199 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
200 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
201 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
202
203 u32 clk_enables; /* CDM + 0x14 reg5 */
204
205 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
206 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
207
208 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
209 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
210 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
211 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
212
213 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
214 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
215 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
216
217 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
218 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
219 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
220 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
221
222 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
223 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
224
225 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
226 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
227
228 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
229 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
230
231 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
232 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
233};
234
235#endif /* __ASSEMBLY__ */
236
237
238/* ========================================================================= */
239/* Prototypes for MPC52xx sysdev */
240/* ========================================================================= */
241
242#ifndef __ASSEMBLY__
243
244extern void __iomem * mpc52xx_find_and_map(const char *);
245extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
246extern void mpc52xx_setup_cpu(void);
247
248extern void mpc52xx_init_irq(void);
249extern unsigned int mpc52xx_get_irq(void);
250
251#endif /* __ASSEMBLY__ */
252
253#endif /* __ASM_POWERPC_MPC52xx_H__ */
254
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
index ccdb8a21138f..54142997a584 100644
--- a/include/asm-powerpc/mpc85xx.h
+++ b/include/asm-powerpc/mpc85xx.h
@@ -31,14 +31,6 @@
31#include <platforms/85xx/mpc85xx_cds.h> 31#include <platforms/85xx/mpc85xx_cds.h>
32#endif 32#endif
33 33
34#define _IO_BASE isa_io_base
35#define _ISA_MEM_BASE isa_mem_base
36#ifdef CONFIG_PCI
37#define PCI_DRAM_OFFSET pci_dram_offset
38#else
39#define PCI_DRAM_OFFSET 0
40#endif
41
42/* Let modules/drivers get at CCSRBAR */ 34/* Let modules/drivers get at CCSRBAR */
43extern phys_addr_t get_ccsrbar(void); 35extern phys_addr_t get_ccsrbar(void);
44 36
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index ef0a5458d2b2..b71e7b32a555 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/irq.h> 5#include <linux/irq.h>
6#include <asm/dcr.h>
6 7
7/* 8/*
8 * Global registers 9 * Global registers
@@ -225,6 +226,23 @@ struct mpic_irq_fixup
225#endif /* CONFIG_MPIC_BROKEN_U3 */ 226#endif /* CONFIG_MPIC_BROKEN_U3 */
226 227
227 228
229enum mpic_reg_type {
230 mpic_access_mmio_le,
231 mpic_access_mmio_be,
232#ifdef CONFIG_PPC_DCR
233 mpic_access_dcr
234#endif
235};
236
237struct mpic_reg_bank {
238 u32 __iomem *base;
239#ifdef CONFIG_PPC_DCR
240 dcr_host_t dhost;
241 unsigned int dbase;
242 unsigned int doff;
243#endif /* CONFIG_PPC_DCR */
244};
245
228/* The instance data of a given MPIC */ 246/* The instance data of a given MPIC */
229struct mpic 247struct mpic
230{ 248{
@@ -264,11 +282,18 @@ struct mpic
264 spinlock_t fixup_lock; 282 spinlock_t fixup_lock;
265#endif 283#endif
266 284
285 /* Register access method */
286 enum mpic_reg_type reg_type;
287
267 /* The various ioremap'ed bases */ 288 /* The various ioremap'ed bases */
268 volatile u32 __iomem *gregs; 289 struct mpic_reg_bank gregs;
269 volatile u32 __iomem *tmregs; 290 struct mpic_reg_bank tmregs;
270 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; 291 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
271 volatile u32 __iomem *isus[MPIC_MAX_ISU]; 292 struct mpic_reg_bank isus[MPIC_MAX_ISU];
293
294#ifdef CONFIG_PPC_DCR
295 unsigned int dcr_base;
296#endif
272 297
273#ifdef CONFIG_MPIC_WEIRD 298#ifdef CONFIG_MPIC_WEIRD
274 /* Pointer to HW info array */ 299 /* Pointer to HW info array */
@@ -305,6 +330,8 @@ struct mpic
305#define MPIC_SPV_EOI 0x00000020 330#define MPIC_SPV_EOI 0x00000020
306/* No passthrough disable */ 331/* No passthrough disable */
307#define MPIC_NO_PTHROU_DIS 0x00000040 332#define MPIC_NO_PTHROU_DIS 0x00000040
333/* DCR based MPIC */
334#define MPIC_USES_DCR 0x00000080
308 335
309/* MPIC HW modification ID */ 336/* MPIC HW modification ID */
310#define MPIC_REGSET_MASK 0xf0000000 337#define MPIC_REGSET_MASK 0xf0000000
@@ -337,7 +364,7 @@ struct mpic
337 * that is senses[0] correspond to linux irq "irq_offset". 364 * that is senses[0] correspond to linux irq "irq_offset".
338 */ 365 */
339extern struct mpic *mpic_alloc(struct device_node *node, 366extern struct mpic *mpic_alloc(struct device_node *node,
340 unsigned long phys_addr, 367 phys_addr_t phys_addr,
341 unsigned int flags, 368 unsigned int flags,
342 unsigned int isu_size, 369 unsigned int isu_size,
343 unsigned int irq_count, 370 unsigned int irq_count,
@@ -350,7 +377,7 @@ extern struct mpic *mpic_alloc(struct device_node *node,
350 * @phys_addr: physical address of the ISU 377 * @phys_addr: physical address of the ISU
351 */ 378 */
352extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 379extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
353 unsigned long phys_addr); 380 phys_addr_t phys_addr);
354 381
355/* Set default sense codes 382/* Set default sense codes
356 * 383 *
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
index c5c0b0b3cd52..a889b2005bf5 100644
--- a/include/asm-powerpc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -6,12 +6,6 @@
6#include <linux/mod_devicetable.h> 6#include <linux/mod_devicetable.h>
7#include <asm/prom.h> 7#include <asm/prom.h>
8 8
9/*
10 * The of_platform_bus_type is a bus type used by drivers that do not
11 * attach to a macio or similar bus but still use OF probing
12 * mechanism
13 */
14extern struct bus_type of_platform_bus_type;
15 9
16/* 10/*
17 * The of_device is a kind of "base class" that is a superset of 11 * The of_device is a kind of "base class" that is a superset of
@@ -20,46 +14,22 @@ extern struct bus_type of_platform_bus_type;
20 */ 14 */
21struct of_device 15struct of_device
22{ 16{
23 struct device_node *node; /* OF device node */ 17 struct device_node *node; /* to be obsoleted */
24 u64 dma_mask; /* DMA mask */ 18 u64 dma_mask; /* DMA mask */
25 struct device dev; /* Generic device interface */ 19 struct device dev; /* Generic device interface */
26}; 20};
27#define to_of_device(d) container_of(d, struct of_device, dev) 21#define to_of_device(d) container_of(d, struct of_device, dev)
28 22
23extern const struct of_device_id *of_match_node(
24 const struct of_device_id *matches, const struct device_node *node);
29extern const struct of_device_id *of_match_device( 25extern const struct of_device_id *of_match_device(
30 const struct of_device_id *matches, const struct of_device *dev); 26 const struct of_device_id *matches, const struct of_device *dev);
31 27
32extern struct of_device *of_dev_get(struct of_device *dev); 28extern struct of_device *of_dev_get(struct of_device *dev);
33extern void of_dev_put(struct of_device *dev); 29extern void of_dev_put(struct of_device *dev);
34 30
35/*
36 * An of_platform_driver driver is attached to a basic of_device on
37 * the "platform bus" (of_platform_bus_type)
38 */
39struct of_platform_driver
40{
41 char *name;
42 struct of_device_id *match_table;
43 struct module *owner;
44
45 int (*probe)(struct of_device* dev, const struct of_device_id *match);
46 int (*remove)(struct of_device* dev);
47
48 int (*suspend)(struct of_device* dev, pm_message_t state);
49 int (*resume)(struct of_device* dev);
50 int (*shutdown)(struct of_device* dev);
51
52 struct device_driver driver;
53};
54#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
55
56extern int of_register_driver(struct of_platform_driver *drv);
57extern void of_unregister_driver(struct of_platform_driver *drv);
58extern int of_device_register(struct of_device *ofdev); 31extern int of_device_register(struct of_device *ofdev);
59extern void of_device_unregister(struct of_device *ofdev); 32extern void of_device_unregister(struct of_device *ofdev);
60extern struct of_device *of_platform_device_create(struct device_node *np,
61 const char *bus_id,
62 struct device *parent);
63extern void of_release_dev(struct device *dev); 33extern void of_release_dev(struct device *dev);
64 34
65#endif /* __KERNEL__ */ 35#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h
new file mode 100644
index 000000000000..217eafb167e9
--- /dev/null
+++ b/include/asm-powerpc/of_platform.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
3 * <benh@kernel.crashing.org>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 */
11
12#include <asm/of_device.h>
13
14/*
15 * The of_platform_bus_type is a bus type used by drivers that do not
16 * attach to a macio or similar bus but still use OF probing
17 * mechanism
18 */
19extern struct bus_type of_platform_bus_type;
20
21/*
22 * An of_platform_driver driver is attached to a basic of_device on
23 * the "platform bus" (of_platform_bus_type)
24 */
25struct of_platform_driver
26{
27 char *name;
28 struct of_device_id *match_table;
29 struct module *owner;
30
31 int (*probe)(struct of_device* dev,
32 const struct of_device_id *match);
33 int (*remove)(struct of_device* dev);
34
35 int (*suspend)(struct of_device* dev, pm_message_t state);
36 int (*resume)(struct of_device* dev);
37 int (*shutdown)(struct of_device* dev);
38
39 struct device_driver driver;
40};
41#define to_of_platform_driver(drv) \
42 container_of(drv,struct of_platform_driver, driver)
43
44/* Platform drivers register/unregister */
45extern int of_register_platform_driver(struct of_platform_driver *drv);
46extern void of_unregister_platform_driver(struct of_platform_driver *drv);
47
48/* Platform devices and busses creation */
49extern struct of_device *of_platform_device_create(struct device_node *np,
50 const char *bus_id,
51 struct device *parent);
52/* pseudo "matches" value to not do deep probe */
53#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
54
55extern int of_platform_bus_probe(struct device_node *root,
56 struct of_device_id *matches,
57 struct device *parent);
58
59extern struct of_device *of_find_device_by_node(struct device_node *np);
60extern struct of_device *of_find_device_by_phandle(phandle ph);
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
index 07a10e590c1d..71043bf3641f 100644
--- a/include/asm-powerpc/oprofile_impl.h
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -44,7 +44,9 @@ struct op_powerpc_model {
44 int num_counters); 44 int num_counters);
45 void (*cpu_setup) (struct op_counter_config *); 45 void (*cpu_setup) (struct op_counter_config *);
46 void (*start) (struct op_counter_config *); 46 void (*start) (struct op_counter_config *);
47 void (*global_start) (struct op_counter_config *);
47 void (*stop) (void); 48 void (*stop) (void);
49 void (*global_stop) (void);
48 void (*handle_interrupt) (struct pt_regs *, 50 void (*handle_interrupt) (struct pt_regs *,
49 struct op_counter_config *); 51 struct op_counter_config *);
50 int num_counters; 52 int num_counters;
@@ -54,6 +56,7 @@ extern struct op_powerpc_model op_model_fsl_booke;
54extern struct op_powerpc_model op_model_rs64; 56extern struct op_powerpc_model op_model_rs64;
55extern struct op_powerpc_model op_model_power4; 57extern struct op_powerpc_model op_model_power4;
56extern struct op_powerpc_model op_model_7450; 58extern struct op_powerpc_model op_model_7450;
59extern struct op_powerpc_model op_model_cell;
57 60
58#ifndef CONFIG_FSL_BOOKE 61#ifndef CONFIG_FSL_BOOKE
59 62
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 0a4e5c93e8e6..0d3adc09c847 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -93,7 +93,8 @@ struct paca_struct {
93 u64 stab_rr; /* stab/slb round-robin counter */ 93 u64 stab_rr; /* stab/slb round-robin counter */
94 u64 saved_r1; /* r1 save for RTAS calls */ 94 u64 saved_r1; /* r1 save for RTAS calls */
95 u64 saved_msr; /* MSR saved here by enter_rtas */ 95 u64 saved_msr; /* MSR saved here by enter_rtas */
96 u8 proc_enabled; /* irq soft-enable flag */ 96 u8 soft_enabled; /* irq soft-enable flag */
97 u8 hard_enabled; /* set if irqs are enabled in MSR */
97 u8 io_sync; /* writel() needs spin_unlock sync */ 98 u8 io_sync; /* writel() needs spin_unlock sync */
98 99
99 /* Stuff for accurate time accounting */ 100 /* Stuff for accurate time accounting */
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index 86ee46b09b8a..7bb7f9009806 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -25,6 +25,7 @@ struct pci_controller {
25 int node; 25 int node;
26 void *arch_data; 26 void *arch_data;
27 struct list_head list_node; 27 struct list_head list_node;
28 struct device *parent;
28 29
29 int first_busno; 30 int first_busno;
30 int last_busno; 31 int last_busno;
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 721c97f09b20..16f13319c769 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -70,15 +70,15 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
70 */ 70 */
71#define PCI_DISABLE_MWI 71#define PCI_DISABLE_MWI
72 72
73extern struct dma_mapping_ops pci_dma_ops; 73extern struct dma_mapping_ops *pci_dma_ops;
74 74
75/* For DAC DMA, we currently don't support it by default, but 75/* For DAC DMA, we currently don't support it by default, but
76 * we let 64-bit platforms override this. 76 * we let 64-bit platforms override this.
77 */ 77 */
78static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask) 78static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
79{ 79{
80 if (pci_dma_ops.dac_dma_supported) 80 if (pci_dma_ops && pci_dma_ops->dac_dma_supported)
81 return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask); 81 return pci_dma_ops->dac_dma_supported(&hwdev->dev, mask);
82 return 0; 82 return 0;
83} 83}
84 84
@@ -210,6 +210,8 @@ extern int remap_bus_range(struct pci_bus *bus);
210extern void pcibios_fixup_device_resources(struct pci_dev *dev, 210extern void pcibios_fixup_device_resources(struct pci_dev *dev,
211 struct pci_bus *bus); 211 struct pci_bus *bus);
212 212
213extern void pcibios_setup_new_device(struct pci_dev *dev);
214
213extern void pcibios_claim_one_bus(struct pci_bus *b); 215extern void pcibios_claim_one_bus(struct pci_bus *b);
214 216
215extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 217extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
@@ -232,12 +234,10 @@ extern pgprot_t pci_phys_mem_access_prot(struct file *file,
232 unsigned long size, 234 unsigned long size,
233 pgprot_t prot); 235 pgprot_t prot);
234 236
235#if defined(CONFIG_PPC_MULTIPLATFORM) || defined(CONFIG_PPC32)
236#define HAVE_ARCH_PCI_RESOURCE_TO_USER 237#define HAVE_ARCH_PCI_RESOURCE_TO_USER
237extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 238extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
238 const struct resource *rsrc, 239 const struct resource *rsrc,
239 resource_size_t *start, resource_size_t *end); 240 resource_size_t *start, resource_size_t *end);
240#endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
241 241
242#endif /* __KERNEL__ */ 242#endif /* __KERNEL__ */
243#endif /* __ASM_POWERPC_PCI_H */ 243#endif /* __ASM_POWERPC_PCI_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index 1115756c79f9..ab6eddb518c7 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -36,18 +36,17 @@ typedef void *(*traverse_func)(struct device_node *me, void *data);
36void *traverse_pci_devices(struct device_node *start, traverse_func pre, 36void *traverse_pci_devices(struct device_node *start, traverse_func pre,
37 void *data); 37 void *data);
38 38
39void pci_devs_phb_init(void); 39extern void pci_devs_phb_init(void);
40void pci_devs_phb_init_dynamic(struct pci_controller *phb); 40extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
41int setup_phb(struct device_node *dev, struct pci_controller *phb); 41extern void scan_phb(struct pci_controller *hose);
42void __devinit scan_phb(struct pci_controller *hose);
43 42
44/* From rtas_pci.h */ 43/* From rtas_pci.h */
45void init_pci_config_tokens (void); 44extern void init_pci_config_tokens (void);
46unsigned long get_phb_buid (struct device_node *); 45extern unsigned long get_phb_buid (struct device_node *);
46extern int rtas_setup_phb(struct pci_controller *phb);
47 47
48/* From pSeries_pci.h */ 48/* From pSeries_pci.h */
49extern void pSeries_final_fixup(void); 49extern void pSeries_final_fixup(void);
50extern void pSeries_irq_bus_setup(struct pci_bus *bus);
51 50
52extern unsigned long pci_probe_only; 51extern unsigned long pci_probe_only;
53 52
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index 6cb6fb19e57f..a26c32ee5527 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -53,10 +53,6 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
53 53
54#endif /* CONFIG_PPC_PREP */ 54#endif /* CONFIG_PPC_PREP */
55 55
56#ifndef CONFIG_PPC_MULTIPLATFORM
57#define _machine 0
58#endif /* CONFIG_PPC_MULTIPLATFORM */
59
60#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 56#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
61 57
62/* 58/*
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index ec11d44eaeb5..0afee17f33b4 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -17,6 +17,7 @@
17 */ 17 */
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/proc_fs.h> 19#include <linux/proc_fs.h>
20#include <linux/platform_device.h>
20#include <asm/atomic.h> 21#include <asm/atomic.h>
21 22
22/* Definitions used by the flattened device tree */ 23/* Definitions used by the flattened device tree */
@@ -333,6 +334,20 @@ extern int of_irq_map_one(struct device_node *device, int index,
333struct pci_dev; 334struct pci_dev;
334extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq); 335extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
335 336
337static inline int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
338{
339 int irq = irq_of_parse_and_map(dev, index);
340
341 /* Only dereference the resource if both the
342 * resource and the irq are valid. */
343 if (r && irq != NO_IRQ) {
344 r->start = r->end = irq;
345 r->flags = IORESOURCE_IRQ;
346 }
347
348 return irq;
349}
350
336 351
337#endif /* __KERNEL__ */ 352#endif /* __KERNEL__ */
338#endif /* _POWERPC_PROM_H */ 353#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
new file mode 100644
index 000000000000..52a69ed0d90a
--- /dev/null
+++ b/include/asm-powerpc/ps3.h
@@ -0,0 +1,462 @@
1/*
2 * PS3 platform declarations.
3 *
4 * Copyright (C) 2006 Sony Computer Entertainment Inc.
5 * Copyright 2006 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#if !defined(_ASM_POWERPC_PS3_H)
22#define _ASM_POWERPC_PS3_H
23
24#include <linux/compiler.h> /* for __deprecated */
25#include <linux/init.h>
26#include <linux/types.h>
27#include <linux/device.h>
28
29/**
30 * struct ps3_device_id - HV bus device identifier from the system repository
31 * @bus_id: HV bus id, {1..} (zero invalid)
32 * @dev_id: HV device id, {0..}
33 */
34
35struct ps3_device_id {
36 unsigned int bus_id;
37 unsigned int dev_id;
38};
39
40
41/* dma routines */
42
43enum ps3_dma_page_size {
44 PS3_DMA_4K = 12U,
45 PS3_DMA_64K = 16U,
46 PS3_DMA_1M = 20U,
47 PS3_DMA_16M = 24U,
48};
49
50enum ps3_dma_region_type {
51 PS3_DMA_OTHER = 0,
52 PS3_DMA_INTERNAL = 2,
53};
54
55/**
56 * struct ps3_dma_region - A per device dma state variables structure
57 * @did: The HV device id.
58 * @page_size: The ioc pagesize.
59 * @region_type: The HV region type.
60 * @bus_addr: The 'translated' bus address of the region.
61 * @len: The length in bytes of the region.
62 * @chunk_list: Opaque variable used by the ioc page manager.
63 */
64
65struct ps3_dma_region {
66 struct ps3_device_id did;
67 enum ps3_dma_page_size page_size;
68 enum ps3_dma_region_type region_type;
69 unsigned long bus_addr;
70 unsigned long len;
71 struct {
72 spinlock_t lock;
73 struct list_head head;
74 } chunk_list;
75};
76
77/**
78 * struct ps3_dma_region_init - Helper to initialize structure variables
79 *
80 * Helper to properly initialize variables prior to calling
81 * ps3_system_bus_device_register.
82 */
83
84static inline void ps3_dma_region_init(struct ps3_dma_region *r,
85 const struct ps3_device_id* did, enum ps3_dma_page_size page_size,
86 enum ps3_dma_region_type region_type)
87{
88 r->did = *did;
89 r->page_size = page_size;
90 r->region_type = region_type;
91}
92int ps3_dma_region_create(struct ps3_dma_region *r);
93int ps3_dma_region_free(struct ps3_dma_region *r);
94int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
95 unsigned long len, unsigned long *bus_addr);
96int ps3_dma_unmap(struct ps3_dma_region *r, unsigned long bus_addr,
97 unsigned long len);
98
99/* mmio routines */
100
101enum ps3_mmio_page_size {
102 PS3_MMIO_4K = 12U,
103 PS3_MMIO_64K = 16U
104};
105
106/**
107 * struct ps3_mmio_region - a per device mmio state variables structure
108 *
109 * Current systems can be supported with a single region per device.
110 */
111
112struct ps3_mmio_region {
113 struct ps3_device_id did;
114 unsigned long bus_addr;
115 unsigned long len;
116 enum ps3_mmio_page_size page_size;
117 unsigned long lpar_addr;
118};
119
120/**
121 * struct ps3_mmio_region_init - Helper to initialize structure variables
122 *
123 * Helper to properly initialize variables prior to calling
124 * ps3_system_bus_device_register.
125 */
126
127static inline void ps3_mmio_region_init(struct ps3_mmio_region *r,
128 const struct ps3_device_id* did, unsigned long bus_addr,
129 unsigned long len, enum ps3_mmio_page_size page_size)
130{
131 r->did = *did;
132 r->bus_addr = bus_addr;
133 r->len = len;
134 r->page_size = page_size;
135}
136int ps3_mmio_region_create(struct ps3_mmio_region *r);
137int ps3_free_mmio_region(struct ps3_mmio_region *r);
138unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
139
140/* inrerrupt routines */
141
142int ps3_alloc_io_irq(unsigned int interrupt_id, unsigned int *virq);
143int ps3_free_io_irq(unsigned int virq);
144int ps3_alloc_event_irq(unsigned int *virq);
145int ps3_free_event_irq(unsigned int virq);
146int ps3_send_event_locally(unsigned int virq);
147int ps3_connect_event_irq(const struct ps3_device_id *did,
148 unsigned int interrupt_id, unsigned int *virq);
149int ps3_disconnect_event_irq(const struct ps3_device_id *did,
150 unsigned int interrupt_id, unsigned int virq);
151int ps3_alloc_vuart_irq(void* virt_addr_bmp, unsigned int *virq);
152int ps3_free_vuart_irq(unsigned int virq);
153int ps3_alloc_spe_irq(unsigned long spe_id, unsigned int class,
154 unsigned int *virq);
155int ps3_free_spe_irq(unsigned int virq);
156
157/* lv1 result codes */
158
159enum lv1_result {
160 LV1_SUCCESS = 0,
161 /* not used -1 */
162 LV1_RESOURCE_SHORTAGE = -2,
163 LV1_NO_PRIVILEGE = -3,
164 LV1_DENIED_BY_POLICY = -4,
165 LV1_ACCESS_VIOLATION = -5,
166 LV1_NO_ENTRY = -6,
167 LV1_DUPLICATE_ENTRY = -7,
168 LV1_TYPE_MISMATCH = -8,
169 LV1_BUSY = -9,
170 LV1_EMPTY = -10,
171 LV1_WRONG_STATE = -11,
172 /* not used -12 */
173 LV1_NO_MATCH = -13,
174 LV1_ALREADY_CONNECTED = -14,
175 LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
176 LV1_CONDITION_NOT_SATISFIED = -16,
177 LV1_ILLEGAL_PARAMETER_VALUE = -17,
178 LV1_BAD_OPTION = -18,
179 LV1_IMPLEMENTATION_LIMITATION = -19,
180 LV1_NOT_IMPLEMENTED = -20,
181 LV1_INVALID_CLASS_ID = -21,
182 LV1_CONSTRAINT_NOT_SATISFIED = -22,
183 LV1_ALIGNMENT_ERROR = -23,
184 LV1_INTERNAL_ERROR = -32768,
185};
186
187static inline const char* ps3_result(int result)
188{
189#if defined(DEBUG)
190 switch (result) {
191 case LV1_SUCCESS:
192 return "LV1_SUCCESS (0)";
193 case -1:
194 return "** unknown result ** (-1)";
195 case LV1_RESOURCE_SHORTAGE:
196 return "LV1_RESOURCE_SHORTAGE (-2)";
197 case LV1_NO_PRIVILEGE:
198 return "LV1_NO_PRIVILEGE (-3)";
199 case LV1_DENIED_BY_POLICY:
200 return "LV1_DENIED_BY_POLICY (-4)";
201 case LV1_ACCESS_VIOLATION:
202 return "LV1_ACCESS_VIOLATION (-5)";
203 case LV1_NO_ENTRY:
204 return "LV1_NO_ENTRY (-6)";
205 case LV1_DUPLICATE_ENTRY:
206 return "LV1_DUPLICATE_ENTRY (-7)";
207 case LV1_TYPE_MISMATCH:
208 return "LV1_TYPE_MISMATCH (-8)";
209 case LV1_BUSY:
210 return "LV1_BUSY (-9)";
211 case LV1_EMPTY:
212 return "LV1_EMPTY (-10)";
213 case LV1_WRONG_STATE:
214 return "LV1_WRONG_STATE (-11)";
215 case -12:
216 return "** unknown result ** (-12)";
217 case LV1_NO_MATCH:
218 return "LV1_NO_MATCH (-13)";
219 case LV1_ALREADY_CONNECTED:
220 return "LV1_ALREADY_CONNECTED (-14)";
221 case LV1_UNSUPPORTED_PARAMETER_VALUE:
222 return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
223 case LV1_CONDITION_NOT_SATISFIED:
224 return "LV1_CONDITION_NOT_SATISFIED (-16)";
225 case LV1_ILLEGAL_PARAMETER_VALUE:
226 return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
227 case LV1_BAD_OPTION:
228 return "LV1_BAD_OPTION (-18)";
229 case LV1_IMPLEMENTATION_LIMITATION:
230 return "LV1_IMPLEMENTATION_LIMITATION (-19)";
231 case LV1_NOT_IMPLEMENTED:
232 return "LV1_NOT_IMPLEMENTED (-20)";
233 case LV1_INVALID_CLASS_ID:
234 return "LV1_INVALID_CLASS_ID (-21)";
235 case LV1_CONSTRAINT_NOT_SATISFIED:
236 return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
237 case LV1_ALIGNMENT_ERROR:
238 return "LV1_ALIGNMENT_ERROR (-23)";
239 case LV1_INTERNAL_ERROR:
240 return "LV1_INTERNAL_ERROR (-32768)";
241 default:
242 BUG();
243 return "** unknown result **";
244 };
245#else
246 return "";
247#endif
248}
249
250/* repository bus info */
251
252enum ps3_bus_type {
253 PS3_BUS_TYPE_SB = 4,
254 PS3_BUS_TYPE_STORAGE = 5,
255};
256
257enum ps3_dev_type {
258 PS3_DEV_TYPE_SB_GELIC = 3,
259 PS3_DEV_TYPE_SB_USB = 4,
260 PS3_DEV_TYPE_SB_GPIO = 6,
261};
262
263int ps3_repository_read_bus_str(unsigned int bus_index, const char *bus_str,
264 u64 *value);
265int ps3_repository_read_bus_id(unsigned int bus_index, unsigned int *bus_id);
266int ps3_repository_read_bus_type(unsigned int bus_index,
267 enum ps3_bus_type *bus_type);
268int ps3_repository_read_bus_num_dev(unsigned int bus_index,
269 unsigned int *num_dev);
270
271/* repository bus device info */
272
273enum ps3_interrupt_type {
274 PS3_INTERRUPT_TYPE_EVENT_PORT = 2,
275 PS3_INTERRUPT_TYPE_SB_OHCI = 3,
276 PS3_INTERRUPT_TYPE_SB_EHCI = 4,
277 PS3_INTERRUPT_TYPE_OTHER = 5,
278};
279
280enum ps3_region_type {
281 PS3_REGION_TYPE_SB_OHCI = 3,
282 PS3_REGION_TYPE_SB_EHCI = 4,
283 PS3_REGION_TYPE_SB_GPIO = 5,
284};
285
286int ps3_repository_read_dev_str(unsigned int bus_index,
287 unsigned int dev_index, const char *dev_str, u64 *value);
288int ps3_repository_read_dev_id(unsigned int bus_index, unsigned int dev_index,
289 unsigned int *dev_id);
290int ps3_repository_read_dev_type(unsigned int bus_index,
291 unsigned int dev_index, enum ps3_dev_type *dev_type);
292int ps3_repository_read_dev_intr(unsigned int bus_index,
293 unsigned int dev_index, unsigned int intr_index,
294 enum ps3_interrupt_type *intr_type, unsigned int *interrupt_id);
295int ps3_repository_read_dev_reg_type(unsigned int bus_index,
296 unsigned int dev_index, unsigned int reg_index,
297 enum ps3_region_type *reg_type);
298int ps3_repository_read_dev_reg_addr(unsigned int bus_index,
299 unsigned int dev_index, unsigned int reg_index, u64 *bus_addr,
300 u64 *len);
301int ps3_repository_read_dev_reg(unsigned int bus_index,
302 unsigned int dev_index, unsigned int reg_index,
303 enum ps3_region_type *reg_type, u64 *bus_addr, u64 *len);
304
305/* repository bus enumerators */
306
307struct ps3_repository_device {
308 unsigned int bus_index;
309 unsigned int dev_index;
310 struct ps3_device_id did;
311};
312
313int ps3_repository_find_device(enum ps3_bus_type bus_type,
314 enum ps3_dev_type dev_type,
315 const struct ps3_repository_device *start_dev,
316 struct ps3_repository_device *dev);
317static inline int ps3_repository_find_first_device(
318 enum ps3_bus_type bus_type, enum ps3_dev_type dev_type,
319 struct ps3_repository_device *dev)
320{
321 return ps3_repository_find_device(bus_type, dev_type, NULL, dev);
322}
323int ps3_repository_find_interrupt(const struct ps3_repository_device *dev,
324 enum ps3_interrupt_type intr_type, unsigned int *interrupt_id);
325int ps3_repository_find_region(const struct ps3_repository_device *dev,
326 enum ps3_region_type reg_type, u64 *bus_addr, u64 *len);
327
328/* repository block device info */
329
330int ps3_repository_read_dev_port(unsigned int bus_index,
331 unsigned int dev_index, u64 *port);
332int ps3_repository_read_dev_blk_size(unsigned int bus_index,
333 unsigned int dev_index, u64 *blk_size);
334int ps3_repository_read_dev_num_blocks(unsigned int bus_index,
335 unsigned int dev_index, u64 *num_blocks);
336int ps3_repository_read_dev_num_regions(unsigned int bus_index,
337 unsigned int dev_index, unsigned int *num_regions);
338int ps3_repository_read_dev_region_id(unsigned int bus_index,
339 unsigned int dev_index, unsigned int region_index,
340 unsigned int *region_id);
341int ps3_repository_read_dev_region_size(unsigned int bus_index,
342 unsigned int dev_index, unsigned int region_index, u64 *region_size);
343int ps3_repository_read_dev_region_start(unsigned int bus_index,
344 unsigned int dev_index, unsigned int region_index, u64 *region_start);
345
346/* repository pu and memory info */
347
348int ps3_repository_read_num_pu(unsigned int *num_pu);
349int ps3_repository_read_ppe_id(unsigned int *pu_index, unsigned int *ppe_id);
350int ps3_repository_read_rm_base(unsigned int ppe_id, u64 *rm_base);
351int ps3_repository_read_rm_size(unsigned int ppe_id, u64 *rm_size);
352int ps3_repository_read_region_total(u64 *region_total);
353int ps3_repository_read_mm_info(u64 *rm_base, u64 *rm_size,
354 u64 *region_total);
355
356/* repository pme info */
357
358int ps3_repository_read_num_be(unsigned int *num_be);
359int ps3_repository_read_be_node_id(unsigned int be_index, u64 *node_id);
360int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq);
361int ps3_repository_read_be_tb_freq(unsigned int be_index, u64 *tb_freq);
362
363/* repository 'Other OS' area */
364
365int ps3_repository_read_boot_dat_addr(u64 *lpar_addr);
366int ps3_repository_read_boot_dat_size(unsigned int *size);
367int ps3_repository_read_boot_dat_info(u64 *lpar_addr, unsigned int *size);
368
369/* repository spu info */
370
371/**
372 * enum spu_resource_type - Type of spu resource.
373 * @spu_resource_type_shared: Logical spu is shared with other partions.
374 * @spu_resource_type_exclusive: Logical spu is not shared with other partions.
375 *
376 * Returned by ps3_repository_read_spu_resource_id().
377 */
378
379enum ps3_spu_resource_type {
380 PS3_SPU_RESOURCE_TYPE_SHARED = 0,
381 PS3_SPU_RESOURCE_TYPE_EXCLUSIVE = 0x8000000000000000UL,
382};
383
384int ps3_repository_read_num_spu_reserved(unsigned int *num_spu_reserved);
385int ps3_repository_read_num_spu_resource_id(unsigned int *num_resource_id);
386int ps3_repository_read_spu_resource_id(unsigned int res_index,
387 enum ps3_spu_resource_type* resource_type, unsigned int *resource_id);
388
389
390/* system bus routines */
391
392enum ps3_match_id {
393 PS3_MATCH_ID_EHCI = 1,
394 PS3_MATCH_ID_OHCI,
395 PS3_MATCH_ID_GELIC,
396 PS3_MATCH_ID_AV_SETTINGS,
397 PS3_MATCH_ID_SYSTEM_MANAGER,
398};
399
400/**
401 * struct ps3_system_bus_device - a device on the system bus
402 */
403
404struct ps3_system_bus_device {
405 enum ps3_match_id match_id;
406 struct ps3_device_id did;
407 unsigned int interrupt_id;
408/* struct iommu_table *iommu_table; -- waiting for Ben's cleanups */
409 struct ps3_dma_region *d_region;
410 struct ps3_mmio_region *m_region;
411 struct device core;
412};
413
414/**
415 * struct ps3_system_bus_driver - a driver for a device on the system bus
416 */
417
418struct ps3_system_bus_driver {
419 enum ps3_match_id match_id;
420 struct device_driver core;
421 int (*probe)(struct ps3_system_bus_device *);
422 int (*remove)(struct ps3_system_bus_device *);
423/* int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
424/* int (*resume)(struct ps3_system_bus_device *); */
425};
426
427int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
428int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
429void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
430static inline struct ps3_system_bus_driver *to_ps3_system_bus_driver(
431 struct device_driver *_drv)
432{
433 return container_of(_drv, struct ps3_system_bus_driver, core);
434}
435static inline struct ps3_system_bus_device *to_ps3_system_bus_device(
436 struct device *_dev)
437{
438 return container_of(_dev, struct ps3_system_bus_device, core);
439}
440
441/**
442 * ps3_system_bus_set_drvdata -
443 * @dev: device structure
444 * @data: Data to set
445 */
446
447static inline void ps3_system_bus_set_driver_data(
448 struct ps3_system_bus_device *dev, void *data)
449{
450 dev->core.driver_data = data;
451}
452static inline void *ps3_system_bus_get_driver_data(
453 struct ps3_system_bus_device *dev)
454{
455 return dev->core.driver_data;
456}
457
458/* These two need global scope for get_dma_ops(). */
459
460extern struct bus_type ps3_system_bus_type;
461
462#endif
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index d34f9e1f242c..5a0c136c0416 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -54,8 +54,6 @@ struct rtas_args {
54 rtas_arg_t *rets; /* Pointer to return values in args[]. */ 54 rtas_arg_t *rets; /* Pointer to return values in args[]. */
55}; 55};
56 56
57extern struct rtas_args rtas_stop_self_args;
58
59struct rtas_t { 57struct rtas_t {
60 unsigned long entry; /* physical address pointer */ 58 unsigned long entry; /* physical address pointer */
61 unsigned long base; /* physical address pointer */ 59 unsigned long base; /* physical address pointer */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index 38b1ea3b58fd..48ad807a0b8a 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -9,8 +9,14 @@
9 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space 9 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
10 */ 10 */
11#define SECTION_SIZE_BITS 24 11#define SECTION_SIZE_BITS 24
12
13#if defined(CONFIG_PS3_USE_LPAR_ADDR)
14#define MAX_PHYSADDR_BITS 47
15#define MAX_PHYSMEM_BITS 47
16#else
12#define MAX_PHYSADDR_BITS 44 17#define MAX_PHYSADDR_BITS 44
13#define MAX_PHYSMEM_BITS 44 18#define MAX_PHYSMEM_BITS 44
19#endif
14 20
15#ifdef CONFIG_MEMORY_HOTPLUG 21#ifdef CONFIG_MEMORY_HOTPLUG
16extern void create_section_mapping(unsigned long start, unsigned long end); 22extern void create_section_mapping(unsigned long start, unsigned long end);
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index e73ea00efd8b..fdad4267b447 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -111,14 +111,12 @@ struct spu {
111 u8 *local_store; 111 u8 *local_store;
112 unsigned long problem_phys; 112 unsigned long problem_phys;
113 struct spu_problem __iomem *problem; 113 struct spu_problem __iomem *problem;
114 struct spu_priv1 __iomem *priv1;
115 struct spu_priv2 __iomem *priv2; 114 struct spu_priv2 __iomem *priv2;
116 struct list_head list; 115 struct list_head list;
117 struct list_head sched_list; 116 struct list_head sched_list;
117 struct list_head full_list;
118 int number; 118 int number;
119 int nid;
120 unsigned int irqs[3]; 119 unsigned int irqs[3];
121 u32 isrc;
122 u32 node; 120 u32 node;
123 u64 flags; 121 u64 flags;
124 u64 dar; 122 u64 dar;
@@ -144,6 +142,7 @@ struct spu {
144 char irq_c1[8]; 142 char irq_c1[8];
145 char irq_c2[8]; 143 char irq_c2[8];
146 144
145 void* pdata; /* platform private data */
147 struct sys_device sysdev; 146 struct sys_device sysdev;
148}; 147};
149 148
@@ -170,6 +169,13 @@ extern struct spufs_calls {
170 struct module *owner; 169 struct module *owner;
171} spufs_calls; 170} spufs_calls;
172 171
172/* coredump calls implemented in spufs */
173struct spu_coredump_calls {
174 asmlinkage int (*arch_notes_size)(void);
175 asmlinkage void (*arch_write_notes)(struct file *file);
176 struct module *owner;
177};
178
173/* return status from spu_run, same as in libspe */ 179/* return status from spu_run, same as in libspe */
174#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */ 180#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
175#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/ 181#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
@@ -182,8 +188,10 @@ extern struct spufs_calls {
182 */ 188 */
183#define SPU_CREATE_EVENTS_ENABLED 0x0001 189#define SPU_CREATE_EVENTS_ENABLED 0x0001
184#define SPU_CREATE_GANG 0x0002 190#define SPU_CREATE_GANG 0x0002
191#define SPU_CREATE_NOSCHED 0x0004
192#define SPU_CREATE_ISOLATE 0x0008
185 193
186#define SPU_CREATE_FLAG_ALL 0x0003 /* mask of all valid flags */ 194#define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */
187 195
188 196
189#ifdef CONFIG_SPU_FS_MODULE 197#ifdef CONFIG_SPU_FS_MODULE
@@ -199,6 +207,15 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
199} 207}
200#endif /* MODULE */ 208#endif /* MODULE */
201 209
210int register_arch_coredump_calls(struct spu_coredump_calls *calls);
211void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
212
213int spu_add_sysdev_attr(struct sysdev_attribute *attr);
214void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
215
216int spu_add_sysdev_attr_group(struct attribute_group *attrs);
217void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
218
202 219
203/* 220/*
204 * Notifier blocks: 221 * Notifier blocks:
@@ -277,6 +294,7 @@ struct spu_problem {
277 u32 spu_runcntl_RW; /* 0x401c */ 294 u32 spu_runcntl_RW; /* 0x401c */
278#define SPU_RUNCNTL_STOP 0L 295#define SPU_RUNCNTL_STOP 0L
279#define SPU_RUNCNTL_RUNNABLE 1L 296#define SPU_RUNCNTL_RUNNABLE 1L
297#define SPU_RUNCNTL_ISOLATE 2L
280 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */ 298 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
281 u32 spu_status_R; /* 0x4024 */ 299 u32 spu_status_R; /* 0x4024 */
282#define SPU_STOP_STATUS_SHIFT 16 300#define SPU_STOP_STATUS_SHIFT 16
@@ -289,8 +307,8 @@ struct spu_problem {
289#define SPU_STATUS_INVALID_INSTR 0x20 307#define SPU_STATUS_INVALID_INSTR 0x20
290#define SPU_STATUS_INVALID_CH 0x40 308#define SPU_STATUS_INVALID_CH 0x40
291#define SPU_STATUS_ISOLATED_STATE 0x80 309#define SPU_STATUS_ISOLATED_STATE 0x80
292#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200 310#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
293#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400 311#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
294 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */ 312 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
295 u32 spu_spe_R; /* 0x402c */ 313 u32 spu_spe_R; /* 0x402c */
296 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */ 314 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index 964c2d38ccb7..bdbf906a767f 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -151,7 +151,6 @@ struct spu_priv1_collapsed {
151 u64 mfc_fir_chkstp_enable_RW; 151 u64 mfc_fir_chkstp_enable_RW;
152 u64 smf_sbi_signal_sel; 152 u64 smf_sbi_signal_sel;
153 u64 smf_ato_signal_sel; 153 u64 smf_ato_signal_sel;
154 u64 mfc_sdr_RW;
155 u64 tlb_index_hint_RO; 154 u64 tlb_index_hint_RO;
156 u64 tlb_index_W; 155 u64 tlb_index_W;
157 u64 tlb_vpn_RW; 156 u64 tlb_vpn_RW;
diff --git a/include/asm-powerpc/spu_info.h b/include/asm-powerpc/spu_info.h
new file mode 100644
index 000000000000..3545efbf9891
--- /dev/null
+++ b/include/asm-powerpc/spu_info.h
@@ -0,0 +1,54 @@
1/*
2 * SPU info structures
3 *
4 * (C) Copyright 2006 IBM Corp.
5 *
6 * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_INFO_H
24#define _SPU_INFO_H
25
26#ifdef __KERNEL__
27#include <asm/spu.h>
28#include <linux/types.h>
29#else
30struct mfc_cq_sr {
31 __u64 mfc_cq_data0_RW;
32 __u64 mfc_cq_data1_RW;
33 __u64 mfc_cq_data2_RW;
34 __u64 mfc_cq_data3_RW;
35};
36#endif /* __KERNEL__ */
37
38struct spu_dma_info {
39 __u64 dma_info_type;
40 __u64 dma_info_mask;
41 __u64 dma_info_status;
42 __u64 dma_info_stall_and_notify;
43 __u64 dma_info_atomic_command_status;
44 struct mfc_cq_sr dma_info_command_data[16];
45};
46
47struct spu_proxydma_info {
48 __u64 proxydma_info_type;
49 __u64 proxydma_info_mask;
50 __u64 proxydma_info_status;
51 struct mfc_cq_sr proxydma_info_command_data[8];
52};
53
54#endif
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 300c458b6d06..69dcb0c53884 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -21,12 +21,13 @@
21#define _SPU_PRIV1_H 21#define _SPU_PRIV1_H
22#if defined(__KERNEL__) 22#if defined(__KERNEL__)
23 23
24#include <linux/types.h>
25
24struct spu; 26struct spu;
25 27
26/* access to priv1 registers */ 28/* access to priv1 registers */
27 29
28struct spu_priv1_ops 30struct spu_priv1_ops {
29{
30 void (*int_mask_and) (struct spu *spu, int class, u64 mask); 31 void (*int_mask_and) (struct spu *spu, int class, u64 mask);
31 void (*int_mask_or) (struct spu *spu, int class, u64 mask); 32 void (*int_mask_or) (struct spu *spu, int class, u64 mask);
32 void (*int_mask_set) (struct spu *spu, int class, u64 mask); 33 void (*int_mask_set) (struct spu *spu, int class, u64 mask);
@@ -37,7 +38,7 @@ struct spu_priv1_ops
37 u64 (*mfc_dar_get) (struct spu *spu); 38 u64 (*mfc_dar_get) (struct spu *spu);
38 u64 (*mfc_dsisr_get) (struct spu *spu); 39 u64 (*mfc_dsisr_get) (struct spu *spu);
39 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr); 40 void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
40 void (*mfc_sdr_set) (struct spu *spu, u64 sdr); 41 void (*mfc_sdr_setup) (struct spu *spu);
41 void (*mfc_sr1_set) (struct spu *spu, u64 sr1); 42 void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
42 u64 (*mfc_sr1_get) (struct spu *spu); 43 u64 (*mfc_sr1_get) (struct spu *spu);
43 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id); 44 void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
@@ -112,9 +113,9 @@ spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
112} 113}
113 114
114static inline void 115static inline void
115spu_mfc_sdr_set (struct spu *spu, u64 sdr) 116spu_mfc_sdr_setup (struct spu *spu)
116{ 117{
117 spu_priv1_ops->mfc_sdr_set(spu, sdr); 118 spu_priv1_ops->mfc_sdr_setup(spu);
118} 119}
119 120
120static inline void 121static inline void
@@ -171,12 +172,41 @@ spu_resource_allocation_enable_get (struct spu *spu)
171 return spu_priv1_ops->resource_allocation_enable_get(spu); 172 return spu_priv1_ops->resource_allocation_enable_get(spu);
172} 173}
173 174
174/* The declarations folowing are put here for convenience 175/* spu management abstraction */
175 * and only intended to be used by the platform setup code 176
176 * for initializing spu_priv1_ops. 177struct spu_management_ops {
178 int (*enumerate_spus)(int (*fn)(void *data));
179 int (*create_spu)(struct spu *spu, void *data);
180 int (*destroy_spu)(struct spu *spu);
181};
182
183extern const struct spu_management_ops* spu_management_ops;
184
185static inline int
186spu_enumerate_spus (int (*fn)(void *data))
187{
188 return spu_management_ops->enumerate_spus(fn);
189}
190
191static inline int
192spu_create_spu (struct spu *spu, void *data)
193{
194 return spu_management_ops->create_spu(spu, data);
195}
196
197static inline int
198spu_destroy_spu (struct spu *spu)
199{
200 return spu_management_ops->destroy_spu(spu);
201}
202
203/*
204 * The declarations folowing are put here for convenience
205 * and only intended to be used by the platform setup code.
177 */ 206 */
178 207
179extern const struct spu_priv1_ops spu_priv1_mmio_ops; 208extern const struct spu_priv1_ops spu_priv1_mmio_ops;
209extern const struct spu_management_ops spu_management_of_ops;
180 210
181#endif /* __KERNEL__ */ 211#endif /* __KERNEL__ */
182#endif 212#endif
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
deleted file mode 100644
index 60a8c39b8c11..000000000000
--- a/include/asm-powerpc/todc.h
+++ /dev/null
@@ -1,487 +0,0 @@
1/*
2 * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
3 * Clock chips.
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
15 * Purpose is to make one generic file that handles all of these chips instead
16 * of every platform implementing the same code over & over again.
17 */
18
19#ifndef __PPC_KERNEL_TODC_H
20#define __PPC_KERNEL_TODC_H
21
22typedef struct {
23 uint rtc_type; /* your particular chip */
24
25 /*
26 * Following are the addresses of the AS0, AS1, and DATA registers
27 * of these chips. Note that these are board-specific.
28 */
29 unsigned int nvram_as0;
30 unsigned int nvram_as1;
31 unsigned int nvram_data;
32
33 /*
34 * Define bits to stop external set of regs from changing so
35 * the chip can be read/written reliably.
36 */
37 unsigned char enable_read;
38 unsigned char enable_write;
39
40 /*
41 * Following is the number of AS0 address bits. This is normally
42 * 8 but some bad hardware routes address lines incorrectly.
43 */
44 int as0_bits;
45
46 int nvram_size; /* Size of NVRAM on chip */
47 int sw_flags; /* Software control flags */
48
49 /* Following are the register offsets for the particular chip */
50 int year;
51 int month;
52 int day_of_month;
53 int day_of_week;
54 int hours;
55 int minutes;
56 int seconds;
57 int control_b;
58 int control_a;
59 int watchdog;
60 int interrupts;
61 int alarm_date;
62 int alarm_hour;
63 int alarm_minutes;
64 int alarm_seconds;
65 int century;
66 int flags;
67
68 /*
69 * Some RTC chips have their NVRAM buried behind a addr/data pair of
70 * regs on the first level/clock registers. The following fields
71 * are the addresses for those addr/data regs.
72 */
73 int nvram_addr_reg;
74 int nvram_data_reg;
75} todc_info_t;
76
77/*
78 * Define the types of TODC/RTC variants that are supported in
79 * arch/ppc/kernel/todc_time.c
80 * Make a new one of these for any chip somehow differs from what's already
81 * defined. That way, if you ever need to put in code to touch those
82 * bits/registers in todc_time.c, you can put it inside an
83 * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
84 * anyone else.
85 */
86#define TODC_TYPE_MK48T35 1
87#define TODC_TYPE_MK48T37 2
88#define TODC_TYPE_MK48T59 3
89#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
90#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
91#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
92#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
93#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
94#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
95#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
96#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
97#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
98#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
99#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
100
101/*
102 * Bit to clear/set to enable reads/writes to the chip
103 */
104#define TODC_MK48TXX_CNTL_A_R 0x40
105#define TODC_MK48TXX_CNTL_A_W 0x80
106#define TODC_MK48TXX_DAY_CB 0x80
107
108#define TODC_DS1501_CNTL_B_TE 0x80
109
110/*
111 * Define flag bits used by todc routines.
112 */
113#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
114
115/*
116 * Define the values for the various RTC's that should to into the todc_info
117 * table.
118 * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
119 * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
120 */
121#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
122#define TODC_TYPE_MK48T35_SW_FLAGS 0
123#define TODC_TYPE_MK48T35_YEAR 0x7fff
124#define TODC_TYPE_MK48T35_MONTH 0x7ffe
125#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
126#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
127#define TODC_TYPE_MK48T35_HOURS 0x7ffb
128#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
129#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
130#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
131#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
132#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
133#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
134#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
135#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
136#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
137#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
138#define TODC_TYPE_MK48T35_CENTURY 0x0000
139#define TODC_TYPE_MK48T35_FLAGS 0x0000
140#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
141#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
142
143#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
144#define TODC_TYPE_MK48T37_SW_FLAGS 0
145#define TODC_TYPE_MK48T37_YEAR 0x7fff
146#define TODC_TYPE_MK48T37_MONTH 0x7ffe
147#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
148#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
149#define TODC_TYPE_MK48T37_HOURS 0x7ffb
150#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
151#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
152#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
153#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
154#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
155#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
156#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
157#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
158#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
159#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
160#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
161#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
162#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
163#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
164
165#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
166#define TODC_TYPE_MK48T59_SW_FLAGS 0
167#define TODC_TYPE_MK48T59_YEAR 0x1fff
168#define TODC_TYPE_MK48T59_MONTH 0x1ffe
169#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
170#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
171#define TODC_TYPE_MK48T59_HOURS 0x1ffb
172#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
173#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
174#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
175#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
176#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
177#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
178#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
179#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
180#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
181#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
182#define TODC_TYPE_MK48T59_CENTURY 0x1fff
183#define TODC_TYPE_MK48T59_FLAGS 0x1fff
184#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
185#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
186
187#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
188#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
189#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
190#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
191#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
192#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
193#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
194#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
195#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
196#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
197#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
198#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
199#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
200#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
201#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
202#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
203#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
204#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
205#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
206#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
207#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
208
209#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
210#define TODC_TYPE_DS1553_SW_FLAGS 0
211#define TODC_TYPE_DS1553_YEAR 0x1fff
212#define TODC_TYPE_DS1553_MONTH 0x1ffe
213#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
214#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
215#define TODC_TYPE_DS1553_HOURS 0x1ffb
216#define TODC_TYPE_DS1553_MINUTES 0x1ffa
217#define TODC_TYPE_DS1553_SECONDS 0x1ff9
218#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
219#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
220#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
221#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
222#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
223#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
224#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
225#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
226#define TODC_TYPE_DS1553_CENTURY 0x1ff8
227#define TODC_TYPE_DS1553_FLAGS 0x1ff0
228#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
229#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
230
231#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
232#define TODC_TYPE_DS1557_SW_FLAGS 0
233#define TODC_TYPE_DS1557_YEAR 0x7ffff
234#define TODC_TYPE_DS1557_MONTH 0x7fffe
235#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
236#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
237#define TODC_TYPE_DS1557_HOURS 0x7fffb
238#define TODC_TYPE_DS1557_MINUTES 0x7fffa
239#define TODC_TYPE_DS1557_SECONDS 0x7fff9
240#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
241#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
242#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
243#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
244#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
245#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
246#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
247#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
248#define TODC_TYPE_DS1557_CENTURY 0x7fff8
249#define TODC_TYPE_DS1557_FLAGS 0x7fff0
250#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
251#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
252
253#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
254#define TODC_TYPE_DS1643_SW_FLAGS 0
255#define TODC_TYPE_DS1643_YEAR 0x1fff
256#define TODC_TYPE_DS1643_MONTH 0x1ffe
257#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
258#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
259#define TODC_TYPE_DS1643_HOURS 0x1ffb
260#define TODC_TYPE_DS1643_MINUTES 0x1ffa
261#define TODC_TYPE_DS1643_SECONDS 0x1ff9
262#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
263#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
264#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
265#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
266#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
267#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
268#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
269#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
270#define TODC_TYPE_DS1643_CENTURY 0x1ff8
271#define TODC_TYPE_DS1643_FLAGS 0x1fff
272#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
273#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
274
275#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
276#define TODC_TYPE_DS1693_SW_FLAGS 0
277#define TODC_TYPE_DS1693_YEAR 0x09
278#define TODC_TYPE_DS1693_MONTH 0x08
279#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
280#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
281#define TODC_TYPE_DS1693_HOURS 0x04
282#define TODC_TYPE_DS1693_MINUTES 0x02
283#define TODC_TYPE_DS1693_SECONDS 0x00
284#define TODC_TYPE_DS1693_CNTL_B 0x0b
285#define TODC_TYPE_DS1693_CNTL_A 0x0a
286#define TODC_TYPE_DS1693_WATCHDOG 0xff
287#define TODC_TYPE_DS1693_INTERRUPTS 0xff
288#define TODC_TYPE_DS1693_ALARM_DATE 0x49
289#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
290#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
291#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
292#define TODC_TYPE_DS1693_CENTURY 0x48
293#define TODC_TYPE_DS1693_FLAGS 0xff
294#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
295#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
296
297#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
298#define TODC_TYPE_DS1743_SW_FLAGS 0
299#define TODC_TYPE_DS1743_YEAR 0x1fff
300#define TODC_TYPE_DS1743_MONTH 0x1ffe
301#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
302#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
303#define TODC_TYPE_DS1743_HOURS 0x1ffb
304#define TODC_TYPE_DS1743_MINUTES 0x1ffa
305#define TODC_TYPE_DS1743_SECONDS 0x1ff9
306#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
307#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
308#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
309#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
310#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
311#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
312#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
313#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
314#define TODC_TYPE_DS1743_CENTURY 0x1ff8
315#define TODC_TYPE_DS1743_FLAGS 0x1fff
316#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
317#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
318
319#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
320#define TODC_TYPE_DS1746_SW_FLAGS 0
321#define TODC_TYPE_DS1746_YEAR 0x1ffff
322#define TODC_TYPE_DS1746_MONTH 0x1fffe
323#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
324#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
325#define TODC_TYPE_DS1746_HOURS 0x1fffb
326#define TODC_TYPE_DS1746_MINUTES 0x1fffa
327#define TODC_TYPE_DS1746_SECONDS 0x1fff9
328#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
329#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
330#define TODC_TYPE_DS1746_WATCHDOG 0x00000
331#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
332#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
333#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
334#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
335#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
336#define TODC_TYPE_DS1746_CENTURY 0x00000
337#define TODC_TYPE_DS1746_FLAGS 0x00000
338#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
339#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
340
341#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
342#define TODC_TYPE_DS1747_SW_FLAGS 0
343#define TODC_TYPE_DS1747_YEAR 0x7ffff
344#define TODC_TYPE_DS1747_MONTH 0x7fffe
345#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
346#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
347#define TODC_TYPE_DS1747_HOURS 0x7fffb
348#define TODC_TYPE_DS1747_MINUTES 0x7fffa
349#define TODC_TYPE_DS1747_SECONDS 0x7fff9
350#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
351#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
352#define TODC_TYPE_DS1747_WATCHDOG 0x00000
353#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
354#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
355#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
356#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
357#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
358#define TODC_TYPE_DS1747_CENTURY 0x00000
359#define TODC_TYPE_DS1747_FLAGS 0x00000
360#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
361#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
362
363#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
364#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
365#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
366#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
367#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
368#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
369#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
370#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
371#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
372#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
373#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
374#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
375#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
376#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
377#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
378#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
379#define TODC_TYPE_DS17285_WATCHDOG 0
380#define TODC_TYPE_DS17285_INTERRUPTS 0
381#define TODC_TYPE_DS17285_ALARM_DATE 0
382#define TODC_TYPE_DS17285_CENTURY 0
383#define TODC_TYPE_DS17285_FLAGS 0
384#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
385#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
386
387#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
388#define TODC_TYPE_MC146818_SW_FLAGS 0
389#define TODC_TYPE_MC146818_YEAR 0x09
390#define TODC_TYPE_MC146818_MONTH 0x08
391#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
392#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
393#define TODC_TYPE_MC146818_HOURS 0x04
394#define TODC_TYPE_MC146818_MINUTES 0x02
395#define TODC_TYPE_MC146818_SECONDS 0x00
396#define TODC_TYPE_MC146818_CNTL_B 0x0a
397#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
398#define TODC_TYPE_MC146818_WATCHDOG 0
399#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
400#define TODC_TYPE_MC146818_ALARM_DATE 0xff
401#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
402#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
403#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
404#define TODC_TYPE_MC146818_CENTURY 0xff
405#define TODC_TYPE_MC146818_FLAGS 0xff
406#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
407#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
408
409#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
410#define TODC_TYPE_PC97307_SW_FLAGS 0
411#define TODC_TYPE_PC97307_YEAR 0x09
412#define TODC_TYPE_PC97307_MONTH 0x08
413#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
414#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
415#define TODC_TYPE_PC97307_HOURS 0x04
416#define TODC_TYPE_PC97307_MINUTES 0x02
417#define TODC_TYPE_PC97307_SECONDS 0x00
418#define TODC_TYPE_PC97307_CNTL_B 0x0a
419#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
420#define TODC_TYPE_PC97307_WATCHDOG 0x0c
421#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
422#define TODC_TYPE_PC97307_ALARM_DATE 0xff
423#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
424#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
425#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
426#define TODC_TYPE_PC97307_CENTURY 0xff
427#define TODC_TYPE_PC97307_FLAGS 0xff
428#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
429#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
430
431/*
432 * Define macros to allocate and init the todc_info_t table that will
433 * be used by the todc_time.c routines.
434 */
435#define TODC_ALLOC() \
436 static todc_info_t todc_info_alloc; \
437 todc_info_t *todc_info = &todc_info_alloc;
438
439#define TODC_INIT(clock_type, as0, as1, data, bits) { \
440 todc_info->rtc_type = clock_type; \
441 \
442 todc_info->nvram_as0 = (unsigned int)(as0); \
443 todc_info->nvram_as1 = (unsigned int)(as1); \
444 todc_info->nvram_data = (unsigned int)(data); \
445 \
446 todc_info->as0_bits = (bits); \
447 \
448 todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
449 todc_info->sw_flags = clock_type ##_SW_FLAGS; \
450 \
451 todc_info->year = clock_type ##_YEAR; \
452 todc_info->month = clock_type ##_MONTH; \
453 todc_info->day_of_month = clock_type ##_DOM; \
454 todc_info->day_of_week = clock_type ##_DOW; \
455 todc_info->hours = clock_type ##_HOURS; \
456 todc_info->minutes = clock_type ##_MINUTES; \
457 todc_info->seconds = clock_type ##_SECONDS; \
458 todc_info->control_b = clock_type ##_CNTL_B; \
459 todc_info->control_a = clock_type ##_CNTL_A; \
460 todc_info->watchdog = clock_type ##_WATCHDOG; \
461 todc_info->interrupts = clock_type ##_INTERRUPTS; \
462 todc_info->alarm_date = clock_type ##_ALARM_DATE; \
463 todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
464 todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
465 todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
466 todc_info->century = clock_type ##_CENTURY; \
467 todc_info->flags = clock_type ##_FLAGS; \
468 \
469 todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
470 todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
471}
472
473extern todc_info_t *todc_info;
474
475unsigned char todc_direct_read_val(int addr);
476void todc_direct_write_val(int addr, unsigned char val);
477unsigned char todc_m48txx_read_val(int addr);
478void todc_m48txx_write_val(int addr, unsigned char val);
479unsigned char todc_mc146818_read_val(int addr);
480void todc_mc146818_write_val(int addr, unsigned char val);
481
482long todc_time_init(void);
483void todc_get_rtc_time(struct rtc_time *);
484int todc_set_rtc_time(struct rtc_time *);
485void todc_calibrate_decr(void);
486
487#endif /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
index 9fe7894ee035..50c014007de7 100644
--- a/include/asm-powerpc/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -32,7 +32,14 @@ static inline int node_to_first_cpu(int node)
32int of_node_to_nid(struct device_node *device); 32int of_node_to_nid(struct device_node *device);
33 33
34struct pci_bus; 34struct pci_bus;
35#ifdef CONFIG_PCI
35extern int pcibus_to_node(struct pci_bus *bus); 36extern int pcibus_to_node(struct pci_bus *bus);
37#else
38static inline int pcibus_to_node(struct pci_bus *bus)
39{
40 return -1;
41}
42#endif
36 43
37#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \ 44#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
38 CPU_MASK_ALL : \ 45 CPU_MASK_ALL : \
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
index 2c702d35a7cf..4e95d153be84 100644
--- a/include/asm-powerpc/tsi108.h
+++ b/include/asm-powerpc/tsi108.h
@@ -98,12 +98,12 @@ typedef struct {
98extern u32 get_vir_csrbase(void); 98extern u32 get_vir_csrbase(void);
99extern u32 tsi108_csr_vir_base; 99extern u32 tsi108_csr_vir_base;
100 100
101extern inline u32 tsi108_read_reg(u32 reg_offset) 101static inline u32 tsi108_read_reg(u32 reg_offset)
102{ 102{
103 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset)); 103 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
104} 104}
105 105
106extern inline void tsi108_write_reg(u32 reg_offset, u32 val) 106static inline void tsi108_write_reg(u32 reg_offset, u32 val)
107{ 107{
108 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); 108 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
109} 109}
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
index d6fb56b80453..3b363757a2bb 100644
--- a/include/asm-powerpc/types.h
+++ b/include/asm-powerpc/types.h
@@ -97,16 +97,6 @@ typedef struct {
97 unsigned long env; 97 unsigned long env;
98} func_descr_t; 98} func_descr_t;
99 99
100#ifdef CONFIG_LBD
101typedef u64 sector_t;
102#define HAVE_SECTOR_T
103#endif
104
105#ifdef CONFIG_LSF
106typedef u64 blkcnt_t;
107#define HAVE_BLKCNT_T
108#endif
109
110#endif /* __ASSEMBLY__ */ 100#endif /* __ASSEMBLY__ */
111 101
112#endif /* __KERNEL__ */ 102#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h
index d83fc29c2bbf..adbf16b8cfbb 100644
--- a/include/asm-powerpc/uaccess.h
+++ b/include/asm-powerpc/uaccess.h
@@ -304,7 +304,7 @@ extern unsigned long __copy_tofrom_user(void __user *to,
304 304
305#ifndef __powerpc64__ 305#ifndef __powerpc64__
306 306
307extern inline unsigned long copy_from_user(void *to, 307static inline unsigned long copy_from_user(void *to,
308 const void __user *from, unsigned long n) 308 const void __user *from, unsigned long n)
309{ 309{
310 unsigned long over; 310 unsigned long over;
@@ -319,7 +319,7 @@ extern inline unsigned long copy_from_user(void *to,
319 return n; 319 return n;
320} 320}
321 321
322extern inline unsigned long copy_to_user(void __user *to, 322static inline unsigned long copy_to_user(void __user *to,
323 const void *from, unsigned long n) 323 const void *from, unsigned long n)
324{ 324{
325 unsigned long over; 325 unsigned long over;
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
index 0e4ea37f6466..04b6c17cc59b 100644
--- a/include/asm-powerpc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -446,7 +446,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
446#include <linux/types.h> 446#include <linux/types.h>
447#include <linux/compiler.h> 447#include <linux/compiler.h>
448#include <linux/linkage.h> 448#include <linux/linkage.h>
449#include <asm/syscalls.h>
450 449
451#define __ARCH_WANT_IPC_PARSE_VERSION 450#define __ARCH_WANT_IPC_PARSE_VERSION
452#define __ARCH_WANT_OLD_READDIR 451#define __ARCH_WANT_OLD_READDIR
@@ -481,16 +480,9 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
481 480
482/* 481/*
483 * "Conditional" syscalls 482 * "Conditional" syscalls
484 *
485 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
486 * but it doesn't work on all toolchains, so we just do it by hand
487 */ 483 */
488#ifdef CONFIG_PPC32 484#define cond_syscall(x) \
489#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") 485 asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
490#else
491#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
492#endif
493
494 486
495#endif /* __ASSEMBLY__ */ 487#endif /* __ASSEMBLY__ */
496#endif /* __KERNEL__ */ 488#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h
index 4b51d42e1419..0117b544ecbc 100644
--- a/include/asm-powerpc/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -45,7 +45,6 @@ struct iommu_table;
45 * The vio_dev structure is used to describe virtual I/O devices. 45 * The vio_dev structure is used to describe virtual I/O devices.
46 */ 46 */
47struct vio_dev { 47struct vio_dev {
48 struct iommu_table *iommu_table; /* vio_map_* uses this */
49 const char *name; 48 const char *name;
50 const char *type; 49 const char *type;
51 uint32_t unit_address; 50 uint32_t unit_address;
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index f1d337ed68d5..88320a05f0a8 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -14,8 +14,10 @@
14 14
15#ifdef CONFIG_XMON 15#ifdef CONFIG_XMON
16extern void xmon_setup(void); 16extern void xmon_setup(void);
17extern void xmon_register_spus(struct list_head *list);
17#else 18#else
18static inline void xmon_setup(void) { }; 19static inline void xmon_setup(void) { };
20static inline void xmon_register_spus(struct list_head *list) { };
19#endif 21#endif
20 22
21#endif /* __KERNEL __ */ 23#endif /* __KERNEL __ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 06:34:14 -0500