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authorStefan Roese <sr@denx.de>2008-03-26 07:39:50 -0400
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-03-26 08:27:54 -0400
commit2a7069190e7a7f19bd37e8c08e2bf02c8d6330f7 (patch)
tree3a13b234c45b32aa31a1c4ac2c84ed2f3b00a473 /include/asm-powerpc
parent145692a734cffa9c3c6f4523d015516406ce21eb (diff)
[POWERPC] 4xx: Add PPC4xx L2-cache support (440GX)
This patch adds support for the 256k L2 cache found on some IBM/AMCC 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c) which currently "only" adds the L2 cache init code. Other common 4xx stuff can be added later here. The L2 cache handling code is a copy of Eugene's code in arch/ppc with small modifications. Tested on AMCC Taishan 440GX. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/dcr-regs.h78
1 files changed, 78 insertions, 0 deletions
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
index 9f1fb98fcdc6..29b0ecef980a 100644
--- a/include/asm-powerpc/dcr-regs.h
+++ b/include/asm-powerpc/dcr-regs.h
@@ -68,4 +68,82 @@
68#define SDR0_UART3 0x0123 68#define SDR0_UART3 0x0123
69#define SDR0_CUST0 0x4000 69#define SDR0_CUST0 0x4000
70 70
71/*
72 * All those DCR register addresses are offsets from the base address
73 * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
74 * excluded here and configured in the device tree.
75 */
76#define DCRN_SRAM0_SB0CR 0x00
77#define DCRN_SRAM0_SB1CR 0x01
78#define DCRN_SRAM0_SB2CR 0x02
79#define DCRN_SRAM0_SB3CR 0x03
80#define SRAM_SBCR_BU_MASK 0x00000180
81#define SRAM_SBCR_BS_64KB 0x00000800
82#define SRAM_SBCR_BU_RO 0x00000080
83#define SRAM_SBCR_BU_RW 0x00000180
84#define DCRN_SRAM0_BEAR 0x04
85#define DCRN_SRAM0_BESR0 0x05
86#define DCRN_SRAM0_BESR1 0x06
87#define DCRN_SRAM0_PMEG 0x07
88#define DCRN_SRAM0_CID 0x08
89#define DCRN_SRAM0_REVID 0x09
90#define DCRN_SRAM0_DPC 0x0a
91#define SRAM_DPC_ENABLE 0x80000000
92
93/*
94 * All those DCR register addresses are offsets from the base address
95 * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
96 * excluded here and configured in the device tree.
97 */
98#define DCRN_L2C0_CFG 0x00
99#define L2C_CFG_L2M 0x80000000
100#define L2C_CFG_ICU 0x40000000
101#define L2C_CFG_DCU 0x20000000
102#define L2C_CFG_DCW_MASK 0x1e000000
103#define L2C_CFG_TPC 0x01000000
104#define L2C_CFG_CPC 0x00800000
105#define L2C_CFG_FRAN 0x00200000
106#define L2C_CFG_SS_MASK 0x00180000
107#define L2C_CFG_SS_256 0x00000000
108#define L2C_CFG_CPIM 0x00040000
109#define L2C_CFG_TPIM 0x00020000
110#define L2C_CFG_LIM 0x00010000
111#define L2C_CFG_PMUX_MASK 0x00007000
112#define L2C_CFG_PMUX_SNP 0x00000000
113#define L2C_CFG_PMUX_IF 0x00001000
114#define L2C_CFG_PMUX_DF 0x00002000
115#define L2C_CFG_PMUX_DS 0x00003000
116#define L2C_CFG_PMIM 0x00000800
117#define L2C_CFG_TPEI 0x00000400
118#define L2C_CFG_CPEI 0x00000200
119#define L2C_CFG_NAM 0x00000100
120#define L2C_CFG_SMCM 0x00000080
121#define L2C_CFG_NBRM 0x00000040
122#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
123#define DCRN_L2C0_CMD 0x01
124#define L2C_CMD_CLR 0x80000000
125#define L2C_CMD_DIAG 0x40000000
126#define L2C_CMD_INV 0x20000000
127#define L2C_CMD_CCP 0x10000000
128#define L2C_CMD_CTE 0x08000000
129#define L2C_CMD_STRC 0x04000000
130#define L2C_CMD_STPC 0x02000000
131#define L2C_CMD_RPMC 0x01000000
132#define L2C_CMD_HCC 0x00800000
133#define DCRN_L2C0_ADDR 0x02
134#define DCRN_L2C0_DATA 0x03
135#define DCRN_L2C0_SR 0x04
136#define L2C_SR_CC 0x80000000
137#define L2C_SR_CPE 0x40000000
138#define L2C_SR_TPE 0x20000000
139#define L2C_SR_LRU 0x10000000
140#define L2C_SR_PCS 0x08000000
141#define DCRN_L2C0_REVID 0x05
142#define DCRN_L2C0_SNP0 0x06
143#define DCRN_L2C0_SNP1 0x07
144#define L2C_SNP_BA_MASK 0xffff0000
145#define L2C_SNP_SSR_MASK 0x0000f000
146#define L2C_SNP_SSR_32G 0x0000f000
147#define L2C_SNP_ESR 0x00000800
148
71#endif /* __DCR_REGS_H__ */ 149#endif /* __DCR_REGS_H__ */