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authorJochen Friedrich <jochen@scram.de>2008-01-24 10:20:05 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:31:06 -0500
commit44f25fb4d0754c6c2ab5bf97990a671e19152139 (patch)
tree88116926057db0050f24d3f3a9dcb526c2342c73 /include/asm-powerpc
parentb5677d848cbb94220ac2cfd36d93bcdbe49c3280 (diff)
[POWERPC] CPM: Move definition of buffer descriptor to cpm.h
Buffer descriptors are used by both CPM1 and CPM2. Move the definitions from the cpm dependent include file to common cpm.h Signed-off-by: Jochen Friedrich <jochen@scram.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/cpm.h73
-rw-r--r--include/asm-powerpc/cpm1.h65
-rw-r--r--include/asm-powerpc/cpm2.h64
3 files changed, 73 insertions, 129 deletions
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index fae83b137337..77e39dad9728 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -4,6 +4,79 @@
4#include <linux/compiler.h> 4#include <linux/compiler.h>
5#include <linux/types.h> 5#include <linux/types.h>
6 6
7/* Buffer descriptors used by many of the CPM protocols. */
8typedef struct cpm_buf_desc {
9 ushort cbd_sc; /* Status and Control */
10 ushort cbd_datlen; /* Data length in buffer */
11 uint cbd_bufaddr; /* Buffer address in host memory */
12} cbd_t;
13
14/* Buffer descriptor control/status used by serial
15 */
16
17#define BD_SC_EMPTY (0x8000) /* Receive is empty */
18#define BD_SC_READY (0x8000) /* Transmit is ready */
19#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
20#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
21#define BD_SC_LAST (0x0800) /* Last buffer in frame */
22#define BD_SC_TC (0x0400) /* Transmit CRC */
23#define BD_SC_CM (0x0200) /* Continous mode */
24#define BD_SC_ID (0x0100) /* Rec'd too many idles */
25#define BD_SC_P (0x0100) /* xmt preamble */
26#define BD_SC_BR (0x0020) /* Break received */
27#define BD_SC_FR (0x0010) /* Framing error */
28#define BD_SC_PR (0x0008) /* Parity error */
29#define BD_SC_NAK (0x0004) /* NAK - did not respond */
30#define BD_SC_OV (0x0002) /* Overrun */
31#define BD_SC_UN (0x0002) /* Underrun */
32#define BD_SC_CD (0x0001) /* */
33#define BD_SC_CL (0x0001) /* Collision */
34
35/* Buffer descriptor control/status used by Ethernet receive.
36 * Common to SCC and FCC.
37 */
38#define BD_ENET_RX_EMPTY (0x8000)
39#define BD_ENET_RX_WRAP (0x2000)
40#define BD_ENET_RX_INTR (0x1000)
41#define BD_ENET_RX_LAST (0x0800)
42#define BD_ENET_RX_FIRST (0x0400)
43#define BD_ENET_RX_MISS (0x0100)
44#define BD_ENET_RX_BC (0x0080) /* FCC Only */
45#define BD_ENET_RX_MC (0x0040) /* FCC Only */
46#define BD_ENET_RX_LG (0x0020)
47#define BD_ENET_RX_NO (0x0010)
48#define BD_ENET_RX_SH (0x0008)
49#define BD_ENET_RX_CR (0x0004)
50#define BD_ENET_RX_OV (0x0002)
51#define BD_ENET_RX_CL (0x0001)
52#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
53
54/* Buffer descriptor control/status used by Ethernet transmit.
55 * Common to SCC and FCC.
56 */
57#define BD_ENET_TX_READY (0x8000)
58#define BD_ENET_TX_PAD (0x4000)
59#define BD_ENET_TX_WRAP (0x2000)
60#define BD_ENET_TX_INTR (0x1000)
61#define BD_ENET_TX_LAST (0x0800)
62#define BD_ENET_TX_TC (0x0400)
63#define BD_ENET_TX_DEF (0x0200)
64#define BD_ENET_TX_HB (0x0100)
65#define BD_ENET_TX_LC (0x0080)
66#define BD_ENET_TX_RL (0x0040)
67#define BD_ENET_TX_RCMASK (0x003c)
68#define BD_ENET_TX_UN (0x0002)
69#define BD_ENET_TX_CSL (0x0001)
70#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
71
72/* Buffer descriptor control/status used by Transparent mode SCC.
73 */
74#define BD_SCC_TX_LAST (0x0800)
75
76/* Buffer descriptor control/status used by I2C.
77 */
78#define BD_I2C_START (0x0400)
79
7int cpm_muram_init(void); 80int cpm_muram_init(void);
8unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); 81unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
9int cpm_muram_free(unsigned long offset); 82int cpm_muram_free(unsigned long offset);
diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h
index 901a00b48959..b2ebd6ac6dae 100644
--- a/include/asm-powerpc/cpm1.h
+++ b/include/asm-powerpc/cpm1.h
@@ -91,32 +91,6 @@ extern void cpm_load_patch(cpm8xx_t *cp);
91 91
92extern void cpm_reset(void); 92extern void cpm_reset(void);
93 93
94/* Buffer descriptors used by many of the CPM protocols.
95*/
96typedef struct cpm_buf_desc {
97 ushort cbd_sc; /* Status and Control */
98 ushort cbd_datlen; /* Data length in buffer */
99 uint cbd_bufaddr; /* Buffer address in host memory */
100} cbd_t;
101
102#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
103#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
104#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
105#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
106#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
107#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
108#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
109#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
110#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
111#define BD_SC_BR ((ushort)0x0020) /* Break received */
112#define BD_SC_FR ((ushort)0x0010) /* Framing error */
113#define BD_SC_PR ((ushort)0x0008) /* Parity error */
114#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
115#define BD_SC_OV ((ushort)0x0002) /* Overrun */
116#define BD_SC_UN ((ushort)0x0002) /* Underrun */
117#define BD_SC_CD ((ushort)0x0001) /* ?? */
118#define BD_SC_CL ((ushort)0x0001) /* Collision */
119
120/* Parameter RAM offsets. 94/* Parameter RAM offsets.
121*/ 95*/
122#define PROFF_SCC1 ((uint)0x0000) 96#define PROFF_SCC1 ((uint)0x0000)
@@ -446,41 +420,6 @@ typedef struct scc_enet {
446#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 420#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
447#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 421#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
448 422
449/* Buffer descriptor control/status used by Ethernet receive.
450*/
451#define BD_ENET_RX_EMPTY ((ushort)0x8000)
452#define BD_ENET_RX_WRAP ((ushort)0x2000)
453#define BD_ENET_RX_INTR ((ushort)0x1000)
454#define BD_ENET_RX_LAST ((ushort)0x0800)
455#define BD_ENET_RX_FIRST ((ushort)0x0400)
456#define BD_ENET_RX_MISS ((ushort)0x0100)
457#define BD_ENET_RX_LG ((ushort)0x0020)
458#define BD_ENET_RX_NO ((ushort)0x0010)
459#define BD_ENET_RX_SH ((ushort)0x0008)
460#define BD_ENET_RX_CR ((ushort)0x0004)
461#define BD_ENET_RX_OV ((ushort)0x0002)
462#define BD_ENET_RX_CL ((ushort)0x0001)
463#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
464#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
465#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
466
467/* Buffer descriptor control/status used by Ethernet transmit.
468*/
469#define BD_ENET_TX_READY ((ushort)0x8000)
470#define BD_ENET_TX_PAD ((ushort)0x4000)
471#define BD_ENET_TX_WRAP ((ushort)0x2000)
472#define BD_ENET_TX_INTR ((ushort)0x1000)
473#define BD_ENET_TX_LAST ((ushort)0x0800)
474#define BD_ENET_TX_TC ((ushort)0x0400)
475#define BD_ENET_TX_DEF ((ushort)0x0200)
476#define BD_ENET_TX_HB ((ushort)0x0100)
477#define BD_ENET_TX_LC ((ushort)0x0080)
478#define BD_ENET_TX_RL ((ushort)0x0040)
479#define BD_ENET_TX_RCMASK ((ushort)0x003c)
480#define BD_ENET_TX_UN ((ushort)0x0002)
481#define BD_ENET_TX_CSL ((ushort)0x0001)
482#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
483
484/* SCC as UART 423/* SCC as UART
485*/ 424*/
486typedef struct scc_uart { 425typedef struct scc_uart {
@@ -549,8 +488,6 @@ typedef struct scc_trans {
549 uint st_cmask; /* Constant mask for CRC */ 488 uint st_cmask; /* Constant mask for CRC */
550} scc_trans_t; 489} scc_trans_t;
551 490
552#define BD_SCC_TX_LAST ((ushort)0x0800)
553
554/* IIC parameter RAM. 491/* IIC parameter RAM.
555*/ 492*/
556typedef struct iic { 493typedef struct iic {
@@ -574,8 +511,6 @@ typedef struct iic {
574 char res2[2]; /* Reserved */ 511 char res2[2]; /* Reserved */
575} iic_t; 512} iic_t;
576 513
577#define BD_IIC_START ((ushort)0x0400)
578
579/* SPI parameter RAM. 514/* SPI parameter RAM.
580*/ 515*/
581typedef struct spi { 516typedef struct spi {
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index f1112c15ef96..b93a53eb55c1 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -132,29 +132,6 @@ extern void cpm_setbrg(uint brg, uint rate);
132extern void cpm2_fastbrg(uint brg, uint rate, int div16); 132extern void cpm2_fastbrg(uint brg, uint rate, int div16);
133extern void cpm2_reset(void); 133extern void cpm2_reset(void);
134 134
135
136/* Buffer descriptors used by many of the CPM protocols.
137*/
138typedef struct cpm_buf_desc {
139 ushort cbd_sc; /* Status and Control */
140 ushort cbd_datlen; /* Data length in buffer */
141 uint cbd_bufaddr; /* Buffer address in host memory */
142} cbd_t;
143
144#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
145#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
146#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
147#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
148#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
149#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
150#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
151#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
152#define BD_SC_BR ((ushort)0x0020) /* Break received */
153#define BD_SC_FR ((ushort)0x0010) /* Framing error */
154#define BD_SC_PR ((ushort)0x0008) /* Parity error */
155#define BD_SC_OV ((ushort)0x0002) /* Overrun */
156#define BD_SC_CD ((ushort)0x0001) /* ?? */
157
158/* Function code bits, usually generic to devices. 135/* Function code bits, usually generic to devices.
159*/ 136*/
160#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 137#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
@@ -456,43 +433,6 @@ typedef struct scc_enet {
456#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 433#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
457#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 434#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
458 435
459/* Buffer descriptor control/status used by Ethernet receive.
460 * Common to SCC and FCC.
461 */
462#define BD_ENET_RX_EMPTY ((ushort)0x8000)
463#define BD_ENET_RX_WRAP ((ushort)0x2000)
464#define BD_ENET_RX_INTR ((ushort)0x1000)
465#define BD_ENET_RX_LAST ((ushort)0x0800)
466#define BD_ENET_RX_FIRST ((ushort)0x0400)
467#define BD_ENET_RX_MISS ((ushort)0x0100)
468#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
469#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
470#define BD_ENET_RX_LG ((ushort)0x0020)
471#define BD_ENET_RX_NO ((ushort)0x0010)
472#define BD_ENET_RX_SH ((ushort)0x0008)
473#define BD_ENET_RX_CR ((ushort)0x0004)
474#define BD_ENET_RX_OV ((ushort)0x0002)
475#define BD_ENET_RX_CL ((ushort)0x0001)
476#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
477
478/* Buffer descriptor control/status used by Ethernet transmit.
479 * Common to SCC and FCC.
480 */
481#define BD_ENET_TX_READY ((ushort)0x8000)
482#define BD_ENET_TX_PAD ((ushort)0x4000)
483#define BD_ENET_TX_WRAP ((ushort)0x2000)
484#define BD_ENET_TX_INTR ((ushort)0x1000)
485#define BD_ENET_TX_LAST ((ushort)0x0800)
486#define BD_ENET_TX_TC ((ushort)0x0400)
487#define BD_ENET_TX_DEF ((ushort)0x0200)
488#define BD_ENET_TX_HB ((ushort)0x0100)
489#define BD_ENET_TX_LC ((ushort)0x0080)
490#define BD_ENET_TX_RL ((ushort)0x0040)
491#define BD_ENET_TX_RCMASK ((ushort)0x003c)
492#define BD_ENET_TX_UN ((ushort)0x0002)
493#define BD_ENET_TX_CSL ((ushort)0x0001)
494#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
495
496/* SCC as UART 436/* SCC as UART
497*/ 437*/
498typedef struct scc_uart { 438typedef struct scc_uart {
@@ -562,8 +502,6 @@ typedef struct scc_trans {
562 uint st_cmask; /* Constant mask for CRC */ 502 uint st_cmask; /* Constant mask for CRC */
563} scc_trans_t; 503} scc_trans_t;
564 504
565#define BD_SCC_TX_LAST ((ushort)0x0800)
566
567/* How about some FCCs..... 505/* How about some FCCs.....
568*/ 506*/
569#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 507#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
@@ -769,8 +707,6 @@ typedef struct spi {
769 707
770#define SPI_EB ((u_char)0x10) /* big endian byte order */ 708#define SPI_EB ((u_char)0x10) /* big endian byte order */
771 709
772#define BD_IIC_START ((ushort)0x0400)
773
774/* IDMA parameter RAM 710/* IDMA parameter RAM
775*/ 711*/
776typedef struct idma { 712typedef struct idma {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 00:52:23 -0500