Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (202 commits)
  [POWERPC] Fix compile breakage for 64-bit UP configs
  [POWERPC] Define copy_siginfo_from_user32
  [POWERPC] Add compat handler for PTRACE_GETSIGINFO
  [POWERPC] i2c: Fix build breakage introduced by OF helpers
  [POWERPC] Optimize fls64() on 64-bit processors
  [POWERPC] irqtrace support for 64-bit powerpc
  [POWERPC] Stacktrace support for lockdep
  [POWERPC] Move stackframe definitions to common header
  [POWERPC] Fix device-tree locking vs. interrupts
  [POWERPC] Make pci_bus_to_host()'s struct pci_bus * argument const
  [POWERPC] Remove unused __max_memory variable
  [POWERPC] Simplify xics direct/lpar irq_host setup
  [POWERPC] Use pseries_setup_i8259_cascade() in pseries_mpic_init_IRQ()
  [POWERPC] Turn xics_setup_8259_cascade() into a generic pseries_setup_i8259_cascade()
  [POWERPC] Move xics_setup_8259_cascade() into platforms/pseries/setup.c
  [POWERPC] Use asm-generic/bitops/find.h in bitops.h
  [POWERPC] 83xx: mpc8315 - fix USB UTMI Host setup
  [POWERPC] 85xx: Fix the size of qe muram for MPC8568E
  [POWERPC] 86xx: mpc86xx_hpcn - Temporarily accept old dts node identifier.
  [POWERPC] 86xx: mark functions static, other minor cleanups
  ...

44 files changed, 786 insertions, 280 deletions

diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild
index 5f640e542475..7381916dfcbb 100644
--- a/include/asm-powerpc/Kbuild
+++ b/include/asm-powerpc/Kbuild
@@ -1,5 +1,6 @@
 include include/asm-generic/Kbuild.asm
 
+header-y += a.out.h
 header-y += auxvec.h
 header-y += ioctls.h
 header-y += mman.h
@@ -23,7 +24,6 @@ header-y += sigcontext.h
 header-y += statfs.h
 header-y += ps3fb.h
 
-unifdef-y += a.out.h
 unifdef-y += asm-compat.h
 unifdef-y += bootx.h
 unifdef-y += byteorder.h
diff --git a/include/asm-powerpc/abs_addr.h b/include/asm-powerpc/abs_addr.h
index 4aa220718b19..98324c5a8286 100644
--- a/include/asm-powerpc/abs_addr.h
+++ b/include/asm-powerpc/abs_addr.h
@@ -12,10 +12,11 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#include <linux/lmb.h>
+
 #include <asm/types.h>
 #include <asm/page.h>
 #include <asm/prom.h>
-#include <asm/lmb.h>
 #include <asm/firmware.h>
 
 struct mschunks_map {
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index 220d9a781ab9..a99a74929475 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -312,24 +312,26 @@ static __inline__ int fls(unsigned int x)
         asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
         return 32 - lz;
 }
+
+/*
+ * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
+ * instruction; for 32-bit we use the generic version, which does two
+ * 32-bit fls calls.
+ */
+#ifdef __powerpc64__
+static __inline__ int fls64(__u64 x)
+{
+        int lz;
+
+        asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
+        return 64 - lz;
+}
+#else
 #include <asm-generic/bitops/fls64.h>
+#endif /* __powerpc64__ */
 
 #include <asm-generic/bitops/hweight.h>
-
-#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
-unsigned long find_next_zero_bit(const unsigned long *addr,
-                                 unsigned long size, unsigned long offset);
-/**
- * find_first_bit - find the first set bit in a memory region
- * @addr: The address to start the search at
- * @size: The maximum size to search
- *
- * Returns the bit-number of the first set bit, not the number of the byte
- * containing a bit.
- */
-#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
-unsigned long find_next_bit(const unsigned long *addr,
-                            unsigned long size, unsigned long offset);
+#include <asm-generic/bitops/find.h>
 
 /* Little-endian versions */
 
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index 77e39dad9728..ede38ffe466a 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -4,6 +4,20 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 
+/* Opcodes common to CPM1 and CPM2
+*/
+#define CPM_CR_INIT_TRX         ((ushort)0x0000)
+#define CPM_CR_INIT_RX          ((ushort)0x0001)
+#define CPM_CR_INIT_TX          ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
+#define CPM_CR_STOP_TX          ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
+#define CPM_CR_RESTART_TX       ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
+#define CPM_CR_SET_GADDR        ((ushort)0x0008)
+#define CPM_CR_SET_TIMER        ((ushort)0x0008)
+#define CPM_CR_STOP_IDMA        ((ushort)0x000b)
+
 /* Buffer descriptors used by many of the CPM protocols. */
 typedef struct cpm_buf_desc {
         ushort  cbd_sc;         /* Status and Control */
diff --git a/include/asm-powerpc/cpm1.h b/include/asm-powerpc/cpm1.h
index b2ebd6ac6dae..3df439678006 100644
--- a/include/asm-powerpc/cpm1.h
+++ b/include/asm-powerpc/cpm1.h
@@ -28,19 +28,6 @@
 #define CPM_CR_CHAN     ((ushort)0x00f0)
 #define CPM_CR_FLG      ((ushort)0x0001)
 
-/* Some commands (there are more...later)
-*/
-#define CPM_CR_INIT_TRX         ((ushort)0x0000)
-#define CPM_CR_INIT_RX          ((ushort)0x0001)
-#define CPM_CR_INIT_TX          ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
-#define CPM_CR_STOP_TX          ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
-#define CPM_CR_RESTART_TX       ((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD      ((ushort)0x0007)
-#define CPM_CR_SET_GADDR        ((ushort)0x0008)
-#define CPM_CR_SET_TIMER        CPM_CR_SET_GADDR
-
 /* Channel numbers.
 */
 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index b93a53eb55c1..4c85ed9cd43f 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -71,18 +71,9 @@
 
 #define CPM_CR_FCC_PAGE(x)      (x + 0x04)
 
-/* Some opcodes (there are more...later)
+/* CPM2-specific opcodes (see cpm.h for common opcodes)
 */
-#define CPM_CR_INIT_TRX         ((ushort)0x0000)
-#define CPM_CR_INIT_RX          ((ushort)0x0001)
-#define CPM_CR_INIT_TX          ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE        ((ushort)0x0003)
-#define CPM_CR_STOP_TX          ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX      ((ushort)0x0005)
-#define CPM_CR_RESTART_TX       ((ushort)0x0006)
-#define CPM_CR_SET_GADDR        ((ushort)0x0008)
 #define CPM_CR_START_IDMA       ((ushort)0x0009)
-#define CPM_CR_STOP_IDMA        ((ushort)0x000b)
 
 #define mk_cr_cmd(PG, SBC, MCN, OP) \
         ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h
index 8485c28b5f47..fb11b0c459b8 100644
--- a/include/asm-powerpc/cputhreads.h
+++ b/include/asm-powerpc/cputhreads.h
@@ -35,7 +35,7 @@ static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads)
 
         res = CPU_MASK_NONE;
         for (i = 0; i < NR_CPUS; i += threads_per_core) {
-                cpus_shift_right(tmp, threads_core_mask, i);
+                cpus_shift_left(tmp, threads_core_mask, i);
                 if (cpus_intersects(threads, tmp))
                         cpu_set(i, res);
         }
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index be6c879e8760..f8398ce80372 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -82,6 +82,19 @@ static inline void __mtdcri(int base_addr, int base_data, int reg,
         spin_unlock_irqrestore(&dcr_ind_lock, flags);
 }
 
+static inline void __dcri_clrset(int base_addr, int base_data, int reg,
+                                 unsigned clr, unsigned set)
+{
+        unsigned long flags;
+        unsigned int val;
+
+        spin_lock_irqsave(&dcr_ind_lock, flags);
+        __mtdcr(base_addr, reg);
+        val = (__mfdcr(base_data) & ~clr) | set;
+        __mtdcr(base_data, val);
+        spin_unlock_irqrestore(&dcr_ind_lock, flags);
+}
+
 #define mfdcri(base, reg)       __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
                                          DCRN_ ## base ## _CONFIG_DATA, \
                                          reg)
@@ -90,6 +103,10 @@ static inline void __mtdcri(int base_addr, int base_data, int reg,
                                          DCRN_ ## base ## _CONFIG_DATA, \
                                          reg, data)
 
+#define dcri_clrset(base, reg, clr, set)        __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,    \
+                                                              DCRN_ ## base ## _CONFIG_DATA,    \
+                                                              reg, clr, set)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
index 9f1fb98fcdc6..29b0ecef980a 100644
--- a/include/asm-powerpc/dcr-regs.h
+++ b/include/asm-powerpc/dcr-regs.h
@@ -68,4 +68,82 @@
 #define SDR0_UART3              0x0123
 #define SDR0_CUST0              0x4000
 
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_SRAM0_SB0CR        0x00
+#define DCRN_SRAM0_SB1CR        0x01
+#define DCRN_SRAM0_SB2CR        0x02
+#define DCRN_SRAM0_SB3CR        0x03
+#define  SRAM_SBCR_BU_MASK      0x00000180
+#define  SRAM_SBCR_BS_64KB      0x00000800
+#define  SRAM_SBCR_BU_RO        0x00000080
+#define  SRAM_SBCR_BU_RW        0x00000180
+#define DCRN_SRAM0_BEAR         0x04
+#define DCRN_SRAM0_BESR0        0x05
+#define DCRN_SRAM0_BESR1        0x06
+#define DCRN_SRAM0_PMEG         0x07
+#define DCRN_SRAM0_CID          0x08
+#define DCRN_SRAM0_REVID        0x09
+#define DCRN_SRAM0_DPC          0x0a
+#define  SRAM_DPC_ENABLE        0x80000000
+
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_L2C0_CFG           0x00
+#define  L2C_CFG_L2M            0x80000000
+#define  L2C_CFG_ICU            0x40000000
+#define  L2C_CFG_DCU            0x20000000
+#define  L2C_CFG_DCW_MASK       0x1e000000
+#define  L2C_CFG_TPC            0x01000000
+#define  L2C_CFG_CPC            0x00800000
+#define  L2C_CFG_FRAN           0x00200000
+#define  L2C_CFG_SS_MASK        0x00180000
+#define  L2C_CFG_SS_256         0x00000000
+#define  L2C_CFG_CPIM           0x00040000
+#define  L2C_CFG_TPIM           0x00020000
+#define  L2C_CFG_LIM            0x00010000
+#define  L2C_CFG_PMUX_MASK      0x00007000
+#define  L2C_CFG_PMUX_SNP       0x00000000
+#define  L2C_CFG_PMUX_IF        0x00001000
+#define  L2C_CFG_PMUX_DF        0x00002000
+#define  L2C_CFG_PMUX_DS        0x00003000
+#define  L2C_CFG_PMIM           0x00000800
+#define  L2C_CFG_TPEI           0x00000400
+#define  L2C_CFG_CPEI           0x00000200
+#define  L2C_CFG_NAM            0x00000100
+#define  L2C_CFG_SMCM           0x00000080
+#define  L2C_CFG_NBRM           0x00000040
+#define  L2C_CFG_RDBW           0x00000008      /* only 460EX/GT */
+#define DCRN_L2C0_CMD           0x01
+#define  L2C_CMD_CLR            0x80000000
+#define  L2C_CMD_DIAG           0x40000000
+#define  L2C_CMD_INV            0x20000000
+#define  L2C_CMD_CCP            0x10000000
+#define  L2C_CMD_CTE            0x08000000
+#define  L2C_CMD_STRC           0x04000000
+#define  L2C_CMD_STPC           0x02000000
+#define  L2C_CMD_RPMC           0x01000000
+#define  L2C_CMD_HCC            0x00800000
+#define DCRN_L2C0_ADDR          0x02
+#define DCRN_L2C0_DATA          0x03
+#define DCRN_L2C0_SR            0x04
+#define  L2C_SR_CC              0x80000000
+#define  L2C_SR_CPE             0x40000000
+#define  L2C_SR_TPE             0x20000000
+#define  L2C_SR_LRU             0x10000000
+#define  L2C_SR_PCS             0x08000000
+#define DCRN_L2C0_REVID         0x05
+#define DCRN_L2C0_SNP0          0x06
+#define DCRN_L2C0_SNP1          0x07
+#define  L2C_SNP_BA_MASK        0xffff0000
+#define  L2C_SNP_SSR_MASK       0x0000f000
+#define  L2C_SNP_SSR_32G        0x0000f000
+#define  L2C_SNP_ESR            0x00000800
+
 #endif /* __DCR_REGS_H__ */
diff --git a/include/asm-powerpc/exception.h b/include/asm-powerpc/exception.h
index 39abdb02fdef..329148b5acc6 100644
--- a/include/asm-powerpc/exception.h
+++ b/include/asm-powerpc/exception.h
@@ -228,18 +228,18 @@ label##_pSeries:							\
 BEGIN_FW_FTR_SECTION;                           \
         stb     r11,PACAHARDIRQEN(r13);         \
 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
+        TRACE_DISABLE_INTS;                     \
 BEGIN_FW_FTR_SECTION;                           \
         mfmsr   r10;                            \
         ori     r10,r10,MSR_EE;                 \
         mtmsrd  r10,1;                          \
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-
 #else
 #define DISABLE_INTS                            \
         li      r11,0;                          \
         stb     r11,PACASOFTIRQEN(r13);         \
-        stb     r11,PACAHARDIRQEN(r13)
-
+        stb     r11,PACAHARDIRQEN(r13);         \
+        TRACE_DISABLE_INTS
 #endif /* CONFIG_PPC_ISERIES */
 
 #define ENABLE_INTS                             \
diff --git a/include/asm-powerpc/fsl_lbc.h b/include/asm-powerpc/fsl_lbc.h
new file mode 100644
index 000000000000..303f5484c050
--- /dev/null
+++ b/include/asm-powerpc/fsl_lbc.h
@@ -0,0 +1,311 @@
+/* Freescale Local Bus Controller
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor
+ *
+ * Authors: Nick Spence <nick.spence@freescale.com>,
+ *          Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_FSL_LBC_H
+#define __ASM_FSL_LBC_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+
+struct fsl_lbc_bank {
+        __be32 br;             /**< Base Register  */
+#define BR_BA           0xFFFF8000
+#define BR_BA_SHIFT             15
+#define BR_PS           0x00001800
+#define BR_PS_SHIFT             11
+#define BR_PS_8         0x00000800  /* Port Size 8 bit */
+#define BR_PS_16        0x00001000  /* Port Size 16 bit */
+#define BR_PS_32        0x00001800  /* Port Size 32 bit */
+#define BR_DECC         0x00000600
+#define BR_DECC_SHIFT            9
+#define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
+#define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
+#define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
+#define BR_WP           0x00000100
+#define BR_WP_SHIFT              8
+#define BR_MSEL         0x000000E0
+#define BR_MSEL_SHIFT            5
+#define BR_MS_GPCM      0x00000000  /* GPCM */
+#define BR_MS_FCM       0x00000020  /* FCM */
+#define BR_MS_SDRAM     0x00000060  /* SDRAM */
+#define BR_MS_UPMA      0x00000080  /* UPMA */
+#define BR_MS_UPMB      0x000000A0  /* UPMB */
+#define BR_MS_UPMC      0x000000C0  /* UPMC */
+#define BR_V            0x00000001
+#define BR_V_SHIFT               0
+#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+        __be32 or;             /**< Base Register  */
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_FCM_AM               0xFFFF8000
+#define OR_FCM_AM_SHIFT                 15
+#define OR_FCM_BCTLD            0x00001000
+#define OR_FCM_BCTLD_SHIFT              12
+#define OR_FCM_PGS              0x00000400
+#define OR_FCM_PGS_SHIFT                10
+#define OR_FCM_CSCT             0x00000200
+#define OR_FCM_CSCT_SHIFT                9
+#define OR_FCM_CST              0x00000100
+#define OR_FCM_CST_SHIFT                 8
+#define OR_FCM_CHT              0x00000080
+#define OR_FCM_CHT_SHIFT                 7
+#define OR_FCM_SCY              0x00000070
+#define OR_FCM_SCY_SHIFT                 4
+#define OR_FCM_SCY_1            0x00000010
+#define OR_FCM_SCY_2            0x00000020
+#define OR_FCM_SCY_3            0x00000030
+#define OR_FCM_SCY_4            0x00000040
+#define OR_FCM_SCY_5            0x00000050
+#define OR_FCM_SCY_6            0x00000060
+#define OR_FCM_SCY_7            0x00000070
+#define OR_FCM_RST              0x00000008
+#define OR_FCM_RST_SHIFT                 3
+#define OR_FCM_TRLX             0x00000004
+#define OR_FCM_TRLX_SHIFT                2
+#define OR_FCM_EHTR             0x00000002
+#define OR_FCM_EHTR_SHIFT                1
+};
+
+struct fsl_lbc_regs {
+        struct fsl_lbc_bank bank[8];
+        u8 res0[0x28];
+        __be32 mar;             /**< UPM Address Register */
+        u8 res1[0x4];
+        __be32 mamr;            /**< UPMA Mode Register */
+#define MxMR_OP_NO      (0 << 28) /**< normal operation */
+#define MxMR_OP_WA      (1 << 28) /**< write array */
+#define MxMR_OP_RA      (2 << 28) /**< read array */
+#define MxMR_OP_RP      (3 << 28) /**< run pattern */
+#define MxMR_MAD        0x3f      /**< machine address */
+        __be32 mbmr;            /**< UPMB Mode Register */
+        __be32 mcmr;            /**< UPMC Mode Register */
+        u8 res2[0x8];
+        __be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
+        __be32 mdr;             /**< UPM Data Register */
+        u8 res3[0x4];
+        __be32 lsor;            /**< Special Operation Initiation Register */
+        __be32 lsdmr;           /**< SDRAM Mode Register */
+        u8 res4[0x8];
+        __be32 lurt;            /**< UPM Refresh Timer */
+        __be32 lsrt;            /**< SDRAM Refresh Timer */
+        u8 res5[0x8];
+        __be32 ltesr;           /**< Transfer Error Status Register */
+#define LTESR_BM   0x80000000
+#define LTESR_FCT  0x40000000
+#define LTESR_PAR  0x20000000
+#define LTESR_WP   0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS   0x00080000
+#define LTESR_CC   0x00000001
+#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+        __be32 ltedr;           /**< Transfer Error Disable Register */
+        __be32 lteir;           /**< Transfer Error Interrupt Register */
+        __be32 lteatr;          /**< Transfer Error Attributes Register */
+        __be32 ltear;           /**< Transfer Error Address Register */
+        u8 res6[0xC];
+        __be32 lbcr;            /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_AHD   0x00200000
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+#define LBCR_INIT  0x00040000
+        __be32 lcrr;            /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+        u8 res7[0x8];
+        __be32 fmr;             /**< Flash Mode Register */
+#define FMR_CWTO     0x0000F000
+#define FMR_CWTO_SHIFT       12
+#define FMR_BOOT     0x00000800
+#define FMR_ECCM     0x00000100
+#define FMR_AL       0x00000030
+#define FMR_AL_SHIFT          4
+#define FMR_OP       0x00000003
+#define FMR_OP_SHIFT          0
+        __be32 fir;             /**< Flash Instruction Register */
+#define FIR_OP0      0xF0000000
+#define FIR_OP0_SHIFT        28
+#define FIR_OP1      0x0F000000
+#define FIR_OP1_SHIFT        24
+#define FIR_OP2      0x00F00000
+#define FIR_OP2_SHIFT        20
+#define FIR_OP3      0x000F0000
+#define FIR_OP3_SHIFT        16
+#define FIR_OP4      0x0000F000
+#define FIR_OP4_SHIFT        12
+#define FIR_OP5      0x00000F00
+#define FIR_OP5_SHIFT         8
+#define FIR_OP6      0x000000F0
+#define FIR_OP6_SHIFT         4
+#define FIR_OP7      0x0000000F
+#define FIR_OP7_SHIFT         0
+#define FIR_OP_NOP   0x0        /* No operation and end of sequence */
+#define FIR_OP_CA    0x1        /* Issue current column address */
+#define FIR_OP_PA    0x2        /* Issue current block+page address */
+#define FIR_OP_UA    0x3        /* Issue user defined address */
+#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
+#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
+        __be32 fcr;             /**< Flash Command Register */
+#define FCR_CMD0     0xFF000000
+#define FCR_CMD0_SHIFT       24
+#define FCR_CMD1     0x00FF0000
+#define FCR_CMD1_SHIFT       16
+#define FCR_CMD2     0x0000FF00
+#define FCR_CMD2_SHIFT        8
+#define FCR_CMD3     0x000000FF
+#define FCR_CMD3_SHIFT        0
+        __be32 fbar;            /**< Flash Block Address Register */
+#define FBAR_BLK     0x00FFFFFF
+        __be32 fpar;            /**< Flash Page Address Register */
+#define FPAR_SP_PI   0x00007C00
+#define FPAR_SP_PI_SHIFT     10
+#define FPAR_SP_MS   0x00000200
+#define FPAR_SP_CI   0x000001FF
+#define FPAR_SP_CI_SHIFT      0
+#define FPAR_LP_PI   0x0003F000
+#define FPAR_LP_PI_SHIFT     12
+#define FPAR_LP_MS   0x00000800
+#define FPAR_LP_CI   0x000007FF
+#define FPAR_LP_CI_SHIFT      0
+        __be32 fbcr;            /**< Flash Byte Count Register */
+#define FBCR_BC      0x00000FFF
+        u8 res11[0x8];
+        u8 res8[0xF00];
+};
+
+extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+extern spinlock_t fsl_lbc_lock;
+
+/*
+ * FSL UPM routines
+ */
+struct fsl_upm {
+        __be32 __iomem *mxmr;
+        int width;
+};
+
+extern int fsl_lbc_find(phys_addr_t addr_base);
+extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
+
+/**
+ * fsl_upm_start_pattern - start UPM patterns execution
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @pat_offset: UPM pattern offset for the command to be executed
+ *
+ * This routine programmes UPM so the next memory access that hits an UPM
+ * will trigger pattern execution, starting at pat_offset.
+ */
+static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
+{
+        clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
+}
+
+/**
+ * fsl_upm_end_pattern - end UPM patterns execution
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ *
+ * This routine reverts UPM to normal operation mode.
+ */
+static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
+{
+        clrbits32(upm->mxmr, MxMR_OP_RP);
+
+        while (in_be32(upm->mxmr) & MxMR_OP_RP)
+                cpu_relax();
+}
+
+/**
+ * fsl_upm_run_pattern - actually run an UPM pattern
+ * @upm:        pointer to the fsl_upm structure obtained via fsl_upm_find
+ * @io_base:    remapped pointer to where memory access should happen
+ * @mar:        MAR register content during pattern execution
+ *
+ * This function triggers dummy write to the memory specified by the io_base,
+ * thus UPM pattern actually executed. Note that mar usage depends on the
+ * pre-programmed AMX bits in the UPM RAM.
+ */
+static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
+                                      void __iomem *io_base, u32 mar)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&fsl_lbc_lock, flags);
+
+        out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
+
+        switch (upm->width) {
+        case 8:
+                out_8(io_base, 0x0);
+                break;
+        case 16:
+                out_be16(io_base, 0x0);
+                break;
+        case 32:
+                out_be32(io_base, 0x0);
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        spin_unlock_irqrestore(&fsl_lbc_lock, flags);
+
+        return ret;
+}
+
+#endif /* __ASM_FSL_LBC_H */
diff --git a/include/asm-powerpc/gpio.h b/include/asm-powerpc/gpio.h
new file mode 100644
index 000000000000..77ad3a890f30
--- /dev/null
+++ b/include/asm-powerpc/gpio.h
@@ -0,0 +1,56 @@
+/*
+ * Generic GPIO API implementation for PowerPC.
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_POWERPC_GPIO_H
+#define __ASM_POWERPC_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_HAVE_GPIO_LIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+/*
+ * Not implemented, yet.
+ */
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return -ENOSYS;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return -EINVAL;
+}
+
+#endif /* CONFIG_HAVE_GPIO_LIB */
+
+#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index a7b60bf639e0..ad8c9f7fd0e3 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -27,7 +27,7 @@ static inline unsigned long local_get_flags(void)
         return flags;
 }
 
-static inline unsigned long local_irq_disable(void)
+static inline unsigned long raw_local_irq_disable(void)
 {
         unsigned long flags, zero;
 
@@ -39,14 +39,15 @@ static inline unsigned long local_irq_disable(void)
         return flags;
 }
 
-extern void local_irq_restore(unsigned long);
+extern void raw_local_irq_restore(unsigned long);
 extern void iseries_handle_interrupts(void);
 
-#define local_irq_enable()      local_irq_restore(1)
-#define local_save_flags(flags) ((flags) = local_get_flags())
-#define local_irq_save(flags)   ((flags) = local_irq_disable())
+#define raw_local_irq_enable()          raw_local_irq_restore(1)
+#define raw_local_save_flags(flags)     ((flags) = local_get_flags())
+#define raw_local_irq_save(flags)       ((flags) = raw_local_irq_disable())
 
-#define irqs_disabled()         (local_get_flags() == 0)
+#define raw_irqs_disabled()             (local_get_flags() == 0)
+#define raw_irqs_disabled_flags(flags)  ((flags) == 0)
 
 #define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
 #define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 82a452615097..7b6f411db3e6 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -20,6 +20,7 @@
 #ifdef __KERNEL__
 
 #include <linux/kernel.h>
+#include <asm/io.h>
 
 #define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
 
@@ -468,7 +469,7 @@ struct qe_immap {
         u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
 } __attribute__ ((packed));
 
-extern struct qe_immap *qe_immr;
+extern struct qe_immap __iomem *qe_immr;
 extern phys_addr_t get_qe_base(void);
 
 static inline unsigned long immrbar_virt_to_phys(void *address)
diff --git a/include/asm-powerpc/irqflags.h b/include/asm-powerpc/irqflags.h
index 7970cbaeaa54..cc6fdba33660 100644
--- a/include/asm-powerpc/irqflags.h
+++ b/include/asm-powerpc/irqflags.h
@@ -2,30 +2,43 @@
  * include/asm-powerpc/irqflags.h
  *
  * IRQ flags handling
- *
- * This file gets included from lowlevel asm headers too, to provide
- * wrapped versions of the local_irq_*() APIs, based on the
- * raw_local_irq_*() macros from the lowlevel headers.
  */
 #ifndef _ASM_IRQFLAGS_H
 #define _ASM_IRQFLAGS_H
 
+#ifndef __ASSEMBLY__
 /*
  * Get definitions for raw_local_save_flags(x), etc.
  */
 #include <asm-powerpc/hw_irq.h>
 
+#else
+#ifdef CONFIG_TRACE_IRQFLAGS
 /*
- * Do the CPU's IRQ-state tracing from assembly code. We call a
- * C function, so save all the C-clobbered registers:
+ * Most of the CPU's IRQ-state tracing is done from assembly code; we
+ * have to call a C function so call a wrapper that saves all the
+ * C-clobbered registers.
  */
-#ifdef CONFIG_TRACE_IRQFLAGS
-
-#error No support on PowerPC yet for CONFIG_TRACE_IRQFLAGS
-
+#define TRACE_ENABLE_INTS       bl .trace_hardirqs_on
+#define TRACE_DISABLE_INTS      bl .trace_hardirqs_off
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)  \
+        cmpdi   en, 0;                          \
+        bne     95f;                            \
+        stb     en,PACASOFTIRQEN(r13);          \
+        bl      .trace_hardirqs_off;            \
+        b       skip;                           \
+95:     bl      .trace_hardirqs_on;             \
+        li      en,1;
+#define TRACE_AND_RESTORE_IRQ(en)               \
+        TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f);  \
+96:     stb     en,PACASOFTIRQEN(r13)
 #else
-# define TRACE_IRQS_ON
-# define TRACE_IRQS_OFF
+#define TRACE_ENABLE_INTS
+#define TRACE_DISABLE_INTS
+#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
+#define TRACE_AND_RESTORE_IRQ(en)               \
+        stb     en,PACASOFTIRQEN(r13)
+#endif
 #endif
 
 #endif
diff --git a/include/asm-powerpc/iseries/alpaca.h b/include/asm-powerpc/iseries/alpaca.h
new file mode 100644
index 000000000000..c0cce6727a69
--- /dev/null
+++ b/include/asm-powerpc/iseries/alpaca.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2008  Stephen Rothwell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
+#define _ASM_POWERPC_ISERIES_ALPACA_H
+
+/*
+ * This is the part of the paca that the iSeries hypervisor
+ * needs to be statically initialised. Immediately after boot
+ * we switch to the normal Linux paca.
+ */
+struct alpaca {
+        struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
+        const void *reg_save_ptr;       /* Pointer to LpRegSave for PLIC */
+};
+
+#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/include/asm-powerpc/iseries/it_lp_reg_save.h b/include/asm-powerpc/iseries/it_lp_reg_save.h
deleted file mode 100644
index 5403b756f654..000000000000
--- a/include/asm-powerpc/iseries/it_lp_reg_save.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
-#define _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
-
-/*
- * This control block contains the data that is shared between PLIC
- * and the OS
- */
-
-struct ItLpRegSave {
-        u32     xDesc;          // Eye catcher  "LpRS" ebcdic   000-003
-        u16     xSize;          // Size of this class           004-005
-        u8      xInUse;         // Area is live                 006-007
-        u8      xRsvd1[9];      // Reserved                     007-00F
-
-        u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
-        u32     xCTRL;          // Control Register             170-173
-        u32     xDEC;           // Decrementer                  174-177
-        u32     xFPSCR;         // FP Status and Control Reg    178-17B
-        u32     xPVR;           // Processor Version Number     17C-17F
-
-        u64     xMMCR0;         // Monitor Mode Control Reg 0   180-187
-        u32     xPMC1;          // Perf Monitor Counter 1       188-18B
-        u32     xPMC2;          // Perf Monitor Counter 2       18C-18F
-        u32     xPMC3;          // Perf Monitor Counter 3       190-193
-        u32     xPMC4;          // Perf Monitor Counter 4       194-197
-        u32     xPIR;           // Processor ID Reg             198-19B
-
-        u32     xMMCR1;         // Monitor Mode Control Reg 1   19C-19F
-        u32     xMMCRA;         // Monitor Mode Control Reg A   1A0-1A3
-        u32     xPMC5;          // Perf Monitor Counter 5       1A4-1A7
-        u32     xPMC6;          // Perf Monitor Counter 6       1A8-1AB
-        u32     xPMC7;          // Perf Monitor Counter 7       1AC-1AF
-        u32     xPMC8;          // Perf Monitor Counter 8       1B0-1B3
-        u32     xTSC;           // Thread Switch Control        1B4-1B7
-        u32     xTST;           // Thread Switch Timeout        1B8-1BB
-        u32     xRsvd;          // Reserved                     1BC-1BF
-
-        u64     xACCR;          // Address Compare Control Reg  1C0-1C7
-        u64     xIMR;           // Instruction Match Register   1C8-1CF
-        u64     xSDR1;          // Storage Description Reg 1    1D0-1D7
-        u64     xSPRG0;         // Special Purpose Reg General0 1D8-1DF
-        u64     xSPRG1;         // Special Purpose Reg General1 1E0-1E7
-        u64     xSPRG2;         // Special Purpose Reg General2 1E8-1EF
-        u64     xSPRG3;         // Special Purpose Reg General3 1F0-1F7
-        u64     xTB;            // Time Base Register           1F8-1FF
-
-        u64     xFPR[32];       // Floating Point Registers     200-2FF
-
-        u64     xMSR;           // Machine State Register       300-307
-        u64     xNIA;           // Next Instruction Address     308-30F
-
-        u64     xDABR;          // Data Address Breakpoint Reg  310-317
-        u64     xIABR;          // Inst Address Breakpoint Reg  318-31F
-
-        u64     xHID0;          // HW Implementation Dependent0 320-327
-
-        u64     xHID4;          // HW Implementation Dependent4 328-32F
-        u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
-        u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
-        u64     xSDAR;          // Sample Data Address Register 340-347
-        u64     xSIAR;          // Sample Inst Address Register 348-34F
-
-        u8      xRsvd3[176];    // Reserved                     350-3FF
-};
-
-extern struct ItLpRegSave iseries_reg_save[];
-
-#endif /* _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H */
diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h
index 5d1dc48a0bb8..6f5fdf0a19ae 100644
--- a/include/asm-powerpc/lmb.h
+++ b/include/asm-powerpc/lmb.h
@@ -1,81 +1,15 @@
 #ifndef _ASM_POWERPC_LMB_H
 #define _ASM_POWERPC_LMB_H
-#ifdef __KERNEL__
 
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 2001 Peter Bergner, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
+#include <asm/udbg.h>
 
-#include <linux/init.h>
-#include <asm/prom.h>
+#define LMB_DBG(fmt...) udbg_printf(fmt)
 
-#define MAX_LMB_REGIONS 128
+#ifdef CONFIG_PPC32
+extern phys_addr_t lowmem_end_addr;
+#define LMB_REAL_LIMIT  lowmem_end_addr
+#else
+#define LMB_REAL_LIMIT  0
+#endif
 
-struct lmb_property {
-        unsigned long base;
-        unsigned long size;
-};
-
-struct lmb_region {
-        unsigned long cnt;
-        unsigned long size;
-        struct lmb_property region[MAX_LMB_REGIONS+1];
-};
-
-struct lmb {
-        unsigned long debug;
-        unsigned long rmo_size;
-        struct lmb_region memory;
-        struct lmb_region reserved;
-};
-
-extern struct lmb lmb;
-
-extern void __init lmb_init(void);
-extern void __init lmb_analyze(void);
-extern long __init lmb_add(unsigned long base, unsigned long size);
-extern long __init lmb_reserve(unsigned long base, unsigned long size);
-extern unsigned long __init lmb_alloc(unsigned long size, unsigned long align);
-extern unsigned long __init lmb_alloc_base(unsigned long size,
-                unsigned long align, unsigned long max_addr);
-extern unsigned long __init __lmb_alloc_base(unsigned long size,
-                unsigned long align, unsigned long max_addr);
-extern unsigned long __init lmb_phys_mem_size(void);
-extern unsigned long __init lmb_end_of_DRAM(void);
-extern void __init lmb_enforce_memory_limit(unsigned long memory_limit);
-extern int __init lmb_is_reserved(unsigned long addr);
-
-extern void lmb_dump_all(void);
-
-static inline unsigned long
-lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
-{
-        return type->region[region_nr].size;
-}
-static inline unsigned long
-lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
-{
-        return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
-}
-static inline unsigned long
-lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
-{
-        return type->region[region_nr].base >> PAGE_SHIFT;
-}
-static inline unsigned long
-lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
-{
-        return lmb_start_pfn(type, region_nr) +
-               lmb_size_pages(type, region_nr);
-}
-
-#endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_LMB_H */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 0872ec228c1e..54ed64df95b8 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -68,6 +68,8 @@ struct machdep_calls {
                                        unsigned long vflags,
                                        int psize, int ssize);
         long            (*hpte_remove)(unsigned long hpte_group);
+        void            (*hpte_removebolted)(unsigned long ea,
+                                             int psize, int ssize);
         void            (*flush_hash_range)(unsigned long number, int local);
 
         /* special for kexec, to be called in real mode, linar mapping is
@@ -196,9 +198,6 @@ struct machdep_calls {
            May be NULL. */
         void            (*init)(void);
 
-        void            (*setup_io_mappings)(void);
-
-        void            (*early_serial_map)(void);
         void            (*kgdb_map_scc)(void);
 
         /*
diff --git a/include/asm-powerpc/macio.h b/include/asm-powerpc/macio.h
index 3a6cb1a513b7..079c06eae446 100644
--- a/include/asm-powerpc/macio.h
+++ b/include/asm-powerpc/macio.h
@@ -2,7 +2,7 @@
 #define __MACIO_ASIC_H__
 #ifdef __KERNEL__
 
-#include <asm/of_device.h>
+#include <linux/of_device.h>
 
 extern struct bus_type macio_bus_type;
 
diff --git a/include/asm-powerpc/mmu-40x.h b/include/asm-powerpc/mmu-40x.h
index 7d37f77043ac..3d108676584c 100644
--- a/include/asm-powerpc/mmu-40x.h
+++ b/include/asm-powerpc/mmu-40x.h
@@ -53,8 +53,6 @@
 
 #ifndef __ASSEMBLY__
 
-typedef unsigned long phys_addr_t;
-
 typedef struct {
         unsigned long id;
         unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-44x.h b/include/asm-powerpc/mmu-44x.h
index 62772ae839ca..c8b02d97f753 100644
--- a/include/asm-powerpc/mmu-44x.h
+++ b/include/asm-powerpc/mmu-44x.h
@@ -53,8 +53,6 @@
 
 #ifndef __ASSEMBLY__
 
-typedef unsigned long long phys_addr_t;
-
 typedef struct {
         unsigned long id;
         unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-8xx.h b/include/asm-powerpc/mmu-8xx.h
index 952bd8899f2f..9db877eb88db 100644
--- a/include/asm-powerpc/mmu-8xx.h
+++ b/include/asm-powerpc/mmu-8xx.h
@@ -136,8 +136,6 @@
 #define SPRN_M_TW       799
 
 #ifndef __ASSEMBLY__
-typedef unsigned long phys_addr_t;
-
 typedef struct {
         unsigned long id;
         unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-fsl-booke.h b/include/asm-powerpc/mmu-fsl-booke.h
index 37580004cd7a..925d93cf64d8 100644
--- a/include/asm-powerpc/mmu-fsl-booke.h
+++ b/include/asm-powerpc/mmu-fsl-booke.h
@@ -73,12 +73,6 @@
 
 #ifndef __ASSEMBLY__
 
-#ifndef CONFIG_PHYS_64BIT
-typedef unsigned long phys_addr_t;
-#else
-typedef unsigned long long phys_addr_t;
-#endif
-
 typedef struct {
         unsigned long id;
         unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
index 4bd735be3833..6e21ca618ec3 100644
--- a/include/asm-powerpc/mmu-hash32.h
+++ b/include/asm-powerpc/mmu-hash32.h
@@ -84,8 +84,6 @@ typedef struct {
         unsigned long vdso_base;
 } mm_context_t;
 
-typedef unsigned long phys_addr_t;
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 2864fa3989ea..0dff76776044 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -469,9 +469,6 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
                                  VSID_MODULUS_256M)
 #define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
 
-/* Physical address used by some IO functions */
-typedef unsigned long phys_addr_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 748b35ab37b5..eb61b9c1edfd 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -42,10 +42,7 @@ struct task_struct;
  * Defines the layout of the paca.
  *
  * This structure is not directly accessed by firmware or the service
- * processor except for the first two pointers that point to the
- * lppaca area and the ItLpRegSave area for this CPU.  The lppaca
- * object is currently contained within the PACA but it doesn't need
- * to be.
+ * processor.
  */
 struct paca_struct {
         /*
@@ -55,14 +52,7 @@ struct paca_struct {
          * avoid cacheline bouncing.
          */
 
-        /*
-         * MAGIC: These first two pointers can't be moved - they're
-         * accessed by the firmware
-         */
         struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
-#ifdef CONFIG_PPC_ISERIES
-        void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
-#endif /* CONFIG_PPC_ISERIES */
 
         /*
          * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index df47bbb6ea13..6c850609b847 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -53,6 +53,7 @@
 
 #define PAGE_OFFSET     ASM_CONST(CONFIG_KERNEL_START)
 #define KERNELBASE      (PAGE_OFFSET + PHYSICAL_START)
+#define LOAD_OFFSET     PAGE_OFFSET
 
 #ifdef CONFIG_FLATMEM
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 65ea19eec956..51f8134b5939 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -3,8 +3,6 @@
 
 #define VM_DATA_DEFAULT_FLAGS   VM_DATA_DEFAULT_FLAGS32
 
-#define PPC_MEMSTART    0
-
 #ifdef CONFIG_NOT_COHERENT_CACHE
 #define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
 #endif
diff --git a/include/asm-powerpc/pasemi_dma.h b/include/asm-powerpc/pasemi_dma.h
index b4526ff3a50d..19fd7933e2d9 100644
--- a/include/asm-powerpc/pasemi_dma.h
+++ b/include/asm-powerpc/pasemi_dma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 PA Semi, Inc
+ * Copyright (C) 2006-2008 PA Semi, Inc
  *
  * Hardware register layout and descriptor formats for the on-board
  * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
@@ -40,6 +40,11 @@ enum {
         PAS_DMA_COM_TXSTA = 0x104,      /* Transmit Status Register   */
         PAS_DMA_COM_RXCMD = 0x108,      /* Receive Command Register   */
         PAS_DMA_COM_RXSTA = 0x10c,      /* Receive Status Register    */
+        PAS_DMA_COM_CFG   = 0x114,      /* Common config reg          */
+        PAS_DMA_TXF_SFLG0 = 0x140,      /* Set flags                  */
+        PAS_DMA_TXF_SFLG1 = 0x144,      /* Set flags                  */
+        PAS_DMA_TXF_CFLG0 = 0x148,      /* Set flags                  */
+        PAS_DMA_TXF_CFLG1 = 0x14c,      /* Set flags                  */
 };
 
 
@@ -123,11 +128,16 @@ enum {
 #define    PAS_DMA_TXCHAN_TCMDSTA_DA    0x00000100
 #define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
 #define    PAS_DMA_TXCHAN_CFG_TY_IFACE  0x00000000      /* Type = interface */
+#define    PAS_DMA_TXCHAN_CFG_TY_COPY   0x00000001      /* Type = copy only */
+#define    PAS_DMA_TXCHAN_CFG_TY_FUNC   0x00000002      /* Type = function */
+#define    PAS_DMA_TXCHAN_CFG_TY_XOR    0x00000003      /* Type = xor only */
 #define    PAS_DMA_TXCHAN_CFG_TATTR_M   0x0000003c
 #define    PAS_DMA_TXCHAN_CFG_TATTR_S   2
 #define    PAS_DMA_TXCHAN_CFG_TATTR(x)  (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
                                          PAS_DMA_TXCHAN_CFG_TATTR_M)
-#define    PAS_DMA_TXCHAN_CFG_WT_M      0x000001c0
+#define    PAS_DMA_TXCHAN_CFG_LPDQ      0x00000800
+#define    PAS_DMA_TXCHAN_CFG_LPSQ      0x00000400
+#define    PAS_DMA_TXCHAN_CFG_WT_M      0x000003c0
 #define    PAS_DMA_TXCHAN_CFG_WT_S      6
 #define    PAS_DMA_TXCHAN_CFG_WT(x)     (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
                                          PAS_DMA_TXCHAN_CFG_WT_M)
@@ -394,11 +404,62 @@ enum {
                                  XCT_COPY_LLEN_M)
 #define XCT_COPY_SE             0x0000000000000001ull
 
+/* Function descriptor fields */
+#define XCT_FUN_T               0x8000000000000000ull
+#define XCT_FUN_ST              0x4000000000000000ull
+#define XCT_FUN_RR_M            0x3000000000000000ull
+#define XCT_FUN_RR_NORES        0x0000000000000000ull
+#define XCT_FUN_RR_8BRES        0x1000000000000000ull
+#define XCT_FUN_RR_24BRES       0x2000000000000000ull
+#define XCT_FUN_RR_40BRES       0x3000000000000000ull
+#define XCT_FUN_I               0x0800000000000000ull
+#define XCT_FUN_O               0x0400000000000000ull
+#define XCT_FUN_E               0x0200000000000000ull
+#define XCT_FUN_FUN_M           0x01c0000000000000ull
+#define XCT_FUN_FUN_S           54
+#define XCT_FUN_FUN(x)          ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
+#define XCT_FUN_CRM_M           0x0038000000000000ull
+#define XCT_FUN_CRM_NOP         0x0000000000000000ull
+#define XCT_FUN_CRM_SIG         0x0008000000000000ull
+#define XCT_FUN_LLEN_M          0x0007ffff00000000ull
+#define XCT_FUN_LLEN_S          32
+#define XCT_FUN_LLEN(x)         ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
+#define XCT_FUN_SHL_M           0x00000000f8000000ull
+#define XCT_FUN_SHL_S           27
+#define XCT_FUN_SHL(x)          ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
+#define XCT_FUN_CHL_M           0x0000000007c00000ull
+#define XCT_FUN_HSZ_M           0x00000000003c0000ull
+#define XCT_FUN_ALG_M           0x0000000000038000ull
+#define XCT_FUN_HP              0x0000000000004000ull
+#define XCT_FUN_BCM_M           0x0000000000003800ull
+#define XCT_FUN_BCP_M           0x0000000000000600ull
+#define XCT_FUN_SIG_M           0x00000000000001f0ull
+#define XCT_FUN_SIG_TCP4        0x0000000000000140ull
+#define XCT_FUN_SIG_TCP6        0x0000000000000150ull
+#define XCT_FUN_SIG_UDP4        0x0000000000000160ull
+#define XCT_FUN_SIG_UDP6        0x0000000000000170ull
+#define XCT_FUN_A               0x0000000000000008ull
+#define XCT_FUN_C               0x0000000000000004ull
+#define XCT_FUN_AL2             0x0000000000000002ull
+#define XCT_FUN_SE              0x0000000000000001ull
+
+/* Function descriptor 8byte result fields */
+#define XCT_FUNRES_8B_CS_M      0x0000ffff00000000ull
+#define XCT_FUNRES_8B_CS_S      32
+#define XCT_FUNRES_8B_CRC_M     0x00000000ffffffffull
+#define XCT_FUNRES_8B_CRC_S     0
+
 /* Control descriptor fields */
 #define CTRL_CMD_T              0x8000000000000000ull
 #define CTRL_CMD_META_EVT       0x2000000000000000ull
 #define CTRL_CMD_O              0x0400000000000000ull
-#define CTRL_CMD_REG_M          0x000000000000000full
+#define CTRL_CMD_ETYPE_M        0x0038000000000000ull
+#define CTRL_CMD_ETYPE_EXT      0x0000000000000000ull
+#define CTRL_CMD_ETYPE_WSET     0x0020000000000000ull
+#define CTRL_CMD_ETYPE_WCLR     0x0028000000000000ull
+#define CTRL_CMD_ETYPE_SET      0x0030000000000000ull
+#define CTRL_CMD_ETYPE_CLR      0x0038000000000000ull
+#define CTRL_CMD_REG_M          0x000000000000007full
 #define CTRL_CMD_REG_S          0
 #define CTRL_CMD_REG(x)         ((((long)(x)) << CTRL_CMD_REG_S) & \
                                  CTRL_CMD_REG_M)
@@ -461,6 +522,16 @@ extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
 extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
                                 dma_addr_t *handle);
 
+/* Routines to allocate flags (events) for channel syncronization */
+extern int  pasemi_dma_alloc_flag(void);
+extern void pasemi_dma_free_flag(int flag);
+extern void pasemi_dma_set_flag(int flag);
+extern void pasemi_dma_clear_flag(int flag);
+
+/* Routines to allocate function engines */
+extern int  pasemi_dma_alloc_fun(void);
+extern void pasemi_dma_free_fun(int fun);
+
 /* Initialize the library, must be called before any other functions */
 extern int pasemi_dma_init(void);
 
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index e5802c62f428..b95d033ae6e6 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -117,7 +117,7 @@ struct pci_controller {
 
 #ifndef CONFIG_PPC64
 
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 {
         return bus->sysdata;
 }
@@ -235,7 +235,7 @@ extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
 
 extern int pcibios_remove_root_bus(struct pci_controller *phb);
 
-static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
+static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 {
         struct device_node *busdn = bus->sysdata;
 
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 2c79f550272b..daea7692d070 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -98,9 +98,6 @@ extern int icache_44x_need_flush;
 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
 
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
                 (unsigned long long)pte_val(e))
@@ -420,7 +417,8 @@ extern int icache_44x_need_flush;
 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
+        defined(CONFIG_KPROBES)
 /* We want the debuggers to be able to set breakpoints anywhere, so
  * don't write protect the kernel text */
 #define _PAGE_RAM_TEXT  _PAGE_RAM
@@ -692,7 +690,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 #define pmd_page_vaddr(pmd)     \
         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 #define pmd_page(pmd)           \
-        (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+        pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 #endif
 
 /* to find an entry in a kernel page-table-directory */
diff --git a/include/asm-powerpc/phyp_dump.h b/include/asm-powerpc/phyp_dump.h
new file mode 100644
index 000000000000..fa74c6c3e106
--- /dev/null
+++ b/include/asm-powerpc/phyp_dump.h
@@ -0,0 +1,47 @@
+/*
+ * Hypervisor-assisted dump
+ *
+ * Linas Vepstas, Manish Ahuja 2008
+ * Copyright 2008 IBM Corp.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _PPC64_PHYP_DUMP_H
+#define _PPC64_PHYP_DUMP_H
+
+#ifdef CONFIG_PHYP_DUMP
+
+/* The RMR region will be saved for later dumping
+ * whenever the kernel crashes. Set this to 256MB. */
+#define PHYP_DUMP_RMR_START 0x0
+#define PHYP_DUMP_RMR_END   (1UL<<28)
+
+struct phyp_dump {
+        /* Memory that is reserved during very early boot. */
+        unsigned long init_reserve_start;
+        unsigned long init_reserve_size;
+        /* cmd line options during boot */
+        unsigned long reserve_bootvar;
+        unsigned long phyp_dump_at_boot;
+        /* Check status during boot if dump supported, active & present*/
+        unsigned long phyp_dump_configured;
+        unsigned long phyp_dump_is_active;
+        /* store cpu & hpte size */
+        unsigned long cpu_state_size;
+        unsigned long hpte_region_size;
+        /* previous scratch area values */
+        unsigned long reserved_scratch_addr;
+        unsigned long reserved_scratch_size;
+};
+
+extern struct phyp_dump *phyp_dump_info;
+
+int early_init_dt_scan_phyp_dump(unsigned long node,
+                const char *uname, int depth, void *data);
+
+#endif /* CONFIG_PHYP_DUMP */
+#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/include/asm-powerpc/pmi.h b/include/asm-powerpc/pmi.h
index 2259d4ce3846..e1dc090748df 100644
--- a/include/asm-powerpc/pmi.h
+++ b/include/asm-powerpc/pmi.h
@@ -29,8 +29,6 @@
 
 #ifdef __KERNEL__
 
-#include <asm/of_device.h>
-
 #define PMI_TYPE_FREQ_CHANGE    0x01
 #define PMI_READ_TYPE           0
 #define PMI_READ_DATA0          1
diff --git a/include/asm-powerpc/ppc4xx.h b/include/asm-powerpc/ppc4xx.h
new file mode 100644
index 000000000000..033039a80c42
--- /dev/null
+++ b/include/asm-powerpc/ppc4xx.h
@@ -0,0 +1,18 @@
+/*
+ * PPC4xx Prototypes and definitions
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_PPC4xx_H__
+#define __ASM_POWERPC_PPC4xx_H__
+
+extern void ppc4xx_reset_system(char *cmd);
+
+#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
index 2b693673eff4..9e8ed6824e15 100644
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -434,8 +434,11 @@ struct ps3_sys_manager_ops {
 };
 
 void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
-void ps3_sys_manager_power_off(void);
-void ps3_sys_manager_restart(void);
+void __noreturn ps3_sys_manager_power_off(void);
+void __noreturn ps3_sys_manager_restart(void);
+void __noreturn ps3_sys_manager_halt(void);
+int ps3_sys_manager_get_wol(void);
+void ps3_sys_manager_set_wol(int state);
 
 struct ps3_prealloc {
     const char *name;
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 891d68932f39..39023dde1cc4 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -58,6 +58,11 @@ struct pt_regs {
 #define __ARCH_WANT_COMPAT_SYS_PTRACE
 
 #define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE     2       /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
+#define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + \
+                                        STACK_FRAME_OVERHEAD + 288)
+#define STACK_FRAME_MARKER      12
 
 /* Size of dummy stack frame allocated when calling signal handler. */
 #define __SIGNAL_FRAMESIZE      128
@@ -66,6 +71,10 @@ struct pt_regs {
 #else /* __powerpc64__ */
 
 #define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
+#define STACK_FRAME_LR_SAVE     1       /* Location of LR in stack frame */
+#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
+#define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
+#define STACK_FRAME_MARKER      2
 
 /* Size of stack frame allocated when calling signal handler. */
 #define __SIGNAL_FRAMESIZE      64
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 430dc77b35fc..c3be6e2e1490 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -85,6 +85,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
 /* QE internal API */
 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
 enum qe_clock qe_clock_source(const char *source);
+unsigned int qe_get_brg_clk(void);
 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
@@ -92,7 +93,16 @@ unsigned long qe_muram_alloc(int size, int align);
 int qe_muram_free(unsigned long offset);
 unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
 void qe_muram_dump(void);
-void *qe_muram_addr(unsigned long offset);
+
+static inline void __iomem *qe_muram_addr(unsigned long offset)
+{
+        return (void __iomem *)&qe_immr->muram[offset];
+}
+
+static inline unsigned long qe_muram_offset(void __iomem *addr)
+{
+        return addr - (void __iomem *)qe_immr->muram;
+}
 
 /* Structure that defines QE firmware binary files.
  *
diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h
index cefc14728cc5..a6cc93b78b98 100644
--- a/include/asm-powerpc/rwsem.h
+++ b/include/asm-powerpc/rwsem.h
@@ -32,11 +32,20 @@ struct rw_semaphore {
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
         spinlock_t              wait_lock;
         struct list_head        wait_list;
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+        struct lockdep_map      dep_map;
+#endif
 };
 
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
+#else
+# define __RWSEM_DEP_MAP_INIT(lockname)
+#endif
+
 #define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) }
+        { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
+          LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
 
 #define DECLARE_RWSEM(name)             \
         struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -46,12 +55,15 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
 extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
 
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-}
+extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
+                         struct lock_class_key *key);
+
+#define init_rwsem(sem)                                 \
+        do {                                            \
+                static struct lock_class_key __key;     \
+                                                        \
+                __init_rwsem((sem), #sem, &__key);      \
+        } while (0)
 
 /*
  * lock for reading
@@ -78,7 +90,7 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
 /*
  * lock for writing
  */
-static inline void __down_write(struct rw_semaphore *sem)
+static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
 {
         int tmp;
 
@@ -88,6 +100,11 @@ static inline void __down_write(struct rw_semaphore *sem)
                 rwsem_down_write_failed(sem);
 }
 
+static inline void __down_write(struct rw_semaphore *sem)
+{
+        __down_write_nested(sem, 0);
+}
+
 static inline int __down_write_trylock(struct rw_semaphore *sem)
 {
         int tmp;
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index e8b493d52b4f..9aea8e9f0bd1 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -15,6 +15,7 @@
 
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern void create_section_mapping(unsigned long start, unsigned long end);
+extern int remove_section_mapping(unsigned long start, unsigned long end);
 #ifdef CONFIG_NUMA
 extern int hot_add_scn_to_nid(unsigned long scn_addr);
 #else
diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h
index cc4cfceac67c..258c93993190 100644
--- a/include/asm-powerpc/spinlock.h
+++ b/include/asm-powerpc/spinlock.h
@@ -19,6 +19,7 @@
  *
  * (the type definitions are in asm/spinlock_types.h)
  */
+#include <linux/irqflags.h>
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 #include <asm/hvcall.h>
diff --git a/include/asm-powerpc/string.h b/include/asm-powerpc/string.h
index aa40f92c298d..e40010abcaf1 100644
--- a/include/asm-powerpc/string.h
+++ b/include/asm-powerpc/string.h
@@ -7,6 +7,7 @@
 #define __HAVE_ARCH_STRNCPY
 #define __HAVE_ARCH_STRLEN
 #define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
 #define __HAVE_ARCH_STRCAT
 #define __HAVE_ARCH_MEMSET
 #define __HAVE_ARCH_MEMCPY
@@ -18,6 +19,7 @@ extern char * strcpy(char *,const char *);
 extern char * strncpy(char *,const char *, __kernel_size_t);
 extern __kernel_size_t strlen(const char *);
 extern int strcmp(const char *,const char *);
+extern int strncmp(const char *, const char *, __kernel_size_t);
 extern char * strcat(char *, const char *);
 extern void * memset(void *,int,__kernel_size_t);
 extern void * memcpy(void *,const void *,__kernel_size_t);
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 29552ff182aa..fab1674b31b6 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -5,6 +5,7 @@
 #define _ASM_POWERPC_SYSTEM_H
 
 #include <linux/kernel.h>
+#include <linux/irqflags.h>
 
 #include <asm/hw_irq.h>
 
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
index 903fd1932436..c243a6ac60e5 100644
--- a/include/asm-powerpc/types.h
+++ b/include/asm-powerpc/types.h
@@ -84,6 +84,13 @@ typedef unsigned long long u64;
 
 typedef __vector128 vector128;
 
+/* Physical address used by some IO functions */
+#if defined(CONFIG_PPC64) || defined(CONFIG_PHYS_64BIT)
+typedef u64 phys_addr_t;
+#else
+typedef u32 phys_addr_t;
+#endif
+
 #ifdef __powerpc64__
 typedef u64 dma_addr_t;
 #else