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authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-04-11 13:03:40 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 02:01:38 -0400
commitacaa7aa30a8cdf7276945629f56d6daf30beb157 (patch)
tree8fa70d5f1417f3d6f48dbb4ceb671e48ad0f752d /include/asm-powerpc
parentd4a32fe40a57d1a47d6ec3ebbf3d3153b12baa2c (diff)
[POWERPC] fsl_lbc: implement few UPM routines
Freescale UPM can be used to adjust localbus timings or to generate orbitrary, pre-programmed "patterns" on the external Localbus signals. This patch implements few routines so drivers could work with UPMs in safe and generic manner. So far there is just one user of these routines: Freescale UPM NAND driver. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/fsl_lbc.h88
1 files changed, 88 insertions, 0 deletions
diff --git a/include/asm-powerpc/fsl_lbc.h b/include/asm-powerpc/fsl_lbc.h
index 13a3c28e1e10..303f5484c050 100644
--- a/include/asm-powerpc/fsl_lbc.h
+++ b/include/asm-powerpc/fsl_lbc.h
@@ -24,6 +24,8 @@
24#define __ASM_FSL_LBC_H 24#define __ASM_FSL_LBC_H
25 25
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/spinlock.h>
28#include <asm/io.h>
27 29
28struct fsl_lbc_bank { 30struct fsl_lbc_bank {
29 __be32 br; /**< Base Register */ 31 __be32 br; /**< Base Register */
@@ -98,6 +100,11 @@ struct fsl_lbc_regs {
98 __be32 mar; /**< UPM Address Register */ 100 __be32 mar; /**< UPM Address Register */
99 u8 res1[0x4]; 101 u8 res1[0x4];
100 __be32 mamr; /**< UPMA Mode Register */ 102 __be32 mamr; /**< UPMA Mode Register */
103#define MxMR_OP_NO (0 << 28) /**< normal operation */
104#define MxMR_OP_WA (1 << 28) /**< write array */
105#define MxMR_OP_RA (2 << 28) /**< read array */
106#define MxMR_OP_RP (3 << 28) /**< run pattern */
107#define MxMR_MAD 0x3f /**< machine address */
101 __be32 mbmr; /**< UPMB Mode Register */ 108 __be32 mbmr; /**< UPMB Mode Register */
102 __be32 mcmr; /**< UPMC Mode Register */ 109 __be32 mcmr; /**< UPMC Mode Register */
103 u8 res2[0x8]; 110 u8 res2[0x8];
@@ -220,4 +227,85 @@ struct fsl_lbc_regs {
220 u8 res8[0xF00]; 227 u8 res8[0xF00];
221}; 228};
222 229
230extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
231extern spinlock_t fsl_lbc_lock;
232
233/*
234 * FSL UPM routines
235 */
236struct fsl_upm {
237 __be32 __iomem *mxmr;
238 int width;
239};
240
241extern int fsl_lbc_find(phys_addr_t addr_base);
242extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
243
244/**
245 * fsl_upm_start_pattern - start UPM patterns execution
246 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
247 * @pat_offset: UPM pattern offset for the command to be executed
248 *
249 * This routine programmes UPM so the next memory access that hits an UPM
250 * will trigger pattern execution, starting at pat_offset.
251 */
252static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
253{
254 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
255}
256
257/**
258 * fsl_upm_end_pattern - end UPM patterns execution
259 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
260 *
261 * This routine reverts UPM to normal operation mode.
262 */
263static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
264{
265 clrbits32(upm->mxmr, MxMR_OP_RP);
266
267 while (in_be32(upm->mxmr) & MxMR_OP_RP)
268 cpu_relax();
269}
270
271/**
272 * fsl_upm_run_pattern - actually run an UPM pattern
273 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
274 * @io_base: remapped pointer to where memory access should happen
275 * @mar: MAR register content during pattern execution
276 *
277 * This function triggers dummy write to the memory specified by the io_base,
278 * thus UPM pattern actually executed. Note that mar usage depends on the
279 * pre-programmed AMX bits in the UPM RAM.
280 */
281static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
282 void __iomem *io_base, u32 mar)
283{
284 int ret = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&fsl_lbc_lock, flags);
288
289 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
290
291 switch (upm->width) {
292 case 8:
293 out_8(io_base, 0x0);
294 break;
295 case 16:
296 out_be16(io_base, 0x0);
297 break;
298 case 32:
299 out_be32(io_base, 0x0);
300 break;
301 default:
302 ret = -EINVAL;
303 break;
304 }
305
306 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
307
308 return ret;
309}
310
223#endif /* __ASM_FSL_LBC_H */ 311#endif /* __ASM_FSL_LBC_H */