diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2006-03-23 01:36:59 -0500 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-03-26 22:48:06 -0500 |
| commit | 7c92943c7b6c42fa631ac2b67aeb507e727cd75b (patch) | |
| tree | 6fcfee97618ff9b2d23d639a825b62e935028496 /include/asm-powerpc | |
| parent | 5d5d7727a8cde78f798ecf04bac8031eff536f9d (diff) | |
[PATCH] powerpc: work around sparse warnings in cputable.h
Christoph noticed that sparse warned about all the enum tags in cuptable.h
that had values that required them to be type log. (enum tags are ints
according to the standard.)
This patch attempts to fix them in the least intrusive way possible by
turning them all into #defines except for the 32 bit CPU_FTRS_POSSIBLE and
CPU_FTRS_ALWAYS which are hard to construct that way. This works because
these last two contain no bits above 2^31.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 299 |
1 files changed, 152 insertions, 147 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index fe45f6f3a4be..4321483cce51 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h | |||
| @@ -188,153 +188,154 @@ extern void do_cpu_ftr_fixups(unsigned long offset); | |||
| 188 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | 188 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ |
| 189 | !defined(CONFIG_BOOKE)) | 189 | !defined(CONFIG_BOOKE)) |
| 190 | 190 | ||
| 191 | enum { | 191 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) |
| 192 | CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE, | 192 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 193 | CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 193 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
| 194 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | | 194 | CPU_FTR_MAYBE_CAN_NAP) |
| 195 | CPU_FTR_MAYBE_CAN_NAP, | 195 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 196 | CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 196 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE) |
| 197 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE, | 197 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 198 | CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 198 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 199 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 199 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) |
| 200 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | 200 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 201 | CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 201 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 202 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 202 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) |
| 203 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | 203 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 204 | CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 204 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 205 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 205 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP) |
| 206 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | 206 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 207 | CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 207 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 208 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 208 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 209 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | 209 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) |
| 210 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM, | 210 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 211 | CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 211 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 212 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 212 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 213 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | 213 | CPU_FTR_NO_DPM) |
| 214 | CPU_FTR_NO_DPM, | 214 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 215 | CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 215 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 216 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 216 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 217 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | 217 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) |
| 218 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, | 218 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
| 219 | CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | 219 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ |
| 220 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | | 220 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
| 221 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | 221 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS) |
| 222 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, | 222 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 223 | CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 223 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 224 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 224 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 225 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | | 225 | CPU_FTR_MAYBE_CAN_NAP) |
| 226 | CPU_FTR_MAYBE_CAN_NAP, | 226 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 227 | CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 227 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 228 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | 228 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ |
| 229 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | | 229 | CPU_FTR_MAYBE_CAN_NAP) |
| 230 | CPU_FTR_MAYBE_CAN_NAP, | 230 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 231 | CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 231 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 232 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 232 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 233 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 233 | CPU_FTR_NEED_COHERENT) |
| 234 | CPU_FTR_NEED_COHERENT, | 234 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 235 | CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 235 | CPU_FTR_USE_TB | \ |
| 236 | CPU_FTR_USE_TB | | 236 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 237 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 237 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 238 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 238 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 239 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | | 239 | CPU_FTR_NEED_COHERENT) |
| 240 | CPU_FTR_NEED_COHERENT, | 240 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 241 | CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 241 | CPU_FTR_USE_TB | \ |
| 242 | CPU_FTR_USE_TB | | 242 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 243 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 243 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 244 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 244 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT) |
| 245 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT, | 245 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 246 | CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 246 | CPU_FTR_USE_TB | \ |
| 247 | CPU_FTR_USE_TB | | 247 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
| 248 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | | 248 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ |
| 249 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | | 249 | CPU_FTR_NEED_COHERENT) |
| 250 | CPU_FTR_NEED_COHERENT, | 250 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 251 | CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 251 | CPU_FTR_USE_TB | \ |
| 252 | CPU_FTR_USE_TB | | 252 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 253 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 253 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 254 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 254 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 255 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | | 255 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS) |
| 256 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS, | 256 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 257 | CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 257 | CPU_FTR_USE_TB | \ |
| 258 | CPU_FTR_USE_TB | | 258 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 259 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 259 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 260 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 260 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 261 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | 261 | CPU_FTR_NEED_COHERENT) |
| 262 | CPU_FTR_NEED_COHERENT, | 262 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 263 | CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 263 | CPU_FTR_USE_TB | \ |
| 264 | CPU_FTR_USE_TB | | 264 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 265 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 265 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 266 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 266 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 267 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | 267 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC) |
| 268 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, | 268 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 269 | CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 269 | CPU_FTR_USE_TB | \ |
| 270 | CPU_FTR_USE_TB | | 270 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 271 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 271 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 272 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 272 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 273 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | 273 | CPU_FTR_NEED_COHERENT) |
| 274 | CPU_FTR_NEED_COHERENT, | 274 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 275 | CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 275 | CPU_FTR_USE_TB | \ |
| 276 | CPU_FTR_USE_TB | | 276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 277 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | 277 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ |
| 278 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | 278 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ |
| 279 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | 279 | CPU_FTR_NEED_COHERENT) |
| 280 | CPU_FTR_NEED_COHERENT, | 280 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 281 | CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 281 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
| 282 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB, | 282 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
| 283 | CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | 283 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) |
| 284 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, | 284 | #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
| 285 | CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | 285 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ |
| 286 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | | 286 | CPU_FTR_COMMON) |
| 287 | CPU_FTR_COMMON, | 287 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 288 | CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 288 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) |
| 289 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | 289 | #define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 290 | CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 290 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) |
| 291 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | 291 | #define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 292 | CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 292 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN) |
| 293 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN, | 293 | #define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
| 294 | CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | 294 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \ |
| 295 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | | 295 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN) |
| 296 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN, | 296 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) |
| 297 | CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | 297 | #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 298 | CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 298 | CPU_FTR_NODSISRALIGN) |
| 299 | CPU_FTR_NODSISRALIGN, | 299 | #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 300 | CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 300 | CPU_FTR_NODSISRALIGN) |
| 301 | CPU_FTR_NODSISRALIGN, | 301 | #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) |
| 302 | CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN, | 302 | #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 303 | CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 303 | CPU_FTR_NODSISRALIGN) |
| 304 | CPU_FTR_NODSISRALIGN, | 304 | #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 305 | CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 305 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) |
| 306 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN, | 306 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
| 307 | CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN, | ||
| 308 | #ifdef __powerpc64__ | 307 | #ifdef __powerpc64__ |
| 309 | CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 308 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 310 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, | 309 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR) |
| 311 | CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 310 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 312 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | 311 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ |
| 313 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | 312 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
| 314 | CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 313 | #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 315 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA, | 314 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA) |
| 316 | CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 315 | #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 317 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | 316 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 318 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA, | 317 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) |
| 319 | CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 318 | #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 320 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | 319 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 321 | CPU_FTR_MMCRA | CPU_FTR_SMT | | 320 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 322 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | | 321 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
| 323 | CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR, | 322 | CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR) |
| 324 | CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 323 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 325 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | 324 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ |
| 326 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | | 325 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
| 327 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO, | 326 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO) |
| 328 | CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | 327 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
| 329 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2, | 328 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) |
| 330 | #endif | 329 | #endif |
| 331 | 330 | ||
| 332 | CPU_FTRS_POSSIBLE = | ||
| 333 | #ifdef __powerpc64__ | 331 | #ifdef __powerpc64__ |
| 334 | CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | | 332 | #define CPU_FTRS_POSSIBLE \ |
| 335 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL | | 333 | (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ |
| 336 | CPU_FTR_CI_LARGE_PAGE | | 334 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL | \ |
| 335 | CPU_FTR_CI_LARGE_PAGE) | ||
| 337 | #else | 336 | #else |
| 337 | enum { | ||
| 338 | CPU_FTRS_POSSIBLE = | ||
| 338 | #if CLASSIC_PPC | 339 | #if CLASSIC_PPC |
| 339 | CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | | 340 | CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | |
| 340 | CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | | 341 | CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | |
| @@ -368,14 +369,18 @@ enum { | |||
| 368 | #ifdef CONFIG_E500 | 369 | #ifdef CONFIG_E500 |
| 369 | CPU_FTRS_E500 | CPU_FTRS_E500_2 | | 370 | CPU_FTRS_E500 | CPU_FTRS_E500_2 | |
| 370 | #endif | 371 | #endif |
| 371 | #endif /* __powerpc64__ */ | ||
| 372 | 0, | 372 | 0, |
| 373 | }; | ||
| 374 | #endif /* __powerpc64__ */ | ||
| 373 | 375 | ||
| 374 | CPU_FTRS_ALWAYS = | ||
| 375 | #ifdef __powerpc64__ | 376 | #ifdef __powerpc64__ |
| 376 | CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & | 377 | #define CPU_FTRS_ALWAYS \ |
| 377 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & | 378 | (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ |
| 379 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & \ | ||
| 380 | CPU_FTRS_POSSIBLE) | ||
| 378 | #else | 381 | #else |
| 382 | enum { | ||
| 383 | CPU_FTRS_ALWAYS = | ||
| 379 | #if CLASSIC_PPC | 384 | #if CLASSIC_PPC |
| 380 | CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & | 385 | CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & |
| 381 | CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & | 386 | CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & |
| @@ -409,9 +414,9 @@ enum { | |||
| 409 | #ifdef CONFIG_E500 | 414 | #ifdef CONFIG_E500 |
| 410 | CPU_FTRS_E500 & CPU_FTRS_E500_2 & | 415 | CPU_FTRS_E500 & CPU_FTRS_E500_2 & |
| 411 | #endif | 416 | #endif |
| 412 | #endif /* __powerpc64__ */ | ||
| 413 | CPU_FTRS_POSSIBLE, | 417 | CPU_FTRS_POSSIBLE, |
| 414 | }; | 418 | }; |
| 419 | #endif /* __powerpc64__ */ | ||
| 415 | 420 | ||
| 416 | static inline int cpu_has_feature(unsigned long feature) | 421 | static inline int cpu_has_feature(unsigned long feature) |
| 417 | { | 422 | { |