diff options
author | Stephen Rothwell <sfr@canb.auug.org.au> | 2005-11-03 00:24:25 -0500 |
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committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2005-11-03 00:24:25 -0500 |
commit | 608f8b3cf3a7fbd009e6bf78e680ea04e6a4e46f (patch) | |
tree | cf3a195fe50b61ce382859117fbe7197ff3a7bad /include/asm-powerpc | |
parent | 879168ee51925f7e68165577fba8ef781ccfccb9 (diff) |
powerpc: merge sigcontext.h
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r-- | include/asm-powerpc/sigcontext.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/include/asm-powerpc/sigcontext.h b/include/asm-powerpc/sigcontext.h new file mode 100644 index 000000000000..165d630e1cf3 --- /dev/null +++ b/include/asm-powerpc/sigcontext.h | |||
@@ -0,0 +1,52 @@ | |||
1 | #ifndef _ASM_POWERPC_SIGCONTEXT_H | ||
2 | #define _ASM_POWERPC_SIGCONTEXT_H | ||
3 | |||
4 | /* | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation; either version | ||
8 | * 2 of the License, or (at your option) any later version. | ||
9 | */ | ||
10 | #include <linux/compiler.h> | ||
11 | #include <asm/ptrace.h> | ||
12 | #ifdef __powerpc64__ | ||
13 | #include <asm/elf.h> | ||
14 | #endif | ||
15 | |||
16 | struct sigcontext { | ||
17 | unsigned long _unused[4]; | ||
18 | int signal; | ||
19 | #ifdef __powerpc64__ | ||
20 | int _pad0; | ||
21 | #endif | ||
22 | unsigned long handler; | ||
23 | unsigned long oldmask; | ||
24 | struct pt_regs __user *regs; | ||
25 | #ifdef __powerpc64__ | ||
26 | elf_gregset_t gp_regs; | ||
27 | elf_fpregset_t fp_regs; | ||
28 | /* | ||
29 | * To maintain compatibility with current implementations the sigcontext is | ||
30 | * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) | ||
31 | * followed by an unstructured (vmx_reserve) field of 69 doublewords. This | ||
32 | * allows the array of vector registers to be quadword aligned independent of | ||
33 | * the alignment of the containing sigcontext or ucontext. It is the | ||
34 | * responsibility of the code setting the sigcontext to set this pointer to | ||
35 | * either NULL (if this processor does not support the VMX feature) or the | ||
36 | * address of the first quadword within the allocated (vmx_reserve) area. | ||
37 | * | ||
38 | * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with | ||
39 | * an array of 34 quadword entries (elf_vrregset_t). The entries with | ||
40 | * indexes 0-31 contain the corresponding vector registers. The entry with | ||
41 | * index 32 contains the vscr as the last word (offset 12) within the | ||
42 | * quadword. This allows the vscr to be stored as either a quadword (since | ||
43 | * it must be copied via a vector register to/from storage) or as a word. | ||
44 | * The entry with index 33 contains the vrsave as the first word (offset 0) | ||
45 | * within the quadword. | ||
46 | */ | ||
47 | elf_vrreg_t __user *v_regs; | ||
48 | long vmx_reserve[ELF_NVRREG+ELF_NVRREG+1]; | ||
49 | #endif | ||
50 | }; | ||
51 | |||
52 | #endif /* _ASM_POWERPC_SIGCONTEXT_H */ | ||