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authorSylvain Munaut <tnt@246tNt.com>2006-11-27 16:16:26 -0500
committerPaul Mackerras <paulus@samba.org>2006-12-04 04:41:41 -0500
commite65fdfd6ca447353ad1b4c0a0d20df55f3f6f233 (patch)
tree0e8bc17286442bac1b04b2b607571fff38e6d2d3 /include/asm-powerpc
parentb9cf5d8e2edc503977be090eff45ef81555dcb1d (diff)
[POWERPC] Separate IRQ config / register set from main header
There is no need to expose these settings outside the scope of the interrupt controller code itself. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/mpc52xx.h37
1 files changed, 0 insertions, 37 deletions
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index e9aa622f19f6..fff752c4bd17 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -20,48 +20,11 @@
20 20
21 21
22/* ======================================================================== */ 22/* ======================================================================== */
23/* HW IRQ mapping */
24/* ======================================================================== */
25
26#define MPC52xx_IRQ_L1_CRIT (0)
27#define MPC52xx_IRQ_L1_MAIN (1)
28#define MPC52xx_IRQ_L1_PERP (2)
29#define MPC52xx_IRQ_L1_SDMA (3)
30
31#define MPC52xx_IRQ_L1_OFFSET (6)
32#define MPC52xx_IRQ_L1_MASK (0xc0)
33
34#define MPC52xx_IRQ_L2_OFFSET (0)
35#define MPC52xx_IRQ_L2_MASK (0x3f)
36
37#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
38
39
40/* ======================================================================== */
41/* Structures mapping of some unit register set */ 23/* Structures mapping of some unit register set */
42/* ======================================================================== */ 24/* ======================================================================== */
43 25
44#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
45 27
46/* Interrupt controller Register set */
47struct mpc52xx_intr {
48 u32 per_mask; /* INTR + 0x00 */
49 u32 per_pri1; /* INTR + 0x04 */
50 u32 per_pri2; /* INTR + 0x08 */
51 u32 per_pri3; /* INTR + 0x0c */
52 u32 ctrl; /* INTR + 0x10 */
53 u32 main_mask; /* INTR + 0x14 */
54 u32 main_pri1; /* INTR + 0x18 */
55 u32 main_pri2; /* INTR + 0x1c */
56 u32 reserved1; /* INTR + 0x20 */
57 u32 enc_status; /* INTR + 0x24 */
58 u32 crit_status; /* INTR + 0x28 */
59 u32 main_status; /* INTR + 0x2c */
60 u32 per_status; /* INTR + 0x30 */
61 u32 reserved2; /* INTR + 0x34 */
62 u32 per_error; /* INTR + 0x38 */
63};
64
65/* Memory Mapping Control */ 28/* Memory Mapping Control */
66struct mpc52xx_mmap_ctl { 29struct mpc52xx_mmap_ctl {
67 u32 mbar; /* MMAP_CTRL + 0x00 */ 30 u32 mbar; /* MMAP_CTRL + 0x00 */